xref: /linux/drivers/tty/serial/21285.c (revision f9bff0e31881d03badf191d3b0005839391f5f2b) 
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Driver for the serial port on the 21285 StrongArm-110 core logic chip.
4  *
5  * Based on drivers/char/serial.c
6  */
7 #include <linux/module.h>
8 #include <linux/tty.h>
9 #include <linux/ioport.h>
10 #include <linux/init.h>
11 #include <linux/console.h>
12 #include <linux/device.h>
13 #include <linux/tty_flip.h>
14 #include <linux/serial_core.h>
15 #include <linux/serial.h>
16 #include <linux/io.h>
17 
18 #include <asm/irq.h>
19 #include <asm/mach-types.h>
20 #include <asm/system_info.h>
21 #include <asm/hardware/dec21285.h>
22 #include <mach/hardware.h>
23 
24 #define BAUD_BASE		(mem_fclk_21285/64)
25 
26 #define SERIAL_21285_NAME	"ttyFB"
27 #define SERIAL_21285_MAJOR	204
28 #define SERIAL_21285_MINOR	4
29 
30 #define RXSTAT_DUMMY_READ	0x80000000
31 #define RXSTAT_FRAME		(1 << 0)
32 #define RXSTAT_PARITY		(1 << 1)
33 #define RXSTAT_OVERRUN		(1 << 2)
34 #define RXSTAT_ANYERR		(RXSTAT_FRAME|RXSTAT_PARITY|RXSTAT_OVERRUN)
35 
36 #define H_UBRLCR_BREAK		(1 << 0)
37 #define H_UBRLCR_PARENB		(1 << 1)
38 #define H_UBRLCR_PAREVN		(1 << 2)
39 #define H_UBRLCR_STOPB		(1 << 3)
40 #define H_UBRLCR_FIFO		(1 << 4)
41 
42 static const char serial21285_name[] = "Footbridge UART";
43 
44 /*
45  * We only need 2 bits of data, so instead of creating a whole structure for
46  * this, use bits of the private_data pointer of the uart port structure.
47  */
48 #define tx_enabled_bit	0
49 #define rx_enabled_bit	1
50 
51 static bool is_enabled(struct uart_port *port, int bit)
52 {
53 	unsigned long *private_data = (unsigned long *)&port->private_data;
54 
55 	if (test_bit(bit, private_data))
56 		return true;
57 	return false;
58 }
59 
60 static void enable(struct uart_port *port, int bit)
61 {
62 	unsigned long *private_data = (unsigned long *)&port->private_data;
63 
64 	set_bit(bit, private_data);
65 }
66 
67 static void disable(struct uart_port *port, int bit)
68 {
69 	unsigned long *private_data = (unsigned long *)&port->private_data;
70 
71 	clear_bit(bit, private_data);
72 }
73 
74 #define is_tx_enabled(port)	is_enabled(port, tx_enabled_bit)
75 #define tx_enable(port)		enable(port, tx_enabled_bit)
76 #define tx_disable(port)	disable(port, tx_enabled_bit)
77 
78 #define is_rx_enabled(port)	is_enabled(port, rx_enabled_bit)
79 #define rx_enable(port)		enable(port, rx_enabled_bit)
80 #define rx_disable(port)	disable(port, rx_enabled_bit)
81 
82 /*
83  * The documented expression for selecting the divisor is:
84  *  BAUD_BASE / baud - 1
85  * However, typically BAUD_BASE is not divisible by baud, so
86  * we want to select the divisor that gives us the minimum
87  * error.  Therefore, we want:
88  *  int(BAUD_BASE / baud - 0.5) ->
89  *  int(BAUD_BASE / baud - (baud >> 1) / baud) ->
90  *  int((BAUD_BASE - (baud >> 1)) / baud)
91  */
92 
93 static void serial21285_stop_tx(struct uart_port *port)
94 {
95 	if (is_tx_enabled(port)) {
96 		disable_irq_nosync(IRQ_CONTX);
97 		tx_disable(port);
98 	}
99 }
100 
101 static void serial21285_start_tx(struct uart_port *port)
102 {
103 	if (!is_tx_enabled(port)) {
104 		enable_irq(IRQ_CONTX);
105 		tx_enable(port);
106 	}
107 }
108 
109 static void serial21285_stop_rx(struct uart_port *port)
110 {
111 	if (is_rx_enabled(port)) {
112 		disable_irq_nosync(IRQ_CONRX);
113 		rx_disable(port);
114 	}
115 }
116 
117 static irqreturn_t serial21285_rx_chars(int irq, void *dev_id)
118 {
119 	struct uart_port *port = dev_id;
120 	unsigned int status, ch, flag, rxs, max_count = 256;
121 
122 	status = *CSR_UARTFLG;
123 	while (!(status & 0x10) && max_count--) {
124 		ch = *CSR_UARTDR;
125 		flag = TTY_NORMAL;
126 		port->icount.rx++;
127 
128 		rxs = *CSR_RXSTAT | RXSTAT_DUMMY_READ;
129 		if (unlikely(rxs & RXSTAT_ANYERR)) {
130 			if (rxs & RXSTAT_PARITY)
131 				port->icount.parity++;
132 			else if (rxs & RXSTAT_FRAME)
133 				port->icount.frame++;
134 			if (rxs & RXSTAT_OVERRUN)
135 				port->icount.overrun++;
136 
137 			rxs &= port->read_status_mask;
138 
139 			if (rxs & RXSTAT_PARITY)
140 				flag = TTY_PARITY;
141 			else if (rxs & RXSTAT_FRAME)
142 				flag = TTY_FRAME;
143 		}
144 
145 		uart_insert_char(port, rxs, RXSTAT_OVERRUN, ch, flag);
146 
147 		status = *CSR_UARTFLG;
148 	}
149 	tty_flip_buffer_push(&port->state->port);
150 
151 	return IRQ_HANDLED;
152 }
153 
154 static irqreturn_t serial21285_tx_chars(int irq, void *dev_id)
155 {
156 	struct uart_port *port = dev_id;
157 	u8 ch;
158 
159 	uart_port_tx_limited(port, ch, 256,
160 		!(*CSR_UARTFLG & 0x20),
161 		*CSR_UARTDR = ch,
162 		({}));
163 
164 	return IRQ_HANDLED;
165 }
166 
167 static unsigned int serial21285_tx_empty(struct uart_port *port)
168 {
169 	return (*CSR_UARTFLG & 8) ? 0 : TIOCSER_TEMT;
170 }
171 
172 /* no modem control lines */
173 static unsigned int serial21285_get_mctrl(struct uart_port *port)
174 {
175 	return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
176 }
177 
178 static void serial21285_set_mctrl(struct uart_port *port, unsigned int mctrl)
179 {
180 }
181 
182 static void serial21285_break_ctl(struct uart_port *port, int break_state)
183 {
184 	unsigned long flags;
185 	unsigned int h_lcr;
186 
187 	spin_lock_irqsave(&port->lock, flags);
188 	h_lcr = *CSR_H_UBRLCR;
189 	if (break_state)
190 		h_lcr |= H_UBRLCR_BREAK;
191 	else
192 		h_lcr &= ~H_UBRLCR_BREAK;
193 	*CSR_H_UBRLCR = h_lcr;
194 	spin_unlock_irqrestore(&port->lock, flags);
195 }
196 
197 static int serial21285_startup(struct uart_port *port)
198 {
199 	int ret;
200 
201 	tx_enable(port);
202 	rx_enable(port);
203 
204 	ret = request_irq(IRQ_CONRX, serial21285_rx_chars, 0,
205 			  serial21285_name, port);
206 	if (ret == 0) {
207 		ret = request_irq(IRQ_CONTX, serial21285_tx_chars, 0,
208 				  serial21285_name, port);
209 		if (ret)
210 			free_irq(IRQ_CONRX, port);
211 	}
212 
213 	return ret;
214 }
215 
216 static void serial21285_shutdown(struct uart_port *port)
217 {
218 	free_irq(IRQ_CONTX, port);
219 	free_irq(IRQ_CONRX, port);
220 }
221 
222 static void
223 serial21285_set_termios(struct uart_port *port, struct ktermios *termios,
224 			const struct ktermios *old)
225 {
226 	unsigned long flags;
227 	unsigned int baud, quot, h_lcr, b;
228 
229 	/*
230 	 * We don't support modem control lines.
231 	 */
232 	termios->c_cflag &= ~(HUPCL | CRTSCTS | CMSPAR);
233 	termios->c_cflag |= CLOCAL;
234 
235 	/*
236 	 * We don't support BREAK character recognition.
237 	 */
238 	termios->c_iflag &= ~(IGNBRK | BRKINT);
239 
240 	/*
241 	 * Ask the core to calculate the divisor for us.
242 	 */
243 	baud = uart_get_baud_rate(port, termios, old, 0, port->uartclk/16);
244 	quot = uart_get_divisor(port, baud);
245 	b = port->uartclk / (16 * quot);
246 	tty_termios_encode_baud_rate(termios, b, b);
247 
248 	switch (termios->c_cflag & CSIZE) {
249 	case CS5:
250 		h_lcr = 0x00;
251 		break;
252 	case CS6:
253 		h_lcr = 0x20;
254 		break;
255 	case CS7:
256 		h_lcr = 0x40;
257 		break;
258 	default: /* CS8 */
259 		h_lcr = 0x60;
260 		break;
261 	}
262 
263 	if (termios->c_cflag & CSTOPB)
264 		h_lcr |= H_UBRLCR_STOPB;
265 	if (termios->c_cflag & PARENB) {
266 		h_lcr |= H_UBRLCR_PARENB;
267 		if (!(termios->c_cflag & PARODD))
268 			h_lcr |= H_UBRLCR_PAREVN;
269 	}
270 
271 	if (port->fifosize)
272 		h_lcr |= H_UBRLCR_FIFO;
273 
274 	spin_lock_irqsave(&port->lock, flags);
275 
276 	/*
277 	 * Update the per-port timeout.
278 	 */
279 	uart_update_timeout(port, termios->c_cflag, baud);
280 
281 	/*
282 	 * Which character status flags are we interested in?
283 	 */
284 	port->read_status_mask = RXSTAT_OVERRUN;
285 	if (termios->c_iflag & INPCK)
286 		port->read_status_mask |= RXSTAT_FRAME | RXSTAT_PARITY;
287 
288 	/*
289 	 * Which character status flags should we ignore?
290 	 */
291 	port->ignore_status_mask = 0;
292 	if (termios->c_iflag & IGNPAR)
293 		port->ignore_status_mask |= RXSTAT_FRAME | RXSTAT_PARITY;
294 	if (termios->c_iflag & IGNBRK && termios->c_iflag & IGNPAR)
295 		port->ignore_status_mask |= RXSTAT_OVERRUN;
296 
297 	/*
298 	 * Ignore all characters if CREAD is not set.
299 	 */
300 	if ((termios->c_cflag & CREAD) == 0)
301 		port->ignore_status_mask |= RXSTAT_DUMMY_READ;
302 
303 	quot -= 1;
304 
305 	*CSR_UARTCON = 0;
306 	*CSR_L_UBRLCR = quot & 0xff;
307 	*CSR_M_UBRLCR = (quot >> 8) & 0x0f;
308 	*CSR_H_UBRLCR = h_lcr;
309 	*CSR_UARTCON = 1;
310 
311 	spin_unlock_irqrestore(&port->lock, flags);
312 }
313 
314 static const char *serial21285_type(struct uart_port *port)
315 {
316 	return port->type == PORT_21285 ? "DC21285" : NULL;
317 }
318 
319 static void serial21285_release_port(struct uart_port *port)
320 {
321 	release_mem_region(port->mapbase, 32);
322 }
323 
324 static int serial21285_request_port(struct uart_port *port)
325 {
326 	return request_mem_region(port->mapbase, 32, serial21285_name)
327 			 != NULL ? 0 : -EBUSY;
328 }
329 
330 static void serial21285_config_port(struct uart_port *port, int flags)
331 {
332 	if (flags & UART_CONFIG_TYPE && serial21285_request_port(port) == 0)
333 		port->type = PORT_21285;
334 }
335 
336 /*
337  * verify the new serial_struct (for TIOCSSERIAL).
338  */
339 static int serial21285_verify_port(struct uart_port *port, struct serial_struct *ser)
340 {
341 	int ret = 0;
342 	if (ser->type != PORT_UNKNOWN && ser->type != PORT_21285)
343 		ret = -EINVAL;
344 	if (ser->irq <= 0)
345 		ret = -EINVAL;
346 	if (ser->baud_base != port->uartclk / 16)
347 		ret = -EINVAL;
348 	return ret;
349 }
350 
351 static const struct uart_ops serial21285_ops = {
352 	.tx_empty	= serial21285_tx_empty,
353 	.get_mctrl	= serial21285_get_mctrl,
354 	.set_mctrl	= serial21285_set_mctrl,
355 	.stop_tx	= serial21285_stop_tx,
356 	.start_tx	= serial21285_start_tx,
357 	.stop_rx	= serial21285_stop_rx,
358 	.break_ctl	= serial21285_break_ctl,
359 	.startup	= serial21285_startup,
360 	.shutdown	= serial21285_shutdown,
361 	.set_termios	= serial21285_set_termios,
362 	.type		= serial21285_type,
363 	.release_port	= serial21285_release_port,
364 	.request_port	= serial21285_request_port,
365 	.config_port	= serial21285_config_port,
366 	.verify_port	= serial21285_verify_port,
367 };
368 
369 static struct uart_port serial21285_port = {
370 	.mapbase	= 0x42000160,
371 	.iotype		= UPIO_MEM,
372 	.irq		= 0,
373 	.fifosize	= 16,
374 	.ops		= &serial21285_ops,
375 	.flags		= UPF_BOOT_AUTOCONF,
376 };
377 
378 static void serial21285_setup_ports(void)
379 {
380 	serial21285_port.uartclk = mem_fclk_21285 / 4;
381 }
382 
383 #ifdef CONFIG_SERIAL_21285_CONSOLE
384 static void serial21285_console_putchar(struct uart_port *port, unsigned char ch)
385 {
386 	while (*CSR_UARTFLG & 0x20)
387 		barrier();
388 	*CSR_UARTDR = ch;
389 }
390 
391 static void
392 serial21285_console_write(struct console *co, const char *s,
393 			  unsigned int count)
394 {
395 	uart_console_write(&serial21285_port, s, count, serial21285_console_putchar);
396 }
397 
398 static void __init
399 serial21285_get_options(struct uart_port *port, int *baud,
400 			int *parity, int *bits)
401 {
402 	if (*CSR_UARTCON == 1) {
403 		unsigned int tmp;
404 
405 		tmp = *CSR_H_UBRLCR;
406 		switch (tmp & 0x60) {
407 		case 0x00:
408 			*bits = 5;
409 			break;
410 		case 0x20:
411 			*bits = 6;
412 			break;
413 		case 0x40:
414 			*bits = 7;
415 			break;
416 		default:
417 		case 0x60:
418 			*bits = 8;
419 			break;
420 		}
421 
422 		if (tmp & H_UBRLCR_PARENB) {
423 			*parity = 'o';
424 			if (tmp & H_UBRLCR_PAREVN)
425 				*parity = 'e';
426 		}
427 
428 		tmp = *CSR_L_UBRLCR | (*CSR_M_UBRLCR << 8);
429 
430 		*baud = port->uartclk / (16 * (tmp + 1));
431 	}
432 }
433 
434 static int __init serial21285_console_setup(struct console *co, char *options)
435 {
436 	struct uart_port *port = &serial21285_port;
437 	int baud = 9600;
438 	int bits = 8;
439 	int parity = 'n';
440 	int flow = 'n';
441 
442 	/*
443 	 * Check whether an invalid uart number has been specified, and
444 	 * if so, search for the first available port that does have
445 	 * console support.
446 	 */
447 	if (options)
448 		uart_parse_options(options, &baud, &parity, &bits, &flow);
449 	else
450 		serial21285_get_options(port, &baud, &parity, &bits);
451 
452 	return uart_set_options(port, co, baud, parity, bits, flow);
453 }
454 
455 static struct uart_driver serial21285_reg;
456 
457 static struct console serial21285_console =
458 {
459 	.name		= SERIAL_21285_NAME,
460 	.write		= serial21285_console_write,
461 	.device		= uart_console_device,
462 	.setup		= serial21285_console_setup,
463 	.flags		= CON_PRINTBUFFER,
464 	.index		= -1,
465 	.data		= &serial21285_reg,
466 };
467 
468 static int __init rs285_console_init(void)
469 {
470 	serial21285_setup_ports();
471 	register_console(&serial21285_console);
472 	return 0;
473 }
474 console_initcall(rs285_console_init);
475 
476 #define SERIAL_21285_CONSOLE	&serial21285_console
477 #else
478 #define SERIAL_21285_CONSOLE	NULL
479 #endif
480 
481 static struct uart_driver serial21285_reg = {
482 	.owner			= THIS_MODULE,
483 	.driver_name		= "ttyFB",
484 	.dev_name		= "ttyFB",
485 	.major			= SERIAL_21285_MAJOR,
486 	.minor			= SERIAL_21285_MINOR,
487 	.nr			= 1,
488 	.cons			= SERIAL_21285_CONSOLE,
489 };
490 
491 static int __init serial21285_init(void)
492 {
493 	int ret;
494 
495 	printk(KERN_INFO "Serial: 21285 driver\n");
496 
497 	serial21285_setup_ports();
498 
499 	ret = uart_register_driver(&serial21285_reg);
500 	if (ret == 0)
501 		uart_add_one_port(&serial21285_reg, &serial21285_port);
502 
503 	return ret;
504 }
505 
506 static void __exit serial21285_exit(void)
507 {
508 	uart_remove_one_port(&serial21285_reg, &serial21285_port);
509 	uart_unregister_driver(&serial21285_reg);
510 }
511 
512 module_init(serial21285_init);
513 module_exit(serial21285_exit);
514 
515 MODULE_LICENSE("GPL");
516 MODULE_DESCRIPTION("Intel Footbridge (21285) serial driver");
517 MODULE_ALIAS_CHARDEV(SERIAL_21285_MAJOR, SERIAL_21285_MINOR);
518