1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * mxser.c -- MOXA Smartio/Industio family multiport serial driver. 4 * 5 * Copyright (C) 1999-2006 Moxa Technologies (support@moxa.com). 6 * Copyright (C) 2006-2008 Jiri Slaby <jirislaby@gmail.com> 7 * 8 * This code is loosely based on the 1.8 moxa driver which is based on 9 * Linux serial driver, written by Linus Torvalds, Theodore T'so and 10 * others. 11 * 12 * Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox 13 * <alan@lxorguk.ukuu.org.uk>. The original 1.8 code is available on 14 * www.moxa.com. 15 * - Fixed x86_64 cleanness 16 */ 17 18 #include <linux/module.h> 19 #include <linux/errno.h> 20 #include <linux/signal.h> 21 #include <linux/sched.h> 22 #include <linux/timer.h> 23 #include <linux/interrupt.h> 24 #include <linux/tty.h> 25 #include <linux/tty_flip.h> 26 #include <linux/serial.h> 27 #include <linux/serial_reg.h> 28 #include <linux/major.h> 29 #include <linux/string.h> 30 #include <linux/fcntl.h> 31 #include <linux/ptrace.h> 32 #include <linux/ioport.h> 33 #include <linux/mm.h> 34 #include <linux/delay.h> 35 #include <linux/pci.h> 36 #include <linux/bitops.h> 37 #include <linux/slab.h> 38 #include <linux/ratelimit.h> 39 40 #include <asm/io.h> 41 #include <asm/irq.h> 42 #include <linux/uaccess.h> 43 44 /* 45 * Semi-public control interfaces 46 */ 47 48 /* 49 * MOXA ioctls 50 */ 51 52 #define MOXA 0x400 53 #define MOXA_SET_OP_MODE (MOXA + 66) 54 #define MOXA_GET_OP_MODE (MOXA + 67) 55 56 #define RS232_MODE 0 57 #define RS485_2WIRE_MODE 1 58 #define RS422_MODE 2 59 #define RS485_4WIRE_MODE 3 60 #define OP_MODE_MASK 3 61 62 /* --------------------------------------------------- */ 63 64 /* 65 * Follow just what Moxa Must chip defines. 66 * 67 * When LCR register (offset 0x03) is written the following value, the Must chip 68 * will enter enhanced mode. And a write to EFR (offset 0x02) bit 6,7 will 69 * change bank. 70 */ 71 #define MOXA_MUST_ENTER_ENHANCED 0xBF 72 73 /* when enhanced mode is enabled, access to general bank register */ 74 #define MOXA_MUST_GDL_REGISTER 0x07 75 #define MOXA_MUST_GDL_MASK 0x7F 76 #define MOXA_MUST_GDL_HAS_BAD_DATA 0x80 77 78 #define MOXA_MUST_LSR_RERR 0x80 /* error in receive FIFO */ 79 /* enhanced register bank select and enhanced mode setting register */ 80 /* This works only when LCR register equals to 0xBF */ 81 #define MOXA_MUST_EFR_REGISTER 0x02 82 #define MOXA_MUST_EFR_EFRB_ENABLE 0x10 /* enhanced mode enable */ 83 /* enhanced register bank set 0, 1, 2 */ 84 #define MOXA_MUST_EFR_BANK0 0x00 85 #define MOXA_MUST_EFR_BANK1 0x40 86 #define MOXA_MUST_EFR_BANK2 0x80 87 #define MOXA_MUST_EFR_BANK3 0xC0 88 #define MOXA_MUST_EFR_BANK_MASK 0xC0 89 90 /* set XON1 value register, when LCR=0xBF and change to bank0 */ 91 #define MOXA_MUST_XON1_REGISTER 0x04 92 93 /* set XON2 value register, when LCR=0xBF and change to bank0 */ 94 #define MOXA_MUST_XON2_REGISTER 0x05 95 96 /* set XOFF1 value register, when LCR=0xBF and change to bank0 */ 97 #define MOXA_MUST_XOFF1_REGISTER 0x06 98 99 /* set XOFF2 value register, when LCR=0xBF and change to bank0 */ 100 #define MOXA_MUST_XOFF2_REGISTER 0x07 101 102 #define MOXA_MUST_RBRTL_REGISTER 0x04 103 #define MOXA_MUST_RBRTH_REGISTER 0x05 104 #define MOXA_MUST_RBRTI_REGISTER 0x06 105 #define MOXA_MUST_THRTL_REGISTER 0x07 106 #define MOXA_MUST_ENUM_REGISTER 0x04 107 #define MOXA_MUST_HWID_REGISTER 0x05 108 #define MOXA_MUST_ECR_REGISTER 0x06 109 #define MOXA_MUST_CSR_REGISTER 0x07 110 111 #define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20 /* good data mode enable */ 112 #define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10 /* only good data put into RxFIFO */ 113 114 #define MOXA_MUST_IER_ECTSI 0x80 /* enable CTS interrupt */ 115 #define MOXA_MUST_IER_ERTSI 0x40 /* enable RTS interrupt */ 116 #define MOXA_MUST_IER_XINT 0x20 /* enable Xon/Xoff interrupt */ 117 #define MOXA_MUST_IER_EGDAI 0x10 /* enable GDA interrupt */ 118 119 #define MOXA_MUST_RECV_ISR (UART_IER_RDI | MOXA_MUST_IER_EGDAI) 120 121 /* GDA interrupt pending */ 122 #define MOXA_MUST_IIR_GDA 0x1C 123 #define MOXA_MUST_IIR_RDA 0x04 124 #define MOXA_MUST_IIR_RTO 0x0C 125 #define MOXA_MUST_IIR_LSR 0x06 126 127 /* received Xon/Xoff or specical interrupt pending */ 128 #define MOXA_MUST_IIR_XSC 0x10 129 130 /* RTS/CTS change state interrupt pending */ 131 #define MOXA_MUST_IIR_RTSCTS 0x20 132 #define MOXA_MUST_IIR_MASK 0x3E 133 134 #define MOXA_MUST_MCR_XON_FLAG 0x40 135 #define MOXA_MUST_MCR_XON_ANY 0x80 136 #define MOXA_MUST_MCR_TX_XON 0x08 137 138 #define MOXA_MUST_EFR_SF_MASK 0x0F /* software flow control on chip mask value */ 139 #define MOXA_MUST_EFR_SF_TX1 0x08 /* send Xon1/Xoff1 */ 140 #define MOXA_MUST_EFR_SF_TX2 0x04 /* send Xon2/Xoff2 */ 141 #define MOXA_MUST_EFR_SF_TX12 0x0C /* send Xon1,Xon2/Xoff1,Xoff2 */ 142 #define MOXA_MUST_EFR_SF_TX_NO 0x00 /* don't send Xon/Xoff */ 143 #define MOXA_MUST_EFR_SF_TX_MASK 0x0C /* Tx software flow control mask */ 144 #define MOXA_MUST_EFR_SF_RX_NO 0x00 /* don't receive Xon/Xoff */ 145 #define MOXA_MUST_EFR_SF_RX1 0x02 /* receive Xon1/Xoff1 */ 146 #define MOXA_MUST_EFR_SF_RX2 0x01 /* receive Xon2/Xoff2 */ 147 #define MOXA_MUST_EFR_SF_RX12 0x03 /* receive Xon1,Xon2/Xoff1,Xoff2 */ 148 #define MOXA_MUST_EFR_SF_RX_MASK 0x03 /* Rx software flow control mask */ 149 150 #define MXSERMAJOR 174 151 152 #define MXSER_BOARDS 4 /* Max. boards */ 153 #define MXSER_PORTS_PER_BOARD 8 /* Max. ports per board */ 154 #define MXSER_PORTS (MXSER_BOARDS * MXSER_PORTS_PER_BOARD) 155 #define MXSER_ISR_PASS_LIMIT 100 156 157 #define WAKEUP_CHARS 256 158 159 #define MXSER_BAUD_BASE 921600 160 #define MXSER_CUSTOM_DIVISOR (MXSER_BAUD_BASE * 16) 161 162 #define PCI_DEVICE_ID_MOXA_RC7000 0x0001 163 #define PCI_DEVICE_ID_MOXA_CP102 0x1020 164 #define PCI_DEVICE_ID_MOXA_CP102UL 0x1021 165 #define PCI_DEVICE_ID_MOXA_CP102U 0x1022 166 #define PCI_DEVICE_ID_MOXA_CP102UF 0x1023 167 #define PCI_DEVICE_ID_MOXA_C104 0x1040 168 #define PCI_DEVICE_ID_MOXA_CP104U 0x1041 169 #define PCI_DEVICE_ID_MOXA_CP104JU 0x1042 170 #define PCI_DEVICE_ID_MOXA_CP104EL 0x1043 171 #define PCI_DEVICE_ID_MOXA_POS104UL 0x1044 172 #define PCI_DEVICE_ID_MOXA_CB108 0x1080 173 #define PCI_DEVICE_ID_MOXA_CP112UL 0x1120 174 #define PCI_DEVICE_ID_MOXA_CT114 0x1140 175 #define PCI_DEVICE_ID_MOXA_CP114 0x1141 176 #define PCI_DEVICE_ID_MOXA_CB114 0x1142 177 #define PCI_DEVICE_ID_MOXA_CP114UL 0x1143 178 #define PCI_DEVICE_ID_MOXA_CP118U 0x1180 179 #define PCI_DEVICE_ID_MOXA_CP118EL 0x1181 180 #define PCI_DEVICE_ID_MOXA_CP132 0x1320 181 #define PCI_DEVICE_ID_MOXA_CP132U 0x1321 182 #define PCI_DEVICE_ID_MOXA_CP134U 0x1340 183 #define PCI_DEVICE_ID_MOXA_CB134I 0x1341 184 #define PCI_DEVICE_ID_MOXA_CP138U 0x1380 185 #define PCI_DEVICE_ID_MOXA_C168 0x1680 186 #define PCI_DEVICE_ID_MOXA_CP168U 0x1681 187 #define PCI_DEVICE_ID_MOXA_CP168EL 0x1682 188 189 #define MXSER_NPORTS(ddata) ((ddata) & 0xffU) 190 #define MXSER_HIGHBAUD 0x0100 191 192 enum mxser_must_hwid { 193 MOXA_OTHER_UART = 0x00, 194 MOXA_MUST_MU150_HWID = 0x01, 195 MOXA_MUST_MU860_HWID = 0x02, 196 }; 197 198 static const struct { 199 u8 type; 200 u8 fifo_size; 201 u8 rx_high_water; 202 u8 rx_low_water; 203 speed_t max_baud; 204 } Gpci_uart_info[] = { 205 { MOXA_OTHER_UART, 16, 14, 1, 921600 }, 206 { MOXA_MUST_MU150_HWID, 64, 48, 16, 230400 }, 207 { MOXA_MUST_MU860_HWID, 128, 96, 32, 921600 } 208 }; 209 #define UART_INFO_NUM ARRAY_SIZE(Gpci_uart_info) 210 211 212 /* driver_data correspond to the lines in the structure above 213 see also ISA probe function before you change something */ 214 static const struct pci_device_id mxser_pcibrds[] = { 215 { PCI_DEVICE_DATA(MOXA, C168, 8) }, 216 { PCI_DEVICE_DATA(MOXA, C104, 4) }, 217 { PCI_DEVICE_DATA(MOXA, CP132, 2) }, 218 { PCI_DEVICE_DATA(MOXA, CP114, 4) }, 219 { PCI_DEVICE_DATA(MOXA, CT114, 4) }, 220 { PCI_DEVICE_DATA(MOXA, CP102, 2 | MXSER_HIGHBAUD) }, 221 { PCI_DEVICE_DATA(MOXA, CP104U, 4) }, 222 { PCI_DEVICE_DATA(MOXA, CP168U, 8) }, 223 { PCI_DEVICE_DATA(MOXA, CP132U, 2) }, 224 { PCI_DEVICE_DATA(MOXA, CP134U, 4) }, 225 { PCI_DEVICE_DATA(MOXA, CP104JU, 4) }, 226 { PCI_DEVICE_DATA(MOXA, RC7000, 8) }, /* RC7000 */ 227 { PCI_DEVICE_DATA(MOXA, CP118U, 8) }, 228 { PCI_DEVICE_DATA(MOXA, CP102UL, 2) }, 229 { PCI_DEVICE_DATA(MOXA, CP102U, 2) }, 230 { PCI_DEVICE_DATA(MOXA, CP118EL, 8) }, 231 { PCI_DEVICE_DATA(MOXA, CP168EL, 8) }, 232 { PCI_DEVICE_DATA(MOXA, CP104EL, 4) }, 233 { PCI_DEVICE_DATA(MOXA, CB108, 8) }, 234 { PCI_DEVICE_DATA(MOXA, CB114, 4) }, 235 { PCI_DEVICE_DATA(MOXA, CB134I, 4) }, 236 { PCI_DEVICE_DATA(MOXA, CP138U, 8) }, 237 { PCI_DEVICE_DATA(MOXA, POS104UL, 4) }, 238 { PCI_DEVICE_DATA(MOXA, CP114UL, 4) }, 239 { PCI_DEVICE_DATA(MOXA, CP102UF, 2) }, 240 { PCI_DEVICE_DATA(MOXA, CP112UL, 2) }, 241 { } 242 }; 243 MODULE_DEVICE_TABLE(pci, mxser_pcibrds); 244 245 static int ttymajor = MXSERMAJOR; 246 247 /* Variables for insmod */ 248 249 MODULE_AUTHOR("Casper Yang"); 250 MODULE_DESCRIPTION("MOXA Smartio/Industio Family Multiport Board Device Driver"); 251 module_param(ttymajor, int, 0); 252 MODULE_LICENSE("GPL"); 253 254 struct mxser_board; 255 256 struct mxser_port { 257 struct tty_port port; 258 struct mxser_board *board; 259 260 unsigned long ioaddr; 261 unsigned long opmode_ioaddr; 262 263 u8 rx_high_water; 264 u8 rx_low_water; 265 int type; /* UART type */ 266 267 unsigned char x_char; /* xon/xoff character */ 268 u8 IER; /* Interrupt Enable Register */ 269 u8 MCR; /* Modem control register */ 270 u8 FCR; /* FIFO control register */ 271 272 struct async_icount icount; /* kernel counters for 4 input interrupts */ 273 unsigned int timeout; 274 275 u8 read_status_mask; 276 u8 ignore_status_mask; 277 u8 xmit_fifo_size; 278 279 spinlock_t slock; 280 }; 281 282 struct mxser_board { 283 unsigned int idx; 284 unsigned short nports; 285 int irq; 286 unsigned long vector; 287 288 enum mxser_must_hwid must_hwid; 289 speed_t max_baud; 290 291 struct mxser_port ports[]; 292 }; 293 294 static DECLARE_BITMAP(mxser_boards, MXSER_BOARDS); 295 static struct tty_driver *mxvar_sdriver; 296 297 static u8 __mxser_must_set_EFR(unsigned long baseio, u8 clear, u8 set, 298 bool restore_LCR) 299 { 300 u8 oldlcr, efr; 301 302 oldlcr = inb(baseio + UART_LCR); 303 outb(MOXA_MUST_ENTER_ENHANCED, baseio + UART_LCR); 304 305 efr = inb(baseio + MOXA_MUST_EFR_REGISTER); 306 efr &= ~clear; 307 efr |= set; 308 309 outb(efr, baseio + MOXA_MUST_EFR_REGISTER); 310 311 if (restore_LCR) 312 outb(oldlcr, baseio + UART_LCR); 313 314 return oldlcr; 315 } 316 317 static u8 mxser_must_select_bank(unsigned long baseio, u8 bank) 318 { 319 return __mxser_must_set_EFR(baseio, MOXA_MUST_EFR_BANK_MASK, bank, 320 false); 321 } 322 323 static void mxser_set_must_xon1_value(unsigned long baseio, u8 value) 324 { 325 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK0); 326 outb(value, baseio + MOXA_MUST_XON1_REGISTER); 327 outb(oldlcr, baseio + UART_LCR); 328 } 329 330 static void mxser_set_must_xoff1_value(unsigned long baseio, u8 value) 331 { 332 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK0); 333 outb(value, baseio + MOXA_MUST_XOFF1_REGISTER); 334 outb(oldlcr, baseio + UART_LCR); 335 } 336 337 static void mxser_set_must_fifo_value(struct mxser_port *info) 338 { 339 u8 oldlcr = mxser_must_select_bank(info->ioaddr, MOXA_MUST_EFR_BANK1); 340 outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTH_REGISTER); 341 outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTI_REGISTER); 342 outb(info->rx_low_water, info->ioaddr + MOXA_MUST_RBRTL_REGISTER); 343 outb(oldlcr, info->ioaddr + UART_LCR); 344 } 345 346 static void mxser_set_must_enum_value(unsigned long baseio, u8 value) 347 { 348 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK2); 349 outb(value, baseio + MOXA_MUST_ENUM_REGISTER); 350 outb(oldlcr, baseio + UART_LCR); 351 } 352 353 static u8 mxser_get_must_hardware_id(unsigned long baseio) 354 { 355 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK2); 356 u8 id = inb(baseio + MOXA_MUST_HWID_REGISTER); 357 outb(oldlcr, baseio + UART_LCR); 358 359 return id; 360 } 361 362 static void mxser_must_set_EFR(unsigned long baseio, u8 clear, u8 set) 363 { 364 __mxser_must_set_EFR(baseio, clear, set, true); 365 } 366 367 static void mxser_must_set_enhance_mode(unsigned long baseio, bool enable) 368 { 369 mxser_must_set_EFR(baseio, 370 enable ? 0 : MOXA_MUST_EFR_EFRB_ENABLE, 371 enable ? MOXA_MUST_EFR_EFRB_ENABLE : 0); 372 } 373 374 static void mxser_must_no_sw_flow_control(unsigned long baseio) 375 { 376 mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_MASK, 0); 377 } 378 379 static void mxser_must_set_tx_sw_flow_control(unsigned long baseio, bool enable) 380 { 381 mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_TX_MASK, 382 enable ? MOXA_MUST_EFR_SF_TX1 : 0); 383 } 384 385 static void mxser_must_set_rx_sw_flow_control(unsigned long baseio, bool enable) 386 { 387 mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_RX_MASK, 388 enable ? MOXA_MUST_EFR_SF_RX1 : 0); 389 } 390 391 static enum mxser_must_hwid mxser_must_get_hwid(unsigned long io) 392 { 393 u8 oldmcr, hwid; 394 int i; 395 396 outb(0, io + UART_LCR); 397 mxser_must_set_enhance_mode(io, false); 398 oldmcr = inb(io + UART_MCR); 399 outb(0, io + UART_MCR); 400 mxser_set_must_xon1_value(io, 0x11); 401 if ((hwid = inb(io + UART_MCR)) != 0) { 402 outb(oldmcr, io + UART_MCR); 403 return MOXA_OTHER_UART; 404 } 405 406 hwid = mxser_get_must_hardware_id(io); 407 for (i = 1; i < UART_INFO_NUM; i++) /* 0 = OTHER_UART */ 408 if (hwid == Gpci_uart_info[i].type) 409 return hwid; 410 411 return MOXA_OTHER_UART; 412 } 413 414 static bool mxser_16550A_or_MUST(struct mxser_port *info) 415 { 416 return info->type == PORT_16550A || info->board->must_hwid; 417 } 418 419 static void mxser_process_txrx_fifo(struct mxser_port *info) 420 { 421 unsigned int i; 422 423 if (info->type == PORT_16450 || info->type == PORT_8250) { 424 info->rx_high_water = 1; 425 info->rx_low_water = 1; 426 info->xmit_fifo_size = 1; 427 return; 428 } 429 430 for (i = 0; i < UART_INFO_NUM; i++) 431 if (info->board->must_hwid == Gpci_uart_info[i].type) { 432 info->rx_low_water = Gpci_uart_info[i].rx_low_water; 433 info->rx_high_water = Gpci_uart_info[i].rx_high_water; 434 info->xmit_fifo_size = Gpci_uart_info[i].fifo_size; 435 break; 436 } 437 } 438 439 static void __mxser_start_tx(struct mxser_port *info) 440 { 441 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER); 442 info->IER |= UART_IER_THRI; 443 outb(info->IER, info->ioaddr + UART_IER); 444 } 445 446 static void mxser_start_tx(struct mxser_port *info) 447 { 448 unsigned long flags; 449 450 spin_lock_irqsave(&info->slock, flags); 451 __mxser_start_tx(info); 452 spin_unlock_irqrestore(&info->slock, flags); 453 } 454 455 static void __mxser_stop_tx(struct mxser_port *info) 456 { 457 info->IER &= ~UART_IER_THRI; 458 outb(info->IER, info->ioaddr + UART_IER); 459 } 460 461 static int mxser_carrier_raised(struct tty_port *port) 462 { 463 struct mxser_port *mp = container_of(port, struct mxser_port, port); 464 return (inb(mp->ioaddr + UART_MSR) & UART_MSR_DCD)?1:0; 465 } 466 467 static void mxser_dtr_rts(struct tty_port *port, int on) 468 { 469 struct mxser_port *mp = container_of(port, struct mxser_port, port); 470 unsigned long flags; 471 u8 mcr; 472 473 spin_lock_irqsave(&mp->slock, flags); 474 mcr = inb(mp->ioaddr + UART_MCR); 475 if (on) 476 mcr |= UART_MCR_DTR | UART_MCR_RTS; 477 else 478 mcr &= ~(UART_MCR_DTR | UART_MCR_RTS); 479 outb(mcr, mp->ioaddr + UART_MCR); 480 spin_unlock_irqrestore(&mp->slock, flags); 481 } 482 483 static int mxser_set_baud(struct tty_struct *tty, speed_t newspd) 484 { 485 struct mxser_port *info = tty->driver_data; 486 unsigned int quot = 0, baud; 487 unsigned char cval; 488 u64 timeout; 489 490 if (newspd > info->board->max_baud) 491 return -1; 492 493 if (newspd == 134) { 494 quot = 2 * MXSER_BAUD_BASE / 269; 495 tty_encode_baud_rate(tty, 134, 134); 496 } else if (newspd) { 497 quot = MXSER_BAUD_BASE / newspd; 498 if (quot == 0) 499 quot = 1; 500 baud = MXSER_BAUD_BASE / quot; 501 tty_encode_baud_rate(tty, baud, baud); 502 } else { 503 quot = 0; 504 } 505 506 /* 507 * worst case (128 * 1000 * 10 * 18432) needs 35 bits, so divide in the 508 * u64 domain 509 */ 510 timeout = (u64)info->xmit_fifo_size * HZ * 10 * quot; 511 do_div(timeout, MXSER_BAUD_BASE); 512 info->timeout = timeout + HZ / 50; /* Add .02 seconds of slop */ 513 514 if (quot) { 515 info->MCR |= UART_MCR_DTR; 516 outb(info->MCR, info->ioaddr + UART_MCR); 517 } else { 518 info->MCR &= ~UART_MCR_DTR; 519 outb(info->MCR, info->ioaddr + UART_MCR); 520 return 0; 521 } 522 523 cval = inb(info->ioaddr + UART_LCR); 524 525 outb(cval | UART_LCR_DLAB, info->ioaddr + UART_LCR); /* set DLAB */ 526 527 outb(quot & 0xff, info->ioaddr + UART_DLL); /* LS of divisor */ 528 outb(quot >> 8, info->ioaddr + UART_DLM); /* MS of divisor */ 529 outb(cval, info->ioaddr + UART_LCR); /* reset DLAB */ 530 531 if (C_BAUD(tty) == BOTHER) { 532 quot = MXSER_BAUD_BASE % newspd; 533 quot *= 8; 534 if (quot % newspd > newspd / 2) { 535 quot /= newspd; 536 quot++; 537 } else 538 quot /= newspd; 539 540 mxser_set_must_enum_value(info->ioaddr, quot); 541 } else { 542 mxser_set_must_enum_value(info->ioaddr, 0); 543 } 544 545 return 0; 546 } 547 548 static void mxser_handle_cts(struct tty_struct *tty, struct mxser_port *info, 549 u8 msr) 550 { 551 bool cts = msr & UART_MSR_CTS; 552 553 if (tty->hw_stopped) { 554 if (cts) { 555 tty->hw_stopped = 0; 556 557 if (!mxser_16550A_or_MUST(info)) 558 __mxser_start_tx(info); 559 tty_wakeup(tty); 560 } 561 return; 562 } else if (cts) 563 return; 564 565 tty->hw_stopped = 1; 566 if (!mxser_16550A_or_MUST(info)) 567 __mxser_stop_tx(info); 568 } 569 570 /* 571 * This routine is called to set the UART divisor registers to match 572 * the specified baud rate for a serial port. 573 */ 574 static void mxser_change_speed(struct tty_struct *tty, struct ktermios *old_termios) 575 { 576 struct mxser_port *info = tty->driver_data; 577 unsigned cflag, cval; 578 579 cflag = tty->termios.c_cflag; 580 581 if (mxser_set_baud(tty, tty_get_baud_rate(tty))) { 582 /* Use previous rate on a failure */ 583 if (old_termios) { 584 speed_t baud = tty_termios_baud_rate(old_termios); 585 tty_encode_baud_rate(tty, baud, baud); 586 } 587 } 588 589 /* byte size and parity */ 590 cval = UART_LCR_WLEN(tty_get_char_size(tty->termios.c_cflag)); 591 592 if (cflag & CSTOPB) 593 cval |= UART_LCR_STOP; 594 if (cflag & PARENB) 595 cval |= UART_LCR_PARITY; 596 if (!(cflag & PARODD)) 597 cval |= UART_LCR_EPAR; 598 if (cflag & CMSPAR) 599 cval |= UART_LCR_SPAR; 600 601 info->FCR = 0; 602 if (info->board->must_hwid) { 603 info->FCR |= UART_FCR_ENABLE_FIFO | 604 MOXA_MUST_FCR_GDA_MODE_ENABLE; 605 mxser_set_must_fifo_value(info); 606 } else if (info->type != PORT_8250 && info->type != PORT_16450) { 607 info->FCR |= UART_FCR_ENABLE_FIFO; 608 switch (info->rx_high_water) { 609 case 1: 610 info->FCR |= UART_FCR_TRIGGER_1; 611 break; 612 case 4: 613 info->FCR |= UART_FCR_TRIGGER_4; 614 break; 615 case 8: 616 info->FCR |= UART_FCR_TRIGGER_8; 617 break; 618 default: 619 info->FCR |= UART_FCR_TRIGGER_14; 620 break; 621 } 622 } 623 624 /* CTS flow control flag and modem status interrupts */ 625 info->IER &= ~UART_IER_MSI; 626 info->MCR &= ~UART_MCR_AFE; 627 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS); 628 if (cflag & CRTSCTS) { 629 info->IER |= UART_IER_MSI; 630 if (mxser_16550A_or_MUST(info)) { 631 info->MCR |= UART_MCR_AFE; 632 } else { 633 mxser_handle_cts(tty, info, 634 inb(info->ioaddr + UART_MSR)); 635 } 636 } 637 outb(info->MCR, info->ioaddr + UART_MCR); 638 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL); 639 if (~cflag & CLOCAL) 640 info->IER |= UART_IER_MSI; 641 outb(info->IER, info->ioaddr + UART_IER); 642 643 /* 644 * Set up parity check flag 645 */ 646 info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 647 if (I_INPCK(tty)) 648 info->read_status_mask |= UART_LSR_FE | UART_LSR_PE; 649 if (I_BRKINT(tty) || I_PARMRK(tty)) 650 info->read_status_mask |= UART_LSR_BI; 651 652 info->ignore_status_mask = 0; 653 654 if (I_IGNBRK(tty)) { 655 info->ignore_status_mask |= UART_LSR_BI; 656 info->read_status_mask |= UART_LSR_BI; 657 /* 658 * If we're ignore parity and break indicators, ignore 659 * overruns too. (For real raw support). 660 */ 661 if (I_IGNPAR(tty)) { 662 info->ignore_status_mask |= 663 UART_LSR_OE | 664 UART_LSR_PE | 665 UART_LSR_FE; 666 info->read_status_mask |= 667 UART_LSR_OE | 668 UART_LSR_PE | 669 UART_LSR_FE; 670 } 671 } 672 if (info->board->must_hwid) { 673 mxser_set_must_xon1_value(info->ioaddr, START_CHAR(tty)); 674 mxser_set_must_xoff1_value(info->ioaddr, STOP_CHAR(tty)); 675 mxser_must_set_rx_sw_flow_control(info->ioaddr, I_IXON(tty)); 676 mxser_must_set_tx_sw_flow_control(info->ioaddr, I_IXOFF(tty)); 677 } 678 679 680 outb(info->FCR, info->ioaddr + UART_FCR); 681 outb(cval, info->ioaddr + UART_LCR); 682 } 683 684 static u8 mxser_check_modem_status(struct tty_struct *tty, 685 struct mxser_port *port) 686 { 687 u8 msr = inb(port->ioaddr + UART_MSR); 688 689 if (!(msr & UART_MSR_ANY_DELTA)) 690 return msr; 691 692 /* update input line counters */ 693 if (msr & UART_MSR_TERI) 694 port->icount.rng++; 695 if (msr & UART_MSR_DDSR) 696 port->icount.dsr++; 697 if (msr & UART_MSR_DDCD) 698 port->icount.dcd++; 699 if (msr & UART_MSR_DCTS) 700 port->icount.cts++; 701 wake_up_interruptible(&port->port.delta_msr_wait); 702 703 if (tty_port_check_carrier(&port->port) && (msr & UART_MSR_DDCD)) { 704 if (msr & UART_MSR_DCD) 705 wake_up_interruptible(&port->port.open_wait); 706 } 707 708 if (tty_port_cts_enabled(&port->port)) 709 mxser_handle_cts(tty, port, msr); 710 711 return msr; 712 } 713 714 static void mxser_disable_and_clear_FIFO(struct mxser_port *info) 715 { 716 u8 fcr = UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT; 717 718 if (info->board->must_hwid) 719 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE; 720 721 outb(fcr, info->ioaddr + UART_FCR); 722 } 723 724 static int mxser_activate(struct tty_port *port, struct tty_struct *tty) 725 { 726 struct mxser_port *info = container_of(port, struct mxser_port, port); 727 unsigned long flags; 728 int ret; 729 730 ret = tty_port_alloc_xmit_buf(port); 731 if (ret < 0) 732 return ret; 733 734 spin_lock_irqsave(&info->slock, flags); 735 736 if (!info->type) { 737 set_bit(TTY_IO_ERROR, &tty->flags); 738 spin_unlock_irqrestore(&info->slock, flags); 739 ret = 0; 740 goto err_free_xmit; 741 } 742 743 /* 744 * Clear the FIFO buffers and disable them 745 * (they will be reenabled in mxser_change_speed()) 746 */ 747 mxser_disable_and_clear_FIFO(info); 748 749 /* 750 * At this point there's no way the LSR could still be 0xFF; 751 * if it is, then bail out, because there's likely no UART 752 * here. 753 */ 754 if (inb(info->ioaddr + UART_LSR) == 0xff) { 755 spin_unlock_irqrestore(&info->slock, flags); 756 if (capable(CAP_SYS_ADMIN)) { 757 set_bit(TTY_IO_ERROR, &tty->flags); 758 return 0; 759 } 760 761 ret = -ENODEV; 762 goto err_free_xmit; 763 } 764 765 /* 766 * Clear the interrupt registers. 767 */ 768 (void) inb(info->ioaddr + UART_LSR); 769 (void) inb(info->ioaddr + UART_RX); 770 (void) inb(info->ioaddr + UART_IIR); 771 (void) inb(info->ioaddr + UART_MSR); 772 773 /* 774 * Now, initialize the UART 775 */ 776 outb(UART_LCR_WLEN8, info->ioaddr + UART_LCR); /* reset DLAB */ 777 info->MCR = UART_MCR_DTR | UART_MCR_RTS; 778 outb(info->MCR, info->ioaddr + UART_MCR); 779 780 /* 781 * Finally, enable interrupts 782 */ 783 info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI; 784 785 if (info->board->must_hwid) 786 info->IER |= MOXA_MUST_IER_EGDAI; 787 outb(info->IER, info->ioaddr + UART_IER); /* enable interrupts */ 788 789 /* 790 * And clear the interrupt registers again for luck. 791 */ 792 (void) inb(info->ioaddr + UART_LSR); 793 (void) inb(info->ioaddr + UART_RX); 794 (void) inb(info->ioaddr + UART_IIR); 795 (void) inb(info->ioaddr + UART_MSR); 796 797 clear_bit(TTY_IO_ERROR, &tty->flags); 798 kfifo_reset(&port->xmit_fifo); 799 800 /* 801 * and set the speed of the serial port 802 */ 803 mxser_change_speed(tty, NULL); 804 spin_unlock_irqrestore(&info->slock, flags); 805 806 return 0; 807 err_free_xmit: 808 tty_port_free_xmit_buf(port); 809 return ret; 810 } 811 812 /* 813 * To stop accepting input, we disable the receive line status interrupts, and 814 * tell the interrupt driver to stop checking the data ready bit in the line 815 * status register. 816 */ 817 static void mxser_stop_rx(struct mxser_port *info) 818 { 819 info->IER &= ~UART_IER_RLSI; 820 if (info->board->must_hwid) 821 info->IER &= ~MOXA_MUST_RECV_ISR; 822 823 outb(info->IER, info->ioaddr + UART_IER); 824 } 825 826 /* 827 * This routine will shutdown a serial port 828 */ 829 static void mxser_shutdown_port(struct tty_port *port) 830 { 831 struct mxser_port *info = container_of(port, struct mxser_port, port); 832 unsigned long flags; 833 834 spin_lock_irqsave(&info->slock, flags); 835 836 mxser_stop_rx(info); 837 838 /* 839 * clear delta_msr_wait queue to avoid mem leaks: we may free the irq 840 * here so the queue might never be waken up 841 */ 842 wake_up_interruptible(&info->port.delta_msr_wait); 843 844 info->IER = 0; 845 outb(0x00, info->ioaddr + UART_IER); 846 847 /* clear Rx/Tx FIFO's */ 848 mxser_disable_and_clear_FIFO(info); 849 850 /* read data port to reset things */ 851 (void) inb(info->ioaddr + UART_RX); 852 853 854 if (info->board->must_hwid) 855 mxser_must_no_sw_flow_control(info->ioaddr); 856 857 spin_unlock_irqrestore(&info->slock, flags); 858 859 /* make sure ISR is not running while we free the buffer */ 860 synchronize_irq(info->board->irq); 861 862 tty_port_free_xmit_buf(port); 863 } 864 865 /* 866 * This routine is called whenever a serial port is opened. It 867 * enables interrupts for a serial port, linking in its async structure into 868 * the IRQ chain. It also performs the serial-specific 869 * initialization for the tty structure. 870 */ 871 static int mxser_open(struct tty_struct *tty, struct file *filp) 872 { 873 struct tty_port *tport = tty->port; 874 struct mxser_port *port = container_of(tport, struct mxser_port, port); 875 876 tty->driver_data = port; 877 878 return tty_port_open(tport, tty, filp); 879 } 880 881 static void mxser_flush_buffer(struct tty_struct *tty) 882 { 883 struct mxser_port *info = tty->driver_data; 884 unsigned long flags; 885 886 spin_lock_irqsave(&info->slock, flags); 887 kfifo_reset(&info->port.xmit_fifo); 888 889 outb(info->FCR | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, 890 info->ioaddr + UART_FCR); 891 892 spin_unlock_irqrestore(&info->slock, flags); 893 894 tty_wakeup(tty); 895 } 896 897 static void mxser_close(struct tty_struct *tty, struct file *filp) 898 { 899 tty_port_close(tty->port, tty, filp); 900 } 901 902 static int mxser_write(struct tty_struct *tty, const unsigned char *buf, int count) 903 { 904 struct mxser_port *info = tty->driver_data; 905 unsigned long flags; 906 int written; 907 bool is_empty; 908 909 spin_lock_irqsave(&info->slock, flags); 910 written = kfifo_in(&info->port.xmit_fifo, buf, count); 911 is_empty = kfifo_is_empty(&info->port.xmit_fifo); 912 spin_unlock_irqrestore(&info->slock, flags); 913 914 if (!is_empty && !tty->flow.stopped) 915 if (!tty->hw_stopped || mxser_16550A_or_MUST(info)) 916 mxser_start_tx(info); 917 918 return written; 919 } 920 921 static int mxser_put_char(struct tty_struct *tty, unsigned char ch) 922 { 923 struct mxser_port *info = tty->driver_data; 924 unsigned long flags; 925 int ret; 926 927 spin_lock_irqsave(&info->slock, flags); 928 ret = kfifo_put(&info->port.xmit_fifo, ch); 929 spin_unlock_irqrestore(&info->slock, flags); 930 931 return ret; 932 } 933 934 935 static void mxser_flush_chars(struct tty_struct *tty) 936 { 937 struct mxser_port *info = tty->driver_data; 938 939 if (kfifo_is_empty(&info->port.xmit_fifo) || tty->flow.stopped || 940 (tty->hw_stopped && !mxser_16550A_or_MUST(info))) 941 return; 942 943 mxser_start_tx(info); 944 } 945 946 static unsigned int mxser_write_room(struct tty_struct *tty) 947 { 948 struct mxser_port *info = tty->driver_data; 949 950 return kfifo_avail(&info->port.xmit_fifo); 951 } 952 953 static unsigned int mxser_chars_in_buffer(struct tty_struct *tty) 954 { 955 struct mxser_port *info = tty->driver_data; 956 957 return kfifo_len(&info->port.xmit_fifo); 958 } 959 960 /* 961 * ------------------------------------------------------------ 962 * friends of mxser_ioctl() 963 * ------------------------------------------------------------ 964 */ 965 static int mxser_get_serial_info(struct tty_struct *tty, 966 struct serial_struct *ss) 967 { 968 struct mxser_port *info = tty->driver_data; 969 struct tty_port *port = &info->port; 970 unsigned int closing_wait, close_delay; 971 972 mutex_lock(&port->mutex); 973 974 close_delay = jiffies_to_msecs(info->port.close_delay) / 10; 975 closing_wait = info->port.closing_wait; 976 if (closing_wait != ASYNC_CLOSING_WAIT_NONE) 977 closing_wait = jiffies_to_msecs(closing_wait) / 10; 978 979 ss->type = info->type; 980 ss->line = tty->index; 981 ss->port = info->ioaddr; 982 ss->irq = info->board->irq; 983 ss->flags = info->port.flags; 984 ss->baud_base = MXSER_BAUD_BASE; 985 ss->close_delay = close_delay; 986 ss->closing_wait = closing_wait; 987 ss->custom_divisor = MXSER_CUSTOM_DIVISOR, 988 mutex_unlock(&port->mutex); 989 return 0; 990 } 991 992 static int mxser_set_serial_info(struct tty_struct *tty, 993 struct serial_struct *ss) 994 { 995 struct mxser_port *info = tty->driver_data; 996 struct tty_port *port = &info->port; 997 speed_t baud; 998 unsigned long sl_flags; 999 unsigned int old_speed, close_delay, closing_wait; 1000 int retval = 0; 1001 1002 if (tty_io_error(tty)) 1003 return -EIO; 1004 1005 mutex_lock(&port->mutex); 1006 1007 if (ss->irq != info->board->irq || 1008 ss->port != info->ioaddr) { 1009 mutex_unlock(&port->mutex); 1010 return -EINVAL; 1011 } 1012 1013 old_speed = port->flags & ASYNC_SPD_MASK; 1014 1015 close_delay = msecs_to_jiffies(ss->close_delay * 10); 1016 closing_wait = ss->closing_wait; 1017 if (closing_wait != ASYNC_CLOSING_WAIT_NONE) 1018 closing_wait = msecs_to_jiffies(closing_wait * 10); 1019 1020 if (!capable(CAP_SYS_ADMIN)) { 1021 if ((ss->baud_base != MXSER_BAUD_BASE) || 1022 (close_delay != port->close_delay) || 1023 (closing_wait != port->closing_wait) || 1024 ((ss->flags & ~ASYNC_USR_MASK) != (port->flags & ~ASYNC_USR_MASK))) { 1025 mutex_unlock(&port->mutex); 1026 return -EPERM; 1027 } 1028 port->flags = (port->flags & ~ASYNC_USR_MASK) | 1029 (ss->flags & ASYNC_USR_MASK); 1030 } else { 1031 /* 1032 * OK, past this point, all the error checking has been done. 1033 * At this point, we start making changes..... 1034 */ 1035 port->flags = ((port->flags & ~ASYNC_FLAGS) | 1036 (ss->flags & ASYNC_FLAGS)); 1037 port->close_delay = close_delay; 1038 port->closing_wait = closing_wait; 1039 if ((port->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST && 1040 (ss->baud_base != MXSER_BAUD_BASE || 1041 ss->custom_divisor != 1042 MXSER_CUSTOM_DIVISOR)) { 1043 if (ss->custom_divisor == 0) { 1044 mutex_unlock(&port->mutex); 1045 return -EINVAL; 1046 } 1047 baud = ss->baud_base / ss->custom_divisor; 1048 tty_encode_baud_rate(tty, baud, baud); 1049 } 1050 1051 info->type = ss->type; 1052 1053 mxser_process_txrx_fifo(info); 1054 } 1055 1056 if (tty_port_initialized(port)) { 1057 if (old_speed != (port->flags & ASYNC_SPD_MASK)) { 1058 spin_lock_irqsave(&info->slock, sl_flags); 1059 mxser_change_speed(tty, NULL); 1060 spin_unlock_irqrestore(&info->slock, sl_flags); 1061 } 1062 } else { 1063 retval = mxser_activate(port, tty); 1064 if (retval == 0) 1065 tty_port_set_initialized(port, 1); 1066 } 1067 mutex_unlock(&port->mutex); 1068 return retval; 1069 } 1070 1071 /* 1072 * mxser_get_lsr_info - get line status register info 1073 * 1074 * Purpose: Let user call ioctl() to get info when the UART physically 1075 * is emptied. On bus types like RS485, the transmitter must 1076 * release the bus after transmitting. This must be done when 1077 * the transmit shift register is empty, not be done when the 1078 * transmit holding register is empty. This functionality 1079 * allows an RS485 driver to be written in user space. 1080 */ 1081 static int mxser_get_lsr_info(struct mxser_port *info, 1082 unsigned int __user *value) 1083 { 1084 unsigned char status; 1085 unsigned int result; 1086 unsigned long flags; 1087 1088 spin_lock_irqsave(&info->slock, flags); 1089 status = inb(info->ioaddr + UART_LSR); 1090 spin_unlock_irqrestore(&info->slock, flags); 1091 result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0); 1092 return put_user(result, value); 1093 } 1094 1095 static int mxser_tiocmget(struct tty_struct *tty) 1096 { 1097 struct mxser_port *info = tty->driver_data; 1098 unsigned char control; 1099 unsigned long flags; 1100 u8 msr; 1101 1102 if (tty_io_error(tty)) 1103 return -EIO; 1104 1105 spin_lock_irqsave(&info->slock, flags); 1106 control = info->MCR; 1107 msr = mxser_check_modem_status(tty, info); 1108 spin_unlock_irqrestore(&info->slock, flags); 1109 1110 return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) | 1111 ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) | 1112 ((msr & UART_MSR_DCD) ? TIOCM_CAR : 0) | 1113 ((msr & UART_MSR_RI) ? TIOCM_RNG : 0) | 1114 ((msr & UART_MSR_DSR) ? TIOCM_DSR : 0) | 1115 ((msr & UART_MSR_CTS) ? TIOCM_CTS : 0); 1116 } 1117 1118 static int mxser_tiocmset(struct tty_struct *tty, 1119 unsigned int set, unsigned int clear) 1120 { 1121 struct mxser_port *info = tty->driver_data; 1122 unsigned long flags; 1123 1124 if (tty_io_error(tty)) 1125 return -EIO; 1126 1127 spin_lock_irqsave(&info->slock, flags); 1128 1129 if (set & TIOCM_RTS) 1130 info->MCR |= UART_MCR_RTS; 1131 if (set & TIOCM_DTR) 1132 info->MCR |= UART_MCR_DTR; 1133 1134 if (clear & TIOCM_RTS) 1135 info->MCR &= ~UART_MCR_RTS; 1136 if (clear & TIOCM_DTR) 1137 info->MCR &= ~UART_MCR_DTR; 1138 1139 outb(info->MCR, info->ioaddr + UART_MCR); 1140 spin_unlock_irqrestore(&info->slock, flags); 1141 return 0; 1142 } 1143 1144 static int mxser_cflags_changed(struct mxser_port *info, unsigned long arg, 1145 struct async_icount *cprev) 1146 { 1147 struct async_icount cnow; 1148 unsigned long flags; 1149 int ret; 1150 1151 spin_lock_irqsave(&info->slock, flags); 1152 cnow = info->icount; /* atomic copy */ 1153 spin_unlock_irqrestore(&info->slock, flags); 1154 1155 ret = ((arg & TIOCM_RNG) && (cnow.rng != cprev->rng)) || 1156 ((arg & TIOCM_DSR) && (cnow.dsr != cprev->dsr)) || 1157 ((arg & TIOCM_CD) && (cnow.dcd != cprev->dcd)) || 1158 ((arg & TIOCM_CTS) && (cnow.cts != cprev->cts)); 1159 1160 *cprev = cnow; 1161 1162 return ret; 1163 } 1164 1165 /* We should likely switch to TIOCGRS485/TIOCSRS485. */ 1166 static int mxser_ioctl_op_mode(struct mxser_port *port, int index, bool set, 1167 int __user *u_opmode) 1168 { 1169 int opmode, p = index % 4; 1170 int shiftbit = p * 2; 1171 u8 val; 1172 1173 if (port->board->must_hwid != MOXA_MUST_MU860_HWID) 1174 return -EFAULT; 1175 1176 if (set) { 1177 if (get_user(opmode, u_opmode)) 1178 return -EFAULT; 1179 1180 if (opmode & ~OP_MODE_MASK) 1181 return -EINVAL; 1182 1183 spin_lock_irq(&port->slock); 1184 val = inb(port->opmode_ioaddr); 1185 val &= ~(OP_MODE_MASK << shiftbit); 1186 val |= (opmode << shiftbit); 1187 outb(val, port->opmode_ioaddr); 1188 spin_unlock_irq(&port->slock); 1189 1190 return 0; 1191 } 1192 1193 spin_lock_irq(&port->slock); 1194 opmode = inb(port->opmode_ioaddr) >> shiftbit; 1195 spin_unlock_irq(&port->slock); 1196 1197 return put_user(opmode & OP_MODE_MASK, u_opmode); 1198 } 1199 1200 static int mxser_ioctl(struct tty_struct *tty, 1201 unsigned int cmd, unsigned long arg) 1202 { 1203 struct mxser_port *info = tty->driver_data; 1204 struct async_icount cnow; 1205 unsigned long flags; 1206 void __user *argp = (void __user *)arg; 1207 1208 if (cmd == MOXA_SET_OP_MODE || cmd == MOXA_GET_OP_MODE) 1209 return mxser_ioctl_op_mode(info, tty->index, 1210 cmd == MOXA_SET_OP_MODE, argp); 1211 1212 if (cmd != TIOCMIWAIT && tty_io_error(tty)) 1213 return -EIO; 1214 1215 switch (cmd) { 1216 case TIOCSERGETLSR: /* Get line status register */ 1217 return mxser_get_lsr_info(info, argp); 1218 /* 1219 * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change 1220 * - mask passed in arg for lines of interest 1221 * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking) 1222 * Caller should use TIOCGICOUNT to see which one it was 1223 */ 1224 case TIOCMIWAIT: 1225 spin_lock_irqsave(&info->slock, flags); 1226 cnow = info->icount; /* note the counters on entry */ 1227 spin_unlock_irqrestore(&info->slock, flags); 1228 1229 return wait_event_interruptible(info->port.delta_msr_wait, 1230 mxser_cflags_changed(info, arg, &cnow)); 1231 default: 1232 return -ENOIOCTLCMD; 1233 } 1234 return 0; 1235 } 1236 1237 /* 1238 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS) 1239 * Return: write counters to the user passed counter struct 1240 * NB: both 1->0 and 0->1 transitions are counted except for 1241 * RI where only 0->1 is counted. 1242 */ 1243 1244 static int mxser_get_icount(struct tty_struct *tty, 1245 struct serial_icounter_struct *icount) 1246 1247 { 1248 struct mxser_port *info = tty->driver_data; 1249 struct async_icount cnow; 1250 unsigned long flags; 1251 1252 spin_lock_irqsave(&info->slock, flags); 1253 cnow = info->icount; 1254 spin_unlock_irqrestore(&info->slock, flags); 1255 1256 icount->frame = cnow.frame; 1257 icount->brk = cnow.brk; 1258 icount->overrun = cnow.overrun; 1259 icount->buf_overrun = cnow.buf_overrun; 1260 icount->parity = cnow.parity; 1261 icount->rx = cnow.rx; 1262 icount->tx = cnow.tx; 1263 icount->cts = cnow.cts; 1264 icount->dsr = cnow.dsr; 1265 icount->rng = cnow.rng; 1266 icount->dcd = cnow.dcd; 1267 return 0; 1268 } 1269 1270 /* 1271 * This routine is called by the upper-layer tty layer to signal that 1272 * incoming characters should be throttled. 1273 */ 1274 static void mxser_throttle(struct tty_struct *tty) 1275 { 1276 struct mxser_port *info = tty->driver_data; 1277 1278 if (I_IXOFF(tty)) { 1279 if (info->board->must_hwid) { 1280 info->IER &= ~MOXA_MUST_RECV_ISR; 1281 outb(info->IER, info->ioaddr + UART_IER); 1282 } else { 1283 info->x_char = STOP_CHAR(tty); 1284 outb(0, info->ioaddr + UART_IER); 1285 info->IER |= UART_IER_THRI; 1286 outb(info->IER, info->ioaddr + UART_IER); 1287 } 1288 } 1289 1290 if (C_CRTSCTS(tty)) { 1291 info->MCR &= ~UART_MCR_RTS; 1292 outb(info->MCR, info->ioaddr + UART_MCR); 1293 } 1294 } 1295 1296 static void mxser_unthrottle(struct tty_struct *tty) 1297 { 1298 struct mxser_port *info = tty->driver_data; 1299 1300 /* startrx */ 1301 if (I_IXOFF(tty)) { 1302 if (info->x_char) 1303 info->x_char = 0; 1304 else { 1305 if (info->board->must_hwid) { 1306 info->IER |= MOXA_MUST_RECV_ISR; 1307 outb(info->IER, info->ioaddr + UART_IER); 1308 } else { 1309 info->x_char = START_CHAR(tty); 1310 outb(0, info->ioaddr + UART_IER); 1311 info->IER |= UART_IER_THRI; 1312 outb(info->IER, info->ioaddr + UART_IER); 1313 } 1314 } 1315 } 1316 1317 if (C_CRTSCTS(tty)) { 1318 info->MCR |= UART_MCR_RTS; 1319 outb(info->MCR, info->ioaddr + UART_MCR); 1320 } 1321 } 1322 1323 /* 1324 * mxser_stop() and mxser_start() 1325 * 1326 * This routines are called before setting or resetting tty->flow.stopped. 1327 * They enable or disable transmitter interrupts, as necessary. 1328 */ 1329 static void mxser_stop(struct tty_struct *tty) 1330 { 1331 struct mxser_port *info = tty->driver_data; 1332 unsigned long flags; 1333 1334 spin_lock_irqsave(&info->slock, flags); 1335 if (info->IER & UART_IER_THRI) 1336 __mxser_stop_tx(info); 1337 spin_unlock_irqrestore(&info->slock, flags); 1338 } 1339 1340 static void mxser_start(struct tty_struct *tty) 1341 { 1342 struct mxser_port *info = tty->driver_data; 1343 unsigned long flags; 1344 1345 spin_lock_irqsave(&info->slock, flags); 1346 if (!kfifo_is_empty(&info->port.xmit_fifo)) 1347 __mxser_start_tx(info); 1348 spin_unlock_irqrestore(&info->slock, flags); 1349 } 1350 1351 static void mxser_set_termios(struct tty_struct *tty, struct ktermios *old_termios) 1352 { 1353 struct mxser_port *info = tty->driver_data; 1354 unsigned long flags; 1355 1356 spin_lock_irqsave(&info->slock, flags); 1357 mxser_change_speed(tty, old_termios); 1358 spin_unlock_irqrestore(&info->slock, flags); 1359 1360 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) { 1361 tty->hw_stopped = 0; 1362 mxser_start(tty); 1363 } 1364 1365 /* Handle sw stopped */ 1366 if ((old_termios->c_iflag & IXON) && !I_IXON(tty)) { 1367 tty->flow.stopped = 0; 1368 1369 if (info->board->must_hwid) { 1370 spin_lock_irqsave(&info->slock, flags); 1371 mxser_must_set_rx_sw_flow_control(info->ioaddr, false); 1372 spin_unlock_irqrestore(&info->slock, flags); 1373 } 1374 1375 mxser_start(tty); 1376 } 1377 } 1378 1379 static bool mxser_tx_empty(struct mxser_port *info) 1380 { 1381 unsigned long flags; 1382 u8 lsr; 1383 1384 spin_lock_irqsave(&info->slock, flags); 1385 lsr = inb(info->ioaddr + UART_LSR); 1386 spin_unlock_irqrestore(&info->slock, flags); 1387 1388 return !(lsr & UART_LSR_TEMT); 1389 } 1390 1391 /* 1392 * mxser_wait_until_sent() --- wait until the transmitter is empty 1393 */ 1394 static void mxser_wait_until_sent(struct tty_struct *tty, int timeout) 1395 { 1396 struct mxser_port *info = tty->driver_data; 1397 unsigned long expire, char_time; 1398 1399 if (info->type == PORT_UNKNOWN) 1400 return; 1401 1402 if (info->xmit_fifo_size == 0) 1403 return; /* Just in case.... */ 1404 1405 /* 1406 * Set the check interval to be 1/5 of the estimated time to 1407 * send a single character, and make it at least 1. The check 1408 * interval should also be less than the timeout. 1409 * 1410 * Note: we have to use pretty tight timings here to satisfy 1411 * the NIST-PCTS. 1412 */ 1413 char_time = (info->timeout - HZ / 50) / info->xmit_fifo_size; 1414 char_time = char_time / 5; 1415 if (char_time == 0) 1416 char_time = 1; 1417 if (timeout && timeout < char_time) 1418 char_time = timeout; 1419 1420 char_time = jiffies_to_msecs(char_time); 1421 1422 /* 1423 * If the transmitter hasn't cleared in twice the approximate 1424 * amount of time to send the entire FIFO, it probably won't 1425 * ever clear. This assumes the UART isn't doing flow 1426 * control, which is currently the case. Hence, if it ever 1427 * takes longer than info->timeout, this is probably due to a 1428 * UART bug of some kind. So, we clamp the timeout parameter at 1429 * 2*info->timeout. 1430 */ 1431 if (!timeout || timeout > 2 * info->timeout) 1432 timeout = 2 * info->timeout; 1433 1434 expire = jiffies + timeout; 1435 1436 while (mxser_tx_empty(info)) { 1437 msleep_interruptible(char_time); 1438 if (signal_pending(current)) 1439 break; 1440 if (time_after(jiffies, expire)) 1441 break; 1442 } 1443 } 1444 1445 /* 1446 * This routine is called by tty_hangup() when a hangup is signaled. 1447 */ 1448 static void mxser_hangup(struct tty_struct *tty) 1449 { 1450 struct mxser_port *info = tty->driver_data; 1451 1452 mxser_flush_buffer(tty); 1453 tty_port_hangup(&info->port); 1454 } 1455 1456 /* 1457 * mxser_rs_break() --- routine which turns the break handling on or off 1458 */ 1459 static int mxser_rs_break(struct tty_struct *tty, int break_state) 1460 { 1461 struct mxser_port *info = tty->driver_data; 1462 unsigned long flags; 1463 u8 lcr; 1464 1465 spin_lock_irqsave(&info->slock, flags); 1466 lcr = inb(info->ioaddr + UART_LCR); 1467 if (break_state == -1) 1468 lcr |= UART_LCR_SBC; 1469 else 1470 lcr &= ~UART_LCR_SBC; 1471 outb(lcr, info->ioaddr + UART_LCR); 1472 spin_unlock_irqrestore(&info->slock, flags); 1473 1474 return 0; 1475 } 1476 1477 static bool mxser_receive_chars_new(struct mxser_port *port, u8 status) 1478 { 1479 enum mxser_must_hwid hwid = port->board->must_hwid; 1480 u8 gdl; 1481 1482 if (hwid == MOXA_OTHER_UART) 1483 return false; 1484 if (status & (UART_LSR_BRK_ERROR_BITS | MOXA_MUST_LSR_RERR)) 1485 return false; 1486 1487 gdl = inb(port->ioaddr + MOXA_MUST_GDL_REGISTER); 1488 if (hwid == MOXA_MUST_MU150_HWID) 1489 gdl &= MOXA_MUST_GDL_MASK; 1490 1491 while (gdl--) { 1492 u8 ch = inb(port->ioaddr + UART_RX); 1493 if (!tty_insert_flip_char(&port->port, ch, 0)) 1494 port->icount.buf_overrun++; 1495 } 1496 1497 return true; 1498 } 1499 1500 static u8 mxser_receive_chars_old(struct tty_struct *tty, 1501 struct mxser_port *port, u8 status) 1502 { 1503 enum mxser_must_hwid hwid = port->board->must_hwid; 1504 int ignored = 0; 1505 int max = 256; 1506 u8 ch; 1507 1508 do { 1509 if (max-- < 0) 1510 break; 1511 1512 ch = inb(port->ioaddr + UART_RX); 1513 if (hwid && (status & UART_LSR_OE)) 1514 outb(port->FCR | UART_FCR_CLEAR_RCVR, 1515 port->ioaddr + UART_FCR); 1516 status &= port->read_status_mask; 1517 if (status & port->ignore_status_mask) { 1518 if (++ignored > 100) 1519 break; 1520 } else { 1521 char flag = 0; 1522 if (status & UART_LSR_BRK_ERROR_BITS) { 1523 if (status & UART_LSR_BI) { 1524 flag = TTY_BREAK; 1525 port->icount.brk++; 1526 1527 if (port->port.flags & ASYNC_SAK) 1528 do_SAK(tty); 1529 } else if (status & UART_LSR_PE) { 1530 flag = TTY_PARITY; 1531 port->icount.parity++; 1532 } else if (status & UART_LSR_FE) { 1533 flag = TTY_FRAME; 1534 port->icount.frame++; 1535 } else if (status & UART_LSR_OE) { 1536 flag = TTY_OVERRUN; 1537 port->icount.overrun++; 1538 } 1539 } 1540 if (!tty_insert_flip_char(&port->port, ch, flag)) { 1541 port->icount.buf_overrun++; 1542 break; 1543 } 1544 } 1545 1546 if (hwid) 1547 break; 1548 1549 status = inb(port->ioaddr + UART_LSR); 1550 } while (status & UART_LSR_DR); 1551 1552 return status; 1553 } 1554 1555 static u8 mxser_receive_chars(struct tty_struct *tty, 1556 struct mxser_port *port, u8 status) 1557 { 1558 if (!mxser_receive_chars_new(port, status)) 1559 status = mxser_receive_chars_old(tty, port, status); 1560 1561 tty_flip_buffer_push(&port->port); 1562 1563 return status; 1564 } 1565 1566 static void mxser_transmit_chars(struct tty_struct *tty, struct mxser_port *port) 1567 { 1568 int count; 1569 1570 if (port->x_char) { 1571 outb(port->x_char, port->ioaddr + UART_TX); 1572 port->x_char = 0; 1573 port->icount.tx++; 1574 return; 1575 } 1576 1577 if (kfifo_is_empty(&port->port.xmit_fifo) || tty->flow.stopped || 1578 (tty->hw_stopped && !mxser_16550A_or_MUST(port))) { 1579 __mxser_stop_tx(port); 1580 return; 1581 } 1582 1583 count = port->xmit_fifo_size; 1584 do { 1585 unsigned char c; 1586 1587 if (!kfifo_get(&port->port.xmit_fifo, &c)) 1588 break; 1589 1590 outb(c, port->ioaddr + UART_TX); 1591 port->icount.tx++; 1592 } while (--count > 0); 1593 1594 if (kfifo_len(&port->port.xmit_fifo) < WAKEUP_CHARS) 1595 tty_wakeup(tty); 1596 1597 if (kfifo_is_empty(&port->port.xmit_fifo)) 1598 __mxser_stop_tx(port); 1599 } 1600 1601 static bool mxser_port_isr(struct mxser_port *port) 1602 { 1603 struct tty_struct *tty; 1604 u8 iir, status; 1605 bool error = false; 1606 1607 iir = inb(port->ioaddr + UART_IIR); 1608 if (iir & UART_IIR_NO_INT) 1609 return true; 1610 1611 iir &= MOXA_MUST_IIR_MASK; 1612 tty = tty_port_tty_get(&port->port); 1613 if (!tty) { 1614 status = inb(port->ioaddr + UART_LSR); 1615 outb(port->FCR | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, 1616 port->ioaddr + UART_FCR); 1617 inb(port->ioaddr + UART_MSR); 1618 1619 error = true; 1620 goto put_tty; 1621 } 1622 1623 status = inb(port->ioaddr + UART_LSR); 1624 1625 if (port->board->must_hwid) { 1626 if (iir == MOXA_MUST_IIR_GDA || 1627 iir == MOXA_MUST_IIR_RDA || 1628 iir == MOXA_MUST_IIR_RTO || 1629 iir == MOXA_MUST_IIR_LSR) 1630 status = mxser_receive_chars(tty, port, status); 1631 } else { 1632 status &= port->read_status_mask; 1633 if (status & UART_LSR_DR) 1634 status = mxser_receive_chars(tty, port, status); 1635 } 1636 1637 mxser_check_modem_status(tty, port); 1638 1639 if (port->board->must_hwid) { 1640 if (iir == 0x02 && (status & UART_LSR_THRE)) 1641 mxser_transmit_chars(tty, port); 1642 } else { 1643 if (status & UART_LSR_THRE) 1644 mxser_transmit_chars(tty, port); 1645 } 1646 1647 put_tty: 1648 tty_kref_put(tty); 1649 1650 return error; 1651 } 1652 1653 /* 1654 * This is the serial driver's generic interrupt routine 1655 */ 1656 static irqreturn_t mxser_interrupt(int irq, void *dev_id) 1657 { 1658 struct mxser_board *brd = dev_id; 1659 struct mxser_port *port; 1660 unsigned int int_cnt, pass_counter = 0; 1661 unsigned int i, max = brd->nports; 1662 int handled = IRQ_NONE; 1663 u8 irqbits, bits, mask = BIT(max) - 1; 1664 1665 while (pass_counter++ < MXSER_ISR_PASS_LIMIT) { 1666 irqbits = inb(brd->vector) & mask; 1667 if (irqbits == mask) 1668 break; 1669 1670 handled = IRQ_HANDLED; 1671 for (i = 0, bits = 1; i < max; i++, irqbits |= bits, bits <<= 1) { 1672 if (irqbits == mask) 1673 break; 1674 if (bits & irqbits) 1675 continue; 1676 port = &brd->ports[i]; 1677 1678 int_cnt = 0; 1679 spin_lock(&port->slock); 1680 do { 1681 if (mxser_port_isr(port)) 1682 break; 1683 } while (int_cnt++ < MXSER_ISR_PASS_LIMIT); 1684 spin_unlock(&port->slock); 1685 } 1686 } 1687 1688 return handled; 1689 } 1690 1691 static const struct tty_operations mxser_ops = { 1692 .open = mxser_open, 1693 .close = mxser_close, 1694 .write = mxser_write, 1695 .put_char = mxser_put_char, 1696 .flush_chars = mxser_flush_chars, 1697 .write_room = mxser_write_room, 1698 .chars_in_buffer = mxser_chars_in_buffer, 1699 .flush_buffer = mxser_flush_buffer, 1700 .ioctl = mxser_ioctl, 1701 .throttle = mxser_throttle, 1702 .unthrottle = mxser_unthrottle, 1703 .set_termios = mxser_set_termios, 1704 .stop = mxser_stop, 1705 .start = mxser_start, 1706 .hangup = mxser_hangup, 1707 .break_ctl = mxser_rs_break, 1708 .wait_until_sent = mxser_wait_until_sent, 1709 .tiocmget = mxser_tiocmget, 1710 .tiocmset = mxser_tiocmset, 1711 .set_serial = mxser_set_serial_info, 1712 .get_serial = mxser_get_serial_info, 1713 .get_icount = mxser_get_icount, 1714 }; 1715 1716 static const struct tty_port_operations mxser_port_ops = { 1717 .carrier_raised = mxser_carrier_raised, 1718 .dtr_rts = mxser_dtr_rts, 1719 .activate = mxser_activate, 1720 .shutdown = mxser_shutdown_port, 1721 }; 1722 1723 /* 1724 * The MOXA Smartio/Industio serial driver boot-time initialization code! 1725 */ 1726 1727 static void mxser_initbrd(struct mxser_board *brd, bool high_baud) 1728 { 1729 struct mxser_port *info; 1730 unsigned int i; 1731 bool is_mu860; 1732 1733 brd->must_hwid = mxser_must_get_hwid(brd->ports[0].ioaddr); 1734 is_mu860 = brd->must_hwid == MOXA_MUST_MU860_HWID; 1735 1736 for (i = 0; i < UART_INFO_NUM; i++) { 1737 if (Gpci_uart_info[i].type == brd->must_hwid) { 1738 brd->max_baud = Gpci_uart_info[i].max_baud; 1739 1740 /* exception....CP-102 */ 1741 if (high_baud) 1742 brd->max_baud = 921600; 1743 break; 1744 } 1745 } 1746 1747 if (is_mu860) { 1748 /* set to RS232 mode by default */ 1749 outb(0, brd->vector + 4); 1750 outb(0, brd->vector + 0x0c); 1751 } 1752 1753 for (i = 0; i < brd->nports; i++) { 1754 info = &brd->ports[i]; 1755 if (is_mu860) { 1756 if (i < 4) 1757 info->opmode_ioaddr = brd->vector + 4; 1758 else 1759 info->opmode_ioaddr = brd->vector + 0x0c; 1760 } 1761 tty_port_init(&info->port); 1762 info->port.ops = &mxser_port_ops; 1763 info->board = brd; 1764 1765 /* Enhance mode enabled here */ 1766 if (brd->must_hwid != MOXA_OTHER_UART) 1767 mxser_must_set_enhance_mode(info->ioaddr, true); 1768 1769 info->type = PORT_16550A; 1770 1771 mxser_process_txrx_fifo(info); 1772 1773 info->port.close_delay = 5 * HZ / 10; 1774 info->port.closing_wait = 30 * HZ; 1775 spin_lock_init(&info->slock); 1776 1777 /* before set INT ISR, disable all int */ 1778 outb(inb(info->ioaddr + UART_IER) & 0xf0, 1779 info->ioaddr + UART_IER); 1780 } 1781 } 1782 1783 static int mxser_probe(struct pci_dev *pdev, 1784 const struct pci_device_id *ent) 1785 { 1786 struct mxser_board *brd; 1787 unsigned int i, base; 1788 unsigned long ioaddress; 1789 unsigned short nports = MXSER_NPORTS(ent->driver_data); 1790 struct device *tty_dev; 1791 int retval = -EINVAL; 1792 1793 i = find_first_zero_bit(mxser_boards, MXSER_BOARDS); 1794 if (i >= MXSER_BOARDS) { 1795 dev_err(&pdev->dev, "too many boards found (maximum %d), board " 1796 "not configured\n", MXSER_BOARDS); 1797 goto err; 1798 } 1799 1800 brd = devm_kzalloc(&pdev->dev, struct_size(brd, ports, nports), 1801 GFP_KERNEL); 1802 if (!brd) 1803 goto err; 1804 1805 brd->idx = i; 1806 __set_bit(brd->idx, mxser_boards); 1807 base = i * MXSER_PORTS_PER_BOARD; 1808 1809 retval = pcim_enable_device(pdev); 1810 if (retval) { 1811 dev_err(&pdev->dev, "PCI enable failed\n"); 1812 goto err_zero; 1813 } 1814 1815 /* io address */ 1816 ioaddress = pci_resource_start(pdev, 2); 1817 retval = pci_request_region(pdev, 2, "mxser(IO)"); 1818 if (retval) 1819 goto err_zero; 1820 1821 brd->nports = nports; 1822 for (i = 0; i < nports; i++) 1823 brd->ports[i].ioaddr = ioaddress + 8 * i; 1824 1825 /* vector */ 1826 ioaddress = pci_resource_start(pdev, 3); 1827 retval = pci_request_region(pdev, 3, "mxser(vector)"); 1828 if (retval) 1829 goto err_zero; 1830 brd->vector = ioaddress; 1831 1832 /* irq */ 1833 brd->irq = pdev->irq; 1834 1835 mxser_initbrd(brd, ent->driver_data & MXSER_HIGHBAUD); 1836 1837 retval = devm_request_irq(&pdev->dev, brd->irq, mxser_interrupt, 1838 IRQF_SHARED, "mxser", brd); 1839 if (retval) { 1840 dev_err(&pdev->dev, "request irq failed"); 1841 goto err_relbrd; 1842 } 1843 1844 for (i = 0; i < nports; i++) { 1845 tty_dev = tty_port_register_device(&brd->ports[i].port, 1846 mxvar_sdriver, base + i, &pdev->dev); 1847 if (IS_ERR(tty_dev)) { 1848 retval = PTR_ERR(tty_dev); 1849 for (; i > 0; i--) 1850 tty_unregister_device(mxvar_sdriver, 1851 base + i - 1); 1852 goto err_relbrd; 1853 } 1854 } 1855 1856 pci_set_drvdata(pdev, brd); 1857 1858 return 0; 1859 err_relbrd: 1860 for (i = 0; i < nports; i++) 1861 tty_port_destroy(&brd->ports[i].port); 1862 err_zero: 1863 __clear_bit(brd->idx, mxser_boards); 1864 err: 1865 return retval; 1866 } 1867 1868 static void mxser_remove(struct pci_dev *pdev) 1869 { 1870 struct mxser_board *brd = pci_get_drvdata(pdev); 1871 unsigned int i, base = brd->idx * MXSER_PORTS_PER_BOARD; 1872 1873 for (i = 0; i < brd->nports; i++) { 1874 tty_unregister_device(mxvar_sdriver, base + i); 1875 tty_port_destroy(&brd->ports[i].port); 1876 } 1877 1878 __clear_bit(brd->idx, mxser_boards); 1879 } 1880 1881 static struct pci_driver mxser_driver = { 1882 .name = "mxser", 1883 .id_table = mxser_pcibrds, 1884 .probe = mxser_probe, 1885 .remove = mxser_remove 1886 }; 1887 1888 static int __init mxser_module_init(void) 1889 { 1890 int retval; 1891 1892 mxvar_sdriver = tty_alloc_driver(MXSER_PORTS, TTY_DRIVER_REAL_RAW | 1893 TTY_DRIVER_DYNAMIC_DEV); 1894 if (IS_ERR(mxvar_sdriver)) 1895 return PTR_ERR(mxvar_sdriver); 1896 1897 /* Initialize the tty_driver structure */ 1898 mxvar_sdriver->name = "ttyMI"; 1899 mxvar_sdriver->major = ttymajor; 1900 mxvar_sdriver->minor_start = 0; 1901 mxvar_sdriver->type = TTY_DRIVER_TYPE_SERIAL; 1902 mxvar_sdriver->subtype = SERIAL_TYPE_NORMAL; 1903 mxvar_sdriver->init_termios = tty_std_termios; 1904 mxvar_sdriver->init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL; 1905 tty_set_operations(mxvar_sdriver, &mxser_ops); 1906 1907 retval = tty_register_driver(mxvar_sdriver); 1908 if (retval) { 1909 printk(KERN_ERR "Couldn't install MOXA Smartio/Industio family " 1910 "tty driver !\n"); 1911 goto err_put; 1912 } 1913 1914 retval = pci_register_driver(&mxser_driver); 1915 if (retval) { 1916 printk(KERN_ERR "mxser: can't register pci driver\n"); 1917 goto err_unr; 1918 } 1919 1920 return 0; 1921 err_unr: 1922 tty_unregister_driver(mxvar_sdriver); 1923 err_put: 1924 tty_driver_kref_put(mxvar_sdriver); 1925 return retval; 1926 } 1927 1928 static void __exit mxser_module_exit(void) 1929 { 1930 pci_unregister_driver(&mxser_driver); 1931 tty_unregister_driver(mxvar_sdriver); 1932 tty_driver_kref_put(mxvar_sdriver); 1933 } 1934 1935 module_init(mxser_module_init); 1936 module_exit(mxser_module_exit); 1937