1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * mxser.c -- MOXA Smartio/Industio family multiport serial driver. 4 * 5 * Copyright (C) 1999-2006 Moxa Technologies (support@moxa.com). 6 * Copyright (C) 2006-2008 Jiri Slaby <jirislaby@gmail.com> 7 * 8 * This code is loosely based on the 1.8 moxa driver which is based on 9 * Linux serial driver, written by Linus Torvalds, Theodore T'so and 10 * others. 11 * 12 * Fed through a cleanup, indent and remove of non 2.6 code by Alan Cox 13 * <alan@lxorguk.ukuu.org.uk>. The original 1.8 code is available on 14 * www.moxa.com. 15 * - Fixed x86_64 cleanness 16 */ 17 18 #include <linux/module.h> 19 #include <linux/errno.h> 20 #include <linux/signal.h> 21 #include <linux/sched.h> 22 #include <linux/timer.h> 23 #include <linux/interrupt.h> 24 #include <linux/tty.h> 25 #include <linux/tty_flip.h> 26 #include <linux/serial.h> 27 #include <linux/serial_reg.h> 28 #include <linux/major.h> 29 #include <linux/string.h> 30 #include <linux/fcntl.h> 31 #include <linux/ptrace.h> 32 #include <linux/ioport.h> 33 #include <linux/mm.h> 34 #include <linux/delay.h> 35 #include <linux/pci.h> 36 #include <linux/bitops.h> 37 #include <linux/slab.h> 38 #include <linux/ratelimit.h> 39 40 #include <asm/io.h> 41 #include <asm/irq.h> 42 #include <linux/uaccess.h> 43 44 /* 45 * Semi-public control interfaces 46 */ 47 48 /* 49 * MOXA ioctls 50 */ 51 52 #define MOXA 0x400 53 #define MOXA_SET_OP_MODE (MOXA + 66) 54 #define MOXA_GET_OP_MODE (MOXA + 67) 55 56 #define RS232_MODE 0 57 #define RS485_2WIRE_MODE 1 58 #define RS422_MODE 2 59 #define RS485_4WIRE_MODE 3 60 #define OP_MODE_MASK 3 61 62 /* --------------------------------------------------- */ 63 64 /* 65 * Follow just what Moxa Must chip defines. 66 * 67 * When LCR register (offset 0x03) is written the following value, the Must chip 68 * will enter enhanced mode. And a write to EFR (offset 0x02) bit 6,7 will 69 * change bank. 70 */ 71 #define MOXA_MUST_ENTER_ENHANCED 0xBF 72 73 /* when enhanced mode is enabled, access to general bank register */ 74 #define MOXA_MUST_GDL_REGISTER 0x07 75 #define MOXA_MUST_GDL_MASK 0x7F 76 #define MOXA_MUST_GDL_HAS_BAD_DATA 0x80 77 78 #define MOXA_MUST_LSR_RERR 0x80 /* error in receive FIFO */ 79 /* enhanced register bank select and enhanced mode setting register */ 80 /* This works only when LCR register equals to 0xBF */ 81 #define MOXA_MUST_EFR_REGISTER 0x02 82 #define MOXA_MUST_EFR_EFRB_ENABLE 0x10 /* enhanced mode enable */ 83 /* enhanced register bank set 0, 1, 2 */ 84 #define MOXA_MUST_EFR_BANK0 0x00 85 #define MOXA_MUST_EFR_BANK1 0x40 86 #define MOXA_MUST_EFR_BANK2 0x80 87 #define MOXA_MUST_EFR_BANK3 0xC0 88 #define MOXA_MUST_EFR_BANK_MASK 0xC0 89 90 /* set XON1 value register, when LCR=0xBF and change to bank0 */ 91 #define MOXA_MUST_XON1_REGISTER 0x04 92 93 /* set XON2 value register, when LCR=0xBF and change to bank0 */ 94 #define MOXA_MUST_XON2_REGISTER 0x05 95 96 /* set XOFF1 value register, when LCR=0xBF and change to bank0 */ 97 #define MOXA_MUST_XOFF1_REGISTER 0x06 98 99 /* set XOFF2 value register, when LCR=0xBF and change to bank0 */ 100 #define MOXA_MUST_XOFF2_REGISTER 0x07 101 102 #define MOXA_MUST_RBRTL_REGISTER 0x04 103 #define MOXA_MUST_RBRTH_REGISTER 0x05 104 #define MOXA_MUST_RBRTI_REGISTER 0x06 105 #define MOXA_MUST_THRTL_REGISTER 0x07 106 #define MOXA_MUST_ENUM_REGISTER 0x04 107 #define MOXA_MUST_HWID_REGISTER 0x05 108 #define MOXA_MUST_ECR_REGISTER 0x06 109 #define MOXA_MUST_CSR_REGISTER 0x07 110 111 #define MOXA_MUST_FCR_GDA_MODE_ENABLE 0x20 /* good data mode enable */ 112 #define MOXA_MUST_FCR_GDA_ONLY_ENABLE 0x10 /* only good data put into RxFIFO */ 113 114 #define MOXA_MUST_IER_ECTSI 0x80 /* enable CTS interrupt */ 115 #define MOXA_MUST_IER_ERTSI 0x40 /* enable RTS interrupt */ 116 #define MOXA_MUST_IER_XINT 0x20 /* enable Xon/Xoff interrupt */ 117 #define MOXA_MUST_IER_EGDAI 0x10 /* enable GDA interrupt */ 118 119 #define MOXA_MUST_RECV_ISR (UART_IER_RDI | MOXA_MUST_IER_EGDAI) 120 121 /* GDA interrupt pending */ 122 #define MOXA_MUST_IIR_GDA 0x1C 123 #define MOXA_MUST_IIR_RDA 0x04 124 #define MOXA_MUST_IIR_RTO 0x0C 125 #define MOXA_MUST_IIR_LSR 0x06 126 127 /* received Xon/Xoff or specical interrupt pending */ 128 #define MOXA_MUST_IIR_XSC 0x10 129 130 /* RTS/CTS change state interrupt pending */ 131 #define MOXA_MUST_IIR_RTSCTS 0x20 132 #define MOXA_MUST_IIR_MASK 0x3E 133 134 #define MOXA_MUST_MCR_XON_FLAG 0x40 135 #define MOXA_MUST_MCR_XON_ANY 0x80 136 #define MOXA_MUST_MCR_TX_XON 0x08 137 138 #define MOXA_MUST_EFR_SF_MASK 0x0F /* software flow control on chip mask value */ 139 #define MOXA_MUST_EFR_SF_TX1 0x08 /* send Xon1/Xoff1 */ 140 #define MOXA_MUST_EFR_SF_TX2 0x04 /* send Xon2/Xoff2 */ 141 #define MOXA_MUST_EFR_SF_TX12 0x0C /* send Xon1,Xon2/Xoff1,Xoff2 */ 142 #define MOXA_MUST_EFR_SF_TX_NO 0x00 /* don't send Xon/Xoff */ 143 #define MOXA_MUST_EFR_SF_TX_MASK 0x0C /* Tx software flow control mask */ 144 #define MOXA_MUST_EFR_SF_RX_NO 0x00 /* don't receive Xon/Xoff */ 145 #define MOXA_MUST_EFR_SF_RX1 0x02 /* receive Xon1/Xoff1 */ 146 #define MOXA_MUST_EFR_SF_RX2 0x01 /* receive Xon2/Xoff2 */ 147 #define MOXA_MUST_EFR_SF_RX12 0x03 /* receive Xon1,Xon2/Xoff1,Xoff2 */ 148 #define MOXA_MUST_EFR_SF_RX_MASK 0x03 /* Rx software flow control mask */ 149 150 #define MXSERMAJOR 174 151 152 #define MXSER_BOARDS 4 /* Max. boards */ 153 #define MXSER_PORTS_PER_BOARD 8 /* Max. ports per board */ 154 #define MXSER_PORTS (MXSER_BOARDS * MXSER_PORTS_PER_BOARD) 155 #define MXSER_ISR_PASS_LIMIT 100 156 157 #define WAKEUP_CHARS 256 158 159 #define MXSER_BAUD_BASE 921600 160 #define MXSER_CUSTOM_DIVISOR (MXSER_BAUD_BASE * 16) 161 162 #define PCI_DEVICE_ID_MOXA_RC7000 0x0001 163 #define PCI_DEVICE_ID_MOXA_CP102 0x1020 164 #define PCI_DEVICE_ID_MOXA_CP102UL 0x1021 165 #define PCI_DEVICE_ID_MOXA_CP102U 0x1022 166 #define PCI_DEVICE_ID_MOXA_CP102UF 0x1023 167 #define PCI_DEVICE_ID_MOXA_C104 0x1040 168 #define PCI_DEVICE_ID_MOXA_CP104U 0x1041 169 #define PCI_DEVICE_ID_MOXA_CP104JU 0x1042 170 #define PCI_DEVICE_ID_MOXA_CP104EL 0x1043 171 #define PCI_DEVICE_ID_MOXA_POS104UL 0x1044 172 #define PCI_DEVICE_ID_MOXA_CB108 0x1080 173 #define PCI_DEVICE_ID_MOXA_CP112UL 0x1120 174 #define PCI_DEVICE_ID_MOXA_CT114 0x1140 175 #define PCI_DEVICE_ID_MOXA_CP114 0x1141 176 #define PCI_DEVICE_ID_MOXA_CB114 0x1142 177 #define PCI_DEVICE_ID_MOXA_CP114UL 0x1143 178 #define PCI_DEVICE_ID_MOXA_CP118U 0x1180 179 #define PCI_DEVICE_ID_MOXA_CP118EL 0x1181 180 #define PCI_DEVICE_ID_MOXA_CP132 0x1320 181 #define PCI_DEVICE_ID_MOXA_CP132U 0x1321 182 #define PCI_DEVICE_ID_MOXA_CP134U 0x1340 183 #define PCI_DEVICE_ID_MOXA_CB134I 0x1341 184 #define PCI_DEVICE_ID_MOXA_CP138U 0x1380 185 #define PCI_DEVICE_ID_MOXA_C168 0x1680 186 #define PCI_DEVICE_ID_MOXA_CP168U 0x1681 187 #define PCI_DEVICE_ID_MOXA_CP168EL 0x1682 188 189 #define MXSER_NPORTS(ddata) ((ddata) & 0xffU) 190 #define MXSER_HIGHBAUD 0x0100 191 192 enum mxser_must_hwid { 193 MOXA_OTHER_UART = 0x00, 194 MOXA_MUST_MU150_HWID = 0x01, 195 MOXA_MUST_MU860_HWID = 0x02, 196 }; 197 198 static const struct { 199 u8 type; 200 u8 fifo_size; 201 u8 rx_high_water; 202 u8 rx_low_water; 203 speed_t max_baud; 204 } Gpci_uart_info[] = { 205 { MOXA_OTHER_UART, 16, 14, 1, 921600 }, 206 { MOXA_MUST_MU150_HWID, 64, 48, 16, 230400 }, 207 { MOXA_MUST_MU860_HWID, 128, 96, 32, 921600 } 208 }; 209 #define UART_INFO_NUM ARRAY_SIZE(Gpci_uart_info) 210 211 static const struct pci_device_id mxser_pcibrds[] = { 212 { PCI_DEVICE_DATA(MOXA, C168, 8) }, 213 { PCI_DEVICE_DATA(MOXA, C104, 4) }, 214 { PCI_DEVICE_DATA(MOXA, CP132, 2) }, 215 { PCI_DEVICE_DATA(MOXA, CP114, 4) }, 216 { PCI_DEVICE_DATA(MOXA, CT114, 4) }, 217 { PCI_DEVICE_DATA(MOXA, CP102, 2 | MXSER_HIGHBAUD) }, 218 { PCI_DEVICE_DATA(MOXA, CP104U, 4) }, 219 { PCI_DEVICE_DATA(MOXA, CP168U, 8) }, 220 { PCI_DEVICE_DATA(MOXA, CP132U, 2) }, 221 { PCI_DEVICE_DATA(MOXA, CP134U, 4) }, 222 { PCI_DEVICE_DATA(MOXA, CP104JU, 4) }, 223 { PCI_DEVICE_DATA(MOXA, RC7000, 8) }, /* RC7000 */ 224 { PCI_DEVICE_DATA(MOXA, CP118U, 8) }, 225 { PCI_DEVICE_DATA(MOXA, CP102UL, 2) }, 226 { PCI_DEVICE_DATA(MOXA, CP102U, 2) }, 227 { PCI_DEVICE_DATA(MOXA, CP118EL, 8) }, 228 { PCI_DEVICE_DATA(MOXA, CP168EL, 8) }, 229 { PCI_DEVICE_DATA(MOXA, CP104EL, 4) }, 230 { PCI_DEVICE_DATA(MOXA, CB108, 8) }, 231 { PCI_DEVICE_DATA(MOXA, CB114, 4) }, 232 { PCI_DEVICE_DATA(MOXA, CB134I, 4) }, 233 { PCI_DEVICE_DATA(MOXA, CP138U, 8) }, 234 { PCI_DEVICE_DATA(MOXA, POS104UL, 4) }, 235 { PCI_DEVICE_DATA(MOXA, CP114UL, 4) }, 236 { PCI_DEVICE_DATA(MOXA, CP102UF, 2) }, 237 { PCI_DEVICE_DATA(MOXA, CP112UL, 2) }, 238 { } 239 }; 240 MODULE_DEVICE_TABLE(pci, mxser_pcibrds); 241 242 static int ttymajor = MXSERMAJOR; 243 244 /* Variables for insmod */ 245 246 MODULE_AUTHOR("Casper Yang"); 247 MODULE_DESCRIPTION("MOXA Smartio/Industio Family Multiport Board Device Driver"); 248 module_param(ttymajor, int, 0); 249 MODULE_LICENSE("GPL"); 250 251 struct mxser_board; 252 253 struct mxser_port { 254 struct tty_port port; 255 struct mxser_board *board; 256 257 unsigned long ioaddr; 258 unsigned long opmode_ioaddr; 259 260 u8 rx_high_water; 261 u8 rx_low_water; 262 int type; /* UART type */ 263 264 u8 x_char; /* xon/xoff character */ 265 u8 IER; /* Interrupt Enable Register */ 266 u8 MCR; /* Modem control register */ 267 u8 FCR; /* FIFO control register */ 268 269 struct async_icount icount; /* kernel counters for 4 input interrupts */ 270 unsigned int timeout; 271 272 u8 read_status_mask; 273 u8 ignore_status_mask; 274 u8 xmit_fifo_size; 275 276 spinlock_t slock; 277 }; 278 279 struct mxser_board { 280 unsigned int idx; 281 unsigned short nports; 282 int irq; 283 unsigned long vector; 284 285 enum mxser_must_hwid must_hwid; 286 speed_t max_baud; 287 288 struct mxser_port ports[] /* __counted_by(nports) */; 289 }; 290 291 static DECLARE_BITMAP(mxser_boards, MXSER_BOARDS); 292 static struct tty_driver *mxvar_sdriver; 293 294 static u8 __mxser_must_set_EFR(unsigned long baseio, u8 clear, u8 set, 295 bool restore_LCR) 296 { 297 u8 oldlcr, efr; 298 299 oldlcr = inb(baseio + UART_LCR); 300 outb(MOXA_MUST_ENTER_ENHANCED, baseio + UART_LCR); 301 302 efr = inb(baseio + MOXA_MUST_EFR_REGISTER); 303 efr &= ~clear; 304 efr |= set; 305 306 outb(efr, baseio + MOXA_MUST_EFR_REGISTER); 307 308 if (restore_LCR) 309 outb(oldlcr, baseio + UART_LCR); 310 311 return oldlcr; 312 } 313 314 static u8 mxser_must_select_bank(unsigned long baseio, u8 bank) 315 { 316 return __mxser_must_set_EFR(baseio, MOXA_MUST_EFR_BANK_MASK, bank, 317 false); 318 } 319 320 static void mxser_set_must_xon1_value(unsigned long baseio, u8 value) 321 { 322 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK0); 323 outb(value, baseio + MOXA_MUST_XON1_REGISTER); 324 outb(oldlcr, baseio + UART_LCR); 325 } 326 327 static void mxser_set_must_xoff1_value(unsigned long baseio, u8 value) 328 { 329 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK0); 330 outb(value, baseio + MOXA_MUST_XOFF1_REGISTER); 331 outb(oldlcr, baseio + UART_LCR); 332 } 333 334 static void mxser_set_must_fifo_value(struct mxser_port *info) 335 { 336 u8 oldlcr = mxser_must_select_bank(info->ioaddr, MOXA_MUST_EFR_BANK1); 337 outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTH_REGISTER); 338 outb(info->rx_high_water, info->ioaddr + MOXA_MUST_RBRTI_REGISTER); 339 outb(info->rx_low_water, info->ioaddr + MOXA_MUST_RBRTL_REGISTER); 340 outb(oldlcr, info->ioaddr + UART_LCR); 341 } 342 343 static void mxser_set_must_enum_value(unsigned long baseio, u8 value) 344 { 345 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK2); 346 outb(value, baseio + MOXA_MUST_ENUM_REGISTER); 347 outb(oldlcr, baseio + UART_LCR); 348 } 349 350 static u8 mxser_get_must_hardware_id(unsigned long baseio) 351 { 352 u8 oldlcr = mxser_must_select_bank(baseio, MOXA_MUST_EFR_BANK2); 353 u8 id = inb(baseio + MOXA_MUST_HWID_REGISTER); 354 outb(oldlcr, baseio + UART_LCR); 355 356 return id; 357 } 358 359 static void mxser_must_set_EFR(unsigned long baseio, u8 clear, u8 set) 360 { 361 __mxser_must_set_EFR(baseio, clear, set, true); 362 } 363 364 static void mxser_must_set_enhance_mode(unsigned long baseio, bool enable) 365 { 366 mxser_must_set_EFR(baseio, 367 enable ? 0 : MOXA_MUST_EFR_EFRB_ENABLE, 368 enable ? MOXA_MUST_EFR_EFRB_ENABLE : 0); 369 } 370 371 static void mxser_must_no_sw_flow_control(unsigned long baseio) 372 { 373 mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_MASK, 0); 374 } 375 376 static void mxser_must_set_tx_sw_flow_control(unsigned long baseio, bool enable) 377 { 378 mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_TX_MASK, 379 enable ? MOXA_MUST_EFR_SF_TX1 : 0); 380 } 381 382 static void mxser_must_set_rx_sw_flow_control(unsigned long baseio, bool enable) 383 { 384 mxser_must_set_EFR(baseio, MOXA_MUST_EFR_SF_RX_MASK, 385 enable ? MOXA_MUST_EFR_SF_RX1 : 0); 386 } 387 388 static enum mxser_must_hwid mxser_must_get_hwid(unsigned long io) 389 { 390 u8 oldmcr, hwid; 391 int i; 392 393 outb(0, io + UART_LCR); 394 mxser_must_set_enhance_mode(io, false); 395 oldmcr = inb(io + UART_MCR); 396 outb(0, io + UART_MCR); 397 mxser_set_must_xon1_value(io, 0x11); 398 if (inb(io + UART_MCR) != 0) { 399 outb(oldmcr, io + UART_MCR); 400 return MOXA_OTHER_UART; 401 } 402 403 hwid = mxser_get_must_hardware_id(io); 404 for (i = 1; i < UART_INFO_NUM; i++) /* 0 = OTHER_UART */ 405 if (hwid == Gpci_uart_info[i].type) 406 return hwid; 407 408 return MOXA_OTHER_UART; 409 } 410 411 static bool mxser_16550A_or_MUST(struct mxser_port *info) 412 { 413 return info->type == PORT_16550A || info->board->must_hwid; 414 } 415 416 static void mxser_process_txrx_fifo(struct mxser_port *info) 417 { 418 unsigned int i; 419 420 if (info->type == PORT_16450 || info->type == PORT_8250) { 421 info->rx_high_water = 1; 422 info->rx_low_water = 1; 423 info->xmit_fifo_size = 1; 424 return; 425 } 426 427 for (i = 0; i < UART_INFO_NUM; i++) 428 if (info->board->must_hwid == Gpci_uart_info[i].type) { 429 info->rx_low_water = Gpci_uart_info[i].rx_low_water; 430 info->rx_high_water = Gpci_uart_info[i].rx_high_water; 431 info->xmit_fifo_size = Gpci_uart_info[i].fifo_size; 432 break; 433 } 434 } 435 436 static void __mxser_start_tx(struct mxser_port *info) 437 { 438 outb(info->IER & ~UART_IER_THRI, info->ioaddr + UART_IER); 439 info->IER |= UART_IER_THRI; 440 outb(info->IER, info->ioaddr + UART_IER); 441 } 442 443 static void mxser_start_tx(struct mxser_port *info) 444 { 445 unsigned long flags; 446 447 spin_lock_irqsave(&info->slock, flags); 448 __mxser_start_tx(info); 449 spin_unlock_irqrestore(&info->slock, flags); 450 } 451 452 static void __mxser_stop_tx(struct mxser_port *info) 453 { 454 info->IER &= ~UART_IER_THRI; 455 outb(info->IER, info->ioaddr + UART_IER); 456 } 457 458 static bool mxser_carrier_raised(struct tty_port *port) 459 { 460 struct mxser_port *mp = container_of(port, struct mxser_port, port); 461 462 return inb(mp->ioaddr + UART_MSR) & UART_MSR_DCD; 463 } 464 465 static void mxser_dtr_rts(struct tty_port *port, bool active) 466 { 467 struct mxser_port *mp = container_of(port, struct mxser_port, port); 468 unsigned long flags; 469 u8 mcr; 470 471 spin_lock_irqsave(&mp->slock, flags); 472 mcr = inb(mp->ioaddr + UART_MCR); 473 if (active) 474 mcr |= UART_MCR_DTR | UART_MCR_RTS; 475 else 476 mcr &= ~(UART_MCR_DTR | UART_MCR_RTS); 477 outb(mcr, mp->ioaddr + UART_MCR); 478 spin_unlock_irqrestore(&mp->slock, flags); 479 } 480 481 static int mxser_set_baud(struct tty_struct *tty, speed_t newspd) 482 { 483 struct mxser_port *info = tty->driver_data; 484 unsigned int quot = 0, baud; 485 unsigned char cval; 486 u64 timeout; 487 488 if (newspd > info->board->max_baud) 489 return -1; 490 491 if (newspd == 134) { 492 quot = 2 * MXSER_BAUD_BASE / 269; 493 tty_encode_baud_rate(tty, 134, 134); 494 } else if (newspd) { 495 quot = MXSER_BAUD_BASE / newspd; 496 if (quot == 0) 497 quot = 1; 498 baud = MXSER_BAUD_BASE / quot; 499 tty_encode_baud_rate(tty, baud, baud); 500 } else { 501 quot = 0; 502 } 503 504 /* 505 * worst case (128 * 1000 * 10 * 18432) needs 35 bits, so divide in the 506 * u64 domain 507 */ 508 timeout = (u64)info->xmit_fifo_size * HZ * 10 * quot; 509 do_div(timeout, MXSER_BAUD_BASE); 510 info->timeout = timeout + HZ / 50; /* Add .02 seconds of slop */ 511 512 if (quot) { 513 info->MCR |= UART_MCR_DTR; 514 outb(info->MCR, info->ioaddr + UART_MCR); 515 } else { 516 info->MCR &= ~UART_MCR_DTR; 517 outb(info->MCR, info->ioaddr + UART_MCR); 518 return 0; 519 } 520 521 cval = inb(info->ioaddr + UART_LCR); 522 523 outb(cval | UART_LCR_DLAB, info->ioaddr + UART_LCR); /* set DLAB */ 524 525 outb(quot & 0xff, info->ioaddr + UART_DLL); /* LS of divisor */ 526 outb(quot >> 8, info->ioaddr + UART_DLM); /* MS of divisor */ 527 outb(cval, info->ioaddr + UART_LCR); /* reset DLAB */ 528 529 if (C_BAUD(tty) == BOTHER) { 530 quot = MXSER_BAUD_BASE % newspd; 531 quot *= 8; 532 if (quot % newspd > newspd / 2) { 533 quot /= newspd; 534 quot++; 535 } else 536 quot /= newspd; 537 538 mxser_set_must_enum_value(info->ioaddr, quot); 539 } else { 540 mxser_set_must_enum_value(info->ioaddr, 0); 541 } 542 543 return 0; 544 } 545 546 static void mxser_handle_cts(struct tty_struct *tty, struct mxser_port *info, 547 u8 msr) 548 { 549 bool cts = msr & UART_MSR_CTS; 550 551 if (tty->hw_stopped) { 552 if (cts) { 553 tty->hw_stopped = false; 554 555 if (!mxser_16550A_or_MUST(info)) 556 __mxser_start_tx(info); 557 tty_wakeup(tty); 558 } 559 return; 560 } else if (cts) 561 return; 562 563 tty->hw_stopped = true; 564 if (!mxser_16550A_or_MUST(info)) 565 __mxser_stop_tx(info); 566 } 567 568 /* 569 * This routine is called to set the UART divisor registers to match 570 * the specified baud rate for a serial port. 571 */ 572 static void mxser_change_speed(struct tty_struct *tty, 573 const struct ktermios *old_termios) 574 { 575 struct mxser_port *info = tty->driver_data; 576 unsigned cflag, cval; 577 578 cflag = tty->termios.c_cflag; 579 580 if (mxser_set_baud(tty, tty_get_baud_rate(tty))) { 581 /* Use previous rate on a failure */ 582 if (old_termios) { 583 speed_t baud = tty_termios_baud_rate(old_termios); 584 tty_encode_baud_rate(tty, baud, baud); 585 } 586 } 587 588 /* byte size and parity */ 589 cval = UART_LCR_WLEN(tty_get_char_size(tty->termios.c_cflag)); 590 591 if (cflag & CSTOPB) 592 cval |= UART_LCR_STOP; 593 if (cflag & PARENB) 594 cval |= UART_LCR_PARITY; 595 if (!(cflag & PARODD)) 596 cval |= UART_LCR_EPAR; 597 if (cflag & CMSPAR) 598 cval |= UART_LCR_SPAR; 599 600 info->FCR = 0; 601 if (info->board->must_hwid) { 602 info->FCR |= UART_FCR_ENABLE_FIFO | 603 MOXA_MUST_FCR_GDA_MODE_ENABLE; 604 mxser_set_must_fifo_value(info); 605 } else if (info->type != PORT_8250 && info->type != PORT_16450) { 606 info->FCR |= UART_FCR_ENABLE_FIFO; 607 switch (info->rx_high_water) { 608 case 1: 609 info->FCR |= UART_FCR_TRIGGER_1; 610 break; 611 case 4: 612 info->FCR |= UART_FCR_TRIGGER_4; 613 break; 614 case 8: 615 info->FCR |= UART_FCR_TRIGGER_8; 616 break; 617 default: 618 info->FCR |= UART_FCR_TRIGGER_14; 619 break; 620 } 621 } 622 623 /* CTS flow control flag and modem status interrupts */ 624 info->IER &= ~UART_IER_MSI; 625 info->MCR &= ~UART_MCR_AFE; 626 tty_port_set_cts_flow(&info->port, cflag & CRTSCTS); 627 if (cflag & CRTSCTS) { 628 info->IER |= UART_IER_MSI; 629 if (mxser_16550A_or_MUST(info)) { 630 info->MCR |= UART_MCR_AFE; 631 } else { 632 mxser_handle_cts(tty, info, 633 inb(info->ioaddr + UART_MSR)); 634 } 635 } 636 outb(info->MCR, info->ioaddr + UART_MCR); 637 tty_port_set_check_carrier(&info->port, ~cflag & CLOCAL); 638 if (~cflag & CLOCAL) 639 info->IER |= UART_IER_MSI; 640 outb(info->IER, info->ioaddr + UART_IER); 641 642 /* 643 * Set up parity check flag 644 */ 645 info->read_status_mask = UART_LSR_OE | UART_LSR_THRE | UART_LSR_DR; 646 if (I_INPCK(tty)) 647 info->read_status_mask |= UART_LSR_FE | UART_LSR_PE; 648 if (I_BRKINT(tty) || I_PARMRK(tty)) 649 info->read_status_mask |= UART_LSR_BI; 650 651 info->ignore_status_mask = 0; 652 653 if (I_IGNBRK(tty)) { 654 info->ignore_status_mask |= UART_LSR_BI; 655 info->read_status_mask |= UART_LSR_BI; 656 /* 657 * If we're ignore parity and break indicators, ignore 658 * overruns too. (For real raw support). 659 */ 660 if (I_IGNPAR(tty)) { 661 info->ignore_status_mask |= 662 UART_LSR_OE | 663 UART_LSR_PE | 664 UART_LSR_FE; 665 info->read_status_mask |= 666 UART_LSR_OE | 667 UART_LSR_PE | 668 UART_LSR_FE; 669 } 670 } 671 if (info->board->must_hwid) { 672 mxser_set_must_xon1_value(info->ioaddr, START_CHAR(tty)); 673 mxser_set_must_xoff1_value(info->ioaddr, STOP_CHAR(tty)); 674 mxser_must_set_rx_sw_flow_control(info->ioaddr, I_IXON(tty)); 675 mxser_must_set_tx_sw_flow_control(info->ioaddr, I_IXOFF(tty)); 676 } 677 678 679 outb(info->FCR, info->ioaddr + UART_FCR); 680 outb(cval, info->ioaddr + UART_LCR); 681 } 682 683 static u8 mxser_check_modem_status(struct tty_struct *tty, 684 struct mxser_port *port) 685 { 686 u8 msr = inb(port->ioaddr + UART_MSR); 687 688 if (!(msr & UART_MSR_ANY_DELTA)) 689 return msr; 690 691 /* update input line counters */ 692 if (msr & UART_MSR_TERI) 693 port->icount.rng++; 694 if (msr & UART_MSR_DDSR) 695 port->icount.dsr++; 696 if (msr & UART_MSR_DDCD) 697 port->icount.dcd++; 698 if (msr & UART_MSR_DCTS) 699 port->icount.cts++; 700 wake_up_interruptible(&port->port.delta_msr_wait); 701 702 if (tty_port_check_carrier(&port->port) && (msr & UART_MSR_DDCD)) { 703 if (msr & UART_MSR_DCD) 704 wake_up_interruptible(&port->port.open_wait); 705 } 706 707 if (tty_port_cts_enabled(&port->port)) 708 mxser_handle_cts(tty, port, msr); 709 710 return msr; 711 } 712 713 static void mxser_disable_and_clear_FIFO(struct mxser_port *info) 714 { 715 u8 fcr = UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT; 716 717 if (info->board->must_hwid) 718 fcr |= MOXA_MUST_FCR_GDA_MODE_ENABLE; 719 720 outb(fcr, info->ioaddr + UART_FCR); 721 } 722 723 static int mxser_activate(struct tty_port *port, struct tty_struct *tty) 724 { 725 struct mxser_port *info = container_of(port, struct mxser_port, port); 726 unsigned long flags; 727 int ret; 728 729 ret = tty_port_alloc_xmit_buf(port); 730 if (ret < 0) 731 return ret; 732 733 spin_lock_irqsave(&info->slock, flags); 734 735 if (!info->type) { 736 set_bit(TTY_IO_ERROR, &tty->flags); 737 spin_unlock_irqrestore(&info->slock, flags); 738 ret = 0; 739 goto err_free_xmit; 740 } 741 742 /* 743 * Clear the FIFO buffers and disable them 744 * (they will be reenabled in mxser_change_speed()) 745 */ 746 mxser_disable_and_clear_FIFO(info); 747 748 /* 749 * At this point there's no way the LSR could still be 0xFF; 750 * if it is, then bail out, because there's likely no UART 751 * here. 752 */ 753 if (inb(info->ioaddr + UART_LSR) == 0xff) { 754 spin_unlock_irqrestore(&info->slock, flags); 755 if (capable(CAP_SYS_ADMIN)) { 756 set_bit(TTY_IO_ERROR, &tty->flags); 757 return 0; 758 } 759 760 ret = -ENODEV; 761 goto err_free_xmit; 762 } 763 764 /* 765 * Clear the interrupt registers. 766 */ 767 (void) inb(info->ioaddr + UART_LSR); 768 (void) inb(info->ioaddr + UART_RX); 769 (void) inb(info->ioaddr + UART_IIR); 770 (void) inb(info->ioaddr + UART_MSR); 771 772 /* 773 * Now, initialize the UART 774 */ 775 outb(UART_LCR_WLEN8, info->ioaddr + UART_LCR); /* reset DLAB */ 776 info->MCR = UART_MCR_DTR | UART_MCR_RTS; 777 outb(info->MCR, info->ioaddr + UART_MCR); 778 779 /* 780 * Finally, enable interrupts 781 */ 782 info->IER = UART_IER_MSI | UART_IER_RLSI | UART_IER_RDI; 783 784 if (info->board->must_hwid) 785 info->IER |= MOXA_MUST_IER_EGDAI; 786 outb(info->IER, info->ioaddr + UART_IER); /* enable interrupts */ 787 788 /* 789 * And clear the interrupt registers again for luck. 790 */ 791 (void) inb(info->ioaddr + UART_LSR); 792 (void) inb(info->ioaddr + UART_RX); 793 (void) inb(info->ioaddr + UART_IIR); 794 (void) inb(info->ioaddr + UART_MSR); 795 796 clear_bit(TTY_IO_ERROR, &tty->flags); 797 kfifo_reset(&port->xmit_fifo); 798 799 /* 800 * and set the speed of the serial port 801 */ 802 mxser_change_speed(tty, NULL); 803 spin_unlock_irqrestore(&info->slock, flags); 804 805 return 0; 806 err_free_xmit: 807 tty_port_free_xmit_buf(port); 808 return ret; 809 } 810 811 /* 812 * To stop accepting input, we disable the receive line status interrupts, and 813 * tell the interrupt driver to stop checking the data ready bit in the line 814 * status register. 815 */ 816 static void mxser_stop_rx(struct mxser_port *info) 817 { 818 info->IER &= ~UART_IER_RLSI; 819 if (info->board->must_hwid) 820 info->IER &= ~MOXA_MUST_RECV_ISR; 821 822 outb(info->IER, info->ioaddr + UART_IER); 823 } 824 825 /* 826 * This routine will shutdown a serial port 827 */ 828 static void mxser_shutdown_port(struct tty_port *port) 829 { 830 struct mxser_port *info = container_of(port, struct mxser_port, port); 831 unsigned long flags; 832 833 spin_lock_irqsave(&info->slock, flags); 834 835 mxser_stop_rx(info); 836 837 /* 838 * clear delta_msr_wait queue to avoid mem leaks: we may free the irq 839 * here so the queue might never be waken up 840 */ 841 wake_up_interruptible(&info->port.delta_msr_wait); 842 843 info->IER = 0; 844 outb(0x00, info->ioaddr + UART_IER); 845 846 /* clear Rx/Tx FIFO's */ 847 mxser_disable_and_clear_FIFO(info); 848 849 /* read data port to reset things */ 850 (void) inb(info->ioaddr + UART_RX); 851 852 853 if (info->board->must_hwid) 854 mxser_must_no_sw_flow_control(info->ioaddr); 855 856 spin_unlock_irqrestore(&info->slock, flags); 857 858 /* make sure ISR is not running while we free the buffer */ 859 synchronize_irq(info->board->irq); 860 861 tty_port_free_xmit_buf(port); 862 } 863 864 /* 865 * This routine is called whenever a serial port is opened. It 866 * enables interrupts for a serial port, linking in its async structure into 867 * the IRQ chain. It also performs the serial-specific 868 * initialization for the tty structure. 869 */ 870 static int mxser_open(struct tty_struct *tty, struct file *filp) 871 { 872 struct tty_port *tport = tty->port; 873 struct mxser_port *port = container_of(tport, struct mxser_port, port); 874 875 tty->driver_data = port; 876 877 return tty_port_open(tport, tty, filp); 878 } 879 880 static void mxser_flush_buffer(struct tty_struct *tty) 881 { 882 struct mxser_port *info = tty->driver_data; 883 unsigned long flags; 884 885 spin_lock_irqsave(&info->slock, flags); 886 kfifo_reset(&info->port.xmit_fifo); 887 888 outb(info->FCR | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, 889 info->ioaddr + UART_FCR); 890 891 spin_unlock_irqrestore(&info->slock, flags); 892 893 tty_wakeup(tty); 894 } 895 896 static void mxser_close(struct tty_struct *tty, struct file *filp) 897 { 898 tty_port_close(tty->port, tty, filp); 899 } 900 901 static ssize_t mxser_write(struct tty_struct *tty, const u8 *buf, size_t count) 902 { 903 struct mxser_port *info = tty->driver_data; 904 unsigned long flags; 905 size_t written; 906 bool is_empty; 907 908 spin_lock_irqsave(&info->slock, flags); 909 written = kfifo_in(&info->port.xmit_fifo, buf, count); 910 is_empty = kfifo_is_empty(&info->port.xmit_fifo); 911 spin_unlock_irqrestore(&info->slock, flags); 912 913 if (!is_empty && !tty->flow.stopped) 914 if (!tty->hw_stopped || mxser_16550A_or_MUST(info)) 915 mxser_start_tx(info); 916 917 return written; 918 } 919 920 static int mxser_put_char(struct tty_struct *tty, u8 ch) 921 { 922 struct mxser_port *info = tty->driver_data; 923 unsigned long flags; 924 int ret; 925 926 spin_lock_irqsave(&info->slock, flags); 927 ret = kfifo_put(&info->port.xmit_fifo, ch); 928 spin_unlock_irqrestore(&info->slock, flags); 929 930 return ret; 931 } 932 933 934 static void mxser_flush_chars(struct tty_struct *tty) 935 { 936 struct mxser_port *info = tty->driver_data; 937 938 if (kfifo_is_empty(&info->port.xmit_fifo) || tty->flow.stopped || 939 (tty->hw_stopped && !mxser_16550A_or_MUST(info))) 940 return; 941 942 mxser_start_tx(info); 943 } 944 945 static unsigned int mxser_write_room(struct tty_struct *tty) 946 { 947 struct mxser_port *info = tty->driver_data; 948 949 return kfifo_avail(&info->port.xmit_fifo); 950 } 951 952 static unsigned int mxser_chars_in_buffer(struct tty_struct *tty) 953 { 954 struct mxser_port *info = tty->driver_data; 955 956 return kfifo_len(&info->port.xmit_fifo); 957 } 958 959 /* 960 * ------------------------------------------------------------ 961 * friends of mxser_ioctl() 962 * ------------------------------------------------------------ 963 */ 964 static int mxser_get_serial_info(struct tty_struct *tty, 965 struct serial_struct *ss) 966 { 967 struct mxser_port *info = tty->driver_data; 968 struct tty_port *port = &info->port; 969 unsigned int closing_wait, close_delay; 970 971 mutex_lock(&port->mutex); 972 973 close_delay = jiffies_to_msecs(info->port.close_delay) / 10; 974 closing_wait = info->port.closing_wait; 975 if (closing_wait != ASYNC_CLOSING_WAIT_NONE) 976 closing_wait = jiffies_to_msecs(closing_wait) / 10; 977 978 ss->type = info->type; 979 ss->line = tty->index; 980 ss->port = info->ioaddr; 981 ss->irq = info->board->irq; 982 ss->flags = info->port.flags; 983 ss->baud_base = MXSER_BAUD_BASE; 984 ss->close_delay = close_delay; 985 ss->closing_wait = closing_wait; 986 ss->custom_divisor = MXSER_CUSTOM_DIVISOR; 987 mutex_unlock(&port->mutex); 988 return 0; 989 } 990 991 static int mxser_set_serial_info(struct tty_struct *tty, 992 struct serial_struct *ss) 993 { 994 struct mxser_port *info = tty->driver_data; 995 struct tty_port *port = &info->port; 996 speed_t baud; 997 unsigned long sl_flags; 998 unsigned int old_speed, close_delay, closing_wait; 999 int retval = 0; 1000 1001 if (tty_io_error(tty)) 1002 return -EIO; 1003 1004 mutex_lock(&port->mutex); 1005 1006 if (ss->irq != info->board->irq || 1007 ss->port != info->ioaddr) { 1008 mutex_unlock(&port->mutex); 1009 return -EINVAL; 1010 } 1011 1012 old_speed = port->flags & ASYNC_SPD_MASK; 1013 1014 close_delay = msecs_to_jiffies(ss->close_delay * 10); 1015 closing_wait = ss->closing_wait; 1016 if (closing_wait != ASYNC_CLOSING_WAIT_NONE) 1017 closing_wait = msecs_to_jiffies(closing_wait * 10); 1018 1019 if (!capable(CAP_SYS_ADMIN)) { 1020 if ((ss->baud_base != MXSER_BAUD_BASE) || 1021 (close_delay != port->close_delay) || 1022 (closing_wait != port->closing_wait) || 1023 ((ss->flags & ~ASYNC_USR_MASK) != (port->flags & ~ASYNC_USR_MASK))) { 1024 mutex_unlock(&port->mutex); 1025 return -EPERM; 1026 } 1027 port->flags = (port->flags & ~ASYNC_USR_MASK) | 1028 (ss->flags & ASYNC_USR_MASK); 1029 } else { 1030 /* 1031 * OK, past this point, all the error checking has been done. 1032 * At this point, we start making changes..... 1033 */ 1034 port->flags = ((port->flags & ~ASYNC_FLAGS) | 1035 (ss->flags & ASYNC_FLAGS)); 1036 port->close_delay = close_delay; 1037 port->closing_wait = closing_wait; 1038 if ((port->flags & ASYNC_SPD_MASK) == ASYNC_SPD_CUST && 1039 (ss->baud_base != MXSER_BAUD_BASE || 1040 ss->custom_divisor != 1041 MXSER_CUSTOM_DIVISOR)) { 1042 if (ss->custom_divisor == 0) { 1043 mutex_unlock(&port->mutex); 1044 return -EINVAL; 1045 } 1046 baud = ss->baud_base / ss->custom_divisor; 1047 tty_encode_baud_rate(tty, baud, baud); 1048 } 1049 1050 info->type = ss->type; 1051 1052 mxser_process_txrx_fifo(info); 1053 } 1054 1055 if (tty_port_initialized(port)) { 1056 if (old_speed != (port->flags & ASYNC_SPD_MASK)) { 1057 spin_lock_irqsave(&info->slock, sl_flags); 1058 mxser_change_speed(tty, NULL); 1059 spin_unlock_irqrestore(&info->slock, sl_flags); 1060 } 1061 } else { 1062 retval = mxser_activate(port, tty); 1063 if (retval == 0) 1064 tty_port_set_initialized(port, true); 1065 } 1066 mutex_unlock(&port->mutex); 1067 return retval; 1068 } 1069 1070 /* 1071 * mxser_get_lsr_info - get line status register info 1072 * 1073 * Purpose: Let user call ioctl() to get info when the UART physically 1074 * is emptied. On bus types like RS485, the transmitter must 1075 * release the bus after transmitting. This must be done when 1076 * the transmit shift register is empty, not be done when the 1077 * transmit holding register is empty. This functionality 1078 * allows an RS485 driver to be written in user space. 1079 */ 1080 static int mxser_get_lsr_info(struct mxser_port *info, 1081 unsigned int __user *value) 1082 { 1083 unsigned char status; 1084 unsigned int result; 1085 unsigned long flags; 1086 1087 spin_lock_irqsave(&info->slock, flags); 1088 status = inb(info->ioaddr + UART_LSR); 1089 spin_unlock_irqrestore(&info->slock, flags); 1090 result = ((status & UART_LSR_TEMT) ? TIOCSER_TEMT : 0); 1091 return put_user(result, value); 1092 } 1093 1094 static int mxser_tiocmget(struct tty_struct *tty) 1095 { 1096 struct mxser_port *info = tty->driver_data; 1097 unsigned char control; 1098 unsigned long flags; 1099 u8 msr; 1100 1101 if (tty_io_error(tty)) 1102 return -EIO; 1103 1104 spin_lock_irqsave(&info->slock, flags); 1105 control = info->MCR; 1106 msr = mxser_check_modem_status(tty, info); 1107 spin_unlock_irqrestore(&info->slock, flags); 1108 1109 return ((control & UART_MCR_RTS) ? TIOCM_RTS : 0) | 1110 ((control & UART_MCR_DTR) ? TIOCM_DTR : 0) | 1111 ((msr & UART_MSR_DCD) ? TIOCM_CAR : 0) | 1112 ((msr & UART_MSR_RI) ? TIOCM_RNG : 0) | 1113 ((msr & UART_MSR_DSR) ? TIOCM_DSR : 0) | 1114 ((msr & UART_MSR_CTS) ? TIOCM_CTS : 0); 1115 } 1116 1117 static int mxser_tiocmset(struct tty_struct *tty, 1118 unsigned int set, unsigned int clear) 1119 { 1120 struct mxser_port *info = tty->driver_data; 1121 unsigned long flags; 1122 1123 if (tty_io_error(tty)) 1124 return -EIO; 1125 1126 spin_lock_irqsave(&info->slock, flags); 1127 1128 if (set & TIOCM_RTS) 1129 info->MCR |= UART_MCR_RTS; 1130 if (set & TIOCM_DTR) 1131 info->MCR |= UART_MCR_DTR; 1132 1133 if (clear & TIOCM_RTS) 1134 info->MCR &= ~UART_MCR_RTS; 1135 if (clear & TIOCM_DTR) 1136 info->MCR &= ~UART_MCR_DTR; 1137 1138 outb(info->MCR, info->ioaddr + UART_MCR); 1139 spin_unlock_irqrestore(&info->slock, flags); 1140 return 0; 1141 } 1142 1143 static int mxser_cflags_changed(struct mxser_port *info, unsigned long arg, 1144 struct async_icount *cprev) 1145 { 1146 struct async_icount cnow; 1147 unsigned long flags; 1148 int ret; 1149 1150 spin_lock_irqsave(&info->slock, flags); 1151 cnow = info->icount; /* atomic copy */ 1152 spin_unlock_irqrestore(&info->slock, flags); 1153 1154 ret = ((arg & TIOCM_RNG) && (cnow.rng != cprev->rng)) || 1155 ((arg & TIOCM_DSR) && (cnow.dsr != cprev->dsr)) || 1156 ((arg & TIOCM_CD) && (cnow.dcd != cprev->dcd)) || 1157 ((arg & TIOCM_CTS) && (cnow.cts != cprev->cts)); 1158 1159 *cprev = cnow; 1160 1161 return ret; 1162 } 1163 1164 /* We should likely switch to TIOCGRS485/TIOCSRS485. */ 1165 static int mxser_ioctl_op_mode(struct mxser_port *port, int index, bool set, 1166 int __user *u_opmode) 1167 { 1168 int opmode, p = index % 4; 1169 int shiftbit = p * 2; 1170 u8 val; 1171 1172 if (port->board->must_hwid != MOXA_MUST_MU860_HWID) 1173 return -EFAULT; 1174 1175 if (set) { 1176 if (get_user(opmode, u_opmode)) 1177 return -EFAULT; 1178 1179 if (opmode & ~OP_MODE_MASK) 1180 return -EINVAL; 1181 1182 spin_lock_irq(&port->slock); 1183 val = inb(port->opmode_ioaddr); 1184 val &= ~(OP_MODE_MASK << shiftbit); 1185 val |= (opmode << shiftbit); 1186 outb(val, port->opmode_ioaddr); 1187 spin_unlock_irq(&port->slock); 1188 1189 return 0; 1190 } 1191 1192 spin_lock_irq(&port->slock); 1193 opmode = inb(port->opmode_ioaddr) >> shiftbit; 1194 spin_unlock_irq(&port->slock); 1195 1196 return put_user(opmode & OP_MODE_MASK, u_opmode); 1197 } 1198 1199 static int mxser_ioctl(struct tty_struct *tty, 1200 unsigned int cmd, unsigned long arg) 1201 { 1202 struct mxser_port *info = tty->driver_data; 1203 struct async_icount cnow; 1204 unsigned long flags; 1205 void __user *argp = (void __user *)arg; 1206 1207 if (cmd == MOXA_SET_OP_MODE || cmd == MOXA_GET_OP_MODE) 1208 return mxser_ioctl_op_mode(info, tty->index, 1209 cmd == MOXA_SET_OP_MODE, argp); 1210 1211 if (cmd != TIOCMIWAIT && tty_io_error(tty)) 1212 return -EIO; 1213 1214 switch (cmd) { 1215 case TIOCSERGETLSR: /* Get line status register */ 1216 return mxser_get_lsr_info(info, argp); 1217 /* 1218 * Wait for any of the 4 modem inputs (DCD,RI,DSR,CTS) to change 1219 * - mask passed in arg for lines of interest 1220 * (use |'ed TIOCM_RNG/DSR/CD/CTS for masking) 1221 * Caller should use TIOCGICOUNT to see which one it was 1222 */ 1223 case TIOCMIWAIT: 1224 spin_lock_irqsave(&info->slock, flags); 1225 cnow = info->icount; /* note the counters on entry */ 1226 spin_unlock_irqrestore(&info->slock, flags); 1227 1228 return wait_event_interruptible(info->port.delta_msr_wait, 1229 mxser_cflags_changed(info, arg, &cnow)); 1230 default: 1231 return -ENOIOCTLCMD; 1232 } 1233 return 0; 1234 } 1235 1236 /* 1237 * Get counter of input serial line interrupts (DCD,RI,DSR,CTS) 1238 * Return: write counters to the user passed counter struct 1239 * NB: both 1->0 and 0->1 transitions are counted except for 1240 * RI where only 0->1 is counted. 1241 */ 1242 1243 static int mxser_get_icount(struct tty_struct *tty, 1244 struct serial_icounter_struct *icount) 1245 1246 { 1247 struct mxser_port *info = tty->driver_data; 1248 struct async_icount cnow; 1249 unsigned long flags; 1250 1251 spin_lock_irqsave(&info->slock, flags); 1252 cnow = info->icount; 1253 spin_unlock_irqrestore(&info->slock, flags); 1254 1255 icount->frame = cnow.frame; 1256 icount->brk = cnow.brk; 1257 icount->overrun = cnow.overrun; 1258 icount->buf_overrun = cnow.buf_overrun; 1259 icount->parity = cnow.parity; 1260 icount->rx = cnow.rx; 1261 icount->tx = cnow.tx; 1262 icount->cts = cnow.cts; 1263 icount->dsr = cnow.dsr; 1264 icount->rng = cnow.rng; 1265 icount->dcd = cnow.dcd; 1266 return 0; 1267 } 1268 1269 /* 1270 * This routine is called by the upper-layer tty layer to signal that 1271 * incoming characters should be throttled. 1272 */ 1273 static void mxser_throttle(struct tty_struct *tty) 1274 { 1275 struct mxser_port *info = tty->driver_data; 1276 1277 if (I_IXOFF(tty)) { 1278 if (info->board->must_hwid) { 1279 info->IER &= ~MOXA_MUST_RECV_ISR; 1280 outb(info->IER, info->ioaddr + UART_IER); 1281 } else { 1282 info->x_char = STOP_CHAR(tty); 1283 outb(0, info->ioaddr + UART_IER); 1284 info->IER |= UART_IER_THRI; 1285 outb(info->IER, info->ioaddr + UART_IER); 1286 } 1287 } 1288 1289 if (C_CRTSCTS(tty)) { 1290 info->MCR &= ~UART_MCR_RTS; 1291 outb(info->MCR, info->ioaddr + UART_MCR); 1292 } 1293 } 1294 1295 static void mxser_unthrottle(struct tty_struct *tty) 1296 { 1297 struct mxser_port *info = tty->driver_data; 1298 1299 /* startrx */ 1300 if (I_IXOFF(tty)) { 1301 if (info->x_char) 1302 info->x_char = 0; 1303 else { 1304 if (info->board->must_hwid) { 1305 info->IER |= MOXA_MUST_RECV_ISR; 1306 outb(info->IER, info->ioaddr + UART_IER); 1307 } else { 1308 info->x_char = START_CHAR(tty); 1309 outb(0, info->ioaddr + UART_IER); 1310 info->IER |= UART_IER_THRI; 1311 outb(info->IER, info->ioaddr + UART_IER); 1312 } 1313 } 1314 } 1315 1316 if (C_CRTSCTS(tty)) { 1317 info->MCR |= UART_MCR_RTS; 1318 outb(info->MCR, info->ioaddr + UART_MCR); 1319 } 1320 } 1321 1322 /* 1323 * mxser_stop() and mxser_start() 1324 * 1325 * This routines are called before setting or resetting tty->flow.stopped. 1326 * They enable or disable transmitter interrupts, as necessary. 1327 */ 1328 static void mxser_stop(struct tty_struct *tty) 1329 { 1330 struct mxser_port *info = tty->driver_data; 1331 unsigned long flags; 1332 1333 spin_lock_irqsave(&info->slock, flags); 1334 if (info->IER & UART_IER_THRI) 1335 __mxser_stop_tx(info); 1336 spin_unlock_irqrestore(&info->slock, flags); 1337 } 1338 1339 static void mxser_start(struct tty_struct *tty) 1340 { 1341 struct mxser_port *info = tty->driver_data; 1342 unsigned long flags; 1343 1344 spin_lock_irqsave(&info->slock, flags); 1345 if (!kfifo_is_empty(&info->port.xmit_fifo)) 1346 __mxser_start_tx(info); 1347 spin_unlock_irqrestore(&info->slock, flags); 1348 } 1349 1350 static void mxser_set_termios(struct tty_struct *tty, 1351 const struct ktermios *old_termios) 1352 { 1353 struct mxser_port *info = tty->driver_data; 1354 unsigned long flags; 1355 1356 spin_lock_irqsave(&info->slock, flags); 1357 mxser_change_speed(tty, old_termios); 1358 spin_unlock_irqrestore(&info->slock, flags); 1359 1360 if ((old_termios->c_cflag & CRTSCTS) && !C_CRTSCTS(tty)) { 1361 tty->hw_stopped = false; 1362 mxser_start(tty); 1363 } 1364 1365 /* Handle sw stopped */ 1366 if ((old_termios->c_iflag & IXON) && !I_IXON(tty)) { 1367 tty->flow.stopped = 0; 1368 1369 if (info->board->must_hwid) { 1370 spin_lock_irqsave(&info->slock, flags); 1371 mxser_must_set_rx_sw_flow_control(info->ioaddr, false); 1372 spin_unlock_irqrestore(&info->slock, flags); 1373 } 1374 1375 mxser_start(tty); 1376 } 1377 } 1378 1379 static bool mxser_tx_empty(struct mxser_port *info) 1380 { 1381 unsigned long flags; 1382 u8 lsr; 1383 1384 spin_lock_irqsave(&info->slock, flags); 1385 lsr = inb(info->ioaddr + UART_LSR); 1386 spin_unlock_irqrestore(&info->slock, flags); 1387 1388 return !(lsr & UART_LSR_TEMT); 1389 } 1390 1391 /* 1392 * mxser_wait_until_sent() --- wait until the transmitter is empty 1393 */ 1394 static void mxser_wait_until_sent(struct tty_struct *tty, int timeout) 1395 { 1396 struct mxser_port *info = tty->driver_data; 1397 unsigned long expire, char_time; 1398 1399 if (info->type == PORT_UNKNOWN) 1400 return; 1401 1402 if (info->xmit_fifo_size == 0) 1403 return; /* Just in case.... */ 1404 1405 /* 1406 * Set the check interval to be 1/5 of the estimated time to 1407 * send a single character, and make it at least 1. The check 1408 * interval should also be less than the timeout. 1409 * 1410 * Note: we have to use pretty tight timings here to satisfy 1411 * the NIST-PCTS. 1412 */ 1413 char_time = (info->timeout - HZ / 50) / info->xmit_fifo_size; 1414 char_time = char_time / 5; 1415 if (char_time == 0) 1416 char_time = 1; 1417 if (timeout && timeout < char_time) 1418 char_time = timeout; 1419 1420 char_time = jiffies_to_msecs(char_time); 1421 1422 /* 1423 * If the transmitter hasn't cleared in twice the approximate 1424 * amount of time to send the entire FIFO, it probably won't 1425 * ever clear. This assumes the UART isn't doing flow 1426 * control, which is currently the case. Hence, if it ever 1427 * takes longer than info->timeout, this is probably due to a 1428 * UART bug of some kind. So, we clamp the timeout parameter at 1429 * 2*info->timeout. 1430 */ 1431 if (!timeout || timeout > 2 * info->timeout) 1432 timeout = 2 * info->timeout; 1433 1434 expire = jiffies + timeout; 1435 1436 while (mxser_tx_empty(info)) { 1437 msleep_interruptible(char_time); 1438 if (signal_pending(current)) 1439 break; 1440 if (time_after(jiffies, expire)) 1441 break; 1442 } 1443 } 1444 1445 /* 1446 * This routine is called by tty_hangup() when a hangup is signaled. 1447 */ 1448 static void mxser_hangup(struct tty_struct *tty) 1449 { 1450 struct mxser_port *info = tty->driver_data; 1451 1452 mxser_flush_buffer(tty); 1453 tty_port_hangup(&info->port); 1454 } 1455 1456 /* 1457 * mxser_rs_break() --- routine which turns the break handling on or off 1458 */ 1459 static int mxser_rs_break(struct tty_struct *tty, int break_state) 1460 { 1461 struct mxser_port *info = tty->driver_data; 1462 unsigned long flags; 1463 u8 lcr; 1464 1465 spin_lock_irqsave(&info->slock, flags); 1466 lcr = inb(info->ioaddr + UART_LCR); 1467 if (break_state == -1) 1468 lcr |= UART_LCR_SBC; 1469 else 1470 lcr &= ~UART_LCR_SBC; 1471 outb(lcr, info->ioaddr + UART_LCR); 1472 spin_unlock_irqrestore(&info->slock, flags); 1473 1474 return 0; 1475 } 1476 1477 static bool mxser_receive_chars_new(struct mxser_port *port, u8 status) 1478 { 1479 enum mxser_must_hwid hwid = port->board->must_hwid; 1480 u8 gdl; 1481 1482 if (hwid == MOXA_OTHER_UART) 1483 return false; 1484 if (status & (UART_LSR_BRK_ERROR_BITS | MOXA_MUST_LSR_RERR)) 1485 return false; 1486 1487 gdl = inb(port->ioaddr + MOXA_MUST_GDL_REGISTER); 1488 if (hwid == MOXA_MUST_MU150_HWID) 1489 gdl &= MOXA_MUST_GDL_MASK; 1490 1491 while (gdl--) { 1492 u8 ch = inb(port->ioaddr + UART_RX); 1493 if (!tty_insert_flip_char(&port->port, ch, 0)) 1494 port->icount.buf_overrun++; 1495 } 1496 1497 return true; 1498 } 1499 1500 static u8 mxser_receive_chars_old(struct tty_struct *tty, 1501 struct mxser_port *port, u8 status) 1502 { 1503 enum mxser_must_hwid hwid = port->board->must_hwid; 1504 int ignored = 0; 1505 int max = 256; 1506 u8 ch; 1507 1508 do { 1509 if (max-- < 0) 1510 break; 1511 1512 ch = inb(port->ioaddr + UART_RX); 1513 if (hwid && (status & UART_LSR_OE)) 1514 outb(port->FCR | UART_FCR_CLEAR_RCVR, 1515 port->ioaddr + UART_FCR); 1516 status &= port->read_status_mask; 1517 if (status & port->ignore_status_mask) { 1518 if (++ignored > 100) 1519 break; 1520 } else { 1521 u8 flag = 0; 1522 if (status & UART_LSR_BRK_ERROR_BITS) { 1523 if (status & UART_LSR_BI) { 1524 flag = TTY_BREAK; 1525 port->icount.brk++; 1526 1527 if (port->port.flags & ASYNC_SAK) 1528 do_SAK(tty); 1529 } else if (status & UART_LSR_PE) { 1530 flag = TTY_PARITY; 1531 port->icount.parity++; 1532 } else if (status & UART_LSR_FE) { 1533 flag = TTY_FRAME; 1534 port->icount.frame++; 1535 } else if (status & UART_LSR_OE) { 1536 flag = TTY_OVERRUN; 1537 port->icount.overrun++; 1538 } 1539 } 1540 if (!tty_insert_flip_char(&port->port, ch, flag)) { 1541 port->icount.buf_overrun++; 1542 break; 1543 } 1544 } 1545 1546 if (hwid) 1547 break; 1548 1549 status = inb(port->ioaddr + UART_LSR); 1550 } while (status & UART_LSR_DR); 1551 1552 return status; 1553 } 1554 1555 static u8 mxser_receive_chars(struct tty_struct *tty, 1556 struct mxser_port *port, u8 status) 1557 { 1558 if (!mxser_receive_chars_new(port, status)) 1559 status = mxser_receive_chars_old(tty, port, status); 1560 1561 tty_flip_buffer_push(&port->port); 1562 1563 return status; 1564 } 1565 1566 static void mxser_transmit_chars(struct tty_struct *tty, struct mxser_port *port) 1567 { 1568 int count; 1569 1570 if (port->x_char) { 1571 outb(port->x_char, port->ioaddr + UART_TX); 1572 port->x_char = 0; 1573 port->icount.tx++; 1574 return; 1575 } 1576 1577 if (kfifo_is_empty(&port->port.xmit_fifo) || tty->flow.stopped || 1578 (tty->hw_stopped && !mxser_16550A_or_MUST(port))) { 1579 __mxser_stop_tx(port); 1580 return; 1581 } 1582 1583 count = port->xmit_fifo_size; 1584 do { 1585 u8 c; 1586 1587 if (!kfifo_get(&port->port.xmit_fifo, &c)) 1588 break; 1589 1590 outb(c, port->ioaddr + UART_TX); 1591 port->icount.tx++; 1592 } while (--count > 0); 1593 1594 if (kfifo_len(&port->port.xmit_fifo) < WAKEUP_CHARS) 1595 tty_wakeup(tty); 1596 1597 if (kfifo_is_empty(&port->port.xmit_fifo)) 1598 __mxser_stop_tx(port); 1599 } 1600 1601 static bool mxser_port_isr(struct mxser_port *port) 1602 { 1603 struct tty_struct *tty; 1604 u8 iir, status; 1605 bool error = false; 1606 1607 iir = inb(port->ioaddr + UART_IIR); 1608 if (iir & UART_IIR_NO_INT) 1609 return true; 1610 1611 iir &= MOXA_MUST_IIR_MASK; 1612 tty = tty_port_tty_get(&port->port); 1613 if (!tty) { 1614 status = inb(port->ioaddr + UART_LSR); 1615 outb(port->FCR | UART_FCR_CLEAR_RCVR | UART_FCR_CLEAR_XMIT, 1616 port->ioaddr + UART_FCR); 1617 inb(port->ioaddr + UART_MSR); 1618 1619 error = true; 1620 goto put_tty; 1621 } 1622 1623 status = inb(port->ioaddr + UART_LSR); 1624 1625 if (port->board->must_hwid) { 1626 if (iir == MOXA_MUST_IIR_GDA || 1627 iir == MOXA_MUST_IIR_RDA || 1628 iir == MOXA_MUST_IIR_RTO || 1629 iir == MOXA_MUST_IIR_LSR) 1630 status = mxser_receive_chars(tty, port, status); 1631 } else { 1632 status &= port->read_status_mask; 1633 if (status & UART_LSR_DR) 1634 status = mxser_receive_chars(tty, port, status); 1635 } 1636 1637 mxser_check_modem_status(tty, port); 1638 1639 if (port->board->must_hwid) { 1640 if (iir == 0x02 && (status & UART_LSR_THRE)) 1641 mxser_transmit_chars(tty, port); 1642 } else { 1643 if (status & UART_LSR_THRE) 1644 mxser_transmit_chars(tty, port); 1645 } 1646 1647 put_tty: 1648 tty_kref_put(tty); 1649 1650 return error; 1651 } 1652 1653 /* 1654 * This is the serial driver's generic interrupt routine 1655 */ 1656 static irqreturn_t mxser_interrupt(int irq, void *dev_id) 1657 { 1658 struct mxser_board *brd = dev_id; 1659 struct mxser_port *port; 1660 unsigned int int_cnt, pass_counter = 0; 1661 unsigned int i, max = brd->nports; 1662 int handled = IRQ_NONE; 1663 u8 irqbits, bits, mask = BIT(max) - 1; 1664 1665 while (pass_counter++ < MXSER_ISR_PASS_LIMIT) { 1666 irqbits = inb(brd->vector) & mask; 1667 if (irqbits == mask) 1668 break; 1669 1670 handled = IRQ_HANDLED; 1671 for (i = 0, bits = 1; i < max; i++, irqbits |= bits, bits <<= 1) { 1672 if (irqbits == mask) 1673 break; 1674 if (bits & irqbits) 1675 continue; 1676 port = &brd->ports[i]; 1677 1678 int_cnt = 0; 1679 spin_lock(&port->slock); 1680 do { 1681 if (mxser_port_isr(port)) 1682 break; 1683 } while (int_cnt++ < MXSER_ISR_PASS_LIMIT); 1684 spin_unlock(&port->slock); 1685 } 1686 } 1687 1688 return handled; 1689 } 1690 1691 static const struct tty_operations mxser_ops = { 1692 .open = mxser_open, 1693 .close = mxser_close, 1694 .write = mxser_write, 1695 .put_char = mxser_put_char, 1696 .flush_chars = mxser_flush_chars, 1697 .write_room = mxser_write_room, 1698 .chars_in_buffer = mxser_chars_in_buffer, 1699 .flush_buffer = mxser_flush_buffer, 1700 .ioctl = mxser_ioctl, 1701 .throttle = mxser_throttle, 1702 .unthrottle = mxser_unthrottle, 1703 .set_termios = mxser_set_termios, 1704 .stop = mxser_stop, 1705 .start = mxser_start, 1706 .hangup = mxser_hangup, 1707 .break_ctl = mxser_rs_break, 1708 .wait_until_sent = mxser_wait_until_sent, 1709 .tiocmget = mxser_tiocmget, 1710 .tiocmset = mxser_tiocmset, 1711 .set_serial = mxser_set_serial_info, 1712 .get_serial = mxser_get_serial_info, 1713 .get_icount = mxser_get_icount, 1714 }; 1715 1716 static const struct tty_port_operations mxser_port_ops = { 1717 .carrier_raised = mxser_carrier_raised, 1718 .dtr_rts = mxser_dtr_rts, 1719 .activate = mxser_activate, 1720 .shutdown = mxser_shutdown_port, 1721 }; 1722 1723 /* 1724 * The MOXA Smartio/Industio serial driver boot-time initialization code! 1725 */ 1726 1727 static void mxser_initbrd(struct mxser_board *brd, bool high_baud) 1728 { 1729 struct mxser_port *info; 1730 unsigned int i; 1731 bool is_mu860; 1732 1733 brd->must_hwid = mxser_must_get_hwid(brd->ports[0].ioaddr); 1734 is_mu860 = brd->must_hwid == MOXA_MUST_MU860_HWID; 1735 1736 for (i = 0; i < UART_INFO_NUM; i++) { 1737 if (Gpci_uart_info[i].type == brd->must_hwid) { 1738 brd->max_baud = Gpci_uart_info[i].max_baud; 1739 1740 /* exception....CP-102 */ 1741 if (high_baud) 1742 brd->max_baud = 921600; 1743 break; 1744 } 1745 } 1746 1747 if (is_mu860) { 1748 /* set to RS232 mode by default */ 1749 outb(0, brd->vector + 4); 1750 outb(0, brd->vector + 0x0c); 1751 } 1752 1753 for (i = 0; i < brd->nports; i++) { 1754 info = &brd->ports[i]; 1755 if (is_mu860) { 1756 if (i < 4) 1757 info->opmode_ioaddr = brd->vector + 4; 1758 else 1759 info->opmode_ioaddr = brd->vector + 0x0c; 1760 } 1761 tty_port_init(&info->port); 1762 info->port.ops = &mxser_port_ops; 1763 info->board = brd; 1764 1765 /* Enhance mode enabled here */ 1766 if (brd->must_hwid != MOXA_OTHER_UART) 1767 mxser_must_set_enhance_mode(info->ioaddr, true); 1768 1769 info->type = PORT_16550A; 1770 1771 mxser_process_txrx_fifo(info); 1772 1773 spin_lock_init(&info->slock); 1774 1775 /* before set INT ISR, disable all int */ 1776 outb(inb(info->ioaddr + UART_IER) & 0xf0, 1777 info->ioaddr + UART_IER); 1778 } 1779 } 1780 1781 static int mxser_probe(struct pci_dev *pdev, 1782 const struct pci_device_id *ent) 1783 { 1784 struct mxser_board *brd; 1785 unsigned int i, base; 1786 unsigned long ioaddress; 1787 unsigned short nports = MXSER_NPORTS(ent->driver_data); 1788 struct device *tty_dev; 1789 int retval = -EINVAL; 1790 1791 i = find_first_zero_bit(mxser_boards, MXSER_BOARDS); 1792 if (i >= MXSER_BOARDS) { 1793 dev_err(&pdev->dev, "too many boards found (maximum %d), board " 1794 "not configured\n", MXSER_BOARDS); 1795 goto err; 1796 } 1797 1798 brd = devm_kzalloc(&pdev->dev, struct_size(brd, ports, nports), 1799 GFP_KERNEL); 1800 if (!brd) 1801 goto err; 1802 1803 brd->idx = i; 1804 __set_bit(brd->idx, mxser_boards); 1805 base = i * MXSER_PORTS_PER_BOARD; 1806 1807 retval = pcim_enable_device(pdev); 1808 if (retval) { 1809 dev_err(&pdev->dev, "PCI enable failed\n"); 1810 goto err_zero; 1811 } 1812 1813 /* io address */ 1814 ioaddress = pci_resource_start(pdev, 2); 1815 retval = pci_request_region(pdev, 2, "mxser(IO)"); 1816 if (retval) 1817 goto err_zero; 1818 1819 brd->nports = nports; 1820 for (i = 0; i < nports; i++) 1821 brd->ports[i].ioaddr = ioaddress + 8 * i; 1822 1823 /* vector */ 1824 ioaddress = pci_resource_start(pdev, 3); 1825 retval = pci_request_region(pdev, 3, "mxser(vector)"); 1826 if (retval) 1827 goto err_zero; 1828 brd->vector = ioaddress; 1829 1830 /* irq */ 1831 brd->irq = pdev->irq; 1832 1833 mxser_initbrd(brd, ent->driver_data & MXSER_HIGHBAUD); 1834 1835 retval = devm_request_irq(&pdev->dev, brd->irq, mxser_interrupt, 1836 IRQF_SHARED, "mxser", brd); 1837 if (retval) { 1838 dev_err(&pdev->dev, "request irq failed"); 1839 goto err_relbrd; 1840 } 1841 1842 for (i = 0; i < nports; i++) { 1843 tty_dev = tty_port_register_device(&brd->ports[i].port, 1844 mxvar_sdriver, base + i, &pdev->dev); 1845 if (IS_ERR(tty_dev)) { 1846 retval = PTR_ERR(tty_dev); 1847 for (; i > 0; i--) 1848 tty_unregister_device(mxvar_sdriver, 1849 base + i - 1); 1850 goto err_relbrd; 1851 } 1852 } 1853 1854 pci_set_drvdata(pdev, brd); 1855 1856 return 0; 1857 err_relbrd: 1858 for (i = 0; i < nports; i++) 1859 tty_port_destroy(&brd->ports[i].port); 1860 err_zero: 1861 __clear_bit(brd->idx, mxser_boards); 1862 err: 1863 return retval; 1864 } 1865 1866 static void mxser_remove(struct pci_dev *pdev) 1867 { 1868 struct mxser_board *brd = pci_get_drvdata(pdev); 1869 unsigned int i, base = brd->idx * MXSER_PORTS_PER_BOARD; 1870 1871 for (i = 0; i < brd->nports; i++) { 1872 tty_unregister_device(mxvar_sdriver, base + i); 1873 tty_port_destroy(&brd->ports[i].port); 1874 } 1875 1876 __clear_bit(brd->idx, mxser_boards); 1877 } 1878 1879 static struct pci_driver mxser_driver = { 1880 .name = "mxser", 1881 .id_table = mxser_pcibrds, 1882 .probe = mxser_probe, 1883 .remove = mxser_remove 1884 }; 1885 1886 static int __init mxser_module_init(void) 1887 { 1888 int retval; 1889 1890 mxvar_sdriver = tty_alloc_driver(MXSER_PORTS, TTY_DRIVER_REAL_RAW | 1891 TTY_DRIVER_DYNAMIC_DEV); 1892 if (IS_ERR(mxvar_sdriver)) 1893 return PTR_ERR(mxvar_sdriver); 1894 1895 /* Initialize the tty_driver structure */ 1896 mxvar_sdriver->name = "ttyMI"; 1897 mxvar_sdriver->major = ttymajor; 1898 mxvar_sdriver->minor_start = 0; 1899 mxvar_sdriver->type = TTY_DRIVER_TYPE_SERIAL; 1900 mxvar_sdriver->subtype = SERIAL_TYPE_NORMAL; 1901 mxvar_sdriver->init_termios = tty_std_termios; 1902 mxvar_sdriver->init_termios.c_cflag = B9600|CS8|CREAD|HUPCL|CLOCAL; 1903 tty_set_operations(mxvar_sdriver, &mxser_ops); 1904 1905 retval = tty_register_driver(mxvar_sdriver); 1906 if (retval) { 1907 printk(KERN_ERR "Couldn't install MOXA Smartio/Industio family " 1908 "tty driver !\n"); 1909 goto err_put; 1910 } 1911 1912 retval = pci_register_driver(&mxser_driver); 1913 if (retval) { 1914 printk(KERN_ERR "mxser: can't register pci driver\n"); 1915 goto err_unr; 1916 } 1917 1918 return 0; 1919 err_unr: 1920 tty_unregister_driver(mxvar_sdriver); 1921 err_put: 1922 tty_driver_kref_put(mxvar_sdriver); 1923 return retval; 1924 } 1925 1926 static void __exit mxser_module_exit(void) 1927 { 1928 pci_unregister_driver(&mxser_driver); 1929 tty_unregister_driver(mxvar_sdriver); 1930 tty_driver_kref_put(mxvar_sdriver); 1931 } 1932 1933 module_init(mxser_module_init); 1934 module_exit(mxser_module_exit); 1935