xref: /linux/drivers/thunderbolt/quirks.c (revision 79790b6818e96c58fe2bffee1b418c16e64e7b80)
11cb36293SMario Limonciello // SPDX-License-Identifier: GPL-2.0
21cb36293SMario Limonciello /*
31cb36293SMario Limonciello  * Thunderbolt driver - quirks
41cb36293SMario Limonciello  *
51cb36293SMario Limonciello  * Copyright (c) 2020 Mario Limonciello <mario.limonciello@dell.com>
61cb36293SMario Limonciello  */
71cb36293SMario Limonciello 
81cb36293SMario Limonciello #include "tb.h"
91cb36293SMario Limonciello 
quirk_force_power_link(struct tb_switch * sw)101cb36293SMario Limonciello static void quirk_force_power_link(struct tb_switch *sw)
111cb36293SMario Limonciello {
121cb36293SMario Limonciello 	sw->quirks |= QUIRK_FORCE_POWER_LINK_CONTROLLER;
13ccdb0900SMika Westerberg 	tb_sw_dbg(sw, "forcing power to link controller\n");
141cb36293SMario Limonciello }
151cb36293SMario Limonciello 
quirk_dp_credit_allocation(struct tb_switch * sw)167c37bb30SMika Westerberg static void quirk_dp_credit_allocation(struct tb_switch *sw)
177c37bb30SMika Westerberg {
187c37bb30SMika Westerberg 	if (sw->credit_allocation && sw->min_dp_main_credits == 56) {
197c37bb30SMika Westerberg 		sw->min_dp_main_credits = 18;
207c37bb30SMika Westerberg 		tb_sw_dbg(sw, "quirked DP main: %u\n", sw->min_dp_main_credits);
217c37bb30SMika Westerberg 	}
227c37bb30SMika Westerberg }
237c37bb30SMika Westerberg 
quirk_clx_disable(struct tb_switch * sw)247af9da8cSSanjay R Mehta static void quirk_clx_disable(struct tb_switch *sw)
257af9da8cSSanjay R Mehta {
267af9da8cSSanjay R Mehta 	sw->quirks |= QUIRK_NO_CLX;
277af9da8cSSanjay R Mehta 	tb_sw_dbg(sw, "disabling CL states\n");
287af9da8cSSanjay R Mehta }
297af9da8cSSanjay R Mehta 
quirk_usb3_maximum_bandwidth(struct tb_switch * sw)30f0a57dd3SGil Fine static void quirk_usb3_maximum_bandwidth(struct tb_switch *sw)
31f0a57dd3SGil Fine {
32f0a57dd3SGil Fine 	struct tb_port *port;
33f0a57dd3SGil Fine 
340c35ac18SMika Westerberg 	if (tb_switch_is_icm(sw))
350c35ac18SMika Westerberg 		return;
360c35ac18SMika Westerberg 
37f0a57dd3SGil Fine 	tb_switch_for_each_port(sw, port) {
38f0a57dd3SGil Fine 		if (!tb_port_is_usb3_down(port))
39f0a57dd3SGil Fine 			continue;
40f0a57dd3SGil Fine 		port->max_bw = 16376;
41f0a57dd3SGil Fine 		tb_port_dbg(port, "USB3 maximum bandwidth limited to %u Mb/s\n",
42f0a57dd3SGil Fine 			    port->max_bw);
43f0a57dd3SGil Fine 	}
44f0a57dd3SGil Fine }
45f0a57dd3SGil Fine 
quirk_block_rpm_in_redrive(struct tb_switch * sw)46*a75e0684SMika Westerberg static void quirk_block_rpm_in_redrive(struct tb_switch *sw)
47*a75e0684SMika Westerberg {
48*a75e0684SMika Westerberg 	sw->quirks |= QUIRK_KEEP_POWER_IN_DP_REDRIVE;
49*a75e0684SMika Westerberg 	tb_sw_dbg(sw, "preventing runtime PM in DP redrive mode\n");
50*a75e0684SMika Westerberg }
51*a75e0684SMika Westerberg 
521cb36293SMario Limonciello struct tb_quirk {
537c37bb30SMika Westerberg 	u16 hw_vendor_id;
547c37bb30SMika Westerberg 	u16 hw_device_id;
551cb36293SMario Limonciello 	u16 vendor;
561cb36293SMario Limonciello 	u16 device;
571cb36293SMario Limonciello 	void (*hook)(struct tb_switch *sw);
581cb36293SMario Limonciello };
591cb36293SMario Limonciello 
60ef7e1207SWei Yongjun static const struct tb_quirk tb_quirks[] = {
611cb36293SMario Limonciello 	/* Dell WD19TB supports self-authentication on unplug */
627c37bb30SMika Westerberg 	{ 0x0000, 0x0000, 0x00d4, 0xb070, quirk_force_power_link },
637c37bb30SMika Westerberg 	{ 0x0000, 0x0000, 0x00d4, 0xb071, quirk_force_power_link },
647c37bb30SMika Westerberg 	/*
657c37bb30SMika Westerberg 	 * Intel Goshen Ridge NVM 27 and before report wrong number of
667c37bb30SMika Westerberg 	 * DP buffers.
677c37bb30SMika Westerberg 	 */
687c37bb30SMika Westerberg 	{ 0x8087, 0x0b26, 0x0000, 0x0000, quirk_dp_credit_allocation },
697af9da8cSSanjay R Mehta 	/*
70f0a57dd3SGil Fine 	 * Limit the maximum USB3 bandwidth for the following Intel USB4
71f0a57dd3SGil Fine 	 * host routers due to a hardware issue.
72f0a57dd3SGil Fine 	 */
73f0a57dd3SGil Fine 	{ 0x8087, PCI_DEVICE_ID_INTEL_ADL_NHI0, 0x0000, 0x0000,
74f0a57dd3SGil Fine 		  quirk_usb3_maximum_bandwidth },
75f0a57dd3SGil Fine 	{ 0x8087, PCI_DEVICE_ID_INTEL_ADL_NHI1, 0x0000, 0x0000,
76f0a57dd3SGil Fine 		  quirk_usb3_maximum_bandwidth },
77f0a57dd3SGil Fine 	{ 0x8087, PCI_DEVICE_ID_INTEL_RPL_NHI0, 0x0000, 0x0000,
78f0a57dd3SGil Fine 		  quirk_usb3_maximum_bandwidth },
79f0a57dd3SGil Fine 	{ 0x8087, PCI_DEVICE_ID_INTEL_RPL_NHI1, 0x0000, 0x0000,
80f0a57dd3SGil Fine 		  quirk_usb3_maximum_bandwidth },
81f0a57dd3SGil Fine 	{ 0x8087, PCI_DEVICE_ID_INTEL_MTL_M_NHI0, 0x0000, 0x0000,
82f0a57dd3SGil Fine 		  quirk_usb3_maximum_bandwidth },
83f0a57dd3SGil Fine 	{ 0x8087, PCI_DEVICE_ID_INTEL_MTL_P_NHI0, 0x0000, 0x0000,
84f0a57dd3SGil Fine 		  quirk_usb3_maximum_bandwidth },
85f0a57dd3SGil Fine 	{ 0x8087, PCI_DEVICE_ID_INTEL_MTL_P_NHI1, 0x0000, 0x0000,
86f0a57dd3SGil Fine 		  quirk_usb3_maximum_bandwidth },
87f2bfa944SMika Westerberg 	{ 0x8087, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_80G_NHI, 0x0000, 0x0000,
88f2bfa944SMika Westerberg 		  quirk_usb3_maximum_bandwidth },
89f2bfa944SMika Westerberg 	{ 0x8087, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_40G_NHI, 0x0000, 0x0000,
90f2bfa944SMika Westerberg 		  quirk_usb3_maximum_bandwidth },
91f2bfa944SMika Westerberg 	{ 0x8087, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HUB_80G_BRIDGE, 0x0000, 0x0000,
92f2bfa944SMika Westerberg 		  quirk_usb3_maximum_bandwidth },
93f2bfa944SMika Westerberg 	{ 0x8087, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HUB_40G_BRIDGE, 0x0000, 0x0000,
94f2bfa944SMika Westerberg 		  quirk_usb3_maximum_bandwidth },
95f0a57dd3SGil Fine 	/*
96*a75e0684SMika Westerberg 	 * Block Runtime PM in DP redrive mode for Intel Barlow Ridge host
97*a75e0684SMika Westerberg 	 * controllers.
98*a75e0684SMika Westerberg 	 */
99*a75e0684SMika Westerberg 	{ 0x8087, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_80G_NHI, 0x0000, 0x0000,
100*a75e0684SMika Westerberg 		  quirk_block_rpm_in_redrive },
101*a75e0684SMika Westerberg 	{ 0x8087, PCI_DEVICE_ID_INTEL_BARLOW_RIDGE_HOST_40G_NHI, 0x0000, 0x0000,
102*a75e0684SMika Westerberg 		  quirk_block_rpm_in_redrive },
103*a75e0684SMika Westerberg 	/*
1047af9da8cSSanjay R Mehta 	 * CLx is not supported on AMD USB4 Yellow Carp and Pink Sardine platforms.
1057af9da8cSSanjay R Mehta 	 */
1067af9da8cSSanjay R Mehta 	{ 0x0438, 0x0208, 0x0000, 0x0000, quirk_clx_disable },
1077af9da8cSSanjay R Mehta 	{ 0x0438, 0x0209, 0x0000, 0x0000, quirk_clx_disable },
1087af9da8cSSanjay R Mehta 	{ 0x0438, 0x020a, 0x0000, 0x0000, quirk_clx_disable },
1097af9da8cSSanjay R Mehta 	{ 0x0438, 0x020b, 0x0000, 0x0000, quirk_clx_disable },
1101cb36293SMario Limonciello };
1111cb36293SMario Limonciello 
1121cb36293SMario Limonciello /**
1131cb36293SMario Limonciello  * tb_check_quirks() - Check for quirks to apply
1141cb36293SMario Limonciello  * @sw: Thunderbolt switch
1151cb36293SMario Limonciello  *
1169c8cac6aSMika Westerberg  * Apply any quirks for the Thunderbolt controller.
1171cb36293SMario Limonciello  */
tb_check_quirks(struct tb_switch * sw)1181cb36293SMario Limonciello void tb_check_quirks(struct tb_switch *sw)
1191cb36293SMario Limonciello {
1201cb36293SMario Limonciello 	int i;
1211cb36293SMario Limonciello 
1221cb36293SMario Limonciello 	for (i = 0; i < ARRAY_SIZE(tb_quirks); i++) {
1231cb36293SMario Limonciello 		const struct tb_quirk *q = &tb_quirks[i];
1241cb36293SMario Limonciello 
1257c37bb30SMika Westerberg 		if (q->hw_vendor_id && q->hw_vendor_id != sw->config.vendor_id)
1267c37bb30SMika Westerberg 			continue;
1277c37bb30SMika Westerberg 		if (q->hw_device_id && q->hw_device_id != sw->config.device_id)
1287c37bb30SMika Westerberg 			continue;
1297c37bb30SMika Westerberg 		if (q->vendor && q->vendor != sw->vendor)
1307c37bb30SMika Westerberg 			continue;
1317c37bb30SMika Westerberg 		if (q->device && q->device != sw->device)
1327c37bb30SMika Westerberg 			continue;
1337c37bb30SMika Westerberg 
134f14d177eSMika Westerberg 		tb_sw_dbg(sw, "running %ps\n", q->hook);
1351cb36293SMario Limonciello 		q->hook(sw);
1361cb36293SMario Limonciello 	}
1371cb36293SMario Limonciello }
138