1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Thunderbolt driver - NHI driver 4 * 5 * The NHI (native host interface) is the pci device that allows us to send and 6 * receive frames from the thunderbolt bus. 7 * 8 * Copyright (c) 2014 Andreas Noever <andreas.noever@gmail.com> 9 * Copyright (C) 2018, Intel Corporation 10 */ 11 12 #include <linux/pm_runtime.h> 13 #include <linux/slab.h> 14 #include <linux/errno.h> 15 #include <linux/pci.h> 16 #include <linux/interrupt.h> 17 #include <linux/module.h> 18 #include <linux/delay.h> 19 #include <linux/property.h> 20 #include <linux/platform_data/x86/apple.h> 21 22 #include "nhi.h" 23 #include "nhi_regs.h" 24 #include "tb.h" 25 26 #define RING_TYPE(ring) ((ring)->is_tx ? "TX ring" : "RX ring") 27 28 #define RING_FIRST_USABLE_HOPID 1 29 30 /* 31 * Minimal number of vectors when we use MSI-X. Two for control channel 32 * Rx/Tx and the rest four are for cross domain DMA paths. 33 */ 34 #define MSIX_MIN_VECS 6 35 #define MSIX_MAX_VECS 16 36 37 #define NHI_MAILBOX_TIMEOUT 500 /* ms */ 38 39 static int ring_interrupt_index(struct tb_ring *ring) 40 { 41 int bit = ring->hop; 42 if (!ring->is_tx) 43 bit += ring->nhi->hop_count; 44 return bit; 45 } 46 47 /* 48 * ring_interrupt_active() - activate/deactivate interrupts for a single ring 49 * 50 * ring->nhi->lock must be held. 51 */ 52 static void ring_interrupt_active(struct tb_ring *ring, bool active) 53 { 54 int reg = REG_RING_INTERRUPT_BASE + 55 ring_interrupt_index(ring) / 32 * 4; 56 int bit = ring_interrupt_index(ring) & 31; 57 int mask = 1 << bit; 58 u32 old, new; 59 60 if (ring->irq > 0) { 61 u32 step, shift, ivr, misc; 62 void __iomem *ivr_base; 63 int index; 64 65 if (ring->is_tx) 66 index = ring->hop; 67 else 68 index = ring->hop + ring->nhi->hop_count; 69 70 /* 71 * Ask the hardware to clear interrupt status bits automatically 72 * since we already know which interrupt was triggered. 73 */ 74 misc = ioread32(ring->nhi->iobase + REG_DMA_MISC); 75 if (!(misc & REG_DMA_MISC_INT_AUTO_CLEAR)) { 76 misc |= REG_DMA_MISC_INT_AUTO_CLEAR; 77 iowrite32(misc, ring->nhi->iobase + REG_DMA_MISC); 78 } 79 80 ivr_base = ring->nhi->iobase + REG_INT_VEC_ALLOC_BASE; 81 step = index / REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS; 82 shift = index % REG_INT_VEC_ALLOC_REGS * REG_INT_VEC_ALLOC_BITS; 83 ivr = ioread32(ivr_base + step); 84 ivr &= ~(REG_INT_VEC_ALLOC_MASK << shift); 85 if (active) 86 ivr |= ring->vector << shift; 87 iowrite32(ivr, ivr_base + step); 88 } 89 90 old = ioread32(ring->nhi->iobase + reg); 91 if (active) 92 new = old | mask; 93 else 94 new = old & ~mask; 95 96 dev_dbg(&ring->nhi->pdev->dev, 97 "%s interrupt at register %#x bit %d (%#x -> %#x)\n", 98 active ? "enabling" : "disabling", reg, bit, old, new); 99 100 if (new == old) 101 dev_WARN(&ring->nhi->pdev->dev, 102 "interrupt for %s %d is already %s\n", 103 RING_TYPE(ring), ring->hop, 104 active ? "enabled" : "disabled"); 105 iowrite32(new, ring->nhi->iobase + reg); 106 } 107 108 /* 109 * nhi_disable_interrupts() - disable interrupts for all rings 110 * 111 * Use only during init and shutdown. 112 */ 113 static void nhi_disable_interrupts(struct tb_nhi *nhi) 114 { 115 int i = 0; 116 /* disable interrupts */ 117 for (i = 0; i < RING_INTERRUPT_REG_COUNT(nhi); i++) 118 iowrite32(0, nhi->iobase + REG_RING_INTERRUPT_BASE + 4 * i); 119 120 /* clear interrupt status bits */ 121 for (i = 0; i < RING_NOTIFY_REG_COUNT(nhi); i++) 122 ioread32(nhi->iobase + REG_RING_NOTIFY_BASE + 4 * i); 123 } 124 125 /* ring helper methods */ 126 127 static void __iomem *ring_desc_base(struct tb_ring *ring) 128 { 129 void __iomem *io = ring->nhi->iobase; 130 io += ring->is_tx ? REG_TX_RING_BASE : REG_RX_RING_BASE; 131 io += ring->hop * 16; 132 return io; 133 } 134 135 static void __iomem *ring_options_base(struct tb_ring *ring) 136 { 137 void __iomem *io = ring->nhi->iobase; 138 io += ring->is_tx ? REG_TX_OPTIONS_BASE : REG_RX_OPTIONS_BASE; 139 io += ring->hop * 32; 140 return io; 141 } 142 143 static void ring_iowrite_cons(struct tb_ring *ring, u16 cons) 144 { 145 /* 146 * The other 16-bits in the register is read-only and writes to it 147 * are ignored by the hardware so we can save one ioread32() by 148 * filling the read-only bits with zeroes. 149 */ 150 iowrite32(cons, ring_desc_base(ring) + 8); 151 } 152 153 static void ring_iowrite_prod(struct tb_ring *ring, u16 prod) 154 { 155 /* See ring_iowrite_cons() above for explanation */ 156 iowrite32(prod << 16, ring_desc_base(ring) + 8); 157 } 158 159 static void ring_iowrite32desc(struct tb_ring *ring, u32 value, u32 offset) 160 { 161 iowrite32(value, ring_desc_base(ring) + offset); 162 } 163 164 static void ring_iowrite64desc(struct tb_ring *ring, u64 value, u32 offset) 165 { 166 iowrite32(value, ring_desc_base(ring) + offset); 167 iowrite32(value >> 32, ring_desc_base(ring) + offset + 4); 168 } 169 170 static void ring_iowrite32options(struct tb_ring *ring, u32 value, u32 offset) 171 { 172 iowrite32(value, ring_options_base(ring) + offset); 173 } 174 175 static bool ring_full(struct tb_ring *ring) 176 { 177 return ((ring->head + 1) % ring->size) == ring->tail; 178 } 179 180 static bool ring_empty(struct tb_ring *ring) 181 { 182 return ring->head == ring->tail; 183 } 184 185 /* 186 * ring_write_descriptors() - post frames from ring->queue to the controller 187 * 188 * ring->lock is held. 189 */ 190 static void ring_write_descriptors(struct tb_ring *ring) 191 { 192 struct ring_frame *frame, *n; 193 struct ring_desc *descriptor; 194 list_for_each_entry_safe(frame, n, &ring->queue, list) { 195 if (ring_full(ring)) 196 break; 197 list_move_tail(&frame->list, &ring->in_flight); 198 descriptor = &ring->descriptors[ring->head]; 199 descriptor->phys = frame->buffer_phy; 200 descriptor->time = 0; 201 descriptor->flags = RING_DESC_POSTED | RING_DESC_INTERRUPT; 202 if (ring->is_tx) { 203 descriptor->length = frame->size; 204 descriptor->eof = frame->eof; 205 descriptor->sof = frame->sof; 206 } 207 ring->head = (ring->head + 1) % ring->size; 208 if (ring->is_tx) 209 ring_iowrite_prod(ring, ring->head); 210 else 211 ring_iowrite_cons(ring, ring->head); 212 } 213 } 214 215 /* 216 * ring_work() - progress completed frames 217 * 218 * If the ring is shutting down then all frames are marked as canceled and 219 * their callbacks are invoked. 220 * 221 * Otherwise we collect all completed frame from the ring buffer, write new 222 * frame to the ring buffer and invoke the callbacks for the completed frames. 223 */ 224 static void ring_work(struct work_struct *work) 225 { 226 struct tb_ring *ring = container_of(work, typeof(*ring), work); 227 struct ring_frame *frame; 228 bool canceled = false; 229 unsigned long flags; 230 LIST_HEAD(done); 231 232 spin_lock_irqsave(&ring->lock, flags); 233 234 if (!ring->running) { 235 /* Move all frames to done and mark them as canceled. */ 236 list_splice_tail_init(&ring->in_flight, &done); 237 list_splice_tail_init(&ring->queue, &done); 238 canceled = true; 239 goto invoke_callback; 240 } 241 242 while (!ring_empty(ring)) { 243 if (!(ring->descriptors[ring->tail].flags 244 & RING_DESC_COMPLETED)) 245 break; 246 frame = list_first_entry(&ring->in_flight, typeof(*frame), 247 list); 248 list_move_tail(&frame->list, &done); 249 if (!ring->is_tx) { 250 frame->size = ring->descriptors[ring->tail].length; 251 frame->eof = ring->descriptors[ring->tail].eof; 252 frame->sof = ring->descriptors[ring->tail].sof; 253 frame->flags = ring->descriptors[ring->tail].flags; 254 } 255 ring->tail = (ring->tail + 1) % ring->size; 256 } 257 ring_write_descriptors(ring); 258 259 invoke_callback: 260 /* allow callbacks to schedule new work */ 261 spin_unlock_irqrestore(&ring->lock, flags); 262 while (!list_empty(&done)) { 263 frame = list_first_entry(&done, typeof(*frame), list); 264 /* 265 * The callback may reenqueue or delete frame. 266 * Do not hold on to it. 267 */ 268 list_del_init(&frame->list); 269 if (frame->callback) 270 frame->callback(ring, frame, canceled); 271 } 272 } 273 274 int __tb_ring_enqueue(struct tb_ring *ring, struct ring_frame *frame) 275 { 276 unsigned long flags; 277 int ret = 0; 278 279 spin_lock_irqsave(&ring->lock, flags); 280 if (ring->running) { 281 list_add_tail(&frame->list, &ring->queue); 282 ring_write_descriptors(ring); 283 } else { 284 ret = -ESHUTDOWN; 285 } 286 spin_unlock_irqrestore(&ring->lock, flags); 287 return ret; 288 } 289 EXPORT_SYMBOL_GPL(__tb_ring_enqueue); 290 291 /** 292 * tb_ring_poll() - Poll one completed frame from the ring 293 * @ring: Ring to poll 294 * 295 * This function can be called when @start_poll callback of the @ring 296 * has been called. It will read one completed frame from the ring and 297 * return it to the caller. Returns %NULL if there is no more completed 298 * frames. 299 */ 300 struct ring_frame *tb_ring_poll(struct tb_ring *ring) 301 { 302 struct ring_frame *frame = NULL; 303 unsigned long flags; 304 305 spin_lock_irqsave(&ring->lock, flags); 306 if (!ring->running) 307 goto unlock; 308 if (ring_empty(ring)) 309 goto unlock; 310 311 if (ring->descriptors[ring->tail].flags & RING_DESC_COMPLETED) { 312 frame = list_first_entry(&ring->in_flight, typeof(*frame), 313 list); 314 list_del_init(&frame->list); 315 316 if (!ring->is_tx) { 317 frame->size = ring->descriptors[ring->tail].length; 318 frame->eof = ring->descriptors[ring->tail].eof; 319 frame->sof = ring->descriptors[ring->tail].sof; 320 frame->flags = ring->descriptors[ring->tail].flags; 321 } 322 323 ring->tail = (ring->tail + 1) % ring->size; 324 } 325 326 unlock: 327 spin_unlock_irqrestore(&ring->lock, flags); 328 return frame; 329 } 330 EXPORT_SYMBOL_GPL(tb_ring_poll); 331 332 static void __ring_interrupt_mask(struct tb_ring *ring, bool mask) 333 { 334 int idx = ring_interrupt_index(ring); 335 int reg = REG_RING_INTERRUPT_BASE + idx / 32 * 4; 336 int bit = idx % 32; 337 u32 val; 338 339 val = ioread32(ring->nhi->iobase + reg); 340 if (mask) 341 val &= ~BIT(bit); 342 else 343 val |= BIT(bit); 344 iowrite32(val, ring->nhi->iobase + reg); 345 } 346 347 /* Both @nhi->lock and @ring->lock should be held */ 348 static void __ring_interrupt(struct tb_ring *ring) 349 { 350 if (!ring->running) 351 return; 352 353 if (ring->start_poll) { 354 __ring_interrupt_mask(ring, true); 355 ring->start_poll(ring->poll_data); 356 } else { 357 schedule_work(&ring->work); 358 } 359 } 360 361 /** 362 * tb_ring_poll_complete() - Re-start interrupt for the ring 363 * @ring: Ring to re-start the interrupt 364 * 365 * This will re-start (unmask) the ring interrupt once the user is done 366 * with polling. 367 */ 368 void tb_ring_poll_complete(struct tb_ring *ring) 369 { 370 unsigned long flags; 371 372 spin_lock_irqsave(&ring->nhi->lock, flags); 373 spin_lock(&ring->lock); 374 if (ring->start_poll) 375 __ring_interrupt_mask(ring, false); 376 spin_unlock(&ring->lock); 377 spin_unlock_irqrestore(&ring->nhi->lock, flags); 378 } 379 EXPORT_SYMBOL_GPL(tb_ring_poll_complete); 380 381 static irqreturn_t ring_msix(int irq, void *data) 382 { 383 struct tb_ring *ring = data; 384 385 spin_lock(&ring->nhi->lock); 386 spin_lock(&ring->lock); 387 __ring_interrupt(ring); 388 spin_unlock(&ring->lock); 389 spin_unlock(&ring->nhi->lock); 390 391 return IRQ_HANDLED; 392 } 393 394 static int ring_request_msix(struct tb_ring *ring, bool no_suspend) 395 { 396 struct tb_nhi *nhi = ring->nhi; 397 unsigned long irqflags; 398 int ret; 399 400 if (!nhi->pdev->msix_enabled) 401 return 0; 402 403 ret = ida_simple_get(&nhi->msix_ida, 0, MSIX_MAX_VECS, GFP_KERNEL); 404 if (ret < 0) 405 return ret; 406 407 ring->vector = ret; 408 409 ret = pci_irq_vector(ring->nhi->pdev, ring->vector); 410 if (ret < 0) 411 goto err_ida_remove; 412 413 ring->irq = ret; 414 415 irqflags = no_suspend ? IRQF_NO_SUSPEND : 0; 416 ret = request_irq(ring->irq, ring_msix, irqflags, "thunderbolt", ring); 417 if (ret) 418 goto err_ida_remove; 419 420 return 0; 421 422 err_ida_remove: 423 ida_simple_remove(&nhi->msix_ida, ring->vector); 424 425 return ret; 426 } 427 428 static void ring_release_msix(struct tb_ring *ring) 429 { 430 if (ring->irq <= 0) 431 return; 432 433 free_irq(ring->irq, ring); 434 ida_simple_remove(&ring->nhi->msix_ida, ring->vector); 435 ring->vector = 0; 436 ring->irq = 0; 437 } 438 439 static int nhi_alloc_hop(struct tb_nhi *nhi, struct tb_ring *ring) 440 { 441 int ret = 0; 442 443 spin_lock_irq(&nhi->lock); 444 445 if (ring->hop < 0) { 446 unsigned int i; 447 448 /* 449 * Automatically allocate HopID from the non-reserved 450 * range 1 .. hop_count - 1. 451 */ 452 for (i = RING_FIRST_USABLE_HOPID; i < nhi->hop_count; i++) { 453 if (ring->is_tx) { 454 if (!nhi->tx_rings[i]) { 455 ring->hop = i; 456 break; 457 } 458 } else { 459 if (!nhi->rx_rings[i]) { 460 ring->hop = i; 461 break; 462 } 463 } 464 } 465 } 466 467 if (ring->hop < 0 || ring->hop >= nhi->hop_count) { 468 dev_warn(&nhi->pdev->dev, "invalid hop: %d\n", ring->hop); 469 ret = -EINVAL; 470 goto err_unlock; 471 } 472 if (ring->is_tx && nhi->tx_rings[ring->hop]) { 473 dev_warn(&nhi->pdev->dev, "TX hop %d already allocated\n", 474 ring->hop); 475 ret = -EBUSY; 476 goto err_unlock; 477 } else if (!ring->is_tx && nhi->rx_rings[ring->hop]) { 478 dev_warn(&nhi->pdev->dev, "RX hop %d already allocated\n", 479 ring->hop); 480 ret = -EBUSY; 481 goto err_unlock; 482 } 483 484 if (ring->is_tx) 485 nhi->tx_rings[ring->hop] = ring; 486 else 487 nhi->rx_rings[ring->hop] = ring; 488 489 err_unlock: 490 spin_unlock_irq(&nhi->lock); 491 492 return ret; 493 } 494 495 static struct tb_ring *tb_ring_alloc(struct tb_nhi *nhi, u32 hop, int size, 496 bool transmit, unsigned int flags, 497 int e2e_tx_hop, u16 sof_mask, u16 eof_mask, 498 void (*start_poll)(void *), 499 void *poll_data) 500 { 501 struct tb_ring *ring = NULL; 502 503 dev_dbg(&nhi->pdev->dev, "allocating %s ring %d of size %d\n", 504 transmit ? "TX" : "RX", hop, size); 505 506 ring = kzalloc(sizeof(*ring), GFP_KERNEL); 507 if (!ring) 508 return NULL; 509 510 spin_lock_init(&ring->lock); 511 INIT_LIST_HEAD(&ring->queue); 512 INIT_LIST_HEAD(&ring->in_flight); 513 INIT_WORK(&ring->work, ring_work); 514 515 ring->nhi = nhi; 516 ring->hop = hop; 517 ring->is_tx = transmit; 518 ring->size = size; 519 ring->flags = flags; 520 ring->e2e_tx_hop = e2e_tx_hop; 521 ring->sof_mask = sof_mask; 522 ring->eof_mask = eof_mask; 523 ring->head = 0; 524 ring->tail = 0; 525 ring->running = false; 526 ring->start_poll = start_poll; 527 ring->poll_data = poll_data; 528 529 ring->descriptors = dma_alloc_coherent(&ring->nhi->pdev->dev, 530 size * sizeof(*ring->descriptors), 531 &ring->descriptors_dma, GFP_KERNEL | __GFP_ZERO); 532 if (!ring->descriptors) 533 goto err_free_ring; 534 535 if (ring_request_msix(ring, flags & RING_FLAG_NO_SUSPEND)) 536 goto err_free_descs; 537 538 if (nhi_alloc_hop(nhi, ring)) 539 goto err_release_msix; 540 541 return ring; 542 543 err_release_msix: 544 ring_release_msix(ring); 545 err_free_descs: 546 dma_free_coherent(&ring->nhi->pdev->dev, 547 ring->size * sizeof(*ring->descriptors), 548 ring->descriptors, ring->descriptors_dma); 549 err_free_ring: 550 kfree(ring); 551 552 return NULL; 553 } 554 555 /** 556 * tb_ring_alloc_tx() - Allocate DMA ring for transmit 557 * @nhi: Pointer to the NHI the ring is to be allocated 558 * @hop: HopID (ring) to allocate 559 * @size: Number of entries in the ring 560 * @flags: Flags for the ring 561 */ 562 struct tb_ring *tb_ring_alloc_tx(struct tb_nhi *nhi, int hop, int size, 563 unsigned int flags) 564 { 565 return tb_ring_alloc(nhi, hop, size, true, flags, 0, 0, 0, NULL, NULL); 566 } 567 EXPORT_SYMBOL_GPL(tb_ring_alloc_tx); 568 569 /** 570 * tb_ring_alloc_rx() - Allocate DMA ring for receive 571 * @nhi: Pointer to the NHI the ring is to be allocated 572 * @hop: HopID (ring) to allocate. Pass %-1 for automatic allocation. 573 * @size: Number of entries in the ring 574 * @flags: Flags for the ring 575 * @e2e_tx_hop: Transmit HopID when E2E is enabled in @flags 576 * @sof_mask: Mask of PDF values that start a frame 577 * @eof_mask: Mask of PDF values that end a frame 578 * @start_poll: If not %NULL the ring will call this function when an 579 * interrupt is triggered and masked, instead of callback 580 * in each Rx frame. 581 * @poll_data: Optional data passed to @start_poll 582 */ 583 struct tb_ring *tb_ring_alloc_rx(struct tb_nhi *nhi, int hop, int size, 584 unsigned int flags, int e2e_tx_hop, 585 u16 sof_mask, u16 eof_mask, 586 void (*start_poll)(void *), void *poll_data) 587 { 588 return tb_ring_alloc(nhi, hop, size, false, flags, e2e_tx_hop, sof_mask, eof_mask, 589 start_poll, poll_data); 590 } 591 EXPORT_SYMBOL_GPL(tb_ring_alloc_rx); 592 593 /** 594 * tb_ring_start() - enable a ring 595 * @ring: Ring to start 596 * 597 * Must not be invoked in parallel with tb_ring_stop(). 598 */ 599 void tb_ring_start(struct tb_ring *ring) 600 { 601 u16 frame_size; 602 u32 flags; 603 604 spin_lock_irq(&ring->nhi->lock); 605 spin_lock(&ring->lock); 606 if (ring->nhi->going_away) 607 goto err; 608 if (ring->running) { 609 dev_WARN(&ring->nhi->pdev->dev, "ring already started\n"); 610 goto err; 611 } 612 dev_dbg(&ring->nhi->pdev->dev, "starting %s %d\n", 613 RING_TYPE(ring), ring->hop); 614 615 if (ring->flags & RING_FLAG_FRAME) { 616 /* Means 4096 */ 617 frame_size = 0; 618 flags = RING_FLAG_ENABLE; 619 } else { 620 frame_size = TB_FRAME_SIZE; 621 flags = RING_FLAG_ENABLE | RING_FLAG_RAW; 622 } 623 624 ring_iowrite64desc(ring, ring->descriptors_dma, 0); 625 if (ring->is_tx) { 626 ring_iowrite32desc(ring, ring->size, 12); 627 ring_iowrite32options(ring, 0, 4); /* time releated ? */ 628 ring_iowrite32options(ring, flags, 0); 629 } else { 630 u32 sof_eof_mask = ring->sof_mask << 16 | ring->eof_mask; 631 632 ring_iowrite32desc(ring, (frame_size << 16) | ring->size, 12); 633 ring_iowrite32options(ring, sof_eof_mask, 4); 634 ring_iowrite32options(ring, flags, 0); 635 } 636 637 /* 638 * Now that the ring valid bit is set we can configure E2E if 639 * enabled for the ring. 640 */ 641 if (ring->flags & RING_FLAG_E2E) { 642 if (!ring->is_tx) { 643 u32 hop; 644 645 hop = ring->e2e_tx_hop << REG_RX_OPTIONS_E2E_HOP_SHIFT; 646 hop &= REG_RX_OPTIONS_E2E_HOP_MASK; 647 flags |= hop; 648 649 dev_dbg(&ring->nhi->pdev->dev, 650 "enabling E2E for %s %d with TX HopID %d\n", 651 RING_TYPE(ring), ring->hop, ring->e2e_tx_hop); 652 } else { 653 dev_dbg(&ring->nhi->pdev->dev, "enabling E2E for %s %d\n", 654 RING_TYPE(ring), ring->hop); 655 } 656 657 flags |= RING_FLAG_E2E_FLOW_CONTROL; 658 ring_iowrite32options(ring, flags, 0); 659 } 660 661 ring_interrupt_active(ring, true); 662 ring->running = true; 663 err: 664 spin_unlock(&ring->lock); 665 spin_unlock_irq(&ring->nhi->lock); 666 } 667 EXPORT_SYMBOL_GPL(tb_ring_start); 668 669 /** 670 * tb_ring_stop() - shutdown a ring 671 * @ring: Ring to stop 672 * 673 * Must not be invoked from a callback. 674 * 675 * This method will disable the ring. Further calls to 676 * tb_ring_tx/tb_ring_rx will return -ESHUTDOWN until ring_stop has been 677 * called. 678 * 679 * All enqueued frames will be canceled and their callbacks will be executed 680 * with frame->canceled set to true (on the callback thread). This method 681 * returns only after all callback invocations have finished. 682 */ 683 void tb_ring_stop(struct tb_ring *ring) 684 { 685 spin_lock_irq(&ring->nhi->lock); 686 spin_lock(&ring->lock); 687 dev_dbg(&ring->nhi->pdev->dev, "stopping %s %d\n", 688 RING_TYPE(ring), ring->hop); 689 if (ring->nhi->going_away) 690 goto err; 691 if (!ring->running) { 692 dev_WARN(&ring->nhi->pdev->dev, "%s %d already stopped\n", 693 RING_TYPE(ring), ring->hop); 694 goto err; 695 } 696 ring_interrupt_active(ring, false); 697 698 ring_iowrite32options(ring, 0, 0); 699 ring_iowrite64desc(ring, 0, 0); 700 ring_iowrite32desc(ring, 0, 8); 701 ring_iowrite32desc(ring, 0, 12); 702 ring->head = 0; 703 ring->tail = 0; 704 ring->running = false; 705 706 err: 707 spin_unlock(&ring->lock); 708 spin_unlock_irq(&ring->nhi->lock); 709 710 /* 711 * schedule ring->work to invoke callbacks on all remaining frames. 712 */ 713 schedule_work(&ring->work); 714 flush_work(&ring->work); 715 } 716 EXPORT_SYMBOL_GPL(tb_ring_stop); 717 718 /* 719 * tb_ring_free() - free ring 720 * 721 * When this method returns all invocations of ring->callback will have 722 * finished. 723 * 724 * Ring must be stopped. 725 * 726 * Must NOT be called from ring_frame->callback! 727 */ 728 void tb_ring_free(struct tb_ring *ring) 729 { 730 spin_lock_irq(&ring->nhi->lock); 731 /* 732 * Dissociate the ring from the NHI. This also ensures that 733 * nhi_interrupt_work cannot reschedule ring->work. 734 */ 735 if (ring->is_tx) 736 ring->nhi->tx_rings[ring->hop] = NULL; 737 else 738 ring->nhi->rx_rings[ring->hop] = NULL; 739 740 if (ring->running) { 741 dev_WARN(&ring->nhi->pdev->dev, "%s %d still running\n", 742 RING_TYPE(ring), ring->hop); 743 } 744 spin_unlock_irq(&ring->nhi->lock); 745 746 ring_release_msix(ring); 747 748 dma_free_coherent(&ring->nhi->pdev->dev, 749 ring->size * sizeof(*ring->descriptors), 750 ring->descriptors, ring->descriptors_dma); 751 752 ring->descriptors = NULL; 753 ring->descriptors_dma = 0; 754 755 756 dev_dbg(&ring->nhi->pdev->dev, "freeing %s %d\n", RING_TYPE(ring), 757 ring->hop); 758 759 /* 760 * ring->work can no longer be scheduled (it is scheduled only 761 * by nhi_interrupt_work, ring_stop and ring_msix). Wait for it 762 * to finish before freeing the ring. 763 */ 764 flush_work(&ring->work); 765 kfree(ring); 766 } 767 EXPORT_SYMBOL_GPL(tb_ring_free); 768 769 /** 770 * nhi_mailbox_cmd() - Send a command through NHI mailbox 771 * @nhi: Pointer to the NHI structure 772 * @cmd: Command to send 773 * @data: Data to be send with the command 774 * 775 * Sends mailbox command to the firmware running on NHI. Returns %0 in 776 * case of success and negative errno in case of failure. 777 */ 778 int nhi_mailbox_cmd(struct tb_nhi *nhi, enum nhi_mailbox_cmd cmd, u32 data) 779 { 780 ktime_t timeout; 781 u32 val; 782 783 iowrite32(data, nhi->iobase + REG_INMAIL_DATA); 784 785 val = ioread32(nhi->iobase + REG_INMAIL_CMD); 786 val &= ~(REG_INMAIL_CMD_MASK | REG_INMAIL_ERROR); 787 val |= REG_INMAIL_OP_REQUEST | cmd; 788 iowrite32(val, nhi->iobase + REG_INMAIL_CMD); 789 790 timeout = ktime_add_ms(ktime_get(), NHI_MAILBOX_TIMEOUT); 791 do { 792 val = ioread32(nhi->iobase + REG_INMAIL_CMD); 793 if (!(val & REG_INMAIL_OP_REQUEST)) 794 break; 795 usleep_range(10, 20); 796 } while (ktime_before(ktime_get(), timeout)); 797 798 if (val & REG_INMAIL_OP_REQUEST) 799 return -ETIMEDOUT; 800 if (val & REG_INMAIL_ERROR) 801 return -EIO; 802 803 return 0; 804 } 805 806 /** 807 * nhi_mailbox_mode() - Return current firmware operation mode 808 * @nhi: Pointer to the NHI structure 809 * 810 * The function reads current firmware operation mode using NHI mailbox 811 * registers and returns it to the caller. 812 */ 813 enum nhi_fw_mode nhi_mailbox_mode(struct tb_nhi *nhi) 814 { 815 u32 val; 816 817 val = ioread32(nhi->iobase + REG_OUTMAIL_CMD); 818 val &= REG_OUTMAIL_CMD_OPMODE_MASK; 819 val >>= REG_OUTMAIL_CMD_OPMODE_SHIFT; 820 821 return (enum nhi_fw_mode)val; 822 } 823 824 static void nhi_interrupt_work(struct work_struct *work) 825 { 826 struct tb_nhi *nhi = container_of(work, typeof(*nhi), interrupt_work); 827 int value = 0; /* Suppress uninitialized usage warning. */ 828 int bit; 829 int hop = -1; 830 int type = 0; /* current interrupt type 0: TX, 1: RX, 2: RX overflow */ 831 struct tb_ring *ring; 832 833 spin_lock_irq(&nhi->lock); 834 835 /* 836 * Starting at REG_RING_NOTIFY_BASE there are three status bitfields 837 * (TX, RX, RX overflow). We iterate over the bits and read a new 838 * dwords as required. The registers are cleared on read. 839 */ 840 for (bit = 0; bit < 3 * nhi->hop_count; bit++) { 841 if (bit % 32 == 0) 842 value = ioread32(nhi->iobase 843 + REG_RING_NOTIFY_BASE 844 + 4 * (bit / 32)); 845 if (++hop == nhi->hop_count) { 846 hop = 0; 847 type++; 848 } 849 if ((value & (1 << (bit % 32))) == 0) 850 continue; 851 if (type == 2) { 852 dev_warn(&nhi->pdev->dev, 853 "RX overflow for ring %d\n", 854 hop); 855 continue; 856 } 857 if (type == 0) 858 ring = nhi->tx_rings[hop]; 859 else 860 ring = nhi->rx_rings[hop]; 861 if (ring == NULL) { 862 dev_warn(&nhi->pdev->dev, 863 "got interrupt for inactive %s ring %d\n", 864 type ? "RX" : "TX", 865 hop); 866 continue; 867 } 868 869 spin_lock(&ring->lock); 870 __ring_interrupt(ring); 871 spin_unlock(&ring->lock); 872 } 873 spin_unlock_irq(&nhi->lock); 874 } 875 876 static irqreturn_t nhi_msi(int irq, void *data) 877 { 878 struct tb_nhi *nhi = data; 879 schedule_work(&nhi->interrupt_work); 880 return IRQ_HANDLED; 881 } 882 883 static int __nhi_suspend_noirq(struct device *dev, bool wakeup) 884 { 885 struct pci_dev *pdev = to_pci_dev(dev); 886 struct tb *tb = pci_get_drvdata(pdev); 887 struct tb_nhi *nhi = tb->nhi; 888 int ret; 889 890 ret = tb_domain_suspend_noirq(tb); 891 if (ret) 892 return ret; 893 894 if (nhi->ops && nhi->ops->suspend_noirq) { 895 ret = nhi->ops->suspend_noirq(tb->nhi, wakeup); 896 if (ret) 897 return ret; 898 } 899 900 return 0; 901 } 902 903 static int nhi_suspend_noirq(struct device *dev) 904 { 905 return __nhi_suspend_noirq(dev, device_may_wakeup(dev)); 906 } 907 908 static int nhi_freeze_noirq(struct device *dev) 909 { 910 struct pci_dev *pdev = to_pci_dev(dev); 911 struct tb *tb = pci_get_drvdata(pdev); 912 913 return tb_domain_freeze_noirq(tb); 914 } 915 916 static int nhi_thaw_noirq(struct device *dev) 917 { 918 struct pci_dev *pdev = to_pci_dev(dev); 919 struct tb *tb = pci_get_drvdata(pdev); 920 921 return tb_domain_thaw_noirq(tb); 922 } 923 924 static bool nhi_wake_supported(struct pci_dev *pdev) 925 { 926 u8 val; 927 928 /* 929 * If power rails are sustainable for wakeup from S4 this 930 * property is set by the BIOS. 931 */ 932 if (device_property_read_u8(&pdev->dev, "WAKE_SUPPORTED", &val)) 933 return !!val; 934 935 return true; 936 } 937 938 static int nhi_poweroff_noirq(struct device *dev) 939 { 940 struct pci_dev *pdev = to_pci_dev(dev); 941 bool wakeup; 942 943 wakeup = device_may_wakeup(dev) && nhi_wake_supported(pdev); 944 return __nhi_suspend_noirq(dev, wakeup); 945 } 946 947 static void nhi_enable_int_throttling(struct tb_nhi *nhi) 948 { 949 /* Throttling is specified in 256ns increments */ 950 u32 throttle = DIV_ROUND_UP(128 * NSEC_PER_USEC, 256); 951 unsigned int i; 952 953 /* 954 * Configure interrupt throttling for all vectors even if we 955 * only use few. 956 */ 957 for (i = 0; i < MSIX_MAX_VECS; i++) { 958 u32 reg = REG_INT_THROTTLING_RATE + i * 4; 959 iowrite32(throttle, nhi->iobase + reg); 960 } 961 } 962 963 static int nhi_resume_noirq(struct device *dev) 964 { 965 struct pci_dev *pdev = to_pci_dev(dev); 966 struct tb *tb = pci_get_drvdata(pdev); 967 struct tb_nhi *nhi = tb->nhi; 968 int ret; 969 970 /* 971 * Check that the device is still there. It may be that the user 972 * unplugged last device which causes the host controller to go 973 * away on PCs. 974 */ 975 if (!pci_device_is_present(pdev)) { 976 nhi->going_away = true; 977 } else { 978 if (nhi->ops && nhi->ops->resume_noirq) { 979 ret = nhi->ops->resume_noirq(nhi); 980 if (ret) 981 return ret; 982 } 983 nhi_enable_int_throttling(tb->nhi); 984 } 985 986 return tb_domain_resume_noirq(tb); 987 } 988 989 static int nhi_suspend(struct device *dev) 990 { 991 struct pci_dev *pdev = to_pci_dev(dev); 992 struct tb *tb = pci_get_drvdata(pdev); 993 994 return tb_domain_suspend(tb); 995 } 996 997 static void nhi_complete(struct device *dev) 998 { 999 struct pci_dev *pdev = to_pci_dev(dev); 1000 struct tb *tb = pci_get_drvdata(pdev); 1001 1002 /* 1003 * If we were runtime suspended when system suspend started, 1004 * schedule runtime resume now. It should bring the domain back 1005 * to functional state. 1006 */ 1007 if (pm_runtime_suspended(&pdev->dev)) 1008 pm_runtime_resume(&pdev->dev); 1009 else 1010 tb_domain_complete(tb); 1011 } 1012 1013 static int nhi_runtime_suspend(struct device *dev) 1014 { 1015 struct pci_dev *pdev = to_pci_dev(dev); 1016 struct tb *tb = pci_get_drvdata(pdev); 1017 struct tb_nhi *nhi = tb->nhi; 1018 int ret; 1019 1020 ret = tb_domain_runtime_suspend(tb); 1021 if (ret) 1022 return ret; 1023 1024 if (nhi->ops && nhi->ops->runtime_suspend) { 1025 ret = nhi->ops->runtime_suspend(tb->nhi); 1026 if (ret) 1027 return ret; 1028 } 1029 return 0; 1030 } 1031 1032 static int nhi_runtime_resume(struct device *dev) 1033 { 1034 struct pci_dev *pdev = to_pci_dev(dev); 1035 struct tb *tb = pci_get_drvdata(pdev); 1036 struct tb_nhi *nhi = tb->nhi; 1037 int ret; 1038 1039 if (nhi->ops && nhi->ops->runtime_resume) { 1040 ret = nhi->ops->runtime_resume(nhi); 1041 if (ret) 1042 return ret; 1043 } 1044 1045 nhi_enable_int_throttling(nhi); 1046 return tb_domain_runtime_resume(tb); 1047 } 1048 1049 static void nhi_shutdown(struct tb_nhi *nhi) 1050 { 1051 int i; 1052 1053 dev_dbg(&nhi->pdev->dev, "shutdown\n"); 1054 1055 for (i = 0; i < nhi->hop_count; i++) { 1056 if (nhi->tx_rings[i]) 1057 dev_WARN(&nhi->pdev->dev, 1058 "TX ring %d is still active\n", i); 1059 if (nhi->rx_rings[i]) 1060 dev_WARN(&nhi->pdev->dev, 1061 "RX ring %d is still active\n", i); 1062 } 1063 nhi_disable_interrupts(nhi); 1064 /* 1065 * We have to release the irq before calling flush_work. Otherwise an 1066 * already executing IRQ handler could call schedule_work again. 1067 */ 1068 if (!nhi->pdev->msix_enabled) { 1069 devm_free_irq(&nhi->pdev->dev, nhi->pdev->irq, nhi); 1070 flush_work(&nhi->interrupt_work); 1071 } 1072 ida_destroy(&nhi->msix_ida); 1073 1074 if (nhi->ops && nhi->ops->shutdown) 1075 nhi->ops->shutdown(nhi); 1076 } 1077 1078 static int nhi_init_msi(struct tb_nhi *nhi) 1079 { 1080 struct pci_dev *pdev = nhi->pdev; 1081 int res, irq, nvec; 1082 1083 /* In case someone left them on. */ 1084 nhi_disable_interrupts(nhi); 1085 1086 nhi_enable_int_throttling(nhi); 1087 1088 ida_init(&nhi->msix_ida); 1089 1090 /* 1091 * The NHI has 16 MSI-X vectors or a single MSI. We first try to 1092 * get all MSI-X vectors and if we succeed, each ring will have 1093 * one MSI-X. If for some reason that does not work out, we 1094 * fallback to a single MSI. 1095 */ 1096 nvec = pci_alloc_irq_vectors(pdev, MSIX_MIN_VECS, MSIX_MAX_VECS, 1097 PCI_IRQ_MSIX); 1098 if (nvec < 0) { 1099 nvec = pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI); 1100 if (nvec < 0) 1101 return nvec; 1102 1103 INIT_WORK(&nhi->interrupt_work, nhi_interrupt_work); 1104 1105 irq = pci_irq_vector(nhi->pdev, 0); 1106 if (irq < 0) 1107 return irq; 1108 1109 res = devm_request_irq(&pdev->dev, irq, nhi_msi, 1110 IRQF_NO_SUSPEND, "thunderbolt", nhi); 1111 if (res) { 1112 dev_err(&pdev->dev, "request_irq failed, aborting\n"); 1113 return res; 1114 } 1115 } 1116 1117 return 0; 1118 } 1119 1120 static bool nhi_imr_valid(struct pci_dev *pdev) 1121 { 1122 u8 val; 1123 1124 if (!device_property_read_u8(&pdev->dev, "IMR_VALID", &val)) 1125 return !!val; 1126 1127 return true; 1128 } 1129 1130 /* 1131 * During suspend the Thunderbolt controller is reset and all PCIe 1132 * tunnels are lost. The NHI driver will try to reestablish all tunnels 1133 * during resume. This adds device links between the tunneled PCIe 1134 * downstream ports and the NHI so that the device core will make sure 1135 * NHI is resumed first before the rest. 1136 */ 1137 static void tb_apple_add_links(struct tb_nhi *nhi) 1138 { 1139 struct pci_dev *upstream, *pdev; 1140 1141 if (!x86_apple_machine) 1142 return; 1143 1144 switch (nhi->pdev->device) { 1145 case PCI_DEVICE_ID_INTEL_LIGHT_RIDGE: 1146 case PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C: 1147 case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI: 1148 case PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI: 1149 break; 1150 default: 1151 return; 1152 } 1153 1154 upstream = pci_upstream_bridge(nhi->pdev); 1155 while (upstream) { 1156 if (!pci_is_pcie(upstream)) 1157 return; 1158 if (pci_pcie_type(upstream) == PCI_EXP_TYPE_UPSTREAM) 1159 break; 1160 upstream = pci_upstream_bridge(upstream); 1161 } 1162 1163 if (!upstream) 1164 return; 1165 1166 /* 1167 * For each hotplug downstream port, create add device link 1168 * back to NHI so that PCIe tunnels can be re-established after 1169 * sleep. 1170 */ 1171 for_each_pci_bridge(pdev, upstream->subordinate) { 1172 const struct device_link *link; 1173 1174 if (!pci_is_pcie(pdev)) 1175 continue; 1176 if (pci_pcie_type(pdev) != PCI_EXP_TYPE_DOWNSTREAM || 1177 !pdev->is_hotplug_bridge) 1178 continue; 1179 1180 link = device_link_add(&pdev->dev, &nhi->pdev->dev, 1181 DL_FLAG_AUTOREMOVE_SUPPLIER | 1182 DL_FLAG_PM_RUNTIME); 1183 if (link) { 1184 dev_dbg(&nhi->pdev->dev, "created link from %s\n", 1185 dev_name(&pdev->dev)); 1186 } else { 1187 dev_warn(&nhi->pdev->dev, "device link creation from %s failed\n", 1188 dev_name(&pdev->dev)); 1189 } 1190 } 1191 } 1192 1193 static struct tb *nhi_select_cm(struct tb_nhi *nhi) 1194 { 1195 struct tb *tb; 1196 1197 /* 1198 * USB4 case is simple. If we got control of any of the 1199 * capabilities, we use software CM. 1200 */ 1201 if (tb_acpi_is_native()) 1202 return tb_probe(nhi); 1203 1204 /* 1205 * Either firmware based CM is running (we did not get control 1206 * from the firmware) or this is pre-USB4 PC so try first 1207 * firmware CM and then fallback to software CM. 1208 */ 1209 tb = icm_probe(nhi); 1210 if (!tb) 1211 tb = tb_probe(nhi); 1212 1213 return tb; 1214 } 1215 1216 static int nhi_probe(struct pci_dev *pdev, const struct pci_device_id *id) 1217 { 1218 struct tb_nhi *nhi; 1219 struct tb *tb; 1220 int res; 1221 1222 if (!nhi_imr_valid(pdev)) { 1223 dev_warn(&pdev->dev, "firmware image not valid, aborting\n"); 1224 return -ENODEV; 1225 } 1226 1227 res = pcim_enable_device(pdev); 1228 if (res) { 1229 dev_err(&pdev->dev, "cannot enable PCI device, aborting\n"); 1230 return res; 1231 } 1232 1233 res = pcim_iomap_regions(pdev, 1 << 0, "thunderbolt"); 1234 if (res) { 1235 dev_err(&pdev->dev, "cannot obtain PCI resources, aborting\n"); 1236 return res; 1237 } 1238 1239 nhi = devm_kzalloc(&pdev->dev, sizeof(*nhi), GFP_KERNEL); 1240 if (!nhi) 1241 return -ENOMEM; 1242 1243 nhi->pdev = pdev; 1244 nhi->ops = (const struct tb_nhi_ops *)id->driver_data; 1245 /* cannot fail - table is allocated bin pcim_iomap_regions */ 1246 nhi->iobase = pcim_iomap_table(pdev)[0]; 1247 nhi->hop_count = ioread32(nhi->iobase + REG_HOP_COUNT) & 0x3ff; 1248 dev_dbg(&pdev->dev, "total paths: %d\n", nhi->hop_count); 1249 1250 nhi->tx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count, 1251 sizeof(*nhi->tx_rings), GFP_KERNEL); 1252 nhi->rx_rings = devm_kcalloc(&pdev->dev, nhi->hop_count, 1253 sizeof(*nhi->rx_rings), GFP_KERNEL); 1254 if (!nhi->tx_rings || !nhi->rx_rings) 1255 return -ENOMEM; 1256 1257 res = nhi_init_msi(nhi); 1258 if (res) { 1259 dev_err(&pdev->dev, "cannot enable MSI, aborting\n"); 1260 return res; 1261 } 1262 1263 spin_lock_init(&nhi->lock); 1264 1265 res = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); 1266 if (res) 1267 res = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)); 1268 if (res) { 1269 dev_err(&pdev->dev, "failed to set DMA mask\n"); 1270 return res; 1271 } 1272 1273 pci_set_master(pdev); 1274 1275 if (nhi->ops && nhi->ops->init) { 1276 res = nhi->ops->init(nhi); 1277 if (res) 1278 return res; 1279 } 1280 1281 tb_apple_add_links(nhi); 1282 tb_acpi_add_links(nhi); 1283 1284 tb = nhi_select_cm(nhi); 1285 if (!tb) { 1286 dev_err(&nhi->pdev->dev, 1287 "failed to determine connection manager, aborting\n"); 1288 return -ENODEV; 1289 } 1290 1291 dev_dbg(&nhi->pdev->dev, "NHI initialized, starting thunderbolt\n"); 1292 1293 res = tb_domain_add(tb); 1294 if (res) { 1295 /* 1296 * At this point the RX/TX rings might already have been 1297 * activated. Do a proper shutdown. 1298 */ 1299 tb_domain_put(tb); 1300 nhi_shutdown(nhi); 1301 return res; 1302 } 1303 pci_set_drvdata(pdev, tb); 1304 1305 device_wakeup_enable(&pdev->dev); 1306 1307 pm_runtime_allow(&pdev->dev); 1308 pm_runtime_set_autosuspend_delay(&pdev->dev, TB_AUTOSUSPEND_DELAY); 1309 pm_runtime_use_autosuspend(&pdev->dev); 1310 pm_runtime_put_autosuspend(&pdev->dev); 1311 1312 return 0; 1313 } 1314 1315 static void nhi_remove(struct pci_dev *pdev) 1316 { 1317 struct tb *tb = pci_get_drvdata(pdev); 1318 struct tb_nhi *nhi = tb->nhi; 1319 1320 pm_runtime_get_sync(&pdev->dev); 1321 pm_runtime_dont_use_autosuspend(&pdev->dev); 1322 pm_runtime_forbid(&pdev->dev); 1323 1324 tb_domain_remove(tb); 1325 nhi_shutdown(nhi); 1326 } 1327 1328 /* 1329 * The tunneled pci bridges are siblings of us. Use resume_noirq to reenable 1330 * the tunnels asap. A corresponding pci quirk blocks the downstream bridges 1331 * resume_noirq until we are done. 1332 */ 1333 static const struct dev_pm_ops nhi_pm_ops = { 1334 .suspend_noirq = nhi_suspend_noirq, 1335 .resume_noirq = nhi_resume_noirq, 1336 .freeze_noirq = nhi_freeze_noirq, /* 1337 * we just disable hotplug, the 1338 * pci-tunnels stay alive. 1339 */ 1340 .thaw_noirq = nhi_thaw_noirq, 1341 .restore_noirq = nhi_resume_noirq, 1342 .suspend = nhi_suspend, 1343 .poweroff_noirq = nhi_poweroff_noirq, 1344 .poweroff = nhi_suspend, 1345 .complete = nhi_complete, 1346 .runtime_suspend = nhi_runtime_suspend, 1347 .runtime_resume = nhi_runtime_resume, 1348 }; 1349 1350 static struct pci_device_id nhi_ids[] = { 1351 /* 1352 * We have to specify class, the TB bridges use the same device and 1353 * vendor (sub)id on gen 1 and gen 2 controllers. 1354 */ 1355 { 1356 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0, 1357 .vendor = PCI_VENDOR_ID_INTEL, 1358 .device = PCI_DEVICE_ID_INTEL_LIGHT_RIDGE, 1359 .subvendor = 0x2222, .subdevice = 0x1111, 1360 }, 1361 { 1362 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0, 1363 .vendor = PCI_VENDOR_ID_INTEL, 1364 .device = PCI_DEVICE_ID_INTEL_CACTUS_RIDGE_4C, 1365 .subvendor = 0x2222, .subdevice = 0x1111, 1366 }, 1367 { 1368 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0, 1369 .vendor = PCI_VENDOR_ID_INTEL, 1370 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_2C_NHI, 1371 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 1372 }, 1373 { 1374 .class = PCI_CLASS_SYSTEM_OTHER << 8, .class_mask = ~0, 1375 .vendor = PCI_VENDOR_ID_INTEL, 1376 .device = PCI_DEVICE_ID_INTEL_FALCON_RIDGE_4C_NHI, 1377 .subvendor = PCI_ANY_ID, .subdevice = PCI_ANY_ID, 1378 }, 1379 1380 /* Thunderbolt 3 */ 1381 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_2C_NHI) }, 1382 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_4C_NHI) }, 1383 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_USBONLY_NHI) }, 1384 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_NHI) }, 1385 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_LP_USBONLY_NHI) }, 1386 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_2C_NHI) }, 1387 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_4C_NHI) }, 1388 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ALPINE_RIDGE_C_USBONLY_NHI) }, 1389 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_2C_NHI) }, 1390 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TITAN_RIDGE_4C_NHI) }, 1391 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI0), 1392 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1393 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_ICL_NHI1), 1394 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1395 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_NHI0), 1396 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1397 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_NHI1), 1398 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1399 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_H_NHI0), 1400 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1401 { PCI_VDEVICE(INTEL, PCI_DEVICE_ID_INTEL_TGL_H_NHI1), 1402 .driver_data = (kernel_ulong_t)&icl_nhi_ops }, 1403 1404 /* Any USB4 compliant host */ 1405 { PCI_DEVICE_CLASS(PCI_CLASS_SERIAL_USB_USB4, ~0) }, 1406 1407 { 0,} 1408 }; 1409 1410 MODULE_DEVICE_TABLE(pci, nhi_ids); 1411 MODULE_LICENSE("GPL"); 1412 1413 static struct pci_driver nhi_driver = { 1414 .name = "thunderbolt", 1415 .id_table = nhi_ids, 1416 .probe = nhi_probe, 1417 .remove = nhi_remove, 1418 .shutdown = nhi_remove, 1419 .driver.pm = &nhi_pm_ops, 1420 }; 1421 1422 static int __init nhi_init(void) 1423 { 1424 int ret; 1425 1426 ret = tb_domain_init(); 1427 if (ret) 1428 return ret; 1429 ret = pci_register_driver(&nhi_driver); 1430 if (ret) 1431 tb_domain_exit(); 1432 return ret; 1433 } 1434 1435 static void __exit nhi_unload(void) 1436 { 1437 pci_unregister_driver(&nhi_driver); 1438 tb_domain_exit(); 1439 } 1440 1441 rootfs_initcall(nhi_init); 1442 module_exit(nhi_unload); 1443