1*5c9d6ac2SWei Ni // SPDX-License-Identifier: GPL-2.0 265b6d57cSWei Ni /* 3*5c9d6ac2SWei Ni * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. 465b6d57cSWei Ni * 565b6d57cSWei Ni * This software is licensed under the terms of the GNU General Public 665b6d57cSWei Ni * License version 2, as published by the Free Software Foundation, and 765b6d57cSWei Ni * may be copied, distributed, and modified under those terms. 865b6d57cSWei Ni * 965b6d57cSWei Ni * This program is distributed in the hope that it will be useful, 1065b6d57cSWei Ni * but WITHOUT ANY WARRANTY; without even the implied warranty of 1165b6d57cSWei Ni * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 1265b6d57cSWei Ni * GNU General Public License for more details. 1365b6d57cSWei Ni * 1465b6d57cSWei Ni */ 1565b6d57cSWei Ni 1665b6d57cSWei Ni #include <linux/module.h> 1765b6d57cSWei Ni #include <linux/platform_device.h> 1865b6d57cSWei Ni 1965b6d57cSWei Ni #include <dt-bindings/thermal/tegra124-soctherm.h> 2065b6d57cSWei Ni 2165b6d57cSWei Ni #include "soctherm.h" 2265b6d57cSWei Ni 232a895871SWei Ni #define TEGRA124_THERMTRIP_ANY_EN_MASK (0x1 << 28) 242a895871SWei Ni #define TEGRA124_THERMTRIP_MEM_EN_MASK (0x1 << 27) 252a895871SWei Ni #define TEGRA124_THERMTRIP_GPU_EN_MASK (0x1 << 26) 262a895871SWei Ni #define TEGRA124_THERMTRIP_CPU_EN_MASK (0x1 << 25) 272a895871SWei Ni #define TEGRA124_THERMTRIP_TSENSE_EN_MASK (0x1 << 24) 282a895871SWei Ni #define TEGRA124_THERMTRIP_GPUMEM_THRESH_MASK (0xff << 16) 292a895871SWei Ni #define TEGRA124_THERMTRIP_CPU_THRESH_MASK (0xff << 8) 302a895871SWei Ni #define TEGRA124_THERMTRIP_TSENSE_THRESH_MASK 0xff 312a895871SWei Ni 32ce0dbf04SWei Ni #define TEGRA124_THERMCTL_LVL0_UP_THRESH_MASK (0xff << 17) 33ce0dbf04SWei Ni #define TEGRA124_THERMCTL_LVL0_DN_THRESH_MASK (0xff << 9) 34ce0dbf04SWei Ni 352a895871SWei Ni #define TEGRA124_THRESH_GRAIN 1000 36ce0dbf04SWei Ni #define TEGRA124_BPTT 8 372a895871SWei Ni 3865b6d57cSWei Ni static const struct tegra_tsensor_configuration tegra124_tsensor_config = { 3965b6d57cSWei Ni .tall = 16300, 4065b6d57cSWei Ni .tiddq_en = 1, 4165b6d57cSWei Ni .ten_count = 1, 4265b6d57cSWei Ni .tsample = 120, 4365b6d57cSWei Ni .tsample_ate = 480, 4465b6d57cSWei Ni }; 4565b6d57cSWei Ni 4665b6d57cSWei Ni static const struct tegra_tsensor_group tegra124_tsensor_group_cpu = { 4765b6d57cSWei Ni .id = TEGRA124_SOCTHERM_SENSOR_CPU, 4865b6d57cSWei Ni .name = "cpu", 4965b6d57cSWei Ni .sensor_temp_offset = SENSOR_TEMP1, 5065b6d57cSWei Ni .sensor_temp_mask = SENSOR_TEMP1_CPU_TEMP_MASK, 5165b6d57cSWei Ni .pdiv = 8, 5265b6d57cSWei Ni .pdiv_ate = 8, 5365b6d57cSWei Ni .pdiv_mask = SENSOR_PDIV_CPU_MASK, 5465b6d57cSWei Ni .pllx_hotspot_diff = 10, 5565b6d57cSWei Ni .pllx_hotspot_mask = SENSOR_HOTSPOT_CPU_MASK, 562a895871SWei Ni .thermtrip_any_en_mask = TEGRA124_THERMTRIP_ANY_EN_MASK, 572a895871SWei Ni .thermtrip_enable_mask = TEGRA124_THERMTRIP_CPU_EN_MASK, 582a895871SWei Ni .thermtrip_threshold_mask = TEGRA124_THERMTRIP_CPU_THRESH_MASK, 59*5c9d6ac2SWei Ni .thermctl_isr_mask = THERM_IRQ_CPU_MASK, 60ce0dbf04SWei Ni .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_CPU, 61ce0dbf04SWei Ni .thermctl_lvl0_up_thresh_mask = TEGRA124_THERMCTL_LVL0_UP_THRESH_MASK, 62ce0dbf04SWei Ni .thermctl_lvl0_dn_thresh_mask = TEGRA124_THERMCTL_LVL0_DN_THRESH_MASK, 6365b6d57cSWei Ni }; 6465b6d57cSWei Ni 6565b6d57cSWei Ni static const struct tegra_tsensor_group tegra124_tsensor_group_gpu = { 6665b6d57cSWei Ni .id = TEGRA124_SOCTHERM_SENSOR_GPU, 6765b6d57cSWei Ni .name = "gpu", 6865b6d57cSWei Ni .sensor_temp_offset = SENSOR_TEMP1, 6965b6d57cSWei Ni .sensor_temp_mask = SENSOR_TEMP1_GPU_TEMP_MASK, 7065b6d57cSWei Ni .pdiv = 8, 7165b6d57cSWei Ni .pdiv_ate = 8, 7265b6d57cSWei Ni .pdiv_mask = SENSOR_PDIV_GPU_MASK, 7365b6d57cSWei Ni .pllx_hotspot_diff = 5, 7465b6d57cSWei Ni .pllx_hotspot_mask = SENSOR_HOTSPOT_GPU_MASK, 752a895871SWei Ni .thermtrip_any_en_mask = TEGRA124_THERMTRIP_ANY_EN_MASK, 762a895871SWei Ni .thermtrip_enable_mask = TEGRA124_THERMTRIP_GPU_EN_MASK, 772a895871SWei Ni .thermtrip_threshold_mask = TEGRA124_THERMTRIP_GPUMEM_THRESH_MASK, 78*5c9d6ac2SWei Ni .thermctl_isr_mask = THERM_IRQ_GPU_MASK, 79ce0dbf04SWei Ni .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_GPU, 80ce0dbf04SWei Ni .thermctl_lvl0_up_thresh_mask = TEGRA124_THERMCTL_LVL0_UP_THRESH_MASK, 81ce0dbf04SWei Ni .thermctl_lvl0_dn_thresh_mask = TEGRA124_THERMCTL_LVL0_DN_THRESH_MASK, 8265b6d57cSWei Ni }; 8365b6d57cSWei Ni 8465b6d57cSWei Ni static const struct tegra_tsensor_group tegra124_tsensor_group_pll = { 8565b6d57cSWei Ni .id = TEGRA124_SOCTHERM_SENSOR_PLLX, 8665b6d57cSWei Ni .name = "pll", 8765b6d57cSWei Ni .sensor_temp_offset = SENSOR_TEMP2, 8865b6d57cSWei Ni .sensor_temp_mask = SENSOR_TEMP2_PLLX_TEMP_MASK, 8965b6d57cSWei Ni .pdiv = 8, 9065b6d57cSWei Ni .pdiv_ate = 8, 9165b6d57cSWei Ni .pdiv_mask = SENSOR_PDIV_PLLX_MASK, 922a895871SWei Ni .thermtrip_any_en_mask = TEGRA124_THERMTRIP_ANY_EN_MASK, 932a895871SWei Ni .thermtrip_enable_mask = TEGRA124_THERMTRIP_TSENSE_EN_MASK, 942a895871SWei Ni .thermtrip_threshold_mask = TEGRA124_THERMTRIP_TSENSE_THRESH_MASK, 95*5c9d6ac2SWei Ni .thermctl_isr_mask = THERM_IRQ_TSENSE_MASK, 96ce0dbf04SWei Ni .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_TSENSE, 97ce0dbf04SWei Ni .thermctl_lvl0_up_thresh_mask = TEGRA124_THERMCTL_LVL0_UP_THRESH_MASK, 98ce0dbf04SWei Ni .thermctl_lvl0_dn_thresh_mask = TEGRA124_THERMCTL_LVL0_DN_THRESH_MASK, 9965b6d57cSWei Ni }; 10065b6d57cSWei Ni 10165b6d57cSWei Ni static const struct tegra_tsensor_group tegra124_tsensor_group_mem = { 10265b6d57cSWei Ni .id = TEGRA124_SOCTHERM_SENSOR_MEM, 10365b6d57cSWei Ni .name = "mem", 10465b6d57cSWei Ni .sensor_temp_offset = SENSOR_TEMP2, 10565b6d57cSWei Ni .sensor_temp_mask = SENSOR_TEMP2_MEM_TEMP_MASK, 10665b6d57cSWei Ni .pdiv = 8, 10765b6d57cSWei Ni .pdiv_ate = 8, 10865b6d57cSWei Ni .pdiv_mask = SENSOR_PDIV_MEM_MASK, 10965b6d57cSWei Ni .pllx_hotspot_diff = 0, 11065b6d57cSWei Ni .pllx_hotspot_mask = SENSOR_HOTSPOT_MEM_MASK, 1112a895871SWei Ni .thermtrip_any_en_mask = TEGRA124_THERMTRIP_ANY_EN_MASK, 1122a895871SWei Ni .thermtrip_enable_mask = TEGRA124_THERMTRIP_MEM_EN_MASK, 1132a895871SWei Ni .thermtrip_threshold_mask = TEGRA124_THERMTRIP_GPUMEM_THRESH_MASK, 114*5c9d6ac2SWei Ni .thermctl_isr_mask = THERM_IRQ_MEM_MASK, 115ce0dbf04SWei Ni .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_MEM, 116ce0dbf04SWei Ni .thermctl_lvl0_up_thresh_mask = TEGRA124_THERMCTL_LVL0_UP_THRESH_MASK, 117ce0dbf04SWei Ni .thermctl_lvl0_dn_thresh_mask = TEGRA124_THERMCTL_LVL0_DN_THRESH_MASK, 11865b6d57cSWei Ni }; 11965b6d57cSWei Ni 12065b6d57cSWei Ni static const struct tegra_tsensor_group *tegra124_tsensor_groups[] = { 12165b6d57cSWei Ni &tegra124_tsensor_group_cpu, 12265b6d57cSWei Ni &tegra124_tsensor_group_gpu, 12365b6d57cSWei Ni &tegra124_tsensor_group_pll, 12465b6d57cSWei Ni &tegra124_tsensor_group_mem, 12565b6d57cSWei Ni }; 12665b6d57cSWei Ni 12765b6d57cSWei Ni static const struct tegra_tsensor tegra124_tsensors[] = { 12865b6d57cSWei Ni { 12965b6d57cSWei Ni .name = "cpu0", 13065b6d57cSWei Ni .base = 0xc0, 13165b6d57cSWei Ni .config = &tegra124_tsensor_config, 13265b6d57cSWei Ni .calib_fuse_offset = 0x098, 13365b6d57cSWei Ni .fuse_corr_alpha = 1135400, 13465b6d57cSWei Ni .fuse_corr_beta = -6266900, 13565b6d57cSWei Ni .group = &tegra124_tsensor_group_cpu, 13665b6d57cSWei Ni }, { 13765b6d57cSWei Ni .name = "cpu1", 13865b6d57cSWei Ni .base = 0xe0, 13965b6d57cSWei Ni .config = &tegra124_tsensor_config, 14065b6d57cSWei Ni .calib_fuse_offset = 0x084, 14165b6d57cSWei Ni .fuse_corr_alpha = 1122220, 14265b6d57cSWei Ni .fuse_corr_beta = -5700700, 14365b6d57cSWei Ni .group = &tegra124_tsensor_group_cpu, 14465b6d57cSWei Ni }, { 14565b6d57cSWei Ni .name = "cpu2", 14665b6d57cSWei Ni .base = 0x100, 14765b6d57cSWei Ni .config = &tegra124_tsensor_config, 14865b6d57cSWei Ni .calib_fuse_offset = 0x088, 14965b6d57cSWei Ni .fuse_corr_alpha = 1127000, 15065b6d57cSWei Ni .fuse_corr_beta = -6768200, 15165b6d57cSWei Ni .group = &tegra124_tsensor_group_cpu, 15265b6d57cSWei Ni }, { 15365b6d57cSWei Ni .name = "cpu3", 15465b6d57cSWei Ni .base = 0x120, 15565b6d57cSWei Ni .config = &tegra124_tsensor_config, 15665b6d57cSWei Ni .calib_fuse_offset = 0x12c, 15765b6d57cSWei Ni .fuse_corr_alpha = 1110900, 15865b6d57cSWei Ni .fuse_corr_beta = -6232000, 15965b6d57cSWei Ni .group = &tegra124_tsensor_group_cpu, 16065b6d57cSWei Ni }, { 16165b6d57cSWei Ni .name = "mem0", 16265b6d57cSWei Ni .base = 0x140, 16365b6d57cSWei Ni .config = &tegra124_tsensor_config, 16465b6d57cSWei Ni .calib_fuse_offset = 0x158, 16565b6d57cSWei Ni .fuse_corr_alpha = 1122300, 16665b6d57cSWei Ni .fuse_corr_beta = -5936400, 16765b6d57cSWei Ni .group = &tegra124_tsensor_group_mem, 16865b6d57cSWei Ni }, { 16965b6d57cSWei Ni .name = "mem1", 17065b6d57cSWei Ni .base = 0x160, 17165b6d57cSWei Ni .config = &tegra124_tsensor_config, 17265b6d57cSWei Ni .calib_fuse_offset = 0x15c, 17365b6d57cSWei Ni .fuse_corr_alpha = 1145700, 17465b6d57cSWei Ni .fuse_corr_beta = -7124600, 17565b6d57cSWei Ni .group = &tegra124_tsensor_group_mem, 17665b6d57cSWei Ni }, { 17765b6d57cSWei Ni .name = "gpu", 17865b6d57cSWei Ni .base = 0x180, 17965b6d57cSWei Ni .config = &tegra124_tsensor_config, 18065b6d57cSWei Ni .calib_fuse_offset = 0x154, 18165b6d57cSWei Ni .fuse_corr_alpha = 1120100, 18265b6d57cSWei Ni .fuse_corr_beta = -6000500, 18365b6d57cSWei Ni .group = &tegra124_tsensor_group_gpu, 18465b6d57cSWei Ni }, { 18565b6d57cSWei Ni .name = "pllx", 18665b6d57cSWei Ni .base = 0x1a0, 18765b6d57cSWei Ni .config = &tegra124_tsensor_config, 18865b6d57cSWei Ni .calib_fuse_offset = 0x160, 18965b6d57cSWei Ni .fuse_corr_alpha = 1106500, 19065b6d57cSWei Ni .fuse_corr_beta = -6729300, 19165b6d57cSWei Ni .group = &tegra124_tsensor_group_pll, 19265b6d57cSWei Ni }, 19365b6d57cSWei Ni }; 19465b6d57cSWei Ni 19565b6d57cSWei Ni /* 19665b6d57cSWei Ni * Mask/shift bits in FUSE_TSENSOR_COMMON and 19765b6d57cSWei Ni * FUSE_TSENSOR_COMMON, which are described in 19865b6d57cSWei Ni * tegra_soctherm_fuse.c 19965b6d57cSWei Ni */ 20065b6d57cSWei Ni static const struct tegra_soctherm_fuse tegra124_soctherm_fuse = { 20165b6d57cSWei Ni .fuse_base_cp_mask = 0x3ff, 20265b6d57cSWei Ni .fuse_base_cp_shift = 0, 20365b6d57cSWei Ni .fuse_base_ft_mask = 0x7ff << 10, 20465b6d57cSWei Ni .fuse_base_ft_shift = 10, 20565b6d57cSWei Ni .fuse_shift_ft_mask = 0x1f << 21, 20665b6d57cSWei Ni .fuse_shift_ft_shift = 21, 20765b6d57cSWei Ni .fuse_spare_realignment = 0x1fc, 20865b6d57cSWei Ni }; 20965b6d57cSWei Ni 21065b6d57cSWei Ni const struct tegra_soctherm_soc tegra124_soctherm = { 21165b6d57cSWei Ni .tsensors = tegra124_tsensors, 21265b6d57cSWei Ni .num_tsensors = ARRAY_SIZE(tegra124_tsensors), 21365b6d57cSWei Ni .ttgs = tegra124_tsensor_groups, 21465b6d57cSWei Ni .num_ttgs = ARRAY_SIZE(tegra124_tsensor_groups), 21565b6d57cSWei Ni .tfuse = &tegra124_soctherm_fuse, 2162a895871SWei Ni .thresh_grain = TEGRA124_THRESH_GRAIN, 217ce0dbf04SWei Ni .bptt = TEGRA124_BPTT, 218ce0dbf04SWei Ni .use_ccroc = false, 21965b6d57cSWei Ni }; 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