1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. 4 * Copyright (c) 2024, Svyatoslav Ryhel <clamor95@gmail.com> 5 */ 6 7 #include <linux/module.h> 8 #include <linux/platform_device.h> 9 10 #include <dt-bindings/thermal/tegra114-soctherm.h> 11 12 #include "soctherm.h" 13 14 #define TEGRA114_THERMTRIP_ANY_EN_MASK (0x1 << 28) 15 #define TEGRA114_THERMTRIP_MEM_EN_MASK (0x1 << 27) 16 #define TEGRA114_THERMTRIP_GPU_EN_MASK (0x1 << 26) 17 #define TEGRA114_THERMTRIP_CPU_EN_MASK (0x1 << 25) 18 #define TEGRA114_THERMTRIP_TSENSE_EN_MASK (0x1 << 24) 19 #define TEGRA114_THERMTRIP_GPUMEM_THRESH_MASK (0xff << 16) 20 #define TEGRA114_THERMTRIP_CPU_THRESH_MASK (0xff << 8) 21 #define TEGRA114_THERMTRIP_TSENSE_THRESH_MASK 0xff 22 23 #define TEGRA114_THERMCTL_LVL0_UP_THRESH_MASK (0xff << 17) 24 #define TEGRA114_THERMCTL_LVL0_DN_THRESH_MASK (0xff << 9) 25 26 #define TEGRA114_THRESH_GRAIN 1000 27 #define TEGRA114_BPTT 8 28 29 static const struct tegra_tsensor_configuration tegra114_tsensor_config = { 30 .tall = 16300, 31 .tiddq_en = 1, 32 .ten_count = 1, 33 .tsample = 163, 34 .tsample_ate = 655, 35 }; 36 37 static const struct tegra_tsensor_group tegra114_tsensor_group_cpu = { 38 .id = TEGRA114_SOCTHERM_SENSOR_CPU, 39 .name = "cpu", 40 .sensor_temp_offset = SENSOR_TEMP1, 41 .sensor_temp_mask = SENSOR_TEMP1_CPU_TEMP_MASK, 42 .pdiv = 10, 43 .pdiv_ate = 10, 44 .pdiv_mask = SENSOR_PDIV_CPU_MASK, 45 .pllx_hotspot_diff = 6, 46 .pllx_hotspot_mask = SENSOR_HOTSPOT_CPU_MASK, 47 .thermtrip_any_en_mask = TEGRA114_THERMTRIP_ANY_EN_MASK, 48 .thermtrip_enable_mask = TEGRA114_THERMTRIP_CPU_EN_MASK, 49 .thermtrip_threshold_mask = TEGRA114_THERMTRIP_CPU_THRESH_MASK, 50 .thermctl_isr_mask = THERM_IRQ_CPU_MASK, 51 .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_CPU, 52 .thermctl_lvl0_up_thresh_mask = TEGRA114_THERMCTL_LVL0_UP_THRESH_MASK, 53 .thermctl_lvl0_dn_thresh_mask = TEGRA114_THERMCTL_LVL0_DN_THRESH_MASK, 54 }; 55 56 static const struct tegra_tsensor_group tegra114_tsensor_group_gpu = { 57 .id = TEGRA114_SOCTHERM_SENSOR_GPU, 58 .name = "gpu", 59 .sensor_temp_offset = SENSOR_TEMP1, 60 .sensor_temp_mask = SENSOR_TEMP1_GPU_TEMP_MASK, 61 .pdiv = 10, 62 .pdiv_ate = 10, 63 .pdiv_mask = SENSOR_PDIV_GPU_MASK, 64 .pllx_hotspot_diff = 6, 65 .pllx_hotspot_mask = SENSOR_HOTSPOT_GPU_MASK, 66 .thermtrip_any_en_mask = TEGRA114_THERMTRIP_ANY_EN_MASK, 67 .thermtrip_enable_mask = TEGRA114_THERMTRIP_GPU_EN_MASK, 68 .thermtrip_threshold_mask = TEGRA114_THERMTRIP_GPUMEM_THRESH_MASK, 69 .thermctl_isr_mask = THERM_IRQ_GPU_MASK, 70 .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_GPU, 71 .thermctl_lvl0_up_thresh_mask = TEGRA114_THERMCTL_LVL0_UP_THRESH_MASK, 72 .thermctl_lvl0_dn_thresh_mask = TEGRA114_THERMCTL_LVL0_DN_THRESH_MASK, 73 }; 74 75 static const struct tegra_tsensor_group tegra114_tsensor_group_pll = { 76 .id = TEGRA114_SOCTHERM_SENSOR_PLLX, 77 .name = "pll", 78 .sensor_temp_offset = SENSOR_TEMP2, 79 .sensor_temp_mask = SENSOR_TEMP2_PLLX_TEMP_MASK, 80 .pdiv = 10, 81 .pdiv_ate = 10, 82 .pdiv_mask = SENSOR_PDIV_PLLX_MASK, 83 .thermtrip_any_en_mask = TEGRA114_THERMTRIP_ANY_EN_MASK, 84 .thermtrip_enable_mask = TEGRA114_THERMTRIP_TSENSE_EN_MASK, 85 .thermtrip_threshold_mask = TEGRA114_THERMTRIP_TSENSE_THRESH_MASK, 86 .thermctl_isr_mask = THERM_IRQ_TSENSE_MASK, 87 .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_TSENSE, 88 .thermctl_lvl0_up_thresh_mask = TEGRA114_THERMCTL_LVL0_UP_THRESH_MASK, 89 .thermctl_lvl0_dn_thresh_mask = TEGRA114_THERMCTL_LVL0_DN_THRESH_MASK, 90 }; 91 92 static const struct tegra_tsensor_group tegra114_tsensor_group_mem = { 93 .id = TEGRA114_SOCTHERM_SENSOR_MEM, 94 .name = "mem", 95 .sensor_temp_offset = SENSOR_TEMP2, 96 .sensor_temp_mask = SENSOR_TEMP2_MEM_TEMP_MASK, 97 .pdiv = 10, 98 .pdiv_ate = 10, 99 .pdiv_mask = SENSOR_PDIV_MEM_MASK, 100 .pllx_hotspot_diff = 0, 101 .pllx_hotspot_mask = SENSOR_HOTSPOT_MEM_MASK, 102 .thermtrip_any_en_mask = TEGRA114_THERMTRIP_ANY_EN_MASK, 103 .thermtrip_enable_mask = TEGRA114_THERMTRIP_MEM_EN_MASK, 104 .thermtrip_threshold_mask = TEGRA114_THERMTRIP_GPUMEM_THRESH_MASK, 105 .thermctl_isr_mask = THERM_IRQ_MEM_MASK, 106 .thermctl_lvl0_offset = THERMCTL_LEVEL0_GROUP_MEM, 107 .thermctl_lvl0_up_thresh_mask = TEGRA114_THERMCTL_LVL0_UP_THRESH_MASK, 108 .thermctl_lvl0_dn_thresh_mask = TEGRA114_THERMCTL_LVL0_DN_THRESH_MASK, 109 }; 110 111 static const struct tegra_tsensor_group *tegra114_tsensor_groups[] = { 112 &tegra114_tsensor_group_cpu, 113 &tegra114_tsensor_group_gpu, 114 &tegra114_tsensor_group_pll, 115 &tegra114_tsensor_group_mem, 116 }; 117 118 static const struct tegra_tsensor tegra114_tsensors[] = { 119 { 120 .name = "cpu0", 121 .base = 0xc0, 122 .config = &tegra114_tsensor_config, 123 .calib_fuse_offset = 0x098, 124 .fuse_corr_alpha = 1196400, 125 .fuse_corr_beta = -13600000, 126 .group = &tegra114_tsensor_group_cpu, 127 }, { 128 .name = "cpu1", 129 .base = 0xe0, 130 .config = &tegra114_tsensor_config, 131 .calib_fuse_offset = 0x084, 132 .fuse_corr_alpha = 1196400, 133 .fuse_corr_beta = -13600000, 134 .group = &tegra114_tsensor_group_cpu, 135 }, { 136 .name = "cpu2", 137 .base = 0x100, 138 .config = &tegra114_tsensor_config, 139 .calib_fuse_offset = 0x088, 140 .fuse_corr_alpha = 1196400, 141 .fuse_corr_beta = -13600000, 142 .group = &tegra114_tsensor_group_cpu, 143 }, { 144 .name = "cpu3", 145 .base = 0x120, 146 .config = &tegra114_tsensor_config, 147 .calib_fuse_offset = 0x12c, 148 .fuse_corr_alpha = 1196400, 149 .fuse_corr_beta = -13600000, 150 .group = &tegra114_tsensor_group_cpu, 151 }, { 152 .name = "mem0", 153 .base = 0x140, 154 .config = &tegra114_tsensor_config, 155 .calib_fuse_offset = 0x158, 156 .fuse_corr_alpha = 1000000, 157 .fuse_corr_beta = 0, 158 .group = &tegra114_tsensor_group_mem, 159 }, { 160 .name = "mem1", 161 .base = 0x160, 162 .config = &tegra114_tsensor_config, 163 .calib_fuse_offset = 0x15c, 164 .fuse_corr_alpha = 1000000, 165 .fuse_corr_beta = 0, 166 .group = &tegra114_tsensor_group_mem, 167 }, { 168 .name = "gpu", 169 .base = 0x180, 170 .config = &tegra114_tsensor_config, 171 .calib_fuse_offset = 0x154, 172 .fuse_corr_alpha = 1124500, 173 .fuse_corr_beta = -9793100, 174 .group = &tegra114_tsensor_group_gpu, 175 }, { 176 .name = "pllx", 177 .base = 0x1a0, 178 .config = &tegra114_tsensor_config, 179 .calib_fuse_offset = 0x160, 180 .fuse_corr_alpha = 1224200, 181 .fuse_corr_beta = -14665000, 182 .group = &tegra114_tsensor_group_pll, 183 }, 184 }; 185 186 static const struct tegra_soctherm_fuse tegra114_soctherm_fuse = { 187 .fuse_base_cp_mask = 0x3ff, 188 .fuse_base_cp_shift = 0, 189 .fuse_shift_cp_mask = 0x3f << 10, 190 .fuse_shift_cp_shift = 10, 191 .fuse_base_ft_mask = 0x7ff << 16, 192 .fuse_base_ft_shift = 16, 193 .fuse_shift_ft_mask = 0x1f << 27, 194 .fuse_shift_ft_shift = 27, 195 .fuse_common_reg = FUSE_VSENSOR_CALIB, 196 .fuse_spare_realignment = 0, 197 .nominal_calib_ft = 90, 198 }; 199 200 const struct tegra_soctherm_soc tegra114_soctherm = { 201 .tsensors = tegra114_tsensors, 202 .num_tsensors = ARRAY_SIZE(tegra114_tsensors), 203 .ttgs = tegra114_tsensor_groups, 204 .num_ttgs = ARRAY_SIZE(tegra114_tsensor_groups), 205 .tfuse = &tegra114_soctherm_fuse, 206 .thresh_grain = TEGRA114_THRESH_GRAIN, 207 .bptt = TEGRA114_BPTT, 208 .use_ccroc = false, 209 }; 210