1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2014 - 2018, NVIDIA CORPORATION. All rights reserved. 4 * 5 * Author: 6 * Mikko Perttunen <mperttunen@nvidia.com> 7 * 8 * This software is licensed under the terms of the GNU General Public 9 * License version 2, as published by the Free Software Foundation, and 10 * may be copied, distributed, and modified under those terms. 11 * 12 * This program is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 15 * GNU General Public License for more details. 16 * 17 */ 18 19 #include <linux/debugfs.h> 20 #include <linux/bitops.h> 21 #include <linux/clk.h> 22 #include <linux/delay.h> 23 #include <linux/err.h> 24 #include <linux/interrupt.h> 25 #include <linux/io.h> 26 #include <linux/module.h> 27 #include <linux/of.h> 28 #include <linux/platform_device.h> 29 #include <linux/reset.h> 30 #include <linux/thermal.h> 31 32 #include <dt-bindings/thermal/tegra124-soctherm.h> 33 34 #include "../thermal_core.h" 35 #include "soctherm.h" 36 37 #define SENSOR_CONFIG0 0 38 #define SENSOR_CONFIG0_STOP BIT(0) 39 #define SENSOR_CONFIG0_CPTR_OVER BIT(2) 40 #define SENSOR_CONFIG0_OVER BIT(3) 41 #define SENSOR_CONFIG0_TCALC_OVER BIT(4) 42 #define SENSOR_CONFIG0_TALL_MASK (0xfffff << 8) 43 #define SENSOR_CONFIG0_TALL_SHIFT 8 44 45 #define SENSOR_CONFIG1 4 46 #define SENSOR_CONFIG1_TSAMPLE_MASK 0x3ff 47 #define SENSOR_CONFIG1_TSAMPLE_SHIFT 0 48 #define SENSOR_CONFIG1_TIDDQ_EN_MASK (0x3f << 15) 49 #define SENSOR_CONFIG1_TIDDQ_EN_SHIFT 15 50 #define SENSOR_CONFIG1_TEN_COUNT_MASK (0x3f << 24) 51 #define SENSOR_CONFIG1_TEN_COUNT_SHIFT 24 52 #define SENSOR_CONFIG1_TEMP_ENABLE BIT(31) 53 54 /* 55 * SENSOR_CONFIG2 is defined in soctherm.h 56 * because, it will be used by tegra_soctherm_fuse.c 57 */ 58 59 #define SENSOR_STATUS0 0xc 60 #define SENSOR_STATUS0_VALID_MASK BIT(31) 61 #define SENSOR_STATUS0_CAPTURE_MASK 0xffff 62 63 #define SENSOR_STATUS1 0x10 64 #define SENSOR_STATUS1_TEMP_VALID_MASK BIT(31) 65 #define SENSOR_STATUS1_TEMP_MASK 0xffff 66 67 #define READBACK_VALUE_MASK 0xff00 68 #define READBACK_VALUE_SHIFT 8 69 #define READBACK_ADD_HALF BIT(7) 70 #define READBACK_NEGATE BIT(0) 71 72 /* 73 * THERMCTL_LEVEL0_GROUP_CPU is defined in soctherm.h 74 * because it will be used by tegraxxx_soctherm.c 75 */ 76 #define THERMCTL_LVL0_CPU0_EN_MASK BIT(8) 77 #define THERMCTL_LVL0_CPU0_CPU_THROT_MASK (0x3 << 5) 78 #define THERMCTL_LVL0_CPU0_CPU_THROT_LIGHT 0x1 79 #define THERMCTL_LVL0_CPU0_CPU_THROT_HEAVY 0x2 80 #define THERMCTL_LVL0_CPU0_GPU_THROT_MASK (0x3 << 3) 81 #define THERMCTL_LVL0_CPU0_GPU_THROT_LIGHT 0x1 82 #define THERMCTL_LVL0_CPU0_GPU_THROT_HEAVY 0x2 83 #define THERMCTL_LVL0_CPU0_MEM_THROT_MASK BIT(2) 84 #define THERMCTL_LVL0_CPU0_STATUS_MASK 0x3 85 86 #define THERMCTL_LVL0_UP_STATS 0x10 87 #define THERMCTL_LVL0_DN_STATS 0x14 88 89 #define THERMCTL_INTR_STATUS 0x84 90 91 #define TH_INTR_MD0_MASK BIT(25) 92 #define TH_INTR_MU0_MASK BIT(24) 93 #define TH_INTR_GD0_MASK BIT(17) 94 #define TH_INTR_GU0_MASK BIT(16) 95 #define TH_INTR_CD0_MASK BIT(9) 96 #define TH_INTR_CU0_MASK BIT(8) 97 #define TH_INTR_PD0_MASK BIT(1) 98 #define TH_INTR_PU0_MASK BIT(0) 99 #define TH_INTR_IGNORE_MASK 0xFCFCFCFC 100 101 #define THERMCTL_STATS_CTL 0x94 102 #define STATS_CTL_CLR_DN 0x8 103 #define STATS_CTL_EN_DN 0x4 104 #define STATS_CTL_CLR_UP 0x2 105 #define STATS_CTL_EN_UP 0x1 106 107 #define THROT_GLOBAL_CFG 0x400 108 #define THROT_GLOBAL_ENB_MASK BIT(0) 109 110 #define CPU_PSKIP_STATUS 0x418 111 #define XPU_PSKIP_STATUS_M_MASK (0xff << 12) 112 #define XPU_PSKIP_STATUS_N_MASK (0xff << 4) 113 #define XPU_PSKIP_STATUS_SW_OVERRIDE_MASK BIT(1) 114 #define XPU_PSKIP_STATUS_ENABLED_MASK BIT(0) 115 116 #define THROT_PRIORITY_LOCK 0x424 117 #define THROT_PRIORITY_LOCK_PRIORITY_MASK 0xff 118 119 #define THROT_STATUS 0x428 120 #define THROT_STATUS_BREACH_MASK BIT(12) 121 #define THROT_STATUS_STATE_MASK (0xff << 4) 122 #define THROT_STATUS_ENABLED_MASK BIT(0) 123 124 #define THROT_PSKIP_CTRL_LITE_CPU 0x430 125 #define THROT_PSKIP_CTRL_ENABLE_MASK BIT(31) 126 #define THROT_PSKIP_CTRL_DIVIDEND_MASK (0xff << 8) 127 #define THROT_PSKIP_CTRL_DIVISOR_MASK 0xff 128 #define THROT_PSKIP_CTRL_VECT_GPU_MASK (0x7 << 16) 129 #define THROT_PSKIP_CTRL_VECT_CPU_MASK (0x7 << 8) 130 #define THROT_PSKIP_CTRL_VECT2_CPU_MASK 0x7 131 132 #define THROT_VECT_NONE 0x0 /* 3'b000 */ 133 #define THROT_VECT_LOW 0x1 /* 3'b001 */ 134 #define THROT_VECT_MED 0x3 /* 3'b011 */ 135 #define THROT_VECT_HIGH 0x7 /* 3'b111 */ 136 137 #define THROT_PSKIP_RAMP_LITE_CPU 0x434 138 #define THROT_PSKIP_RAMP_SEQ_BYPASS_MODE_MASK BIT(31) 139 #define THROT_PSKIP_RAMP_DURATION_MASK (0xffff << 8) 140 #define THROT_PSKIP_RAMP_STEP_MASK 0xff 141 142 #define THROT_PRIORITY_LITE 0x444 143 #define THROT_PRIORITY_LITE_PRIO_MASK 0xff 144 145 #define THROT_DELAY_LITE 0x448 146 #define THROT_DELAY_LITE_DELAY_MASK 0xff 147 148 /* car register offsets needed for enabling HW throttling */ 149 #define CAR_SUPER_CCLKG_DIVIDER 0x36c 150 #define CDIVG_USE_THERM_CONTROLS_MASK BIT(30) 151 152 /* ccroc register offsets needed for enabling HW throttling for Tegra132 */ 153 #define CCROC_SUPER_CCLKG_DIVIDER 0x024 154 155 #define CCROC_GLOBAL_CFG 0x148 156 157 #define CCROC_THROT_PSKIP_RAMP_CPU 0x150 158 #define CCROC_THROT_PSKIP_RAMP_SEQ_BYPASS_MODE_MASK BIT(31) 159 #define CCROC_THROT_PSKIP_RAMP_DURATION_MASK (0xffff << 8) 160 #define CCROC_THROT_PSKIP_RAMP_STEP_MASK 0xff 161 162 #define CCROC_THROT_PSKIP_CTRL_CPU 0x154 163 #define CCROC_THROT_PSKIP_CTRL_ENB_MASK BIT(31) 164 #define CCROC_THROT_PSKIP_CTRL_DIVIDEND_MASK (0xff << 8) 165 #define CCROC_THROT_PSKIP_CTRL_DIVISOR_MASK 0xff 166 167 /* get val from register(r) mask bits(m) */ 168 #define REG_GET_MASK(r, m) (((r) & (m)) >> (ffs(m) - 1)) 169 /* set val(v) to mask bits(m) of register(r) */ 170 #define REG_SET_MASK(r, m, v) (((r) & ~(m)) | \ 171 (((v) & (m >> (ffs(m) - 1))) << (ffs(m) - 1))) 172 173 /* get dividend from the depth */ 174 #define THROT_DEPTH_DIVIDEND(depth) ((256 * (100 - (depth)) / 100) - 1) 175 176 /* gk20a nv_therm interface N:3 Mapping. Levels defined in tegra124-sochterm.h 177 * level vector 178 * NONE 3'b000 179 * LOW 3'b001 180 * MED 3'b011 181 * HIGH 3'b111 182 */ 183 #define THROT_LEVEL_TO_DEPTH(level) ((0x1 << (level)) - 1) 184 185 /* get THROT_PSKIP_xxx offset per LIGHT/HEAVY throt and CPU/GPU dev */ 186 #define THROT_OFFSET 0x30 187 #define THROT_PSKIP_CTRL(throt, dev) (THROT_PSKIP_CTRL_LITE_CPU + \ 188 (THROT_OFFSET * throt) + (8 * dev)) 189 #define THROT_PSKIP_RAMP(throt, dev) (THROT_PSKIP_RAMP_LITE_CPU + \ 190 (THROT_OFFSET * throt) + (8 * dev)) 191 192 /* get THROT_xxx_CTRL offset per LIGHT/HEAVY throt */ 193 #define THROT_PRIORITY_CTRL(throt) (THROT_PRIORITY_LITE + \ 194 (THROT_OFFSET * throt)) 195 #define THROT_DELAY_CTRL(throt) (THROT_DELAY_LITE + \ 196 (THROT_OFFSET * throt)) 197 198 /* get CCROC_THROT_PSKIP_xxx offset per HIGH/MED/LOW vect*/ 199 #define CCROC_THROT_OFFSET 0x0c 200 #define CCROC_THROT_PSKIP_CTRL_CPU_REG(vect) (CCROC_THROT_PSKIP_CTRL_CPU + \ 201 (CCROC_THROT_OFFSET * vect)) 202 #define CCROC_THROT_PSKIP_RAMP_CPU_REG(vect) (CCROC_THROT_PSKIP_RAMP_CPU + \ 203 (CCROC_THROT_OFFSET * vect)) 204 205 /* get THERMCTL_LEVELx offset per CPU/GPU/MEM/TSENSE rg and LEVEL0~3 lv */ 206 #define THERMCTL_LVL_REGS_SIZE 0x20 207 #define THERMCTL_LVL_REG(rg, lv) ((rg) + ((lv) * THERMCTL_LVL_REGS_SIZE)) 208 209 static const int min_low_temp = -127000; 210 static const int max_high_temp = 127000; 211 212 enum soctherm_throttle_id { 213 THROTTLE_LIGHT = 0, 214 THROTTLE_HEAVY, 215 THROTTLE_SIZE, 216 }; 217 218 enum soctherm_throttle_dev_id { 219 THROTTLE_DEV_CPU = 0, 220 THROTTLE_DEV_GPU, 221 THROTTLE_DEV_SIZE, 222 }; 223 224 static const char *const throt_names[] = { 225 [THROTTLE_LIGHT] = "light", 226 [THROTTLE_HEAVY] = "heavy", 227 }; 228 229 struct tegra_soctherm; 230 struct tegra_thermctl_zone { 231 void __iomem *reg; 232 struct device *dev; 233 struct tegra_soctherm *ts; 234 struct thermal_zone_device *tz; 235 const struct tegra_tsensor_group *sg; 236 }; 237 238 struct soctherm_throt_cfg { 239 const char *name; 240 unsigned int id; 241 u8 priority; 242 u8 cpu_throt_level; 243 u32 cpu_throt_depth; 244 u32 gpu_throt_level; 245 struct thermal_cooling_device *cdev; 246 bool init; 247 }; 248 249 struct tegra_soctherm { 250 struct reset_control *reset; 251 struct clk *clock_tsensor; 252 struct clk *clock_soctherm; 253 void __iomem *regs; 254 void __iomem *clk_regs; 255 void __iomem *ccroc_regs; 256 257 int thermal_irq; 258 259 u32 *calib; 260 struct thermal_zone_device **thermctl_tzs; 261 struct tegra_soctherm_soc *soc; 262 263 struct soctherm_throt_cfg throt_cfgs[THROTTLE_SIZE]; 264 265 struct dentry *debugfs_dir; 266 267 struct mutex thermctl_lock; 268 }; 269 270 /** 271 * ccroc_writel() - writes a value to a CCROC register 272 * @ts: pointer to a struct tegra_soctherm 273 * @v: the value to write 274 * @reg: the register offset 275 * 276 * Writes @v to @reg. No return value. 277 */ 278 static inline void ccroc_writel(struct tegra_soctherm *ts, u32 value, u32 reg) 279 { 280 writel(value, (ts->ccroc_regs + reg)); 281 } 282 283 /** 284 * ccroc_readl() - reads specified register from CCROC IP block 285 * @ts: pointer to a struct tegra_soctherm 286 * @reg: register address to be read 287 * 288 * Return: the value of the register 289 */ 290 static inline u32 ccroc_readl(struct tegra_soctherm *ts, u32 reg) 291 { 292 return readl(ts->ccroc_regs + reg); 293 } 294 295 static void enable_tsensor(struct tegra_soctherm *tegra, unsigned int i) 296 { 297 const struct tegra_tsensor *sensor = &tegra->soc->tsensors[i]; 298 void __iomem *base = tegra->regs + sensor->base; 299 unsigned int val; 300 301 val = sensor->config->tall << SENSOR_CONFIG0_TALL_SHIFT; 302 writel(val, base + SENSOR_CONFIG0); 303 304 val = (sensor->config->tsample - 1) << SENSOR_CONFIG1_TSAMPLE_SHIFT; 305 val |= sensor->config->tiddq_en << SENSOR_CONFIG1_TIDDQ_EN_SHIFT; 306 val |= sensor->config->ten_count << SENSOR_CONFIG1_TEN_COUNT_SHIFT; 307 val |= SENSOR_CONFIG1_TEMP_ENABLE; 308 writel(val, base + SENSOR_CONFIG1); 309 310 writel(tegra->calib[i], base + SENSOR_CONFIG2); 311 } 312 313 /* 314 * Translate from soctherm readback format to millicelsius. 315 * The soctherm readback format in bits is as follows: 316 * TTTTTTTT H______N 317 * where T's contain the temperature in Celsius, 318 * H denotes an addition of 0.5 Celsius and N denotes negation 319 * of the final value. 320 */ 321 static int translate_temp(u16 val) 322 { 323 int t; 324 325 t = ((val & READBACK_VALUE_MASK) >> READBACK_VALUE_SHIFT) * 1000; 326 if (val & READBACK_ADD_HALF) 327 t += 500; 328 if (val & READBACK_NEGATE) 329 t *= -1; 330 331 return t; 332 } 333 334 static int tegra_thermctl_get_temp(void *data, int *out_temp) 335 { 336 struct tegra_thermctl_zone *zone = data; 337 u32 val; 338 339 val = readl(zone->reg); 340 val = REG_GET_MASK(val, zone->sg->sensor_temp_mask); 341 *out_temp = translate_temp(val); 342 343 return 0; 344 } 345 346 /** 347 * enforce_temp_range() - check and enforce temperature range [min, max] 348 * @trip_temp: the trip temperature to check 349 * 350 * Checks and enforces the permitted temperature range that SOC_THERM 351 * HW can support This is 352 * done while taking care of precision. 353 * 354 * Return: The precision adjusted capped temperature in millicelsius. 355 */ 356 static int enforce_temp_range(struct device *dev, int trip_temp) 357 { 358 int temp; 359 360 temp = clamp_val(trip_temp, min_low_temp, max_high_temp); 361 if (temp != trip_temp) 362 dev_info(dev, "soctherm: trip temperature %d forced to %d\n", 363 trip_temp, temp); 364 return temp; 365 } 366 367 /** 368 * thermtrip_program() - Configures the hardware to shut down the 369 * system if a given sensor group reaches a given temperature 370 * @dev: ptr to the struct device for the SOC_THERM IP block 371 * @sg: pointer to the sensor group to set the thermtrip temperature for 372 * @trip_temp: the temperature in millicelsius to trigger the thermal trip at 373 * 374 * Sets the thermal trip threshold of the given sensor group to be the 375 * @trip_temp. If this threshold is crossed, the hardware will shut 376 * down. 377 * 378 * Note that, although @trip_temp is specified in millicelsius, the 379 * hardware is programmed in degrees Celsius. 380 * 381 * Return: 0 upon success, or %-EINVAL upon failure. 382 */ 383 static int thermtrip_program(struct device *dev, 384 const struct tegra_tsensor_group *sg, 385 int trip_temp) 386 { 387 struct tegra_soctherm *ts = dev_get_drvdata(dev); 388 int temp; 389 u32 r; 390 391 if (!sg || !sg->thermtrip_threshold_mask) 392 return -EINVAL; 393 394 temp = enforce_temp_range(dev, trip_temp) / ts->soc->thresh_grain; 395 396 r = readl(ts->regs + THERMCTL_THERMTRIP_CTL); 397 r = REG_SET_MASK(r, sg->thermtrip_threshold_mask, temp); 398 r = REG_SET_MASK(r, sg->thermtrip_enable_mask, 1); 399 r = REG_SET_MASK(r, sg->thermtrip_any_en_mask, 0); 400 writel(r, ts->regs + THERMCTL_THERMTRIP_CTL); 401 402 return 0; 403 } 404 405 /** 406 * throttrip_program() - Configures the hardware to throttle the 407 * pulse if a given sensor group reaches a given temperature 408 * @dev: ptr to the struct device for the SOC_THERM IP block 409 * @sg: pointer to the sensor group to set the thermtrip temperature for 410 * @stc: pointer to the throttle need to be triggered 411 * @trip_temp: the temperature in millicelsius to trigger the thermal trip at 412 * 413 * Sets the thermal trip threshold and throttle event of the given sensor 414 * group. If this threshold is crossed, the hardware will trigger the 415 * throttle. 416 * 417 * Note that, although @trip_temp is specified in millicelsius, the 418 * hardware is programmed in degrees Celsius. 419 * 420 * Return: 0 upon success, or %-EINVAL upon failure. 421 */ 422 static int throttrip_program(struct device *dev, 423 const struct tegra_tsensor_group *sg, 424 struct soctherm_throt_cfg *stc, 425 int trip_temp) 426 { 427 struct tegra_soctherm *ts = dev_get_drvdata(dev); 428 int temp, cpu_throt, gpu_throt; 429 unsigned int throt; 430 u32 r, reg_off; 431 432 if (!sg || !stc || !stc->init) 433 return -EINVAL; 434 435 temp = enforce_temp_range(dev, trip_temp) / ts->soc->thresh_grain; 436 437 /* Hardcode LIGHT on LEVEL1 and HEAVY on LEVEL2 */ 438 throt = stc->id; 439 reg_off = THERMCTL_LVL_REG(sg->thermctl_lvl0_offset, throt + 1); 440 441 if (throt == THROTTLE_LIGHT) { 442 cpu_throt = THERMCTL_LVL0_CPU0_CPU_THROT_LIGHT; 443 gpu_throt = THERMCTL_LVL0_CPU0_GPU_THROT_LIGHT; 444 } else { 445 cpu_throt = THERMCTL_LVL0_CPU0_CPU_THROT_HEAVY; 446 gpu_throt = THERMCTL_LVL0_CPU0_GPU_THROT_HEAVY; 447 if (throt != THROTTLE_HEAVY) 448 dev_warn(dev, 449 "invalid throt id %d - assuming HEAVY", 450 throt); 451 } 452 453 r = readl(ts->regs + reg_off); 454 r = REG_SET_MASK(r, sg->thermctl_lvl0_up_thresh_mask, temp); 455 r = REG_SET_MASK(r, sg->thermctl_lvl0_dn_thresh_mask, temp); 456 r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_CPU_THROT_MASK, cpu_throt); 457 r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_GPU_THROT_MASK, gpu_throt); 458 r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_EN_MASK, 1); 459 writel(r, ts->regs + reg_off); 460 461 return 0; 462 } 463 464 static struct soctherm_throt_cfg * 465 find_throttle_cfg_by_name(struct tegra_soctherm *ts, const char *name) 466 { 467 unsigned int i; 468 469 for (i = 0; ts->throt_cfgs[i].name; i++) 470 if (!strcmp(ts->throt_cfgs[i].name, name)) 471 return &ts->throt_cfgs[i]; 472 473 return NULL; 474 } 475 476 static int tsensor_group_thermtrip_get(struct tegra_soctherm *ts, int id) 477 { 478 int i, temp = min_low_temp; 479 struct tsensor_group_thermtrips *tt = ts->soc->thermtrips; 480 481 if (id >= TEGRA124_SOCTHERM_SENSOR_NUM) 482 return temp; 483 484 if (tt) { 485 for (i = 0; i < ts->soc->num_ttgs; i++) { 486 if (tt[i].id == id) 487 return tt[i].temp; 488 } 489 } 490 491 return temp; 492 } 493 494 static int tegra_thermctl_set_trip_temp(void *data, int trip, int temp) 495 { 496 struct tegra_thermctl_zone *zone = data; 497 struct thermal_zone_device *tz = zone->tz; 498 struct tegra_soctherm *ts = zone->ts; 499 const struct tegra_tsensor_group *sg = zone->sg; 500 struct device *dev = zone->dev; 501 enum thermal_trip_type type; 502 int ret; 503 504 if (!tz) 505 return -EINVAL; 506 507 ret = tz->ops->get_trip_type(tz, trip, &type); 508 if (ret) 509 return ret; 510 511 if (type == THERMAL_TRIP_CRITICAL) { 512 /* 513 * If thermtrips property is set in DT, 514 * doesn't need to program critical type trip to HW, 515 * if not, program critical trip to HW. 516 */ 517 if (min_low_temp == tsensor_group_thermtrip_get(ts, sg->id)) 518 return thermtrip_program(dev, sg, temp); 519 else 520 return 0; 521 522 } else if (type == THERMAL_TRIP_HOT) { 523 int i; 524 525 for (i = 0; i < THROTTLE_SIZE; i++) { 526 struct thermal_cooling_device *cdev; 527 struct soctherm_throt_cfg *stc; 528 529 if (!ts->throt_cfgs[i].init) 530 continue; 531 532 cdev = ts->throt_cfgs[i].cdev; 533 if (get_thermal_instance(tz, cdev, trip)) 534 stc = find_throttle_cfg_by_name(ts, cdev->type); 535 else 536 continue; 537 538 return throttrip_program(dev, sg, stc, temp); 539 } 540 } 541 542 return 0; 543 } 544 545 static int tegra_thermctl_get_trend(void *data, int trip, 546 enum thermal_trend *trend) 547 { 548 struct tegra_thermctl_zone *zone = data; 549 struct thermal_zone_device *tz = zone->tz; 550 int trip_temp, temp, last_temp, ret; 551 552 if (!tz) 553 return -EINVAL; 554 555 ret = tz->ops->get_trip_temp(zone->tz, trip, &trip_temp); 556 if (ret) 557 return ret; 558 559 temp = READ_ONCE(tz->temperature); 560 last_temp = READ_ONCE(tz->last_temperature); 561 562 if (temp > trip_temp) { 563 if (temp >= last_temp) 564 *trend = THERMAL_TREND_RAISING; 565 else 566 *trend = THERMAL_TREND_STABLE; 567 } else if (temp < trip_temp) { 568 *trend = THERMAL_TREND_DROPPING; 569 } else { 570 *trend = THERMAL_TREND_STABLE; 571 } 572 573 return 0; 574 } 575 576 static void thermal_irq_enable(struct tegra_thermctl_zone *zn) 577 { 578 u32 r; 579 580 /* multiple zones could be handling and setting trips at once */ 581 mutex_lock(&zn->ts->thermctl_lock); 582 r = readl(zn->ts->regs + THERMCTL_INTR_ENABLE); 583 r = REG_SET_MASK(r, zn->sg->thermctl_isr_mask, TH_INTR_UP_DN_EN); 584 writel(r, zn->ts->regs + THERMCTL_INTR_ENABLE); 585 mutex_unlock(&zn->ts->thermctl_lock); 586 } 587 588 static void thermal_irq_disable(struct tegra_thermctl_zone *zn) 589 { 590 u32 r; 591 592 /* multiple zones could be handling and setting trips at once */ 593 mutex_lock(&zn->ts->thermctl_lock); 594 r = readl(zn->ts->regs + THERMCTL_INTR_DISABLE); 595 r = REG_SET_MASK(r, zn->sg->thermctl_isr_mask, 0); 596 writel(r, zn->ts->regs + THERMCTL_INTR_DISABLE); 597 mutex_unlock(&zn->ts->thermctl_lock); 598 } 599 600 static int tegra_thermctl_set_trips(void *data, int lo, int hi) 601 { 602 struct tegra_thermctl_zone *zone = data; 603 u32 r; 604 605 thermal_irq_disable(zone); 606 607 r = readl(zone->ts->regs + zone->sg->thermctl_lvl0_offset); 608 r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_EN_MASK, 0); 609 writel(r, zone->ts->regs + zone->sg->thermctl_lvl0_offset); 610 611 lo = enforce_temp_range(zone->dev, lo) / zone->ts->soc->thresh_grain; 612 hi = enforce_temp_range(zone->dev, hi) / zone->ts->soc->thresh_grain; 613 dev_dbg(zone->dev, "%s hi:%d, lo:%d\n", __func__, hi, lo); 614 615 r = REG_SET_MASK(r, zone->sg->thermctl_lvl0_up_thresh_mask, hi); 616 r = REG_SET_MASK(r, zone->sg->thermctl_lvl0_dn_thresh_mask, lo); 617 r = REG_SET_MASK(r, THERMCTL_LVL0_CPU0_EN_MASK, 1); 618 writel(r, zone->ts->regs + zone->sg->thermctl_lvl0_offset); 619 620 thermal_irq_enable(zone); 621 622 return 0; 623 } 624 625 static const struct thermal_zone_of_device_ops tegra_of_thermal_ops = { 626 .get_temp = tegra_thermctl_get_temp, 627 .set_trip_temp = tegra_thermctl_set_trip_temp, 628 .get_trend = tegra_thermctl_get_trend, 629 .set_trips = tegra_thermctl_set_trips, 630 }; 631 632 static int get_hot_temp(struct thermal_zone_device *tz, int *trip, int *temp) 633 { 634 int ntrips, i, ret; 635 enum thermal_trip_type type; 636 637 ntrips = of_thermal_get_ntrips(tz); 638 if (ntrips <= 0) 639 return -EINVAL; 640 641 for (i = 0; i < ntrips; i++) { 642 ret = tz->ops->get_trip_type(tz, i, &type); 643 if (ret) 644 return -EINVAL; 645 if (type == THERMAL_TRIP_HOT) { 646 ret = tz->ops->get_trip_temp(tz, i, temp); 647 if (!ret) 648 *trip = i; 649 650 return ret; 651 } 652 } 653 654 return -EINVAL; 655 } 656 657 /** 658 * tegra_soctherm_set_hwtrips() - set HW trip point from DT data 659 * @dev: struct device * of the SOC_THERM instance 660 * 661 * Configure the SOC_THERM HW trip points, setting "THERMTRIP" 662 * "THROTTLE" trip points , using "thermtrips", "critical" or "hot" 663 * type trip_temp 664 * from thermal zone. 665 * After they have been configured, THERMTRIP or THROTTLE will take 666 * action when the configured SoC thermal sensor group reaches a 667 * certain temperature. 668 * 669 * Return: 0 upon success, or a negative error code on failure. 670 * "Success" does not mean that trips was enabled; it could also 671 * mean that no node was found in DT. 672 * THERMTRIP has been enabled successfully when a message similar to 673 * this one appears on the serial console: 674 * "thermtrip: will shut down when sensor group XXX reaches YYYYYY mC" 675 * THROTTLE has been enabled successfully when a message similar to 676 * this one appears on the serial console: 677 * ""throttrip: will throttle when sensor group XXX reaches YYYYYY mC" 678 */ 679 static int tegra_soctherm_set_hwtrips(struct device *dev, 680 const struct tegra_tsensor_group *sg, 681 struct thermal_zone_device *tz) 682 { 683 struct tegra_soctherm *ts = dev_get_drvdata(dev); 684 struct soctherm_throt_cfg *stc; 685 int i, trip, temperature, ret; 686 687 /* Get thermtrips. If missing, try to get critical trips. */ 688 temperature = tsensor_group_thermtrip_get(ts, sg->id); 689 if (min_low_temp == temperature) 690 if (tz->ops->get_crit_temp(tz, &temperature)) 691 temperature = max_high_temp; 692 693 ret = thermtrip_program(dev, sg, temperature); 694 if (ret) { 695 dev_err(dev, "thermtrip: %s: error during enable\n", sg->name); 696 return ret; 697 } 698 699 dev_info(dev, "thermtrip: will shut down when %s reaches %d mC\n", 700 sg->name, temperature); 701 702 ret = get_hot_temp(tz, &trip, &temperature); 703 if (ret) { 704 dev_info(dev, "throttrip: %s: missing hot temperature\n", 705 sg->name); 706 return 0; 707 } 708 709 for (i = 0; i < THROTTLE_SIZE; i++) { 710 struct thermal_cooling_device *cdev; 711 712 if (!ts->throt_cfgs[i].init) 713 continue; 714 715 cdev = ts->throt_cfgs[i].cdev; 716 if (get_thermal_instance(tz, cdev, trip)) 717 stc = find_throttle_cfg_by_name(ts, cdev->type); 718 else 719 continue; 720 721 ret = throttrip_program(dev, sg, stc, temperature); 722 if (ret) { 723 dev_err(dev, "throttrip: %s: error during enable\n", 724 sg->name); 725 return ret; 726 } 727 728 dev_info(dev, 729 "throttrip: will throttle when %s reaches %d mC\n", 730 sg->name, temperature); 731 break; 732 } 733 734 if (i == THROTTLE_SIZE) 735 dev_info(dev, "throttrip: %s: missing throttle cdev\n", 736 sg->name); 737 738 return 0; 739 } 740 741 static irqreturn_t soctherm_thermal_isr(int irq, void *dev_id) 742 { 743 struct tegra_soctherm *ts = dev_id; 744 u32 r; 745 746 /* Case for no lock: 747 * Although interrupts are enabled in set_trips, there is still no need 748 * to lock here because the interrupts are disabled before programming 749 * new trip points. Hence there cant be a interrupt on the same sensor. 750 * An interrupt can however occur on a sensor while trips are being 751 * programmed on a different one. This beign a LEVEL interrupt won't 752 * cause a new interrupt but this is taken care of by the re-reading of 753 * the STATUS register in the thread function. 754 */ 755 r = readl(ts->regs + THERMCTL_INTR_STATUS); 756 writel(r, ts->regs + THERMCTL_INTR_DISABLE); 757 758 return IRQ_WAKE_THREAD; 759 } 760 761 /** 762 * soctherm_thermal_isr_thread() - Handles a thermal interrupt request 763 * @irq: The interrupt number being requested; not used 764 * @dev_id: Opaque pointer to tegra_soctherm; 765 * 766 * Clears the interrupt status register if there are expected 767 * interrupt bits set. 768 * The interrupt(s) are then handled by updating the corresponding 769 * thermal zones. 770 * 771 * An error is logged if any unexpected interrupt bits are set. 772 * 773 * Disabled interrupts are re-enabled. 774 * 775 * Return: %IRQ_HANDLED. Interrupt was handled and no further processing 776 * is needed. 777 */ 778 static irqreturn_t soctherm_thermal_isr_thread(int irq, void *dev_id) 779 { 780 struct tegra_soctherm *ts = dev_id; 781 struct thermal_zone_device *tz; 782 u32 st, ex = 0, cp = 0, gp = 0, pl = 0, me = 0; 783 784 st = readl(ts->regs + THERMCTL_INTR_STATUS); 785 786 /* deliberately clear expected interrupts handled in SW */ 787 cp |= st & TH_INTR_CD0_MASK; 788 cp |= st & TH_INTR_CU0_MASK; 789 790 gp |= st & TH_INTR_GD0_MASK; 791 gp |= st & TH_INTR_GU0_MASK; 792 793 pl |= st & TH_INTR_PD0_MASK; 794 pl |= st & TH_INTR_PU0_MASK; 795 796 me |= st & TH_INTR_MD0_MASK; 797 me |= st & TH_INTR_MU0_MASK; 798 799 ex |= cp | gp | pl | me; 800 if (ex) { 801 writel(ex, ts->regs + THERMCTL_INTR_STATUS); 802 st &= ~ex; 803 804 if (cp) { 805 tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_CPU]; 806 thermal_zone_device_update(tz, 807 THERMAL_EVENT_UNSPECIFIED); 808 } 809 810 if (gp) { 811 tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_GPU]; 812 thermal_zone_device_update(tz, 813 THERMAL_EVENT_UNSPECIFIED); 814 } 815 816 if (pl) { 817 tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_PLLX]; 818 thermal_zone_device_update(tz, 819 THERMAL_EVENT_UNSPECIFIED); 820 } 821 822 if (me) { 823 tz = ts->thermctl_tzs[TEGRA124_SOCTHERM_SENSOR_MEM]; 824 thermal_zone_device_update(tz, 825 THERMAL_EVENT_UNSPECIFIED); 826 } 827 } 828 829 /* deliberately ignore expected interrupts NOT handled in SW */ 830 ex |= TH_INTR_IGNORE_MASK; 831 st &= ~ex; 832 833 if (st) { 834 /* Whine about any other unexpected INTR bits still set */ 835 pr_err("soctherm: Ignored unexpected INTRs 0x%08x\n", st); 836 writel(st, ts->regs + THERMCTL_INTR_STATUS); 837 } 838 839 return IRQ_HANDLED; 840 } 841 842 #ifdef CONFIG_DEBUG_FS 843 static int regs_show(struct seq_file *s, void *data) 844 { 845 struct platform_device *pdev = s->private; 846 struct tegra_soctherm *ts = platform_get_drvdata(pdev); 847 const struct tegra_tsensor *tsensors = ts->soc->tsensors; 848 const struct tegra_tsensor_group **ttgs = ts->soc->ttgs; 849 u32 r, state; 850 int i, level; 851 852 seq_puts(s, "-----TSENSE (convert HW)-----\n"); 853 854 for (i = 0; i < ts->soc->num_tsensors; i++) { 855 r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG1); 856 state = REG_GET_MASK(r, SENSOR_CONFIG1_TEMP_ENABLE); 857 858 seq_printf(s, "%s: ", tsensors[i].name); 859 seq_printf(s, "En(%d) ", state); 860 861 if (!state) { 862 seq_puts(s, "\n"); 863 continue; 864 } 865 866 state = REG_GET_MASK(r, SENSOR_CONFIG1_TIDDQ_EN_MASK); 867 seq_printf(s, "tiddq(%d) ", state); 868 state = REG_GET_MASK(r, SENSOR_CONFIG1_TEN_COUNT_MASK); 869 seq_printf(s, "ten_count(%d) ", state); 870 state = REG_GET_MASK(r, SENSOR_CONFIG1_TSAMPLE_MASK); 871 seq_printf(s, "tsample(%d) ", state + 1); 872 873 r = readl(ts->regs + tsensors[i].base + SENSOR_STATUS1); 874 state = REG_GET_MASK(r, SENSOR_STATUS1_TEMP_VALID_MASK); 875 seq_printf(s, "Temp(%d/", state); 876 state = REG_GET_MASK(r, SENSOR_STATUS1_TEMP_MASK); 877 seq_printf(s, "%d) ", translate_temp(state)); 878 879 r = readl(ts->regs + tsensors[i].base + SENSOR_STATUS0); 880 state = REG_GET_MASK(r, SENSOR_STATUS0_VALID_MASK); 881 seq_printf(s, "Capture(%d/", state); 882 state = REG_GET_MASK(r, SENSOR_STATUS0_CAPTURE_MASK); 883 seq_printf(s, "%d) ", state); 884 885 r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG0); 886 state = REG_GET_MASK(r, SENSOR_CONFIG0_STOP); 887 seq_printf(s, "Stop(%d) ", state); 888 state = REG_GET_MASK(r, SENSOR_CONFIG0_TALL_MASK); 889 seq_printf(s, "Tall(%d) ", state); 890 state = REG_GET_MASK(r, SENSOR_CONFIG0_TCALC_OVER); 891 seq_printf(s, "Over(%d/", state); 892 state = REG_GET_MASK(r, SENSOR_CONFIG0_OVER); 893 seq_printf(s, "%d/", state); 894 state = REG_GET_MASK(r, SENSOR_CONFIG0_CPTR_OVER); 895 seq_printf(s, "%d) ", state); 896 897 r = readl(ts->regs + tsensors[i].base + SENSOR_CONFIG2); 898 state = REG_GET_MASK(r, SENSOR_CONFIG2_THERMA_MASK); 899 seq_printf(s, "Therm_A/B(%d/", state); 900 state = REG_GET_MASK(r, SENSOR_CONFIG2_THERMB_MASK); 901 seq_printf(s, "%d)\n", (s16)state); 902 } 903 904 r = readl(ts->regs + SENSOR_PDIV); 905 seq_printf(s, "PDIV: 0x%x\n", r); 906 907 r = readl(ts->regs + SENSOR_HOTSPOT_OFF); 908 seq_printf(s, "HOTSPOT: 0x%x\n", r); 909 910 seq_puts(s, "\n"); 911 seq_puts(s, "-----SOC_THERM-----\n"); 912 913 r = readl(ts->regs + SENSOR_TEMP1); 914 state = REG_GET_MASK(r, SENSOR_TEMP1_CPU_TEMP_MASK); 915 seq_printf(s, "Temperatures: CPU(%d) ", translate_temp(state)); 916 state = REG_GET_MASK(r, SENSOR_TEMP1_GPU_TEMP_MASK); 917 seq_printf(s, " GPU(%d) ", translate_temp(state)); 918 r = readl(ts->regs + SENSOR_TEMP2); 919 state = REG_GET_MASK(r, SENSOR_TEMP2_PLLX_TEMP_MASK); 920 seq_printf(s, " PLLX(%d) ", translate_temp(state)); 921 state = REG_GET_MASK(r, SENSOR_TEMP2_MEM_TEMP_MASK); 922 seq_printf(s, " MEM(%d)\n", translate_temp(state)); 923 924 for (i = 0; i < ts->soc->num_ttgs; i++) { 925 seq_printf(s, "%s:\n", ttgs[i]->name); 926 for (level = 0; level < 4; level++) { 927 s32 v; 928 u32 mask; 929 u16 off = ttgs[i]->thermctl_lvl0_offset; 930 931 r = readl(ts->regs + THERMCTL_LVL_REG(off, level)); 932 933 mask = ttgs[i]->thermctl_lvl0_up_thresh_mask; 934 state = REG_GET_MASK(r, mask); 935 v = sign_extend32(state, ts->soc->bptt - 1); 936 v *= ts->soc->thresh_grain; 937 seq_printf(s, " %d: Up/Dn(%d /", level, v); 938 939 mask = ttgs[i]->thermctl_lvl0_dn_thresh_mask; 940 state = REG_GET_MASK(r, mask); 941 v = sign_extend32(state, ts->soc->bptt - 1); 942 v *= ts->soc->thresh_grain; 943 seq_printf(s, "%d ) ", v); 944 945 mask = THERMCTL_LVL0_CPU0_EN_MASK; 946 state = REG_GET_MASK(r, mask); 947 seq_printf(s, "En(%d) ", state); 948 949 mask = THERMCTL_LVL0_CPU0_CPU_THROT_MASK; 950 state = REG_GET_MASK(r, mask); 951 seq_puts(s, "CPU Throt"); 952 if (!state) 953 seq_printf(s, "(%s) ", "none"); 954 else if (state == THERMCTL_LVL0_CPU0_CPU_THROT_LIGHT) 955 seq_printf(s, "(%s) ", "L"); 956 else if (state == THERMCTL_LVL0_CPU0_CPU_THROT_HEAVY) 957 seq_printf(s, "(%s) ", "H"); 958 else 959 seq_printf(s, "(%s) ", "H+L"); 960 961 mask = THERMCTL_LVL0_CPU0_GPU_THROT_MASK; 962 state = REG_GET_MASK(r, mask); 963 seq_puts(s, "GPU Throt"); 964 if (!state) 965 seq_printf(s, "(%s) ", "none"); 966 else if (state == THERMCTL_LVL0_CPU0_GPU_THROT_LIGHT) 967 seq_printf(s, "(%s) ", "L"); 968 else if (state == THERMCTL_LVL0_CPU0_GPU_THROT_HEAVY) 969 seq_printf(s, "(%s) ", "H"); 970 else 971 seq_printf(s, "(%s) ", "H+L"); 972 973 mask = THERMCTL_LVL0_CPU0_STATUS_MASK; 974 state = REG_GET_MASK(r, mask); 975 seq_printf(s, "Status(%s)\n", 976 state == 0 ? "LO" : 977 state == 1 ? "In" : 978 state == 2 ? "Res" : "HI"); 979 } 980 } 981 982 r = readl(ts->regs + THERMCTL_STATS_CTL); 983 seq_printf(s, "STATS: Up(%s) Dn(%s)\n", 984 r & STATS_CTL_EN_UP ? "En" : "--", 985 r & STATS_CTL_EN_DN ? "En" : "--"); 986 987 for (level = 0; level < 4; level++) { 988 u16 off; 989 990 off = THERMCTL_LVL0_UP_STATS; 991 r = readl(ts->regs + THERMCTL_LVL_REG(off, level)); 992 seq_printf(s, " Level_%d Up(%d) ", level, r); 993 994 off = THERMCTL_LVL0_DN_STATS; 995 r = readl(ts->regs + THERMCTL_LVL_REG(off, level)); 996 seq_printf(s, "Dn(%d)\n", r); 997 } 998 999 r = readl(ts->regs + THERMCTL_THERMTRIP_CTL); 1000 state = REG_GET_MASK(r, ttgs[0]->thermtrip_any_en_mask); 1001 seq_printf(s, "Thermtrip Any En(%d)\n", state); 1002 for (i = 0; i < ts->soc->num_ttgs; i++) { 1003 state = REG_GET_MASK(r, ttgs[i]->thermtrip_enable_mask); 1004 seq_printf(s, " %s En(%d) ", ttgs[i]->name, state); 1005 state = REG_GET_MASK(r, ttgs[i]->thermtrip_threshold_mask); 1006 state *= ts->soc->thresh_grain; 1007 seq_printf(s, "Thresh(%d)\n", state); 1008 } 1009 1010 r = readl(ts->regs + THROT_GLOBAL_CFG); 1011 seq_puts(s, "\n"); 1012 seq_printf(s, "GLOBAL THROTTLE CONFIG: 0x%08x\n", r); 1013 1014 seq_puts(s, "---------------------------------------------------\n"); 1015 r = readl(ts->regs + THROT_STATUS); 1016 state = REG_GET_MASK(r, THROT_STATUS_BREACH_MASK); 1017 seq_printf(s, "THROT STATUS: breach(%d) ", state); 1018 state = REG_GET_MASK(r, THROT_STATUS_STATE_MASK); 1019 seq_printf(s, "state(%d) ", state); 1020 state = REG_GET_MASK(r, THROT_STATUS_ENABLED_MASK); 1021 seq_printf(s, "enabled(%d)\n", state); 1022 1023 r = readl(ts->regs + CPU_PSKIP_STATUS); 1024 if (ts->soc->use_ccroc) { 1025 state = REG_GET_MASK(r, XPU_PSKIP_STATUS_ENABLED_MASK); 1026 seq_printf(s, "CPU PSKIP STATUS: enabled(%d)\n", state); 1027 } else { 1028 state = REG_GET_MASK(r, XPU_PSKIP_STATUS_M_MASK); 1029 seq_printf(s, "CPU PSKIP STATUS: M(%d) ", state); 1030 state = REG_GET_MASK(r, XPU_PSKIP_STATUS_N_MASK); 1031 seq_printf(s, "N(%d) ", state); 1032 state = REG_GET_MASK(r, XPU_PSKIP_STATUS_ENABLED_MASK); 1033 seq_printf(s, "enabled(%d)\n", state); 1034 } 1035 1036 return 0; 1037 } 1038 1039 DEFINE_SHOW_ATTRIBUTE(regs); 1040 1041 static void soctherm_debug_init(struct platform_device *pdev) 1042 { 1043 struct tegra_soctherm *tegra = platform_get_drvdata(pdev); 1044 struct dentry *root, *file; 1045 1046 root = debugfs_create_dir("soctherm", NULL); 1047 if (!root) { 1048 dev_err(&pdev->dev, "failed to create debugfs directory\n"); 1049 return; 1050 } 1051 1052 tegra->debugfs_dir = root; 1053 1054 file = debugfs_create_file("reg_contents", 0644, root, 1055 pdev, ®s_fops); 1056 if (!file) { 1057 dev_err(&pdev->dev, "failed to create debugfs file\n"); 1058 debugfs_remove_recursive(tegra->debugfs_dir); 1059 tegra->debugfs_dir = NULL; 1060 } 1061 } 1062 #else 1063 static inline void soctherm_debug_init(struct platform_device *pdev) {} 1064 #endif 1065 1066 static int soctherm_clk_enable(struct platform_device *pdev, bool enable) 1067 { 1068 struct tegra_soctherm *tegra = platform_get_drvdata(pdev); 1069 int err; 1070 1071 if (!tegra->clock_soctherm || !tegra->clock_tsensor) 1072 return -EINVAL; 1073 1074 reset_control_assert(tegra->reset); 1075 1076 if (enable) { 1077 err = clk_prepare_enable(tegra->clock_soctherm); 1078 if (err) { 1079 reset_control_deassert(tegra->reset); 1080 return err; 1081 } 1082 1083 err = clk_prepare_enable(tegra->clock_tsensor); 1084 if (err) { 1085 clk_disable_unprepare(tegra->clock_soctherm); 1086 reset_control_deassert(tegra->reset); 1087 return err; 1088 } 1089 } else { 1090 clk_disable_unprepare(tegra->clock_tsensor); 1091 clk_disable_unprepare(tegra->clock_soctherm); 1092 } 1093 1094 reset_control_deassert(tegra->reset); 1095 1096 return 0; 1097 } 1098 1099 static int throt_get_cdev_max_state(struct thermal_cooling_device *cdev, 1100 unsigned long *max_state) 1101 { 1102 *max_state = 1; 1103 return 0; 1104 } 1105 1106 static int throt_get_cdev_cur_state(struct thermal_cooling_device *cdev, 1107 unsigned long *cur_state) 1108 { 1109 struct tegra_soctherm *ts = cdev->devdata; 1110 u32 r; 1111 1112 r = readl(ts->regs + THROT_STATUS); 1113 if (REG_GET_MASK(r, THROT_STATUS_STATE_MASK)) 1114 *cur_state = 1; 1115 else 1116 *cur_state = 0; 1117 1118 return 0; 1119 } 1120 1121 static int throt_set_cdev_state(struct thermal_cooling_device *cdev, 1122 unsigned long cur_state) 1123 { 1124 return 0; 1125 } 1126 1127 static const struct thermal_cooling_device_ops throt_cooling_ops = { 1128 .get_max_state = throt_get_cdev_max_state, 1129 .get_cur_state = throt_get_cdev_cur_state, 1130 .set_cur_state = throt_set_cdev_state, 1131 }; 1132 1133 static int soctherm_thermtrips_parse(struct platform_device *pdev) 1134 { 1135 struct device *dev = &pdev->dev; 1136 struct tegra_soctherm *ts = dev_get_drvdata(dev); 1137 struct tsensor_group_thermtrips *tt = ts->soc->thermtrips; 1138 const int max_num_prop = ts->soc->num_ttgs * 2; 1139 u32 *tlb; 1140 int i, j, n, ret; 1141 1142 if (!tt) 1143 return -ENOMEM; 1144 1145 n = of_property_count_u32_elems(dev->of_node, "nvidia,thermtrips"); 1146 if (n <= 0) { 1147 dev_info(dev, 1148 "missing thermtrips, will use critical trips as shut down temp\n"); 1149 return n; 1150 } 1151 1152 n = min(max_num_prop, n); 1153 1154 tlb = devm_kcalloc(&pdev->dev, max_num_prop, sizeof(u32), GFP_KERNEL); 1155 if (!tlb) 1156 return -ENOMEM; 1157 ret = of_property_read_u32_array(dev->of_node, "nvidia,thermtrips", 1158 tlb, n); 1159 if (ret) { 1160 dev_err(dev, "invalid num ele: thermtrips:%d\n", ret); 1161 return ret; 1162 } 1163 1164 i = 0; 1165 for (j = 0; j < n; j = j + 2) { 1166 if (tlb[j] >= TEGRA124_SOCTHERM_SENSOR_NUM) 1167 continue; 1168 1169 tt[i].id = tlb[j]; 1170 tt[i].temp = tlb[j + 1]; 1171 i++; 1172 } 1173 1174 return 0; 1175 } 1176 1177 static int soctherm_throt_cfg_parse(struct device *dev, 1178 struct device_node *np, 1179 struct soctherm_throt_cfg *stc) 1180 { 1181 struct tegra_soctherm *ts = dev_get_drvdata(dev); 1182 int ret; 1183 u32 val; 1184 1185 ret = of_property_read_u32(np, "nvidia,priority", &val); 1186 if (ret) { 1187 dev_err(dev, "throttle-cfg: %s: invalid priority\n", stc->name); 1188 return -EINVAL; 1189 } 1190 stc->priority = val; 1191 1192 ret = of_property_read_u32(np, ts->soc->use_ccroc ? 1193 "nvidia,cpu-throt-level" : 1194 "nvidia,cpu-throt-percent", &val); 1195 if (!ret) { 1196 if (ts->soc->use_ccroc && 1197 val <= TEGRA_SOCTHERM_THROT_LEVEL_HIGH) 1198 stc->cpu_throt_level = val; 1199 else if (!ts->soc->use_ccroc && val <= 100) 1200 stc->cpu_throt_depth = val; 1201 else 1202 goto err; 1203 } else { 1204 goto err; 1205 } 1206 1207 ret = of_property_read_u32(np, "nvidia,gpu-throt-level", &val); 1208 if (!ret && val <= TEGRA_SOCTHERM_THROT_LEVEL_HIGH) 1209 stc->gpu_throt_level = val; 1210 else 1211 goto err; 1212 1213 return 0; 1214 1215 err: 1216 dev_err(dev, "throttle-cfg: %s: no throt prop or invalid prop\n", 1217 stc->name); 1218 return -EINVAL; 1219 } 1220 1221 /** 1222 * soctherm_init_hw_throt_cdev() - Parse the HW throttle configurations 1223 * and register them as cooling devices. 1224 */ 1225 static void soctherm_init_hw_throt_cdev(struct platform_device *pdev) 1226 { 1227 struct device *dev = &pdev->dev; 1228 struct tegra_soctherm *ts = dev_get_drvdata(dev); 1229 struct device_node *np_stc, *np_stcc; 1230 const char *name; 1231 int i; 1232 1233 for (i = 0; i < THROTTLE_SIZE; i++) { 1234 ts->throt_cfgs[i].name = throt_names[i]; 1235 ts->throt_cfgs[i].id = i; 1236 ts->throt_cfgs[i].init = false; 1237 } 1238 1239 np_stc = of_get_child_by_name(dev->of_node, "throttle-cfgs"); 1240 if (!np_stc) { 1241 dev_info(dev, 1242 "throttle-cfg: no throttle-cfgs - not enabling\n"); 1243 return; 1244 } 1245 1246 for_each_child_of_node(np_stc, np_stcc) { 1247 struct soctherm_throt_cfg *stc; 1248 struct thermal_cooling_device *tcd; 1249 int err; 1250 1251 name = np_stcc->name; 1252 stc = find_throttle_cfg_by_name(ts, name); 1253 if (!stc) { 1254 dev_err(dev, 1255 "throttle-cfg: could not find %s\n", name); 1256 continue; 1257 } 1258 1259 1260 err = soctherm_throt_cfg_parse(dev, np_stcc, stc); 1261 if (err) 1262 continue; 1263 1264 tcd = thermal_of_cooling_device_register(np_stcc, 1265 (char *)name, ts, 1266 &throt_cooling_ops); 1267 of_node_put(np_stcc); 1268 if (IS_ERR_OR_NULL(tcd)) { 1269 dev_err(dev, 1270 "throttle-cfg: %s: failed to register cooling device\n", 1271 name); 1272 continue; 1273 } 1274 1275 stc->cdev = tcd; 1276 stc->init = true; 1277 } 1278 1279 of_node_put(np_stc); 1280 } 1281 1282 /** 1283 * throttlectl_cpu_level_cfg() - programs CCROC NV_THERM level config 1284 * @level: describing the level LOW/MED/HIGH of throttling 1285 * 1286 * It's necessary to set up the CPU-local CCROC NV_THERM instance with 1287 * the M/N values desired for each level. This function does this. 1288 * 1289 * This function pre-programs the CCROC NV_THERM levels in terms of 1290 * pre-configured "Low", "Medium" or "Heavy" throttle levels which are 1291 * mapped to THROT_LEVEL_LOW, THROT_LEVEL_MED and THROT_LEVEL_HVY. 1292 */ 1293 static void throttlectl_cpu_level_cfg(struct tegra_soctherm *ts, int level) 1294 { 1295 u8 depth, dividend; 1296 u32 r; 1297 1298 switch (level) { 1299 case TEGRA_SOCTHERM_THROT_LEVEL_LOW: 1300 depth = 50; 1301 break; 1302 case TEGRA_SOCTHERM_THROT_LEVEL_MED: 1303 depth = 75; 1304 break; 1305 case TEGRA_SOCTHERM_THROT_LEVEL_HIGH: 1306 depth = 80; 1307 break; 1308 case TEGRA_SOCTHERM_THROT_LEVEL_NONE: 1309 return; 1310 default: 1311 return; 1312 } 1313 1314 dividend = THROT_DEPTH_DIVIDEND(depth); 1315 1316 /* setup PSKIP in ccroc nv_therm registers */ 1317 r = ccroc_readl(ts, CCROC_THROT_PSKIP_RAMP_CPU_REG(level)); 1318 r = REG_SET_MASK(r, CCROC_THROT_PSKIP_RAMP_DURATION_MASK, 0xff); 1319 r = REG_SET_MASK(r, CCROC_THROT_PSKIP_RAMP_STEP_MASK, 0xf); 1320 ccroc_writel(ts, r, CCROC_THROT_PSKIP_RAMP_CPU_REG(level)); 1321 1322 r = ccroc_readl(ts, CCROC_THROT_PSKIP_CTRL_CPU_REG(level)); 1323 r = REG_SET_MASK(r, CCROC_THROT_PSKIP_CTRL_ENB_MASK, 1); 1324 r = REG_SET_MASK(r, CCROC_THROT_PSKIP_CTRL_DIVIDEND_MASK, dividend); 1325 r = REG_SET_MASK(r, CCROC_THROT_PSKIP_CTRL_DIVISOR_MASK, 0xff); 1326 ccroc_writel(ts, r, CCROC_THROT_PSKIP_CTRL_CPU_REG(level)); 1327 } 1328 1329 /** 1330 * throttlectl_cpu_level_select() - program CPU pulse skipper config 1331 * @throt: the LIGHT/HEAVY of throttle event id 1332 * 1333 * Pulse skippers are used to throttle clock frequencies. This 1334 * function programs the pulse skippers based on @throt and platform 1335 * data. This function is used on SoCs which have CPU-local pulse 1336 * skipper control, such as T13x. It programs soctherm's interface to 1337 * Denver:CCROC NV_THERM in terms of Low, Medium and HIGH throttling 1338 * vectors. PSKIP_BYPASS mode is set as required per HW spec. 1339 */ 1340 static void throttlectl_cpu_level_select(struct tegra_soctherm *ts, 1341 enum soctherm_throttle_id throt) 1342 { 1343 u32 r, throt_vect; 1344 1345 /* Denver:CCROC NV_THERM interface N:3 Mapping */ 1346 switch (ts->throt_cfgs[throt].cpu_throt_level) { 1347 case TEGRA_SOCTHERM_THROT_LEVEL_LOW: 1348 throt_vect = THROT_VECT_LOW; 1349 break; 1350 case TEGRA_SOCTHERM_THROT_LEVEL_MED: 1351 throt_vect = THROT_VECT_MED; 1352 break; 1353 case TEGRA_SOCTHERM_THROT_LEVEL_HIGH: 1354 throt_vect = THROT_VECT_HIGH; 1355 break; 1356 default: 1357 throt_vect = THROT_VECT_NONE; 1358 break; 1359 } 1360 1361 r = readl(ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU)); 1362 r = REG_SET_MASK(r, THROT_PSKIP_CTRL_ENABLE_MASK, 1); 1363 r = REG_SET_MASK(r, THROT_PSKIP_CTRL_VECT_CPU_MASK, throt_vect); 1364 r = REG_SET_MASK(r, THROT_PSKIP_CTRL_VECT2_CPU_MASK, throt_vect); 1365 writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU)); 1366 1367 /* bypass sequencer in soc_therm as it is programmed in ccroc */ 1368 r = REG_SET_MASK(0, THROT_PSKIP_RAMP_SEQ_BYPASS_MODE_MASK, 1); 1369 writel(r, ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU)); 1370 } 1371 1372 /** 1373 * throttlectl_cpu_mn() - program CPU pulse skipper configuration 1374 * @throt: the LIGHT/HEAVY of throttle event id 1375 * 1376 * Pulse skippers are used to throttle clock frequencies. This 1377 * function programs the pulse skippers based on @throt and platform 1378 * data. This function is used for CPUs that have "remote" pulse 1379 * skipper control, e.g., the CPU pulse skipper is controlled by the 1380 * SOC_THERM IP block. (SOC_THERM is located outside the CPU 1381 * complex.) 1382 */ 1383 static void throttlectl_cpu_mn(struct tegra_soctherm *ts, 1384 enum soctherm_throttle_id throt) 1385 { 1386 u32 r; 1387 int depth; 1388 u8 dividend; 1389 1390 depth = ts->throt_cfgs[throt].cpu_throt_depth; 1391 dividend = THROT_DEPTH_DIVIDEND(depth); 1392 1393 r = readl(ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU)); 1394 r = REG_SET_MASK(r, THROT_PSKIP_CTRL_ENABLE_MASK, 1); 1395 r = REG_SET_MASK(r, THROT_PSKIP_CTRL_DIVIDEND_MASK, dividend); 1396 r = REG_SET_MASK(r, THROT_PSKIP_CTRL_DIVISOR_MASK, 0xff); 1397 writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_CPU)); 1398 1399 r = readl(ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU)); 1400 r = REG_SET_MASK(r, THROT_PSKIP_RAMP_DURATION_MASK, 0xff); 1401 r = REG_SET_MASK(r, THROT_PSKIP_RAMP_STEP_MASK, 0xf); 1402 writel(r, ts->regs + THROT_PSKIP_RAMP(throt, THROTTLE_DEV_CPU)); 1403 } 1404 1405 /** 1406 * throttlectl_gpu_level_select() - selects throttling level for GPU 1407 * @throt: the LIGHT/HEAVY of throttle event id 1408 * 1409 * This function programs soctherm's interface to GK20a NV_THERM to select 1410 * pre-configured "Low", "Medium" or "Heavy" throttle levels. 1411 * 1412 * Return: boolean true if HW was programmed 1413 */ 1414 static void throttlectl_gpu_level_select(struct tegra_soctherm *ts, 1415 enum soctherm_throttle_id throt) 1416 { 1417 u32 r, level, throt_vect; 1418 1419 level = ts->throt_cfgs[throt].gpu_throt_level; 1420 throt_vect = THROT_LEVEL_TO_DEPTH(level); 1421 r = readl(ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_GPU)); 1422 r = REG_SET_MASK(r, THROT_PSKIP_CTRL_ENABLE_MASK, 1); 1423 r = REG_SET_MASK(r, THROT_PSKIP_CTRL_VECT_GPU_MASK, throt_vect); 1424 writel(r, ts->regs + THROT_PSKIP_CTRL(throt, THROTTLE_DEV_GPU)); 1425 } 1426 1427 /** 1428 * soctherm_throttle_program() - programs pulse skippers' configuration 1429 * @throt: the LIGHT/HEAVY of the throttle event id. 1430 * 1431 * Pulse skippers are used to throttle clock frequencies. 1432 * This function programs the pulse skippers. 1433 */ 1434 static void soctherm_throttle_program(struct tegra_soctherm *ts, 1435 enum soctherm_throttle_id throt) 1436 { 1437 u32 r; 1438 struct soctherm_throt_cfg stc = ts->throt_cfgs[throt]; 1439 1440 if (!stc.init) 1441 return; 1442 1443 /* Setup PSKIP parameters */ 1444 if (ts->soc->use_ccroc) 1445 throttlectl_cpu_level_select(ts, throt); 1446 else 1447 throttlectl_cpu_mn(ts, throt); 1448 1449 throttlectl_gpu_level_select(ts, throt); 1450 1451 r = REG_SET_MASK(0, THROT_PRIORITY_LITE_PRIO_MASK, stc.priority); 1452 writel(r, ts->regs + THROT_PRIORITY_CTRL(throt)); 1453 1454 r = REG_SET_MASK(0, THROT_DELAY_LITE_DELAY_MASK, 0); 1455 writel(r, ts->regs + THROT_DELAY_CTRL(throt)); 1456 1457 r = readl(ts->regs + THROT_PRIORITY_LOCK); 1458 r = REG_GET_MASK(r, THROT_PRIORITY_LOCK_PRIORITY_MASK); 1459 if (r >= stc.priority) 1460 return; 1461 r = REG_SET_MASK(0, THROT_PRIORITY_LOCK_PRIORITY_MASK, 1462 stc.priority); 1463 writel(r, ts->regs + THROT_PRIORITY_LOCK); 1464 } 1465 1466 static void tegra_soctherm_throttle(struct device *dev) 1467 { 1468 struct tegra_soctherm *ts = dev_get_drvdata(dev); 1469 u32 v; 1470 int i; 1471 1472 /* configure LOW, MED and HIGH levels for CCROC NV_THERM */ 1473 if (ts->soc->use_ccroc) { 1474 throttlectl_cpu_level_cfg(ts, TEGRA_SOCTHERM_THROT_LEVEL_LOW); 1475 throttlectl_cpu_level_cfg(ts, TEGRA_SOCTHERM_THROT_LEVEL_MED); 1476 throttlectl_cpu_level_cfg(ts, TEGRA_SOCTHERM_THROT_LEVEL_HIGH); 1477 } 1478 1479 /* Thermal HW throttle programming */ 1480 for (i = 0; i < THROTTLE_SIZE; i++) 1481 soctherm_throttle_program(ts, i); 1482 1483 v = REG_SET_MASK(0, THROT_GLOBAL_ENB_MASK, 1); 1484 if (ts->soc->use_ccroc) { 1485 ccroc_writel(ts, v, CCROC_GLOBAL_CFG); 1486 1487 v = ccroc_readl(ts, CCROC_SUPER_CCLKG_DIVIDER); 1488 v = REG_SET_MASK(v, CDIVG_USE_THERM_CONTROLS_MASK, 1); 1489 ccroc_writel(ts, v, CCROC_SUPER_CCLKG_DIVIDER); 1490 } else { 1491 writel(v, ts->regs + THROT_GLOBAL_CFG); 1492 1493 v = readl(ts->clk_regs + CAR_SUPER_CCLKG_DIVIDER); 1494 v = REG_SET_MASK(v, CDIVG_USE_THERM_CONTROLS_MASK, 1); 1495 writel(v, ts->clk_regs + CAR_SUPER_CCLKG_DIVIDER); 1496 } 1497 1498 /* initialize stats collection */ 1499 v = STATS_CTL_CLR_DN | STATS_CTL_EN_DN | 1500 STATS_CTL_CLR_UP | STATS_CTL_EN_UP; 1501 writel(v, ts->regs + THERMCTL_STATS_CTL); 1502 } 1503 1504 static int soctherm_interrupts_init(struct platform_device *pdev, 1505 struct tegra_soctherm *tegra) 1506 { 1507 int ret; 1508 1509 tegra->thermal_irq = platform_get_irq(pdev, 0); 1510 if (tegra->thermal_irq < 0) { 1511 dev_dbg(&pdev->dev, "get 'thermal_irq' failed.\n"); 1512 return 0; 1513 } 1514 1515 ret = devm_request_threaded_irq(&pdev->dev, 1516 tegra->thermal_irq, 1517 soctherm_thermal_isr, 1518 soctherm_thermal_isr_thread, 1519 IRQF_ONESHOT, 1520 dev_name(&pdev->dev), 1521 tegra); 1522 if (ret < 0) { 1523 dev_err(&pdev->dev, "request_irq 'thermal_irq' failed.\n"); 1524 return ret; 1525 } 1526 1527 return 0; 1528 } 1529 1530 static void soctherm_init(struct platform_device *pdev) 1531 { 1532 struct tegra_soctherm *tegra = platform_get_drvdata(pdev); 1533 const struct tegra_tsensor_group **ttgs = tegra->soc->ttgs; 1534 int i; 1535 u32 pdiv, hotspot; 1536 1537 /* Initialize raw sensors */ 1538 for (i = 0; i < tegra->soc->num_tsensors; ++i) 1539 enable_tsensor(tegra, i); 1540 1541 /* program pdiv and hotspot offsets per THERM */ 1542 pdiv = readl(tegra->regs + SENSOR_PDIV); 1543 hotspot = readl(tegra->regs + SENSOR_HOTSPOT_OFF); 1544 for (i = 0; i < tegra->soc->num_ttgs; ++i) { 1545 pdiv = REG_SET_MASK(pdiv, ttgs[i]->pdiv_mask, 1546 ttgs[i]->pdiv); 1547 /* hotspot offset from PLLX, doesn't need to configure PLLX */ 1548 if (ttgs[i]->id == TEGRA124_SOCTHERM_SENSOR_PLLX) 1549 continue; 1550 hotspot = REG_SET_MASK(hotspot, 1551 ttgs[i]->pllx_hotspot_mask, 1552 ttgs[i]->pllx_hotspot_diff); 1553 } 1554 writel(pdiv, tegra->regs + SENSOR_PDIV); 1555 writel(hotspot, tegra->regs + SENSOR_HOTSPOT_OFF); 1556 1557 /* Configure hw throttle */ 1558 tegra_soctherm_throttle(&pdev->dev); 1559 } 1560 1561 static const struct of_device_id tegra_soctherm_of_match[] = { 1562 #ifdef CONFIG_ARCH_TEGRA_124_SOC 1563 { 1564 .compatible = "nvidia,tegra124-soctherm", 1565 .data = &tegra124_soctherm, 1566 }, 1567 #endif 1568 #ifdef CONFIG_ARCH_TEGRA_132_SOC 1569 { 1570 .compatible = "nvidia,tegra132-soctherm", 1571 .data = &tegra132_soctherm, 1572 }, 1573 #endif 1574 #ifdef CONFIG_ARCH_TEGRA_210_SOC 1575 { 1576 .compatible = "nvidia,tegra210-soctherm", 1577 .data = &tegra210_soctherm, 1578 }, 1579 #endif 1580 { }, 1581 }; 1582 MODULE_DEVICE_TABLE(of, tegra_soctherm_of_match); 1583 1584 static int tegra_soctherm_probe(struct platform_device *pdev) 1585 { 1586 const struct of_device_id *match; 1587 struct tegra_soctherm *tegra; 1588 struct thermal_zone_device *z; 1589 struct tsensor_shared_calib shared_calib; 1590 struct resource *res; 1591 struct tegra_soctherm_soc *soc; 1592 unsigned int i; 1593 int err; 1594 1595 match = of_match_node(tegra_soctherm_of_match, pdev->dev.of_node); 1596 if (!match) 1597 return -ENODEV; 1598 1599 soc = (struct tegra_soctherm_soc *)match->data; 1600 if (soc->num_ttgs > TEGRA124_SOCTHERM_SENSOR_NUM) 1601 return -EINVAL; 1602 1603 tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL); 1604 if (!tegra) 1605 return -ENOMEM; 1606 1607 mutex_init(&tegra->thermctl_lock); 1608 dev_set_drvdata(&pdev->dev, tegra); 1609 1610 tegra->soc = soc; 1611 1612 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1613 "soctherm-reg"); 1614 tegra->regs = devm_ioremap_resource(&pdev->dev, res); 1615 if (IS_ERR(tegra->regs)) { 1616 dev_err(&pdev->dev, "can't get soctherm registers"); 1617 return PTR_ERR(tegra->regs); 1618 } 1619 1620 if (!tegra->soc->use_ccroc) { 1621 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1622 "car-reg"); 1623 tegra->clk_regs = devm_ioremap_resource(&pdev->dev, res); 1624 if (IS_ERR(tegra->clk_regs)) { 1625 dev_err(&pdev->dev, "can't get car clk registers"); 1626 return PTR_ERR(tegra->clk_regs); 1627 } 1628 } else { 1629 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, 1630 "ccroc-reg"); 1631 tegra->ccroc_regs = devm_ioremap_resource(&pdev->dev, res); 1632 if (IS_ERR(tegra->ccroc_regs)) { 1633 dev_err(&pdev->dev, "can't get ccroc registers"); 1634 return PTR_ERR(tegra->ccroc_regs); 1635 } 1636 } 1637 1638 tegra->reset = devm_reset_control_get(&pdev->dev, "soctherm"); 1639 if (IS_ERR(tegra->reset)) { 1640 dev_err(&pdev->dev, "can't get soctherm reset\n"); 1641 return PTR_ERR(tegra->reset); 1642 } 1643 1644 tegra->clock_tsensor = devm_clk_get(&pdev->dev, "tsensor"); 1645 if (IS_ERR(tegra->clock_tsensor)) { 1646 dev_err(&pdev->dev, "can't get tsensor clock\n"); 1647 return PTR_ERR(tegra->clock_tsensor); 1648 } 1649 1650 tegra->clock_soctherm = devm_clk_get(&pdev->dev, "soctherm"); 1651 if (IS_ERR(tegra->clock_soctherm)) { 1652 dev_err(&pdev->dev, "can't get soctherm clock\n"); 1653 return PTR_ERR(tegra->clock_soctherm); 1654 } 1655 1656 tegra->calib = devm_kcalloc(&pdev->dev, 1657 soc->num_tsensors, sizeof(u32), 1658 GFP_KERNEL); 1659 if (!tegra->calib) 1660 return -ENOMEM; 1661 1662 /* calculate shared calibration data */ 1663 err = tegra_calc_shared_calib(soc->tfuse, &shared_calib); 1664 if (err) 1665 return err; 1666 1667 /* calculate tsensor calibaration data */ 1668 for (i = 0; i < soc->num_tsensors; ++i) { 1669 err = tegra_calc_tsensor_calib(&soc->tsensors[i], 1670 &shared_calib, 1671 &tegra->calib[i]); 1672 if (err) 1673 return err; 1674 } 1675 1676 tegra->thermctl_tzs = devm_kcalloc(&pdev->dev, 1677 soc->num_ttgs, sizeof(z), 1678 GFP_KERNEL); 1679 if (!tegra->thermctl_tzs) 1680 return -ENOMEM; 1681 1682 err = soctherm_clk_enable(pdev, true); 1683 if (err) 1684 return err; 1685 1686 soctherm_thermtrips_parse(pdev); 1687 1688 soctherm_init_hw_throt_cdev(pdev); 1689 1690 soctherm_init(pdev); 1691 1692 for (i = 0; i < soc->num_ttgs; ++i) { 1693 struct tegra_thermctl_zone *zone = 1694 devm_kzalloc(&pdev->dev, sizeof(*zone), GFP_KERNEL); 1695 if (!zone) { 1696 err = -ENOMEM; 1697 goto disable_clocks; 1698 } 1699 1700 zone->reg = tegra->regs + soc->ttgs[i]->sensor_temp_offset; 1701 zone->dev = &pdev->dev; 1702 zone->sg = soc->ttgs[i]; 1703 zone->ts = tegra; 1704 1705 z = devm_thermal_zone_of_sensor_register(&pdev->dev, 1706 soc->ttgs[i]->id, zone, 1707 &tegra_of_thermal_ops); 1708 if (IS_ERR(z)) { 1709 err = PTR_ERR(z); 1710 dev_err(&pdev->dev, "failed to register sensor: %d\n", 1711 err); 1712 goto disable_clocks; 1713 } 1714 1715 zone->tz = z; 1716 tegra->thermctl_tzs[soc->ttgs[i]->id] = z; 1717 1718 /* Configure hw trip points */ 1719 err = tegra_soctherm_set_hwtrips(&pdev->dev, soc->ttgs[i], z); 1720 if (err) 1721 goto disable_clocks; 1722 } 1723 1724 err = soctherm_interrupts_init(pdev, tegra); 1725 1726 soctherm_debug_init(pdev); 1727 1728 return 0; 1729 1730 disable_clocks: 1731 soctherm_clk_enable(pdev, false); 1732 1733 return err; 1734 } 1735 1736 static int tegra_soctherm_remove(struct platform_device *pdev) 1737 { 1738 struct tegra_soctherm *tegra = platform_get_drvdata(pdev); 1739 1740 debugfs_remove_recursive(tegra->debugfs_dir); 1741 1742 soctherm_clk_enable(pdev, false); 1743 1744 return 0; 1745 } 1746 1747 static int __maybe_unused soctherm_suspend(struct device *dev) 1748 { 1749 struct platform_device *pdev = to_platform_device(dev); 1750 1751 soctherm_clk_enable(pdev, false); 1752 1753 return 0; 1754 } 1755 1756 static int __maybe_unused soctherm_resume(struct device *dev) 1757 { 1758 struct platform_device *pdev = to_platform_device(dev); 1759 struct tegra_soctherm *tegra = platform_get_drvdata(pdev); 1760 struct tegra_soctherm_soc *soc = tegra->soc; 1761 int err, i; 1762 1763 err = soctherm_clk_enable(pdev, true); 1764 if (err) { 1765 dev_err(&pdev->dev, 1766 "Resume failed: enable clocks failed\n"); 1767 return err; 1768 } 1769 1770 soctherm_init(pdev); 1771 1772 for (i = 0; i < soc->num_ttgs; ++i) { 1773 struct thermal_zone_device *tz; 1774 1775 tz = tegra->thermctl_tzs[soc->ttgs[i]->id]; 1776 err = tegra_soctherm_set_hwtrips(dev, soc->ttgs[i], tz); 1777 if (err) { 1778 dev_err(&pdev->dev, 1779 "Resume failed: set hwtrips failed\n"); 1780 return err; 1781 } 1782 } 1783 1784 return 0; 1785 } 1786 1787 static SIMPLE_DEV_PM_OPS(tegra_soctherm_pm, soctherm_suspend, soctherm_resume); 1788 1789 static struct platform_driver tegra_soctherm_driver = { 1790 .probe = tegra_soctherm_probe, 1791 .remove = tegra_soctherm_remove, 1792 .driver = { 1793 .name = "tegra_soctherm", 1794 .pm = &tegra_soctherm_pm, 1795 .of_match_table = tegra_soctherm_of_match, 1796 }, 1797 }; 1798 module_platform_driver(tegra_soctherm_driver); 1799 1800 MODULE_AUTHOR("Mikko Perttunen <mperttunen@nvidia.com>"); 1801 MODULE_DESCRIPTION("NVIDIA Tegra SOCTHERM thermal management driver"); 1802 MODULE_LICENSE("GPL v2"); 1803