1 /* 2 * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit) 3 * 4 * Copyright (C) 2014 Samsung Electronics 5 * Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> 6 * Lukasz Majewski <l.majewski@samsung.com> 7 * 8 * Copyright (C) 2011 Samsung Electronics 9 * Donggeun Kim <dg77.kim@samsung.com> 10 * Amit Daniel Kachhap <amit.kachhap@linaro.org> 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 * 26 */ 27 28 #include <linux/clk.h> 29 #include <linux/io.h> 30 #include <linux/interrupt.h> 31 #include <linux/module.h> 32 #include <linux/of_device.h> 33 #include <linux/of_address.h> 34 #include <linux/of_irq.h> 35 #include <linux/platform_device.h> 36 #include <linux/regulator/consumer.h> 37 38 #include "exynos_tmu.h" 39 #include "../thermal_core.h" 40 41 /* Exynos generic registers */ 42 #define EXYNOS_TMU_REG_TRIMINFO 0x0 43 #define EXYNOS_TMU_REG_CONTROL 0x20 44 #define EXYNOS_TMU_REG_STATUS 0x28 45 #define EXYNOS_TMU_REG_CURRENT_TEMP 0x40 46 #define EXYNOS_TMU_REG_INTEN 0x70 47 #define EXYNOS_TMU_REG_INTSTAT 0x74 48 #define EXYNOS_TMU_REG_INTCLEAR 0x78 49 50 #define EXYNOS_TMU_TEMP_MASK 0xff 51 #define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24 52 #define EXYNOS_TMU_REF_VOLTAGE_MASK 0x1f 53 #define EXYNOS_TMU_BUF_SLOPE_SEL_MASK 0xf 54 #define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT 8 55 #define EXYNOS_TMU_CORE_EN_SHIFT 0 56 57 /* Exynos3250 specific registers */ 58 #define EXYNOS_TMU_TRIMINFO_CON1 0x10 59 60 /* Exynos4210 specific registers */ 61 #define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44 62 #define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50 63 64 /* Exynos5250, Exynos4412, Exynos3250 specific registers */ 65 #define EXYNOS_TMU_TRIMINFO_CON2 0x14 66 #define EXYNOS_THD_TEMP_RISE 0x50 67 #define EXYNOS_THD_TEMP_FALL 0x54 68 #define EXYNOS_EMUL_CON 0x80 69 70 #define EXYNOS_TRIMINFO_RELOAD_ENABLE 1 71 #define EXYNOS_TRIMINFO_25_SHIFT 0 72 #define EXYNOS_TRIMINFO_85_SHIFT 8 73 #define EXYNOS_TMU_TRIP_MODE_SHIFT 13 74 #define EXYNOS_TMU_TRIP_MODE_MASK 0x7 75 #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12 76 77 #define EXYNOS_TMU_INTEN_RISE0_SHIFT 0 78 #define EXYNOS_TMU_INTEN_RISE1_SHIFT 4 79 #define EXYNOS_TMU_INTEN_RISE2_SHIFT 8 80 #define EXYNOS_TMU_INTEN_RISE3_SHIFT 12 81 #define EXYNOS_TMU_INTEN_FALL0_SHIFT 16 82 83 #define EXYNOS_EMUL_TIME 0x57F0 84 #define EXYNOS_EMUL_TIME_MASK 0xffff 85 #define EXYNOS_EMUL_TIME_SHIFT 16 86 #define EXYNOS_EMUL_DATA_SHIFT 8 87 #define EXYNOS_EMUL_DATA_MASK 0xFF 88 #define EXYNOS_EMUL_ENABLE 0x1 89 90 /* Exynos5260 specific */ 91 #define EXYNOS5260_TMU_REG_INTEN 0xC0 92 #define EXYNOS5260_TMU_REG_INTSTAT 0xC4 93 #define EXYNOS5260_TMU_REG_INTCLEAR 0xC8 94 #define EXYNOS5260_EMUL_CON 0x100 95 96 /* Exynos4412 specific */ 97 #define EXYNOS4412_MUX_ADDR_VALUE 6 98 #define EXYNOS4412_MUX_ADDR_SHIFT 20 99 100 /* Exynos5433 specific registers */ 101 #define EXYNOS5433_TMU_REG_CONTROL1 0x024 102 #define EXYNOS5433_TMU_SAMPLING_INTERVAL 0x02c 103 #define EXYNOS5433_TMU_COUNTER_VALUE0 0x030 104 #define EXYNOS5433_TMU_COUNTER_VALUE1 0x034 105 #define EXYNOS5433_TMU_REG_CURRENT_TEMP1 0x044 106 #define EXYNOS5433_THD_TEMP_RISE3_0 0x050 107 #define EXYNOS5433_THD_TEMP_RISE7_4 0x054 108 #define EXYNOS5433_THD_TEMP_FALL3_0 0x060 109 #define EXYNOS5433_THD_TEMP_FALL7_4 0x064 110 #define EXYNOS5433_TMU_REG_INTEN 0x0c0 111 #define EXYNOS5433_TMU_REG_INTPEND 0x0c8 112 #define EXYNOS5433_TMU_EMUL_CON 0x110 113 #define EXYNOS5433_TMU_PD_DET_EN 0x130 114 115 #define EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT 16 116 #define EXYNOS5433_TRIMINFO_CALIB_SEL_SHIFT 23 117 #define EXYNOS5433_TRIMINFO_SENSOR_ID_MASK \ 118 (0xf << EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT) 119 #define EXYNOS5433_TRIMINFO_CALIB_SEL_MASK BIT(23) 120 121 #define EXYNOS5433_TRIMINFO_ONE_POINT_TRIMMING 0 122 #define EXYNOS5433_TRIMINFO_TWO_POINT_TRIMMING 1 123 124 #define EXYNOS5433_PD_DET_EN 1 125 126 #define EXYNOS5433_G3D_BASE 0x10070000 127 128 /*exynos5440 specific registers*/ 129 #define EXYNOS5440_TMU_S0_7_TRIM 0x000 130 #define EXYNOS5440_TMU_S0_7_CTRL 0x020 131 #define EXYNOS5440_TMU_S0_7_DEBUG 0x040 132 #define EXYNOS5440_TMU_S0_7_TEMP 0x0f0 133 #define EXYNOS5440_TMU_S0_7_TH0 0x110 134 #define EXYNOS5440_TMU_S0_7_TH1 0x130 135 #define EXYNOS5440_TMU_S0_7_TH2 0x150 136 #define EXYNOS5440_TMU_S0_7_IRQEN 0x210 137 #define EXYNOS5440_TMU_S0_7_IRQ 0x230 138 /* exynos5440 common registers */ 139 #define EXYNOS5440_TMU_IRQ_STATUS 0x000 140 #define EXYNOS5440_TMU_PMIN 0x004 141 142 #define EXYNOS5440_TMU_INTEN_RISE0_SHIFT 0 143 #define EXYNOS5440_TMU_INTEN_RISE1_SHIFT 1 144 #define EXYNOS5440_TMU_INTEN_RISE2_SHIFT 2 145 #define EXYNOS5440_TMU_INTEN_RISE3_SHIFT 3 146 #define EXYNOS5440_TMU_INTEN_FALL0_SHIFT 4 147 #define EXYNOS5440_TMU_TH_RISE4_SHIFT 24 148 #define EXYNOS5440_EFUSE_SWAP_OFFSET 8 149 150 /* Exynos7 specific registers */ 151 #define EXYNOS7_THD_TEMP_RISE7_6 0x50 152 #define EXYNOS7_THD_TEMP_FALL7_6 0x60 153 #define EXYNOS7_TMU_REG_INTEN 0x110 154 #define EXYNOS7_TMU_REG_INTPEND 0x118 155 #define EXYNOS7_TMU_REG_EMUL_CON 0x160 156 157 #define EXYNOS7_TMU_TEMP_MASK 0x1ff 158 #define EXYNOS7_PD_DET_EN_SHIFT 23 159 #define EXYNOS7_TMU_INTEN_RISE0_SHIFT 0 160 #define EXYNOS7_TMU_INTEN_RISE1_SHIFT 1 161 #define EXYNOS7_TMU_INTEN_RISE2_SHIFT 2 162 #define EXYNOS7_TMU_INTEN_RISE3_SHIFT 3 163 #define EXYNOS7_TMU_INTEN_RISE4_SHIFT 4 164 #define EXYNOS7_TMU_INTEN_RISE5_SHIFT 5 165 #define EXYNOS7_TMU_INTEN_RISE6_SHIFT 6 166 #define EXYNOS7_TMU_INTEN_RISE7_SHIFT 7 167 #define EXYNOS7_EMUL_DATA_SHIFT 7 168 #define EXYNOS7_EMUL_DATA_MASK 0x1ff 169 170 #define EXYNOS_FIRST_POINT_TRIM 25 171 #define EXYNOS_SECOND_POINT_TRIM 85 172 173 #define EXYNOS_NOISE_CANCEL_MODE 4 174 175 #define MCELSIUS 1000 176 /** 177 * struct exynos_tmu_data : A structure to hold the private data of the TMU 178 driver 179 * @id: identifier of the one instance of the TMU controller. 180 * @pdata: pointer to the tmu platform/configuration data 181 * @base: base address of the single instance of the TMU controller. 182 * @base_second: base address of the common registers of the TMU controller. 183 * @irq: irq number of the TMU controller. 184 * @soc: id of the SOC type. 185 * @irq_work: pointer to the irq work structure. 186 * @lock: lock to implement synchronization. 187 * @clk: pointer to the clock structure. 188 * @clk_sec: pointer to the clock structure for accessing the base_second. 189 * @sclk: pointer to the clock structure for accessing the tmu special clk. 190 * @efuse_value: SoC defined fuse value 191 * @min_efuse_value: minimum valid trimming data 192 * @max_efuse_value: maximum valid trimming data 193 * @temp_error1: fused value of the first point trim. 194 * @temp_error2: fused value of the second point trim. 195 * @gain: gain of amplifier in the positive-TC generator block 196 * 0 < gain <= 15 197 * @reference_voltage: reference voltage of amplifier 198 * in the positive-TC generator block 199 * 0 < reference_voltage <= 31 200 * @regulator: pointer to the TMU regulator structure. 201 * @reg_conf: pointer to structure to register with core thermal. 202 * @ntrip: number of supported trip points. 203 * @enabled: current status of TMU device 204 * @tmu_initialize: SoC specific TMU initialization method 205 * @tmu_control: SoC specific TMU control method 206 * @tmu_read: SoC specific TMU temperature read method 207 * @tmu_set_emulation: SoC specific TMU emulation setting method 208 * @tmu_clear_irqs: SoC specific TMU interrupts clearing method 209 */ 210 struct exynos_tmu_data { 211 int id; 212 struct exynos_tmu_platform_data *pdata; 213 void __iomem *base; 214 void __iomem *base_second; 215 int irq; 216 enum soc_type soc; 217 struct work_struct irq_work; 218 struct mutex lock; 219 struct clk *clk, *clk_sec, *sclk; 220 u32 efuse_value; 221 u32 min_efuse_value; 222 u32 max_efuse_value; 223 u16 temp_error1, temp_error2; 224 u8 gain; 225 u8 reference_voltage; 226 struct regulator *regulator; 227 struct thermal_zone_device *tzd; 228 unsigned int ntrip; 229 bool enabled; 230 231 int (*tmu_initialize)(struct platform_device *pdev); 232 void (*tmu_control)(struct platform_device *pdev, bool on); 233 int (*tmu_read)(struct exynos_tmu_data *data); 234 void (*tmu_set_emulation)(struct exynos_tmu_data *data, int temp); 235 void (*tmu_clear_irqs)(struct exynos_tmu_data *data); 236 }; 237 238 static void exynos_report_trigger(struct exynos_tmu_data *p) 239 { 240 char data[10], *envp[] = { data, NULL }; 241 struct thermal_zone_device *tz = p->tzd; 242 int temp; 243 unsigned int i; 244 245 if (!tz) { 246 pr_err("No thermal zone device defined\n"); 247 return; 248 } 249 250 thermal_zone_device_update(tz, THERMAL_EVENT_UNSPECIFIED); 251 252 mutex_lock(&tz->lock); 253 /* Find the level for which trip happened */ 254 for (i = 0; i < of_thermal_get_ntrips(tz); i++) { 255 tz->ops->get_trip_temp(tz, i, &temp); 256 if (tz->last_temperature < temp) 257 break; 258 } 259 260 snprintf(data, sizeof(data), "%u", i); 261 kobject_uevent_env(&tz->device.kobj, KOBJ_CHANGE, envp); 262 mutex_unlock(&tz->lock); 263 } 264 265 /* 266 * TMU treats temperature as a mapped temperature code. 267 * The temperature is converted differently depending on the calibration type. 268 */ 269 static int temp_to_code(struct exynos_tmu_data *data, u8 temp) 270 { 271 struct exynos_tmu_platform_data *pdata = data->pdata; 272 273 if (pdata->cal_type == TYPE_ONE_POINT_TRIMMING) 274 return temp + data->temp_error1 - EXYNOS_FIRST_POINT_TRIM; 275 276 return (temp - EXYNOS_FIRST_POINT_TRIM) * 277 (data->temp_error2 - data->temp_error1) / 278 (EXYNOS_SECOND_POINT_TRIM - EXYNOS_FIRST_POINT_TRIM) + 279 data->temp_error1; 280 } 281 282 /* 283 * Calculate a temperature value from a temperature code. 284 * The unit of the temperature is degree Celsius. 285 */ 286 static int code_to_temp(struct exynos_tmu_data *data, u16 temp_code) 287 { 288 struct exynos_tmu_platform_data *pdata = data->pdata; 289 290 if (pdata->cal_type == TYPE_ONE_POINT_TRIMMING) 291 return temp_code - data->temp_error1 + EXYNOS_FIRST_POINT_TRIM; 292 293 return (temp_code - data->temp_error1) * 294 (EXYNOS_SECOND_POINT_TRIM - EXYNOS_FIRST_POINT_TRIM) / 295 (data->temp_error2 - data->temp_error1) + 296 EXYNOS_FIRST_POINT_TRIM; 297 } 298 299 static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_info) 300 { 301 data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK; 302 data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) & 303 EXYNOS_TMU_TEMP_MASK); 304 305 if (!data->temp_error1 || 306 (data->min_efuse_value > data->temp_error1) || 307 (data->temp_error1 > data->max_efuse_value)) 308 data->temp_error1 = data->efuse_value & EXYNOS_TMU_TEMP_MASK; 309 310 if (!data->temp_error2) 311 data->temp_error2 = 312 (data->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) & 313 EXYNOS_TMU_TEMP_MASK; 314 } 315 316 static u32 get_th_reg(struct exynos_tmu_data *data, u32 threshold, bool falling) 317 { 318 struct thermal_zone_device *tz = data->tzd; 319 const struct thermal_trip * const trips = 320 of_thermal_get_trip_points(tz); 321 unsigned long temp; 322 int i; 323 324 if (!trips) { 325 pr_err("%s: Cannot get trip points from of-thermal.c!\n", 326 __func__); 327 return 0; 328 } 329 330 for (i = 0; i < of_thermal_get_ntrips(tz); i++) { 331 if (trips[i].type == THERMAL_TRIP_CRITICAL) 332 continue; 333 334 temp = trips[i].temperature / MCELSIUS; 335 if (falling) 336 temp -= (trips[i].hysteresis / MCELSIUS); 337 else 338 threshold &= ~(0xff << 8 * i); 339 340 threshold |= temp_to_code(data, temp) << 8 * i; 341 } 342 343 return threshold; 344 } 345 346 static int exynos_tmu_initialize(struct platform_device *pdev) 347 { 348 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 349 int ret; 350 351 if (of_thermal_get_ntrips(data->tzd) > data->ntrip) { 352 dev_info(&pdev->dev, 353 "More trip points than supported by this TMU.\n"); 354 dev_info(&pdev->dev, 355 "%d trip points should be configured in polling mode.\n", 356 (of_thermal_get_ntrips(data->tzd) - data->ntrip)); 357 } 358 359 mutex_lock(&data->lock); 360 clk_enable(data->clk); 361 if (!IS_ERR(data->clk_sec)) 362 clk_enable(data->clk_sec); 363 ret = data->tmu_initialize(pdev); 364 clk_disable(data->clk); 365 mutex_unlock(&data->lock); 366 if (!IS_ERR(data->clk_sec)) 367 clk_disable(data->clk_sec); 368 369 return ret; 370 } 371 372 static u32 get_con_reg(struct exynos_tmu_data *data, u32 con) 373 { 374 if (data->soc == SOC_ARCH_EXYNOS4412 || 375 data->soc == SOC_ARCH_EXYNOS3250) 376 con |= (EXYNOS4412_MUX_ADDR_VALUE << EXYNOS4412_MUX_ADDR_SHIFT); 377 378 con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK << EXYNOS_TMU_REF_VOLTAGE_SHIFT); 379 con |= data->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT; 380 381 con &= ~(EXYNOS_TMU_BUF_SLOPE_SEL_MASK << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT); 382 con |= (data->gain << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT); 383 384 con &= ~(EXYNOS_TMU_TRIP_MODE_MASK << EXYNOS_TMU_TRIP_MODE_SHIFT); 385 con |= (EXYNOS_NOISE_CANCEL_MODE << EXYNOS_TMU_TRIP_MODE_SHIFT); 386 387 return con; 388 } 389 390 static void exynos_tmu_control(struct platform_device *pdev, bool on) 391 { 392 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 393 394 mutex_lock(&data->lock); 395 clk_enable(data->clk); 396 data->tmu_control(pdev, on); 397 data->enabled = on; 398 clk_disable(data->clk); 399 mutex_unlock(&data->lock); 400 } 401 402 static int exynos4210_tmu_initialize(struct platform_device *pdev) 403 { 404 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 405 struct thermal_zone_device *tz = data->tzd; 406 const struct thermal_trip * const trips = 407 of_thermal_get_trip_points(tz); 408 int ret = 0, threshold_code, i; 409 unsigned long reference, temp; 410 unsigned int status; 411 412 if (!trips) { 413 pr_err("%s: Cannot get trip points from of-thermal.c!\n", 414 __func__); 415 ret = -ENODEV; 416 goto out; 417 } 418 419 status = readb(data->base + EXYNOS_TMU_REG_STATUS); 420 if (!status) { 421 ret = -EBUSY; 422 goto out; 423 } 424 425 sanitize_temp_error(data, readl(data->base + EXYNOS_TMU_REG_TRIMINFO)); 426 427 /* Write temperature code for threshold */ 428 reference = trips[0].temperature / MCELSIUS; 429 threshold_code = temp_to_code(data, reference); 430 if (threshold_code < 0) { 431 ret = threshold_code; 432 goto out; 433 } 434 writeb(threshold_code, data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP); 435 436 for (i = 0; i < of_thermal_get_ntrips(tz); i++) { 437 temp = trips[i].temperature / MCELSIUS; 438 writeb(temp - reference, data->base + 439 EXYNOS4210_TMU_REG_TRIG_LEVEL0 + i * 4); 440 } 441 442 data->tmu_clear_irqs(data); 443 out: 444 return ret; 445 } 446 447 static int exynos4412_tmu_initialize(struct platform_device *pdev) 448 { 449 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 450 const struct thermal_trip * const trips = 451 of_thermal_get_trip_points(data->tzd); 452 unsigned int status, trim_info, con, ctrl, rising_threshold; 453 int ret = 0, threshold_code, i; 454 unsigned long crit_temp = 0; 455 456 status = readb(data->base + EXYNOS_TMU_REG_STATUS); 457 if (!status) { 458 ret = -EBUSY; 459 goto out; 460 } 461 462 if (data->soc == SOC_ARCH_EXYNOS3250 || 463 data->soc == SOC_ARCH_EXYNOS4412 || 464 data->soc == SOC_ARCH_EXYNOS5250) { 465 if (data->soc == SOC_ARCH_EXYNOS3250) { 466 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON1); 467 ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE; 468 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON1); 469 } 470 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON2); 471 ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE; 472 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON2); 473 } 474 475 /* On exynos5420 the triminfo register is in the shared space */ 476 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) 477 trim_info = readl(data->base_second + EXYNOS_TMU_REG_TRIMINFO); 478 else 479 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); 480 481 sanitize_temp_error(data, trim_info); 482 483 /* Write temperature code for rising and falling threshold */ 484 rising_threshold = readl(data->base + EXYNOS_THD_TEMP_RISE); 485 rising_threshold = get_th_reg(data, rising_threshold, false); 486 writel(rising_threshold, data->base + EXYNOS_THD_TEMP_RISE); 487 writel(get_th_reg(data, 0, true), data->base + EXYNOS_THD_TEMP_FALL); 488 489 data->tmu_clear_irqs(data); 490 491 /* if last threshold limit is also present */ 492 for (i = 0; i < of_thermal_get_ntrips(data->tzd); i++) { 493 if (trips[i].type == THERMAL_TRIP_CRITICAL) { 494 crit_temp = trips[i].temperature; 495 break; 496 } 497 } 498 499 if (i == of_thermal_get_ntrips(data->tzd)) { 500 pr_err("%s: No CRITICAL trip point defined at of-thermal.c!\n", 501 __func__); 502 ret = -EINVAL; 503 goto out; 504 } 505 506 threshold_code = temp_to_code(data, crit_temp / MCELSIUS); 507 /* 1-4 level to be assigned in th0 reg */ 508 rising_threshold &= ~(0xff << 8 * i); 509 rising_threshold |= threshold_code << 8 * i; 510 writel(rising_threshold, data->base + EXYNOS_THD_TEMP_RISE); 511 con = readl(data->base + EXYNOS_TMU_REG_CONTROL); 512 con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT); 513 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 514 515 out: 516 return ret; 517 } 518 519 static int exynos5433_tmu_initialize(struct platform_device *pdev) 520 { 521 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 522 struct exynos_tmu_platform_data *pdata = data->pdata; 523 struct thermal_zone_device *tz = data->tzd; 524 unsigned int status, trim_info; 525 unsigned int rising_threshold = 0, falling_threshold = 0; 526 int temp, temp_hist; 527 int ret = 0, threshold_code, i, sensor_id, cal_type; 528 529 status = readb(data->base + EXYNOS_TMU_REG_STATUS); 530 if (!status) { 531 ret = -EBUSY; 532 goto out; 533 } 534 535 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); 536 sanitize_temp_error(data, trim_info); 537 538 /* Read the temperature sensor id */ 539 sensor_id = (trim_info & EXYNOS5433_TRIMINFO_SENSOR_ID_MASK) 540 >> EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT; 541 dev_info(&pdev->dev, "Temperature sensor ID: 0x%x\n", sensor_id); 542 543 /* Read the calibration mode */ 544 writel(trim_info, data->base + EXYNOS_TMU_REG_TRIMINFO); 545 cal_type = (trim_info & EXYNOS5433_TRIMINFO_CALIB_SEL_MASK) 546 >> EXYNOS5433_TRIMINFO_CALIB_SEL_SHIFT; 547 548 switch (cal_type) { 549 case EXYNOS5433_TRIMINFO_ONE_POINT_TRIMMING: 550 pdata->cal_type = TYPE_ONE_POINT_TRIMMING; 551 break; 552 case EXYNOS5433_TRIMINFO_TWO_POINT_TRIMMING: 553 pdata->cal_type = TYPE_TWO_POINT_TRIMMING; 554 break; 555 default: 556 pdata->cal_type = TYPE_ONE_POINT_TRIMMING; 557 break; 558 } 559 560 dev_info(&pdev->dev, "Calibration type is %d-point calibration\n", 561 cal_type ? 2 : 1); 562 563 /* Write temperature code for rising and falling threshold */ 564 for (i = 0; i < of_thermal_get_ntrips(tz); i++) { 565 int rising_reg_offset, falling_reg_offset; 566 int j = 0; 567 568 switch (i) { 569 case 0: 570 case 1: 571 case 2: 572 case 3: 573 rising_reg_offset = EXYNOS5433_THD_TEMP_RISE3_0; 574 falling_reg_offset = EXYNOS5433_THD_TEMP_FALL3_0; 575 j = i; 576 break; 577 case 4: 578 case 5: 579 case 6: 580 case 7: 581 rising_reg_offset = EXYNOS5433_THD_TEMP_RISE7_4; 582 falling_reg_offset = EXYNOS5433_THD_TEMP_FALL7_4; 583 j = i - 4; 584 break; 585 default: 586 continue; 587 } 588 589 /* Write temperature code for rising threshold */ 590 tz->ops->get_trip_temp(tz, i, &temp); 591 temp /= MCELSIUS; 592 threshold_code = temp_to_code(data, temp); 593 594 rising_threshold = readl(data->base + rising_reg_offset); 595 rising_threshold |= (threshold_code << j * 8); 596 writel(rising_threshold, data->base + rising_reg_offset); 597 598 /* Write temperature code for falling threshold */ 599 tz->ops->get_trip_hyst(tz, i, &temp_hist); 600 temp_hist = temp - (temp_hist / MCELSIUS); 601 threshold_code = temp_to_code(data, temp_hist); 602 603 falling_threshold = readl(data->base + falling_reg_offset); 604 falling_threshold &= ~(0xff << j * 8); 605 falling_threshold |= (threshold_code << j * 8); 606 writel(falling_threshold, data->base + falling_reg_offset); 607 } 608 609 data->tmu_clear_irqs(data); 610 out: 611 return ret; 612 } 613 614 static int exynos5440_tmu_initialize(struct platform_device *pdev) 615 { 616 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 617 unsigned int trim_info = 0, con, rising_threshold; 618 int threshold_code; 619 int crit_temp = 0; 620 621 /* 622 * For exynos5440 soc triminfo value is swapped between TMU0 and 623 * TMU2, so the below logic is needed. 624 */ 625 switch (data->id) { 626 case 0: 627 trim_info = readl(data->base + EXYNOS5440_EFUSE_SWAP_OFFSET + 628 EXYNOS5440_TMU_S0_7_TRIM); 629 break; 630 case 1: 631 trim_info = readl(data->base + EXYNOS5440_TMU_S0_7_TRIM); 632 break; 633 case 2: 634 trim_info = readl(data->base - EXYNOS5440_EFUSE_SWAP_OFFSET + 635 EXYNOS5440_TMU_S0_7_TRIM); 636 } 637 sanitize_temp_error(data, trim_info); 638 639 /* Write temperature code for rising and falling threshold */ 640 rising_threshold = readl(data->base + EXYNOS5440_TMU_S0_7_TH0); 641 rising_threshold = get_th_reg(data, rising_threshold, false); 642 writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH0); 643 writel(0, data->base + EXYNOS5440_TMU_S0_7_TH1); 644 645 data->tmu_clear_irqs(data); 646 647 /* if last threshold limit is also present */ 648 if (!data->tzd->ops->get_crit_temp(data->tzd, &crit_temp)) { 649 threshold_code = temp_to_code(data, crit_temp / MCELSIUS); 650 /* 5th level to be assigned in th2 reg */ 651 rising_threshold = 652 threshold_code << EXYNOS5440_TMU_TH_RISE4_SHIFT; 653 writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH2); 654 con = readl(data->base + EXYNOS5440_TMU_S0_7_CTRL); 655 con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT); 656 writel(con, data->base + EXYNOS5440_TMU_S0_7_CTRL); 657 } 658 /* Clear the PMIN in the common TMU register */ 659 if (!data->id) 660 writel(0, data->base_second + EXYNOS5440_TMU_PMIN); 661 662 return 0; 663 } 664 665 static int exynos7_tmu_initialize(struct platform_device *pdev) 666 { 667 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 668 struct thermal_zone_device *tz = data->tzd; 669 unsigned int status, trim_info; 670 unsigned int rising_threshold = 0, falling_threshold = 0; 671 int ret = 0, threshold_code, i; 672 int temp, temp_hist; 673 unsigned int reg_off, bit_off; 674 675 status = readb(data->base + EXYNOS_TMU_REG_STATUS); 676 if (!status) { 677 ret = -EBUSY; 678 goto out; 679 } 680 681 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); 682 683 data->temp_error1 = trim_info & EXYNOS7_TMU_TEMP_MASK; 684 if (!data->temp_error1 || 685 (data->min_efuse_value > data->temp_error1) || 686 (data->temp_error1 > data->max_efuse_value)) 687 data->temp_error1 = data->efuse_value & EXYNOS_TMU_TEMP_MASK; 688 689 /* Write temperature code for rising and falling threshold */ 690 for (i = (of_thermal_get_ntrips(tz) - 1); i >= 0; i--) { 691 /* 692 * On exynos7 there are 4 rising and 4 falling threshold 693 * registers (0x50-0x5c and 0x60-0x6c respectively). Each 694 * register holds the value of two threshold levels (at bit 695 * offsets 0 and 16). Based on the fact that there are atmost 696 * eight possible trigger levels, calculate the register and 697 * bit offsets where the threshold levels are to be written. 698 * 699 * e.g. EXYNOS7_THD_TEMP_RISE7_6 (0x50) 700 * [24:16] - Threshold level 7 701 * [8:0] - Threshold level 6 702 * e.g. EXYNOS7_THD_TEMP_RISE5_4 (0x54) 703 * [24:16] - Threshold level 5 704 * [8:0] - Threshold level 4 705 * 706 * and similarly for falling thresholds. 707 * 708 * Based on the above, calculate the register and bit offsets 709 * for rising/falling threshold levels and populate them. 710 */ 711 reg_off = ((7 - i) / 2) * 4; 712 bit_off = ((8 - i) % 2); 713 714 tz->ops->get_trip_temp(tz, i, &temp); 715 temp /= MCELSIUS; 716 717 tz->ops->get_trip_hyst(tz, i, &temp_hist); 718 temp_hist = temp - (temp_hist / MCELSIUS); 719 720 /* Set 9-bit temperature code for rising threshold levels */ 721 threshold_code = temp_to_code(data, temp); 722 rising_threshold = readl(data->base + 723 EXYNOS7_THD_TEMP_RISE7_6 + reg_off); 724 rising_threshold &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off)); 725 rising_threshold |= threshold_code << (16 * bit_off); 726 writel(rising_threshold, 727 data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off); 728 729 /* Set 9-bit temperature code for falling threshold levels */ 730 threshold_code = temp_to_code(data, temp_hist); 731 falling_threshold &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off)); 732 falling_threshold |= threshold_code << (16 * bit_off); 733 writel(falling_threshold, 734 data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off); 735 } 736 737 data->tmu_clear_irqs(data); 738 out: 739 return ret; 740 } 741 742 static void exynos4210_tmu_control(struct platform_device *pdev, bool on) 743 { 744 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 745 struct thermal_zone_device *tz = data->tzd; 746 unsigned int con, interrupt_en; 747 748 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); 749 750 if (on) { 751 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); 752 interrupt_en = 753 (of_thermal_is_trip_valid(tz, 3) 754 << EXYNOS_TMU_INTEN_RISE3_SHIFT) | 755 (of_thermal_is_trip_valid(tz, 2) 756 << EXYNOS_TMU_INTEN_RISE2_SHIFT) | 757 (of_thermal_is_trip_valid(tz, 1) 758 << EXYNOS_TMU_INTEN_RISE1_SHIFT) | 759 (of_thermal_is_trip_valid(tz, 0) 760 << EXYNOS_TMU_INTEN_RISE0_SHIFT); 761 762 if (data->soc != SOC_ARCH_EXYNOS4210) 763 interrupt_en |= 764 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; 765 } else { 766 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); 767 interrupt_en = 0; /* Disable all interrupts */ 768 } 769 writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN); 770 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 771 } 772 773 static void exynos5433_tmu_control(struct platform_device *pdev, bool on) 774 { 775 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 776 struct thermal_zone_device *tz = data->tzd; 777 unsigned int con, interrupt_en, pd_det_en; 778 779 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); 780 781 if (on) { 782 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); 783 interrupt_en = 784 (of_thermal_is_trip_valid(tz, 7) 785 << EXYNOS7_TMU_INTEN_RISE7_SHIFT) | 786 (of_thermal_is_trip_valid(tz, 6) 787 << EXYNOS7_TMU_INTEN_RISE6_SHIFT) | 788 (of_thermal_is_trip_valid(tz, 5) 789 << EXYNOS7_TMU_INTEN_RISE5_SHIFT) | 790 (of_thermal_is_trip_valid(tz, 4) 791 << EXYNOS7_TMU_INTEN_RISE4_SHIFT) | 792 (of_thermal_is_trip_valid(tz, 3) 793 << EXYNOS7_TMU_INTEN_RISE3_SHIFT) | 794 (of_thermal_is_trip_valid(tz, 2) 795 << EXYNOS7_TMU_INTEN_RISE2_SHIFT) | 796 (of_thermal_is_trip_valid(tz, 1) 797 << EXYNOS7_TMU_INTEN_RISE1_SHIFT) | 798 (of_thermal_is_trip_valid(tz, 0) 799 << EXYNOS7_TMU_INTEN_RISE0_SHIFT); 800 801 interrupt_en |= 802 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; 803 } else { 804 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); 805 interrupt_en = 0; /* Disable all interrupts */ 806 } 807 808 pd_det_en = on ? EXYNOS5433_PD_DET_EN : 0; 809 810 writel(pd_det_en, data->base + EXYNOS5433_TMU_PD_DET_EN); 811 writel(interrupt_en, data->base + EXYNOS5433_TMU_REG_INTEN); 812 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 813 } 814 815 static void exynos5440_tmu_control(struct platform_device *pdev, bool on) 816 { 817 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 818 struct thermal_zone_device *tz = data->tzd; 819 unsigned int con, interrupt_en; 820 821 con = get_con_reg(data, readl(data->base + EXYNOS5440_TMU_S0_7_CTRL)); 822 823 if (on) { 824 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); 825 interrupt_en = 826 (of_thermal_is_trip_valid(tz, 3) 827 << EXYNOS5440_TMU_INTEN_RISE3_SHIFT) | 828 (of_thermal_is_trip_valid(tz, 2) 829 << EXYNOS5440_TMU_INTEN_RISE2_SHIFT) | 830 (of_thermal_is_trip_valid(tz, 1) 831 << EXYNOS5440_TMU_INTEN_RISE1_SHIFT) | 832 (of_thermal_is_trip_valid(tz, 0) 833 << EXYNOS5440_TMU_INTEN_RISE0_SHIFT); 834 interrupt_en |= 835 interrupt_en << EXYNOS5440_TMU_INTEN_FALL0_SHIFT; 836 } else { 837 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); 838 interrupt_en = 0; /* Disable all interrupts */ 839 } 840 writel(interrupt_en, data->base + EXYNOS5440_TMU_S0_7_IRQEN); 841 writel(con, data->base + EXYNOS5440_TMU_S0_7_CTRL); 842 } 843 844 static void exynos7_tmu_control(struct platform_device *pdev, bool on) 845 { 846 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 847 struct thermal_zone_device *tz = data->tzd; 848 unsigned int con, interrupt_en; 849 850 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); 851 852 if (on) { 853 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); 854 con |= (1 << EXYNOS7_PD_DET_EN_SHIFT); 855 interrupt_en = 856 (of_thermal_is_trip_valid(tz, 7) 857 << EXYNOS7_TMU_INTEN_RISE7_SHIFT) | 858 (of_thermal_is_trip_valid(tz, 6) 859 << EXYNOS7_TMU_INTEN_RISE6_SHIFT) | 860 (of_thermal_is_trip_valid(tz, 5) 861 << EXYNOS7_TMU_INTEN_RISE5_SHIFT) | 862 (of_thermal_is_trip_valid(tz, 4) 863 << EXYNOS7_TMU_INTEN_RISE4_SHIFT) | 864 (of_thermal_is_trip_valid(tz, 3) 865 << EXYNOS7_TMU_INTEN_RISE3_SHIFT) | 866 (of_thermal_is_trip_valid(tz, 2) 867 << EXYNOS7_TMU_INTEN_RISE2_SHIFT) | 868 (of_thermal_is_trip_valid(tz, 1) 869 << EXYNOS7_TMU_INTEN_RISE1_SHIFT) | 870 (of_thermal_is_trip_valid(tz, 0) 871 << EXYNOS7_TMU_INTEN_RISE0_SHIFT); 872 873 interrupt_en |= 874 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; 875 } else { 876 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); 877 con &= ~(1 << EXYNOS7_PD_DET_EN_SHIFT); 878 interrupt_en = 0; /* Disable all interrupts */ 879 } 880 881 writel(interrupt_en, data->base + EXYNOS7_TMU_REG_INTEN); 882 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 883 } 884 885 static int exynos_get_temp(void *p, int *temp) 886 { 887 struct exynos_tmu_data *data = p; 888 int value, ret = 0; 889 890 if (!data || !data->tmu_read || !data->enabled) 891 return -EINVAL; 892 893 mutex_lock(&data->lock); 894 clk_enable(data->clk); 895 896 value = data->tmu_read(data); 897 if (value < 0) 898 ret = value; 899 else 900 *temp = code_to_temp(data, value) * MCELSIUS; 901 902 clk_disable(data->clk); 903 mutex_unlock(&data->lock); 904 905 return ret; 906 } 907 908 #ifdef CONFIG_THERMAL_EMULATION 909 static u32 get_emul_con_reg(struct exynos_tmu_data *data, unsigned int val, 910 int temp) 911 { 912 if (temp) { 913 temp /= MCELSIUS; 914 915 if (data->soc != SOC_ARCH_EXYNOS5440) { 916 val &= ~(EXYNOS_EMUL_TIME_MASK << EXYNOS_EMUL_TIME_SHIFT); 917 val |= (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT); 918 } 919 if (data->soc == SOC_ARCH_EXYNOS7) { 920 val &= ~(EXYNOS7_EMUL_DATA_MASK << 921 EXYNOS7_EMUL_DATA_SHIFT); 922 val |= (temp_to_code(data, temp) << 923 EXYNOS7_EMUL_DATA_SHIFT) | 924 EXYNOS_EMUL_ENABLE; 925 } else { 926 val &= ~(EXYNOS_EMUL_DATA_MASK << 927 EXYNOS_EMUL_DATA_SHIFT); 928 val |= (temp_to_code(data, temp) << 929 EXYNOS_EMUL_DATA_SHIFT) | 930 EXYNOS_EMUL_ENABLE; 931 } 932 } else { 933 val &= ~EXYNOS_EMUL_ENABLE; 934 } 935 936 return val; 937 } 938 939 static void exynos4412_tmu_set_emulation(struct exynos_tmu_data *data, 940 int temp) 941 { 942 unsigned int val; 943 u32 emul_con; 944 945 if (data->soc == SOC_ARCH_EXYNOS5260) 946 emul_con = EXYNOS5260_EMUL_CON; 947 else if (data->soc == SOC_ARCH_EXYNOS5433) 948 emul_con = EXYNOS5433_TMU_EMUL_CON; 949 else if (data->soc == SOC_ARCH_EXYNOS7) 950 emul_con = EXYNOS7_TMU_REG_EMUL_CON; 951 else 952 emul_con = EXYNOS_EMUL_CON; 953 954 val = readl(data->base + emul_con); 955 val = get_emul_con_reg(data, val, temp); 956 writel(val, data->base + emul_con); 957 } 958 959 static void exynos5440_tmu_set_emulation(struct exynos_tmu_data *data, 960 int temp) 961 { 962 unsigned int val; 963 964 val = readl(data->base + EXYNOS5440_TMU_S0_7_DEBUG); 965 val = get_emul_con_reg(data, val, temp); 966 writel(val, data->base + EXYNOS5440_TMU_S0_7_DEBUG); 967 } 968 969 static int exynos_tmu_set_emulation(void *drv_data, int temp) 970 { 971 struct exynos_tmu_data *data = drv_data; 972 int ret = -EINVAL; 973 974 if (data->soc == SOC_ARCH_EXYNOS4210) 975 goto out; 976 977 if (temp && temp < MCELSIUS) 978 goto out; 979 980 mutex_lock(&data->lock); 981 clk_enable(data->clk); 982 data->tmu_set_emulation(data, temp); 983 clk_disable(data->clk); 984 mutex_unlock(&data->lock); 985 return 0; 986 out: 987 return ret; 988 } 989 #else 990 #define exynos4412_tmu_set_emulation NULL 991 #define exynos5440_tmu_set_emulation NULL 992 static int exynos_tmu_set_emulation(void *drv_data, int temp) 993 { return -EINVAL; } 994 #endif /* CONFIG_THERMAL_EMULATION */ 995 996 static int exynos4210_tmu_read(struct exynos_tmu_data *data) 997 { 998 int ret = readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP); 999 1000 /* "temp_code" should range between 75 and 175 */ 1001 return (ret < 75 || ret > 175) ? -ENODATA : ret; 1002 } 1003 1004 static int exynos4412_tmu_read(struct exynos_tmu_data *data) 1005 { 1006 return readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP); 1007 } 1008 1009 static int exynos5440_tmu_read(struct exynos_tmu_data *data) 1010 { 1011 return readb(data->base + EXYNOS5440_TMU_S0_7_TEMP); 1012 } 1013 1014 static int exynos7_tmu_read(struct exynos_tmu_data *data) 1015 { 1016 return readw(data->base + EXYNOS_TMU_REG_CURRENT_TEMP) & 1017 EXYNOS7_TMU_TEMP_MASK; 1018 } 1019 1020 static void exynos_tmu_work(struct work_struct *work) 1021 { 1022 struct exynos_tmu_data *data = container_of(work, 1023 struct exynos_tmu_data, irq_work); 1024 unsigned int val_type; 1025 1026 if (!IS_ERR(data->clk_sec)) 1027 clk_enable(data->clk_sec); 1028 /* Find which sensor generated this interrupt */ 1029 if (data->soc == SOC_ARCH_EXYNOS5440) { 1030 val_type = readl(data->base_second + EXYNOS5440_TMU_IRQ_STATUS); 1031 if (!((val_type >> data->id) & 0x1)) 1032 goto out; 1033 } 1034 if (!IS_ERR(data->clk_sec)) 1035 clk_disable(data->clk_sec); 1036 1037 exynos_report_trigger(data); 1038 mutex_lock(&data->lock); 1039 clk_enable(data->clk); 1040 1041 /* TODO: take action based on particular interrupt */ 1042 data->tmu_clear_irqs(data); 1043 1044 clk_disable(data->clk); 1045 mutex_unlock(&data->lock); 1046 out: 1047 enable_irq(data->irq); 1048 } 1049 1050 static void exynos4210_tmu_clear_irqs(struct exynos_tmu_data *data) 1051 { 1052 unsigned int val_irq; 1053 u32 tmu_intstat, tmu_intclear; 1054 1055 if (data->soc == SOC_ARCH_EXYNOS5260) { 1056 tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT; 1057 tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR; 1058 } else if (data->soc == SOC_ARCH_EXYNOS7) { 1059 tmu_intstat = EXYNOS7_TMU_REG_INTPEND; 1060 tmu_intclear = EXYNOS7_TMU_REG_INTPEND; 1061 } else if (data->soc == SOC_ARCH_EXYNOS5433) { 1062 tmu_intstat = EXYNOS5433_TMU_REG_INTPEND; 1063 tmu_intclear = EXYNOS5433_TMU_REG_INTPEND; 1064 } else { 1065 tmu_intstat = EXYNOS_TMU_REG_INTSTAT; 1066 tmu_intclear = EXYNOS_TMU_REG_INTCLEAR; 1067 } 1068 1069 val_irq = readl(data->base + tmu_intstat); 1070 /* 1071 * Clear the interrupts. Please note that the documentation for 1072 * Exynos3250, Exynos4412, Exynos5250 and Exynos5260 incorrectly 1073 * states that INTCLEAR register has a different placing of bits 1074 * responsible for FALL IRQs than INTSTAT register. Exynos5420 1075 * and Exynos5440 documentation is correct (Exynos4210 doesn't 1076 * support FALL IRQs at all). 1077 */ 1078 writel(val_irq, data->base + tmu_intclear); 1079 } 1080 1081 static void exynos5440_tmu_clear_irqs(struct exynos_tmu_data *data) 1082 { 1083 unsigned int val_irq; 1084 1085 val_irq = readl(data->base + EXYNOS5440_TMU_S0_7_IRQ); 1086 /* clear the interrupts */ 1087 writel(val_irq, data->base + EXYNOS5440_TMU_S0_7_IRQ); 1088 } 1089 1090 static irqreturn_t exynos_tmu_irq(int irq, void *id) 1091 { 1092 struct exynos_tmu_data *data = id; 1093 1094 disable_irq_nosync(irq); 1095 schedule_work(&data->irq_work); 1096 1097 return IRQ_HANDLED; 1098 } 1099 1100 static const struct of_device_id exynos_tmu_match[] = { 1101 { 1102 .compatible = "samsung,exynos3250-tmu", 1103 .data = (const void *)SOC_ARCH_EXYNOS3250, 1104 }, { 1105 .compatible = "samsung,exynos4210-tmu", 1106 .data = (const void *)SOC_ARCH_EXYNOS4210, 1107 }, { 1108 .compatible = "samsung,exynos4412-tmu", 1109 .data = (const void *)SOC_ARCH_EXYNOS4412, 1110 }, { 1111 .compatible = "samsung,exynos5250-tmu", 1112 .data = (const void *)SOC_ARCH_EXYNOS5250, 1113 }, { 1114 .compatible = "samsung,exynos5260-tmu", 1115 .data = (const void *)SOC_ARCH_EXYNOS5260, 1116 }, { 1117 .compatible = "samsung,exynos5420-tmu", 1118 .data = (const void *)SOC_ARCH_EXYNOS5420, 1119 }, { 1120 .compatible = "samsung,exynos5420-tmu-ext-triminfo", 1121 .data = (const void *)SOC_ARCH_EXYNOS5420_TRIMINFO, 1122 }, { 1123 .compatible = "samsung,exynos5433-tmu", 1124 .data = (const void *)SOC_ARCH_EXYNOS5433, 1125 }, { 1126 .compatible = "samsung,exynos5440-tmu", 1127 .data = (const void *)SOC_ARCH_EXYNOS5440, 1128 }, { 1129 .compatible = "samsung,exynos7-tmu", 1130 .data = (const void *)SOC_ARCH_EXYNOS7, 1131 }, 1132 { }, 1133 }; 1134 MODULE_DEVICE_TABLE(of, exynos_tmu_match); 1135 1136 static int exynos_of_sensor_conf(struct device_node *np, 1137 struct exynos_tmu_platform_data *pdata) 1138 { 1139 of_node_get(np); 1140 1141 of_property_read_u32(np, "samsung,tmu_cal_type", &pdata->cal_type); 1142 1143 of_node_put(np); 1144 return 0; 1145 } 1146 1147 static int exynos_map_dt_data(struct platform_device *pdev) 1148 { 1149 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 1150 struct exynos_tmu_platform_data *pdata; 1151 struct resource res; 1152 1153 if (!data || !pdev->dev.of_node) 1154 return -ENODEV; 1155 1156 data->id = of_alias_get_id(pdev->dev.of_node, "tmuctrl"); 1157 if (data->id < 0) 1158 data->id = 0; 1159 1160 data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 1161 if (data->irq <= 0) { 1162 dev_err(&pdev->dev, "failed to get IRQ\n"); 1163 return -ENODEV; 1164 } 1165 1166 if (of_address_to_resource(pdev->dev.of_node, 0, &res)) { 1167 dev_err(&pdev->dev, "failed to get Resource 0\n"); 1168 return -ENODEV; 1169 } 1170 1171 data->base = devm_ioremap(&pdev->dev, res.start, resource_size(&res)); 1172 if (!data->base) { 1173 dev_err(&pdev->dev, "Failed to ioremap memory\n"); 1174 return -EADDRNOTAVAIL; 1175 } 1176 1177 pdata = devm_kzalloc(&pdev->dev, 1178 sizeof(struct exynos_tmu_platform_data), 1179 GFP_KERNEL); 1180 if (!pdata) 1181 return -ENOMEM; 1182 1183 exynos_of_sensor_conf(pdev->dev.of_node, pdata); 1184 data->pdata = pdata; 1185 data->soc = (enum soc_type)of_device_get_match_data(&pdev->dev); 1186 1187 switch (data->soc) { 1188 case SOC_ARCH_EXYNOS4210: 1189 data->tmu_initialize = exynos4210_tmu_initialize; 1190 data->tmu_control = exynos4210_tmu_control; 1191 data->tmu_read = exynos4210_tmu_read; 1192 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; 1193 data->ntrip = 4; 1194 data->gain = 15; 1195 data->reference_voltage = 7; 1196 data->efuse_value = 55; 1197 data->min_efuse_value = 40; 1198 data->max_efuse_value = 100; 1199 break; 1200 case SOC_ARCH_EXYNOS3250: 1201 case SOC_ARCH_EXYNOS4412: 1202 case SOC_ARCH_EXYNOS5250: 1203 case SOC_ARCH_EXYNOS5260: 1204 case SOC_ARCH_EXYNOS5420: 1205 case SOC_ARCH_EXYNOS5420_TRIMINFO: 1206 data->tmu_initialize = exynos4412_tmu_initialize; 1207 data->tmu_control = exynos4210_tmu_control; 1208 data->tmu_read = exynos4412_tmu_read; 1209 data->tmu_set_emulation = exynos4412_tmu_set_emulation; 1210 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; 1211 data->ntrip = 4; 1212 data->gain = 8; 1213 data->reference_voltage = 16; 1214 data->efuse_value = 55; 1215 if (data->soc != SOC_ARCH_EXYNOS5420 && 1216 data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO) 1217 data->min_efuse_value = 40; 1218 else 1219 data->min_efuse_value = 0; 1220 data->max_efuse_value = 100; 1221 break; 1222 case SOC_ARCH_EXYNOS5433: 1223 data->tmu_initialize = exynos5433_tmu_initialize; 1224 data->tmu_control = exynos5433_tmu_control; 1225 data->tmu_read = exynos4412_tmu_read; 1226 data->tmu_set_emulation = exynos4412_tmu_set_emulation; 1227 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; 1228 data->ntrip = 8; 1229 data->gain = 8; 1230 if (res.start == EXYNOS5433_G3D_BASE) 1231 data->reference_voltage = 23; 1232 else 1233 data->reference_voltage = 16; 1234 data->efuse_value = 75; 1235 data->min_efuse_value = 40; 1236 data->max_efuse_value = 150; 1237 break; 1238 case SOC_ARCH_EXYNOS5440: 1239 data->tmu_initialize = exynos5440_tmu_initialize; 1240 data->tmu_control = exynos5440_tmu_control; 1241 data->tmu_read = exynos5440_tmu_read; 1242 data->tmu_set_emulation = exynos5440_tmu_set_emulation; 1243 data->tmu_clear_irqs = exynos5440_tmu_clear_irqs; 1244 data->ntrip = 4; 1245 data->gain = 5; 1246 data->reference_voltage = 16; 1247 data->efuse_value = 0x5d2d; 1248 data->min_efuse_value = 16; 1249 data->max_efuse_value = 76; 1250 break; 1251 case SOC_ARCH_EXYNOS7: 1252 data->tmu_initialize = exynos7_tmu_initialize; 1253 data->tmu_control = exynos7_tmu_control; 1254 data->tmu_read = exynos7_tmu_read; 1255 data->tmu_set_emulation = exynos4412_tmu_set_emulation; 1256 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; 1257 data->ntrip = 8; 1258 data->gain = 9; 1259 data->reference_voltage = 17; 1260 data->efuse_value = 75; 1261 data->min_efuse_value = 15; 1262 data->max_efuse_value = 100; 1263 break; 1264 default: 1265 dev_err(&pdev->dev, "Platform not supported\n"); 1266 return -EINVAL; 1267 } 1268 1269 /* 1270 * Check if the TMU shares some registers and then try to map the 1271 * memory of common registers. 1272 */ 1273 if (data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO && 1274 data->soc != SOC_ARCH_EXYNOS5440) 1275 return 0; 1276 1277 if (of_address_to_resource(pdev->dev.of_node, 1, &res)) { 1278 dev_err(&pdev->dev, "failed to get Resource 1\n"); 1279 return -ENODEV; 1280 } 1281 1282 data->base_second = devm_ioremap(&pdev->dev, res.start, 1283 resource_size(&res)); 1284 if (!data->base_second) { 1285 dev_err(&pdev->dev, "Failed to ioremap memory\n"); 1286 return -ENOMEM; 1287 } 1288 1289 return 0; 1290 } 1291 1292 static const struct thermal_zone_of_device_ops exynos_sensor_ops = { 1293 .get_temp = exynos_get_temp, 1294 .set_emul_temp = exynos_tmu_set_emulation, 1295 }; 1296 1297 static int exynos_tmu_probe(struct platform_device *pdev) 1298 { 1299 struct exynos_tmu_data *data; 1300 int ret; 1301 1302 data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data), 1303 GFP_KERNEL); 1304 if (!data) 1305 return -ENOMEM; 1306 1307 platform_set_drvdata(pdev, data); 1308 mutex_init(&data->lock); 1309 1310 /* 1311 * Try enabling the regulator if found 1312 * TODO: Add regulator as an SOC feature, so that regulator enable 1313 * is a compulsory call. 1314 */ 1315 data->regulator = devm_regulator_get_optional(&pdev->dev, "vtmu"); 1316 if (!IS_ERR(data->regulator)) { 1317 ret = regulator_enable(data->regulator); 1318 if (ret) { 1319 dev_err(&pdev->dev, "failed to enable vtmu\n"); 1320 return ret; 1321 } 1322 } else { 1323 if (PTR_ERR(data->regulator) == -EPROBE_DEFER) 1324 return -EPROBE_DEFER; 1325 dev_info(&pdev->dev, "Regulator node (vtmu) not found\n"); 1326 } 1327 1328 ret = exynos_map_dt_data(pdev); 1329 if (ret) 1330 goto err_sensor; 1331 1332 INIT_WORK(&data->irq_work, exynos_tmu_work); 1333 1334 data->clk = devm_clk_get(&pdev->dev, "tmu_apbif"); 1335 if (IS_ERR(data->clk)) { 1336 dev_err(&pdev->dev, "Failed to get clock\n"); 1337 ret = PTR_ERR(data->clk); 1338 goto err_sensor; 1339 } 1340 1341 data->clk_sec = devm_clk_get(&pdev->dev, "tmu_triminfo_apbif"); 1342 if (IS_ERR(data->clk_sec)) { 1343 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) { 1344 dev_err(&pdev->dev, "Failed to get triminfo clock\n"); 1345 ret = PTR_ERR(data->clk_sec); 1346 goto err_sensor; 1347 } 1348 } else { 1349 ret = clk_prepare(data->clk_sec); 1350 if (ret) { 1351 dev_err(&pdev->dev, "Failed to get clock\n"); 1352 goto err_sensor; 1353 } 1354 } 1355 1356 ret = clk_prepare(data->clk); 1357 if (ret) { 1358 dev_err(&pdev->dev, "Failed to get clock\n"); 1359 goto err_clk_sec; 1360 } 1361 1362 switch (data->soc) { 1363 case SOC_ARCH_EXYNOS5433: 1364 case SOC_ARCH_EXYNOS7: 1365 data->sclk = devm_clk_get(&pdev->dev, "tmu_sclk"); 1366 if (IS_ERR(data->sclk)) { 1367 dev_err(&pdev->dev, "Failed to get sclk\n"); 1368 goto err_clk; 1369 } else { 1370 ret = clk_prepare_enable(data->sclk); 1371 if (ret) { 1372 dev_err(&pdev->dev, "Failed to enable sclk\n"); 1373 goto err_clk; 1374 } 1375 } 1376 break; 1377 default: 1378 break; 1379 } 1380 1381 /* 1382 * data->tzd must be registered before calling exynos_tmu_initialize(), 1383 * requesting irq and calling exynos_tmu_control(). 1384 */ 1385 data->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, data, 1386 &exynos_sensor_ops); 1387 if (IS_ERR(data->tzd)) { 1388 ret = PTR_ERR(data->tzd); 1389 dev_err(&pdev->dev, "Failed to register sensor: %d\n", ret); 1390 goto err_sclk; 1391 } 1392 1393 ret = exynos_tmu_initialize(pdev); 1394 if (ret) { 1395 dev_err(&pdev->dev, "Failed to initialize TMU\n"); 1396 goto err_thermal; 1397 } 1398 1399 ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq, 1400 IRQF_TRIGGER_RISING | IRQF_SHARED, dev_name(&pdev->dev), data); 1401 if (ret) { 1402 dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq); 1403 goto err_thermal; 1404 } 1405 1406 exynos_tmu_control(pdev, true); 1407 return 0; 1408 1409 err_thermal: 1410 thermal_zone_of_sensor_unregister(&pdev->dev, data->tzd); 1411 err_sclk: 1412 clk_disable_unprepare(data->sclk); 1413 err_clk: 1414 clk_unprepare(data->clk); 1415 err_clk_sec: 1416 if (!IS_ERR(data->clk_sec)) 1417 clk_unprepare(data->clk_sec); 1418 err_sensor: 1419 if (!IS_ERR(data->regulator)) 1420 regulator_disable(data->regulator); 1421 1422 return ret; 1423 } 1424 1425 static int exynos_tmu_remove(struct platform_device *pdev) 1426 { 1427 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 1428 struct thermal_zone_device *tzd = data->tzd; 1429 1430 thermal_zone_of_sensor_unregister(&pdev->dev, tzd); 1431 exynos_tmu_control(pdev, false); 1432 1433 clk_disable_unprepare(data->sclk); 1434 clk_unprepare(data->clk); 1435 if (!IS_ERR(data->clk_sec)) 1436 clk_unprepare(data->clk_sec); 1437 1438 if (!IS_ERR(data->regulator)) 1439 regulator_disable(data->regulator); 1440 1441 return 0; 1442 } 1443 1444 #ifdef CONFIG_PM_SLEEP 1445 static int exynos_tmu_suspend(struct device *dev) 1446 { 1447 exynos_tmu_control(to_platform_device(dev), false); 1448 1449 return 0; 1450 } 1451 1452 static int exynos_tmu_resume(struct device *dev) 1453 { 1454 struct platform_device *pdev = to_platform_device(dev); 1455 1456 exynos_tmu_initialize(pdev); 1457 exynos_tmu_control(pdev, true); 1458 1459 return 0; 1460 } 1461 1462 static SIMPLE_DEV_PM_OPS(exynos_tmu_pm, 1463 exynos_tmu_suspend, exynos_tmu_resume); 1464 #define EXYNOS_TMU_PM (&exynos_tmu_pm) 1465 #else 1466 #define EXYNOS_TMU_PM NULL 1467 #endif 1468 1469 static struct platform_driver exynos_tmu_driver = { 1470 .driver = { 1471 .name = "exynos-tmu", 1472 .pm = EXYNOS_TMU_PM, 1473 .of_match_table = exynos_tmu_match, 1474 }, 1475 .probe = exynos_tmu_probe, 1476 .remove = exynos_tmu_remove, 1477 }; 1478 1479 module_platform_driver(exynos_tmu_driver); 1480 1481 MODULE_DESCRIPTION("EXYNOS TMU Driver"); 1482 MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>"); 1483 MODULE_LICENSE("GPL"); 1484 MODULE_ALIAS("platform:exynos-tmu"); 1485