1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * exynos_tmu.c - Samsung Exynos TMU (Thermal Management Unit) 4 * 5 * Copyright (C) 2014 Samsung Electronics 6 * Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> 7 * Lukasz Majewski <l.majewski@samsung.com> 8 * 9 * Copyright (C) 2011 Samsung Electronics 10 * Donggeun Kim <dg77.kim@samsung.com> 11 * Amit Daniel Kachhap <amit.kachhap@linaro.org> 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/io.h> 16 #include <linux/interrupt.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/of_address.h> 20 #include <linux/of_irq.h> 21 #include <linux/platform_device.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/thermal.h> 24 25 #include <dt-bindings/thermal/thermal_exynos.h> 26 27 /* Exynos generic registers */ 28 #define EXYNOS_TMU_REG_TRIMINFO 0x0 29 #define EXYNOS_TMU_REG_CONTROL 0x20 30 #define EXYNOS_TMU_REG_STATUS 0x28 31 #define EXYNOS_TMU_REG_CURRENT_TEMP 0x40 32 #define EXYNOS_TMU_REG_INTEN 0x70 33 #define EXYNOS_TMU_REG_INTSTAT 0x74 34 #define EXYNOS_TMU_REG_INTCLEAR 0x78 35 36 #define EXYNOS_TMU_TEMP_MASK 0xff 37 #define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24 38 #define EXYNOS_TMU_REF_VOLTAGE_MASK 0x1f 39 #define EXYNOS_TMU_BUF_SLOPE_SEL_MASK 0xf 40 #define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT 8 41 #define EXYNOS_TMU_CORE_EN_SHIFT 0 42 43 /* Exynos3250 specific registers */ 44 #define EXYNOS_TMU_TRIMINFO_CON1 0x10 45 46 /* Exynos4210 specific registers */ 47 #define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44 48 #define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50 49 50 /* Exynos5250, Exynos4412, Exynos3250 specific registers */ 51 #define EXYNOS_TMU_TRIMINFO_CON2 0x14 52 #define EXYNOS_THD_TEMP_RISE 0x50 53 #define EXYNOS_THD_TEMP_FALL 0x54 54 #define EXYNOS_EMUL_CON 0x80 55 56 #define EXYNOS_TRIMINFO_RELOAD_ENABLE 1 57 #define EXYNOS_TRIMINFO_25_SHIFT 0 58 #define EXYNOS_TRIMINFO_85_SHIFT 8 59 #define EXYNOS_TMU_TRIP_MODE_SHIFT 13 60 #define EXYNOS_TMU_TRIP_MODE_MASK 0x7 61 #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12 62 63 #define EXYNOS_TMU_INTEN_RISE0_SHIFT 0 64 #define EXYNOS_TMU_INTEN_FALL0_SHIFT 16 65 66 #define EXYNOS_EMUL_TIME 0x57F0 67 #define EXYNOS_EMUL_TIME_MASK 0xffff 68 #define EXYNOS_EMUL_TIME_SHIFT 16 69 #define EXYNOS_EMUL_DATA_SHIFT 8 70 #define EXYNOS_EMUL_DATA_MASK 0xFF 71 #define EXYNOS_EMUL_ENABLE 0x1 72 73 /* Exynos5260 specific */ 74 #define EXYNOS5260_TMU_REG_INTEN 0xC0 75 #define EXYNOS5260_TMU_REG_INTSTAT 0xC4 76 #define EXYNOS5260_TMU_REG_INTCLEAR 0xC8 77 #define EXYNOS5260_EMUL_CON 0x100 78 79 /* Exynos4412 specific */ 80 #define EXYNOS4412_MUX_ADDR_VALUE 6 81 #define EXYNOS4412_MUX_ADDR_SHIFT 20 82 83 /* Exynos5433 specific registers */ 84 #define EXYNOS5433_THD_TEMP_RISE3_0 0x050 85 #define EXYNOS5433_THD_TEMP_RISE7_4 0x054 86 #define EXYNOS5433_THD_TEMP_FALL3_0 0x060 87 #define EXYNOS5433_THD_TEMP_FALL7_4 0x064 88 #define EXYNOS5433_TMU_REG_INTEN 0x0c0 89 #define EXYNOS5433_TMU_REG_INTPEND 0x0c8 90 #define EXYNOS5433_TMU_EMUL_CON 0x110 91 #define EXYNOS5433_TMU_PD_DET_EN 0x130 92 93 #define EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT 16 94 #define EXYNOS5433_TRIMINFO_CALIB_SEL_SHIFT 23 95 #define EXYNOS5433_TRIMINFO_SENSOR_ID_MASK \ 96 (0xf << EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT) 97 #define EXYNOS5433_TRIMINFO_CALIB_SEL_MASK BIT(23) 98 99 #define EXYNOS5433_TRIMINFO_ONE_POINT_TRIMMING 0 100 #define EXYNOS5433_TRIMINFO_TWO_POINT_TRIMMING 1 101 102 #define EXYNOS5433_PD_DET_EN 1 103 104 #define EXYNOS5433_G3D_BASE 0x10070000 105 106 /* Exynos7 specific registers */ 107 #define EXYNOS7_THD_TEMP_RISE7_6 0x50 108 #define EXYNOS7_THD_TEMP_FALL7_6 0x60 109 #define EXYNOS7_TMU_REG_INTEN 0x110 110 #define EXYNOS7_TMU_REG_INTPEND 0x118 111 #define EXYNOS7_TMU_REG_EMUL_CON 0x160 112 113 #define EXYNOS7_TMU_TEMP_MASK 0x1ff 114 #define EXYNOS7_PD_DET_EN_SHIFT 23 115 #define EXYNOS7_TMU_INTEN_RISE0_SHIFT 0 116 #define EXYNOS7_EMUL_DATA_SHIFT 7 117 #define EXYNOS7_EMUL_DATA_MASK 0x1ff 118 119 #define EXYNOS_FIRST_POINT_TRIM 25 120 #define EXYNOS_SECOND_POINT_TRIM 85 121 122 #define EXYNOS_NOISE_CANCEL_MODE 4 123 124 #define MCELSIUS 1000 125 126 enum soc_type { 127 SOC_ARCH_EXYNOS3250 = 1, 128 SOC_ARCH_EXYNOS4210, 129 SOC_ARCH_EXYNOS4412, 130 SOC_ARCH_EXYNOS5250, 131 SOC_ARCH_EXYNOS5260, 132 SOC_ARCH_EXYNOS5420, 133 SOC_ARCH_EXYNOS5420_TRIMINFO, 134 SOC_ARCH_EXYNOS5433, 135 SOC_ARCH_EXYNOS7, 136 }; 137 138 /** 139 * struct exynos_tmu_data : A structure to hold the private data of the TMU 140 * driver 141 * @base: base address of the single instance of the TMU controller. 142 * @base_second: base address of the common registers of the TMU controller. 143 * @irq: irq number of the TMU controller. 144 * @soc: id of the SOC type. 145 * @lock: lock to implement synchronization. 146 * @clk: pointer to the clock structure. 147 * @clk_sec: pointer to the clock structure for accessing the base_second. 148 * @sclk: pointer to the clock structure for accessing the tmu special clk. 149 * @cal_type: calibration type for temperature 150 * @efuse_value: SoC defined fuse value 151 * @min_efuse_value: minimum valid trimming data 152 * @max_efuse_value: maximum valid trimming data 153 * @temp_error1: fused value of the first point trim. 154 * @temp_error2: fused value of the second point trim. 155 * @gain: gain of amplifier in the positive-TC generator block 156 * 0 < gain <= 15 157 * @reference_voltage: reference voltage of amplifier 158 * in the positive-TC generator block 159 * 0 < reference_voltage <= 31 160 * @tzd: pointer to thermal_zone_device structure 161 * @ntrip: number of supported trip points. 162 * @enabled: current status of TMU device 163 * @tmu_set_trip_temp: SoC specific method to set trip (rising threshold) 164 * @tmu_set_trip_hyst: SoC specific to set hysteresis (falling threshold) 165 * @tmu_initialize: SoC specific TMU initialization method 166 * @tmu_control: SoC specific TMU control method 167 * @tmu_read: SoC specific TMU temperature read method 168 * @tmu_set_emulation: SoC specific TMU emulation setting method 169 * @tmu_clear_irqs: SoC specific TMU interrupts clearing method 170 */ 171 struct exynos_tmu_data { 172 void __iomem *base; 173 void __iomem *base_second; 174 int irq; 175 enum soc_type soc; 176 struct mutex lock; 177 struct clk *clk, *clk_sec, *sclk; 178 u32 cal_type; 179 u32 efuse_value; 180 u32 min_efuse_value; 181 u32 max_efuse_value; 182 u16 temp_error1, temp_error2; 183 u8 gain; 184 u8 reference_voltage; 185 struct thermal_zone_device *tzd; 186 unsigned int ntrip; 187 bool enabled; 188 189 void (*tmu_set_trip_temp)(struct exynos_tmu_data *data, int trip, 190 u8 temp); 191 void (*tmu_set_trip_hyst)(struct exynos_tmu_data *data, int trip, 192 u8 temp, u8 hyst); 193 void (*tmu_initialize)(struct platform_device *pdev); 194 void (*tmu_control)(struct platform_device *pdev, bool on); 195 int (*tmu_read)(struct exynos_tmu_data *data); 196 void (*tmu_set_emulation)(struct exynos_tmu_data *data, int temp); 197 void (*tmu_clear_irqs)(struct exynos_tmu_data *data); 198 }; 199 200 /* 201 * TMU treats temperature as a mapped temperature code. 202 * The temperature is converted differently depending on the calibration type. 203 */ 204 static int temp_to_code(struct exynos_tmu_data *data, u8 temp) 205 { 206 if (data->cal_type == TYPE_ONE_POINT_TRIMMING) 207 return temp + data->temp_error1 - EXYNOS_FIRST_POINT_TRIM; 208 209 return (temp - EXYNOS_FIRST_POINT_TRIM) * 210 (data->temp_error2 - data->temp_error1) / 211 (EXYNOS_SECOND_POINT_TRIM - EXYNOS_FIRST_POINT_TRIM) + 212 data->temp_error1; 213 } 214 215 /* 216 * Calculate a temperature value from a temperature code. 217 * The unit of the temperature is degree Celsius. 218 */ 219 static int code_to_temp(struct exynos_tmu_data *data, u16 temp_code) 220 { 221 if (data->cal_type == TYPE_ONE_POINT_TRIMMING) 222 return temp_code - data->temp_error1 + EXYNOS_FIRST_POINT_TRIM; 223 224 return (temp_code - data->temp_error1) * 225 (EXYNOS_SECOND_POINT_TRIM - EXYNOS_FIRST_POINT_TRIM) / 226 (data->temp_error2 - data->temp_error1) + 227 EXYNOS_FIRST_POINT_TRIM; 228 } 229 230 static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_info) 231 { 232 u16 tmu_temp_mask = 233 (data->soc == SOC_ARCH_EXYNOS7) ? EXYNOS7_TMU_TEMP_MASK 234 : EXYNOS_TMU_TEMP_MASK; 235 236 data->temp_error1 = trim_info & tmu_temp_mask; 237 data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) & 238 EXYNOS_TMU_TEMP_MASK); 239 240 if (!data->temp_error1 || 241 (data->min_efuse_value > data->temp_error1) || 242 (data->temp_error1 > data->max_efuse_value)) 243 data->temp_error1 = data->efuse_value & EXYNOS_TMU_TEMP_MASK; 244 245 if (!data->temp_error2) 246 data->temp_error2 = 247 (data->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) & 248 EXYNOS_TMU_TEMP_MASK; 249 } 250 251 static int exynos_tmu_initialize(struct platform_device *pdev) 252 { 253 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 254 struct thermal_zone_device *tzd = data->tzd; 255 int num_trips = thermal_zone_get_num_trips(tzd); 256 unsigned int status; 257 int ret = 0, temp; 258 259 ret = thermal_zone_get_crit_temp(tzd, &temp); 260 if (ret && data->soc != SOC_ARCH_EXYNOS5433) { /* FIXME */ 261 dev_err(&pdev->dev, 262 "No CRITICAL trip point defined in device tree!\n"); 263 goto out; 264 } 265 266 if (num_trips > data->ntrip) { 267 dev_info(&pdev->dev, 268 "More trip points than supported by this TMU.\n"); 269 dev_info(&pdev->dev, 270 "%d trip points should be configured in polling mode.\n", 271 num_trips - data->ntrip); 272 } 273 274 mutex_lock(&data->lock); 275 clk_enable(data->clk); 276 if (!IS_ERR(data->clk_sec)) 277 clk_enable(data->clk_sec); 278 279 status = readb(data->base + EXYNOS_TMU_REG_STATUS); 280 if (!status) { 281 ret = -EBUSY; 282 } else { 283 int i, ntrips = 284 min_t(int, num_trips, data->ntrip); 285 286 data->tmu_initialize(pdev); 287 288 /* Write temperature code for rising and falling threshold */ 289 for (i = 0; i < ntrips; i++) { 290 291 struct thermal_trip trip; 292 293 ret = thermal_zone_get_trip(tzd, i, &trip); 294 if (ret) 295 goto err; 296 297 data->tmu_set_trip_temp(data, i, trip.temperature / MCELSIUS); 298 data->tmu_set_trip_hyst(data, i, trip.temperature / MCELSIUS, 299 trip.hysteresis / MCELSIUS); 300 } 301 302 data->tmu_clear_irqs(data); 303 } 304 err: 305 clk_disable(data->clk); 306 mutex_unlock(&data->lock); 307 if (!IS_ERR(data->clk_sec)) 308 clk_disable(data->clk_sec); 309 out: 310 return ret; 311 } 312 313 static u32 get_con_reg(struct exynos_tmu_data *data, u32 con) 314 { 315 if (data->soc == SOC_ARCH_EXYNOS4412 || 316 data->soc == SOC_ARCH_EXYNOS3250) 317 con |= (EXYNOS4412_MUX_ADDR_VALUE << EXYNOS4412_MUX_ADDR_SHIFT); 318 319 con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK << EXYNOS_TMU_REF_VOLTAGE_SHIFT); 320 con |= data->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT; 321 322 con &= ~(EXYNOS_TMU_BUF_SLOPE_SEL_MASK << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT); 323 con |= (data->gain << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT); 324 325 con &= ~(EXYNOS_TMU_TRIP_MODE_MASK << EXYNOS_TMU_TRIP_MODE_SHIFT); 326 con |= (EXYNOS_NOISE_CANCEL_MODE << EXYNOS_TMU_TRIP_MODE_SHIFT); 327 328 return con; 329 } 330 331 static void exynos_tmu_control(struct platform_device *pdev, bool on) 332 { 333 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 334 335 mutex_lock(&data->lock); 336 clk_enable(data->clk); 337 data->tmu_control(pdev, on); 338 data->enabled = on; 339 clk_disable(data->clk); 340 mutex_unlock(&data->lock); 341 } 342 343 static void exynos4210_tmu_set_trip_temp(struct exynos_tmu_data *data, 344 int trip_id, u8 temp) 345 { 346 temp = temp_to_code(data, temp); 347 writeb(temp, data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL0 + trip_id * 4); 348 } 349 350 /* failing thresholds are not supported on Exynos4210 */ 351 static void exynos4210_tmu_set_trip_hyst(struct exynos_tmu_data *data, 352 int trip, u8 temp, u8 hyst) 353 { 354 } 355 356 static void exynos4210_tmu_initialize(struct platform_device *pdev) 357 { 358 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 359 360 sanitize_temp_error(data, readl(data->base + EXYNOS_TMU_REG_TRIMINFO)); 361 362 writeb(0, data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP); 363 } 364 365 static void exynos4412_tmu_set_trip_temp(struct exynos_tmu_data *data, 366 int trip, u8 temp) 367 { 368 u32 th, con; 369 370 th = readl(data->base + EXYNOS_THD_TEMP_RISE); 371 th &= ~(0xff << 8 * trip); 372 th |= temp_to_code(data, temp) << 8 * trip; 373 writel(th, data->base + EXYNOS_THD_TEMP_RISE); 374 375 if (trip == 3) { 376 con = readl(data->base + EXYNOS_TMU_REG_CONTROL); 377 con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT); 378 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 379 } 380 } 381 382 static void exynos4412_tmu_set_trip_hyst(struct exynos_tmu_data *data, 383 int trip, u8 temp, u8 hyst) 384 { 385 u32 th; 386 387 th = readl(data->base + EXYNOS_THD_TEMP_FALL); 388 th &= ~(0xff << 8 * trip); 389 if (hyst) 390 th |= temp_to_code(data, temp - hyst) << 8 * trip; 391 writel(th, data->base + EXYNOS_THD_TEMP_FALL); 392 } 393 394 static void exynos4412_tmu_initialize(struct platform_device *pdev) 395 { 396 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 397 unsigned int trim_info, ctrl; 398 399 if (data->soc == SOC_ARCH_EXYNOS3250 || 400 data->soc == SOC_ARCH_EXYNOS4412 || 401 data->soc == SOC_ARCH_EXYNOS5250) { 402 if (data->soc == SOC_ARCH_EXYNOS3250) { 403 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON1); 404 ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE; 405 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON1); 406 } 407 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON2); 408 ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE; 409 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON2); 410 } 411 412 /* On exynos5420 the triminfo register is in the shared space */ 413 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) 414 trim_info = readl(data->base_second + EXYNOS_TMU_REG_TRIMINFO); 415 else 416 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); 417 418 sanitize_temp_error(data, trim_info); 419 } 420 421 static void exynos5433_tmu_set_trip_temp(struct exynos_tmu_data *data, 422 int trip, u8 temp) 423 { 424 unsigned int reg_off, j; 425 u32 th; 426 427 if (trip > 3) { 428 reg_off = EXYNOS5433_THD_TEMP_RISE7_4; 429 j = trip - 4; 430 } else { 431 reg_off = EXYNOS5433_THD_TEMP_RISE3_0; 432 j = trip; 433 } 434 435 th = readl(data->base + reg_off); 436 th &= ~(0xff << j * 8); 437 th |= (temp_to_code(data, temp) << j * 8); 438 writel(th, data->base + reg_off); 439 } 440 441 static void exynos5433_tmu_set_trip_hyst(struct exynos_tmu_data *data, 442 int trip, u8 temp, u8 hyst) 443 { 444 unsigned int reg_off, j; 445 u32 th; 446 447 if (trip > 3) { 448 reg_off = EXYNOS5433_THD_TEMP_FALL7_4; 449 j = trip - 4; 450 } else { 451 reg_off = EXYNOS5433_THD_TEMP_FALL3_0; 452 j = trip; 453 } 454 455 th = readl(data->base + reg_off); 456 th &= ~(0xff << j * 8); 457 th |= (temp_to_code(data, temp - hyst) << j * 8); 458 writel(th, data->base + reg_off); 459 } 460 461 static void exynos5433_tmu_initialize(struct platform_device *pdev) 462 { 463 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 464 unsigned int trim_info; 465 int sensor_id, cal_type; 466 467 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); 468 sanitize_temp_error(data, trim_info); 469 470 /* Read the temperature sensor id */ 471 sensor_id = (trim_info & EXYNOS5433_TRIMINFO_SENSOR_ID_MASK) 472 >> EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT; 473 dev_info(&pdev->dev, "Temperature sensor ID: 0x%x\n", sensor_id); 474 475 /* Read the calibration mode */ 476 writel(trim_info, data->base + EXYNOS_TMU_REG_TRIMINFO); 477 cal_type = (trim_info & EXYNOS5433_TRIMINFO_CALIB_SEL_MASK) 478 >> EXYNOS5433_TRIMINFO_CALIB_SEL_SHIFT; 479 480 switch (cal_type) { 481 case EXYNOS5433_TRIMINFO_TWO_POINT_TRIMMING: 482 data->cal_type = TYPE_TWO_POINT_TRIMMING; 483 break; 484 case EXYNOS5433_TRIMINFO_ONE_POINT_TRIMMING: 485 default: 486 data->cal_type = TYPE_ONE_POINT_TRIMMING; 487 break; 488 } 489 490 dev_info(&pdev->dev, "Calibration type is %d-point calibration\n", 491 cal_type ? 2 : 1); 492 } 493 494 static void exynos7_tmu_set_trip_temp(struct exynos_tmu_data *data, 495 int trip, u8 temp) 496 { 497 unsigned int reg_off, bit_off; 498 u32 th; 499 500 reg_off = ((7 - trip) / 2) * 4; 501 bit_off = ((8 - trip) % 2); 502 503 th = readl(data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off); 504 th &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off)); 505 th |= temp_to_code(data, temp) << (16 * bit_off); 506 writel(th, data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off); 507 } 508 509 static void exynos7_tmu_set_trip_hyst(struct exynos_tmu_data *data, 510 int trip, u8 temp, u8 hyst) 511 { 512 unsigned int reg_off, bit_off; 513 u32 th; 514 515 reg_off = ((7 - trip) / 2) * 4; 516 bit_off = ((8 - trip) % 2); 517 518 th = readl(data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off); 519 th &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off)); 520 th |= temp_to_code(data, temp - hyst) << (16 * bit_off); 521 writel(th, data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off); 522 } 523 524 static void exynos7_tmu_initialize(struct platform_device *pdev) 525 { 526 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 527 unsigned int trim_info; 528 529 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); 530 sanitize_temp_error(data, trim_info); 531 } 532 533 static void exynos4210_tmu_control(struct platform_device *pdev, bool on) 534 { 535 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 536 struct thermal_zone_device *tz = data->tzd; 537 struct thermal_trip trip; 538 unsigned int con, interrupt_en = 0, i; 539 540 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); 541 542 if (on) { 543 for (i = 0; i < data->ntrip; i++) { 544 if (thermal_zone_get_trip(tz, i, &trip)) 545 continue; 546 547 interrupt_en |= 548 (1 << (EXYNOS_TMU_INTEN_RISE0_SHIFT + i * 4)); 549 } 550 551 if (data->soc != SOC_ARCH_EXYNOS4210) 552 interrupt_en |= 553 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; 554 555 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); 556 } else { 557 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); 558 } 559 560 writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN); 561 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 562 } 563 564 static void exynos5433_tmu_control(struct platform_device *pdev, bool on) 565 { 566 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 567 struct thermal_zone_device *tz = data->tzd; 568 struct thermal_trip trip; 569 unsigned int con, interrupt_en = 0, pd_det_en, i; 570 571 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); 572 573 if (on) { 574 for (i = 0; i < data->ntrip; i++) { 575 if (thermal_zone_get_trip(tz, i, &trip)) 576 continue; 577 578 interrupt_en |= 579 (1 << (EXYNOS7_TMU_INTEN_RISE0_SHIFT + i)); 580 } 581 582 interrupt_en |= 583 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; 584 585 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); 586 } else 587 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); 588 589 pd_det_en = on ? EXYNOS5433_PD_DET_EN : 0; 590 591 writel(pd_det_en, data->base + EXYNOS5433_TMU_PD_DET_EN); 592 writel(interrupt_en, data->base + EXYNOS5433_TMU_REG_INTEN); 593 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 594 } 595 596 static void exynos7_tmu_control(struct platform_device *pdev, bool on) 597 { 598 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 599 struct thermal_zone_device *tz = data->tzd; 600 struct thermal_trip trip; 601 unsigned int con, interrupt_en = 0, i; 602 603 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); 604 605 if (on) { 606 for (i = 0; i < data->ntrip; i++) { 607 if (thermal_zone_get_trip(tz, i, &trip)) 608 continue; 609 610 interrupt_en |= 611 (1 << (EXYNOS7_TMU_INTEN_RISE0_SHIFT + i)); 612 } 613 614 interrupt_en |= 615 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; 616 617 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); 618 con |= (1 << EXYNOS7_PD_DET_EN_SHIFT); 619 } else { 620 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); 621 con &= ~(1 << EXYNOS7_PD_DET_EN_SHIFT); 622 } 623 624 writel(interrupt_en, data->base + EXYNOS7_TMU_REG_INTEN); 625 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 626 } 627 628 static int exynos_get_temp(struct thermal_zone_device *tz, int *temp) 629 { 630 struct exynos_tmu_data *data = thermal_zone_device_priv(tz); 631 int value, ret = 0; 632 633 if (!data || !data->tmu_read) 634 return -EINVAL; 635 else if (!data->enabled) 636 /* 637 * Called too early, probably 638 * from thermal_zone_of_sensor_register(). 639 */ 640 return -EAGAIN; 641 642 mutex_lock(&data->lock); 643 clk_enable(data->clk); 644 645 value = data->tmu_read(data); 646 if (value < 0) 647 ret = value; 648 else 649 *temp = code_to_temp(data, value) * MCELSIUS; 650 651 clk_disable(data->clk); 652 mutex_unlock(&data->lock); 653 654 return ret; 655 } 656 657 #ifdef CONFIG_THERMAL_EMULATION 658 static u32 get_emul_con_reg(struct exynos_tmu_data *data, unsigned int val, 659 int temp) 660 { 661 if (temp) { 662 temp /= MCELSIUS; 663 664 val &= ~(EXYNOS_EMUL_TIME_MASK << EXYNOS_EMUL_TIME_SHIFT); 665 val |= (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT); 666 if (data->soc == SOC_ARCH_EXYNOS7) { 667 val &= ~(EXYNOS7_EMUL_DATA_MASK << 668 EXYNOS7_EMUL_DATA_SHIFT); 669 val |= (temp_to_code(data, temp) << 670 EXYNOS7_EMUL_DATA_SHIFT) | 671 EXYNOS_EMUL_ENABLE; 672 } else { 673 val &= ~(EXYNOS_EMUL_DATA_MASK << 674 EXYNOS_EMUL_DATA_SHIFT); 675 val |= (temp_to_code(data, temp) << 676 EXYNOS_EMUL_DATA_SHIFT) | 677 EXYNOS_EMUL_ENABLE; 678 } 679 } else { 680 val &= ~EXYNOS_EMUL_ENABLE; 681 } 682 683 return val; 684 } 685 686 static void exynos4412_tmu_set_emulation(struct exynos_tmu_data *data, 687 int temp) 688 { 689 unsigned int val; 690 u32 emul_con; 691 692 if (data->soc == SOC_ARCH_EXYNOS5260) 693 emul_con = EXYNOS5260_EMUL_CON; 694 else if (data->soc == SOC_ARCH_EXYNOS5433) 695 emul_con = EXYNOS5433_TMU_EMUL_CON; 696 else if (data->soc == SOC_ARCH_EXYNOS7) 697 emul_con = EXYNOS7_TMU_REG_EMUL_CON; 698 else 699 emul_con = EXYNOS_EMUL_CON; 700 701 val = readl(data->base + emul_con); 702 val = get_emul_con_reg(data, val, temp); 703 writel(val, data->base + emul_con); 704 } 705 706 static int exynos_tmu_set_emulation(struct thermal_zone_device *tz, int temp) 707 { 708 struct exynos_tmu_data *data = thermal_zone_device_priv(tz); 709 int ret = -EINVAL; 710 711 if (data->soc == SOC_ARCH_EXYNOS4210) 712 goto out; 713 714 if (temp && temp < MCELSIUS) 715 goto out; 716 717 mutex_lock(&data->lock); 718 clk_enable(data->clk); 719 data->tmu_set_emulation(data, temp); 720 clk_disable(data->clk); 721 mutex_unlock(&data->lock); 722 return 0; 723 out: 724 return ret; 725 } 726 #else 727 #define exynos4412_tmu_set_emulation NULL 728 static int exynos_tmu_set_emulation(struct thermal_zone_device *tz, int temp) 729 { return -EINVAL; } 730 #endif /* CONFIG_THERMAL_EMULATION */ 731 732 static int exynos4210_tmu_read(struct exynos_tmu_data *data) 733 { 734 int ret = readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP); 735 736 /* "temp_code" should range between 75 and 175 */ 737 return (ret < 75 || ret > 175) ? -ENODATA : ret; 738 } 739 740 static int exynos4412_tmu_read(struct exynos_tmu_data *data) 741 { 742 return readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP); 743 } 744 745 static int exynos7_tmu_read(struct exynos_tmu_data *data) 746 { 747 return readw(data->base + EXYNOS_TMU_REG_CURRENT_TEMP) & 748 EXYNOS7_TMU_TEMP_MASK; 749 } 750 751 static irqreturn_t exynos_tmu_threaded_irq(int irq, void *id) 752 { 753 struct exynos_tmu_data *data = id; 754 755 thermal_zone_device_update(data->tzd, THERMAL_EVENT_UNSPECIFIED); 756 757 mutex_lock(&data->lock); 758 clk_enable(data->clk); 759 760 /* TODO: take action based on particular interrupt */ 761 data->tmu_clear_irqs(data); 762 763 clk_disable(data->clk); 764 mutex_unlock(&data->lock); 765 766 return IRQ_HANDLED; 767 } 768 769 static void exynos4210_tmu_clear_irqs(struct exynos_tmu_data *data) 770 { 771 unsigned int val_irq; 772 u32 tmu_intstat, tmu_intclear; 773 774 if (data->soc == SOC_ARCH_EXYNOS5260) { 775 tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT; 776 tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR; 777 } else if (data->soc == SOC_ARCH_EXYNOS7) { 778 tmu_intstat = EXYNOS7_TMU_REG_INTPEND; 779 tmu_intclear = EXYNOS7_TMU_REG_INTPEND; 780 } else if (data->soc == SOC_ARCH_EXYNOS5433) { 781 tmu_intstat = EXYNOS5433_TMU_REG_INTPEND; 782 tmu_intclear = EXYNOS5433_TMU_REG_INTPEND; 783 } else { 784 tmu_intstat = EXYNOS_TMU_REG_INTSTAT; 785 tmu_intclear = EXYNOS_TMU_REG_INTCLEAR; 786 } 787 788 val_irq = readl(data->base + tmu_intstat); 789 /* 790 * Clear the interrupts. Please note that the documentation for 791 * Exynos3250, Exynos4412, Exynos5250 and Exynos5260 incorrectly 792 * states that INTCLEAR register has a different placing of bits 793 * responsible for FALL IRQs than INTSTAT register. Exynos5420 794 * and Exynos5440 documentation is correct (Exynos4210 doesn't 795 * support FALL IRQs at all). 796 */ 797 writel(val_irq, data->base + tmu_intclear); 798 } 799 800 static const struct of_device_id exynos_tmu_match[] = { 801 { 802 .compatible = "samsung,exynos3250-tmu", 803 .data = (const void *)SOC_ARCH_EXYNOS3250, 804 }, { 805 .compatible = "samsung,exynos4210-tmu", 806 .data = (const void *)SOC_ARCH_EXYNOS4210, 807 }, { 808 .compatible = "samsung,exynos4412-tmu", 809 .data = (const void *)SOC_ARCH_EXYNOS4412, 810 }, { 811 .compatible = "samsung,exynos5250-tmu", 812 .data = (const void *)SOC_ARCH_EXYNOS5250, 813 }, { 814 .compatible = "samsung,exynos5260-tmu", 815 .data = (const void *)SOC_ARCH_EXYNOS5260, 816 }, { 817 .compatible = "samsung,exynos5420-tmu", 818 .data = (const void *)SOC_ARCH_EXYNOS5420, 819 }, { 820 .compatible = "samsung,exynos5420-tmu-ext-triminfo", 821 .data = (const void *)SOC_ARCH_EXYNOS5420_TRIMINFO, 822 }, { 823 .compatible = "samsung,exynos5433-tmu", 824 .data = (const void *)SOC_ARCH_EXYNOS5433, 825 }, { 826 .compatible = "samsung,exynos7-tmu", 827 .data = (const void *)SOC_ARCH_EXYNOS7, 828 }, 829 { }, 830 }; 831 MODULE_DEVICE_TABLE(of, exynos_tmu_match); 832 833 static int exynos_map_dt_data(struct platform_device *pdev) 834 { 835 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 836 struct resource res; 837 838 if (!data || !pdev->dev.of_node) 839 return -ENODEV; 840 841 data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 842 if (data->irq <= 0) { 843 dev_err(&pdev->dev, "failed to get IRQ\n"); 844 return -ENODEV; 845 } 846 847 if (of_address_to_resource(pdev->dev.of_node, 0, &res)) { 848 dev_err(&pdev->dev, "failed to get Resource 0\n"); 849 return -ENODEV; 850 } 851 852 data->base = devm_ioremap(&pdev->dev, res.start, resource_size(&res)); 853 if (!data->base) { 854 dev_err(&pdev->dev, "Failed to ioremap memory\n"); 855 return -EADDRNOTAVAIL; 856 } 857 858 data->soc = (uintptr_t)of_device_get_match_data(&pdev->dev); 859 860 switch (data->soc) { 861 case SOC_ARCH_EXYNOS4210: 862 data->tmu_set_trip_temp = exynos4210_tmu_set_trip_temp; 863 data->tmu_set_trip_hyst = exynos4210_tmu_set_trip_hyst; 864 data->tmu_initialize = exynos4210_tmu_initialize; 865 data->tmu_control = exynos4210_tmu_control; 866 data->tmu_read = exynos4210_tmu_read; 867 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; 868 data->ntrip = 4; 869 data->gain = 15; 870 data->reference_voltage = 7; 871 data->efuse_value = 55; 872 data->min_efuse_value = 40; 873 data->max_efuse_value = 100; 874 break; 875 case SOC_ARCH_EXYNOS3250: 876 case SOC_ARCH_EXYNOS4412: 877 case SOC_ARCH_EXYNOS5250: 878 case SOC_ARCH_EXYNOS5260: 879 case SOC_ARCH_EXYNOS5420: 880 case SOC_ARCH_EXYNOS5420_TRIMINFO: 881 data->tmu_set_trip_temp = exynos4412_tmu_set_trip_temp; 882 data->tmu_set_trip_hyst = exynos4412_tmu_set_trip_hyst; 883 data->tmu_initialize = exynos4412_tmu_initialize; 884 data->tmu_control = exynos4210_tmu_control; 885 data->tmu_read = exynos4412_tmu_read; 886 data->tmu_set_emulation = exynos4412_tmu_set_emulation; 887 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; 888 data->ntrip = 4; 889 data->gain = 8; 890 data->reference_voltage = 16; 891 data->efuse_value = 55; 892 if (data->soc != SOC_ARCH_EXYNOS5420 && 893 data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO) 894 data->min_efuse_value = 40; 895 else 896 data->min_efuse_value = 0; 897 data->max_efuse_value = 100; 898 break; 899 case SOC_ARCH_EXYNOS5433: 900 data->tmu_set_trip_temp = exynos5433_tmu_set_trip_temp; 901 data->tmu_set_trip_hyst = exynos5433_tmu_set_trip_hyst; 902 data->tmu_initialize = exynos5433_tmu_initialize; 903 data->tmu_control = exynos5433_tmu_control; 904 data->tmu_read = exynos4412_tmu_read; 905 data->tmu_set_emulation = exynos4412_tmu_set_emulation; 906 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; 907 data->ntrip = 8; 908 data->gain = 8; 909 if (res.start == EXYNOS5433_G3D_BASE) 910 data->reference_voltage = 23; 911 else 912 data->reference_voltage = 16; 913 data->efuse_value = 75; 914 data->min_efuse_value = 40; 915 data->max_efuse_value = 150; 916 break; 917 case SOC_ARCH_EXYNOS7: 918 data->tmu_set_trip_temp = exynos7_tmu_set_trip_temp; 919 data->tmu_set_trip_hyst = exynos7_tmu_set_trip_hyst; 920 data->tmu_initialize = exynos7_tmu_initialize; 921 data->tmu_control = exynos7_tmu_control; 922 data->tmu_read = exynos7_tmu_read; 923 data->tmu_set_emulation = exynos4412_tmu_set_emulation; 924 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; 925 data->ntrip = 8; 926 data->gain = 9; 927 data->reference_voltage = 17; 928 data->efuse_value = 75; 929 data->min_efuse_value = 15; 930 data->max_efuse_value = 100; 931 break; 932 default: 933 dev_err(&pdev->dev, "Platform not supported\n"); 934 return -EINVAL; 935 } 936 937 data->cal_type = TYPE_ONE_POINT_TRIMMING; 938 939 /* 940 * Check if the TMU shares some registers and then try to map the 941 * memory of common registers. 942 */ 943 if (data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO) 944 return 0; 945 946 if (of_address_to_resource(pdev->dev.of_node, 1, &res)) { 947 dev_err(&pdev->dev, "failed to get Resource 1\n"); 948 return -ENODEV; 949 } 950 951 data->base_second = devm_ioremap(&pdev->dev, res.start, 952 resource_size(&res)); 953 if (!data->base_second) { 954 dev_err(&pdev->dev, "Failed to ioremap memory\n"); 955 return -ENOMEM; 956 } 957 958 return 0; 959 } 960 961 static const struct thermal_zone_device_ops exynos_sensor_ops = { 962 .get_temp = exynos_get_temp, 963 .set_emul_temp = exynos_tmu_set_emulation, 964 }; 965 966 static int exynos_tmu_probe(struct platform_device *pdev) 967 { 968 struct exynos_tmu_data *data; 969 int ret; 970 971 data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data), 972 GFP_KERNEL); 973 if (!data) 974 return -ENOMEM; 975 976 platform_set_drvdata(pdev, data); 977 mutex_init(&data->lock); 978 979 /* 980 * Try enabling the regulator if found 981 * TODO: Add regulator as an SOC feature, so that regulator enable 982 * is a compulsory call. 983 */ 984 ret = devm_regulator_get_enable_optional(&pdev->dev, "vtmu"); 985 switch (ret) { 986 case 0: 987 case -ENODEV: 988 break; 989 case -EPROBE_DEFER: 990 return -EPROBE_DEFER; 991 default: 992 dev_err(&pdev->dev, "Failed to get enabled regulator: %d\n", 993 ret); 994 return ret; 995 } 996 997 ret = exynos_map_dt_data(pdev); 998 if (ret) 999 return ret; 1000 1001 data->clk = devm_clk_get(&pdev->dev, "tmu_apbif"); 1002 if (IS_ERR(data->clk)) { 1003 dev_err(&pdev->dev, "Failed to get clock\n"); 1004 return PTR_ERR(data->clk); 1005 } 1006 1007 data->clk_sec = devm_clk_get(&pdev->dev, "tmu_triminfo_apbif"); 1008 if (IS_ERR(data->clk_sec)) { 1009 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) { 1010 dev_err(&pdev->dev, "Failed to get triminfo clock\n"); 1011 return PTR_ERR(data->clk_sec); 1012 } 1013 } else { 1014 ret = clk_prepare(data->clk_sec); 1015 if (ret) { 1016 dev_err(&pdev->dev, "Failed to get clock\n"); 1017 return ret; 1018 } 1019 } 1020 1021 ret = clk_prepare(data->clk); 1022 if (ret) { 1023 dev_err(&pdev->dev, "Failed to get clock\n"); 1024 goto err_clk_sec; 1025 } 1026 1027 switch (data->soc) { 1028 case SOC_ARCH_EXYNOS5433: 1029 case SOC_ARCH_EXYNOS7: 1030 data->sclk = devm_clk_get(&pdev->dev, "tmu_sclk"); 1031 if (IS_ERR(data->sclk)) { 1032 dev_err(&pdev->dev, "Failed to get sclk\n"); 1033 ret = PTR_ERR(data->sclk); 1034 goto err_clk; 1035 } else { 1036 ret = clk_prepare_enable(data->sclk); 1037 if (ret) { 1038 dev_err(&pdev->dev, "Failed to enable sclk\n"); 1039 goto err_clk; 1040 } 1041 } 1042 break; 1043 default: 1044 break; 1045 } 1046 1047 /* 1048 * data->tzd must be registered before calling exynos_tmu_initialize(), 1049 * requesting irq and calling exynos_tmu_control(). 1050 */ 1051 data->tzd = devm_thermal_of_zone_register(&pdev->dev, 0, data, 1052 &exynos_sensor_ops); 1053 if (IS_ERR(data->tzd)) { 1054 ret = PTR_ERR(data->tzd); 1055 if (ret != -EPROBE_DEFER) 1056 dev_err(&pdev->dev, "Failed to register sensor: %d\n", 1057 ret); 1058 goto err_sclk; 1059 } 1060 1061 ret = exynos_tmu_initialize(pdev); 1062 if (ret) { 1063 dev_err(&pdev->dev, "Failed to initialize TMU\n"); 1064 goto err_sclk; 1065 } 1066 1067 ret = devm_request_threaded_irq(&pdev->dev, data->irq, NULL, 1068 exynos_tmu_threaded_irq, 1069 IRQF_TRIGGER_RISING 1070 | IRQF_SHARED | IRQF_ONESHOT, 1071 dev_name(&pdev->dev), data); 1072 if (ret) { 1073 dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq); 1074 goto err_sclk; 1075 } 1076 1077 exynos_tmu_control(pdev, true); 1078 return 0; 1079 1080 err_sclk: 1081 clk_disable_unprepare(data->sclk); 1082 err_clk: 1083 clk_unprepare(data->clk); 1084 err_clk_sec: 1085 if (!IS_ERR(data->clk_sec)) 1086 clk_unprepare(data->clk_sec); 1087 return ret; 1088 } 1089 1090 static void exynos_tmu_remove(struct platform_device *pdev) 1091 { 1092 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 1093 1094 exynos_tmu_control(pdev, false); 1095 1096 clk_disable_unprepare(data->sclk); 1097 clk_unprepare(data->clk); 1098 if (!IS_ERR(data->clk_sec)) 1099 clk_unprepare(data->clk_sec); 1100 } 1101 1102 #ifdef CONFIG_PM_SLEEP 1103 static int exynos_tmu_suspend(struct device *dev) 1104 { 1105 exynos_tmu_control(to_platform_device(dev), false); 1106 1107 return 0; 1108 } 1109 1110 static int exynos_tmu_resume(struct device *dev) 1111 { 1112 struct platform_device *pdev = to_platform_device(dev); 1113 1114 exynos_tmu_initialize(pdev); 1115 exynos_tmu_control(pdev, true); 1116 1117 return 0; 1118 } 1119 1120 static SIMPLE_DEV_PM_OPS(exynos_tmu_pm, 1121 exynos_tmu_suspend, exynos_tmu_resume); 1122 #define EXYNOS_TMU_PM (&exynos_tmu_pm) 1123 #else 1124 #define EXYNOS_TMU_PM NULL 1125 #endif 1126 1127 static struct platform_driver exynos_tmu_driver = { 1128 .driver = { 1129 .name = "exynos-tmu", 1130 .pm = EXYNOS_TMU_PM, 1131 .of_match_table = exynos_tmu_match, 1132 }, 1133 .probe = exynos_tmu_probe, 1134 .remove_new = exynos_tmu_remove, 1135 }; 1136 1137 module_platform_driver(exynos_tmu_driver); 1138 1139 MODULE_DESCRIPTION("Exynos TMU Driver"); 1140 MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>"); 1141 MODULE_LICENSE("GPL"); 1142 MODULE_ALIAS("platform:exynos-tmu"); 1143