1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit) 4 * 5 * Copyright (C) 2014 Samsung Electronics 6 * Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> 7 * Lukasz Majewski <l.majewski@samsung.com> 8 * 9 * Copyright (C) 2011 Samsung Electronics 10 * Donggeun Kim <dg77.kim@samsung.com> 11 * Amit Daniel Kachhap <amit.kachhap@linaro.org> 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/io.h> 16 #include <linux/interrupt.h> 17 #include <linux/module.h> 18 #include <linux/of_device.h> 19 #include <linux/of_address.h> 20 #include <linux/of_irq.h> 21 #include <linux/platform_device.h> 22 #include <linux/regulator/consumer.h> 23 24 #include <dt-bindings/thermal/thermal_exynos.h> 25 26 #include "../thermal_core.h" 27 28 /* Exynos generic registers */ 29 #define EXYNOS_TMU_REG_TRIMINFO 0x0 30 #define EXYNOS_TMU_REG_CONTROL 0x20 31 #define EXYNOS_TMU_REG_STATUS 0x28 32 #define EXYNOS_TMU_REG_CURRENT_TEMP 0x40 33 #define EXYNOS_TMU_REG_INTEN 0x70 34 #define EXYNOS_TMU_REG_INTSTAT 0x74 35 #define EXYNOS_TMU_REG_INTCLEAR 0x78 36 37 #define EXYNOS_TMU_TEMP_MASK 0xff 38 #define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24 39 #define EXYNOS_TMU_REF_VOLTAGE_MASK 0x1f 40 #define EXYNOS_TMU_BUF_SLOPE_SEL_MASK 0xf 41 #define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT 8 42 #define EXYNOS_TMU_CORE_EN_SHIFT 0 43 44 /* Exynos3250 specific registers */ 45 #define EXYNOS_TMU_TRIMINFO_CON1 0x10 46 47 /* Exynos4210 specific registers */ 48 #define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44 49 #define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50 50 51 /* Exynos5250, Exynos4412, Exynos3250 specific registers */ 52 #define EXYNOS_TMU_TRIMINFO_CON2 0x14 53 #define EXYNOS_THD_TEMP_RISE 0x50 54 #define EXYNOS_THD_TEMP_FALL 0x54 55 #define EXYNOS_EMUL_CON 0x80 56 57 #define EXYNOS_TRIMINFO_RELOAD_ENABLE 1 58 #define EXYNOS_TRIMINFO_25_SHIFT 0 59 #define EXYNOS_TRIMINFO_85_SHIFT 8 60 #define EXYNOS_TMU_TRIP_MODE_SHIFT 13 61 #define EXYNOS_TMU_TRIP_MODE_MASK 0x7 62 #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12 63 64 #define EXYNOS_TMU_INTEN_RISE0_SHIFT 0 65 #define EXYNOS_TMU_INTEN_FALL0_SHIFT 16 66 67 #define EXYNOS_EMUL_TIME 0x57F0 68 #define EXYNOS_EMUL_TIME_MASK 0xffff 69 #define EXYNOS_EMUL_TIME_SHIFT 16 70 #define EXYNOS_EMUL_DATA_SHIFT 8 71 #define EXYNOS_EMUL_DATA_MASK 0xFF 72 #define EXYNOS_EMUL_ENABLE 0x1 73 74 /* Exynos5260 specific */ 75 #define EXYNOS5260_TMU_REG_INTEN 0xC0 76 #define EXYNOS5260_TMU_REG_INTSTAT 0xC4 77 #define EXYNOS5260_TMU_REG_INTCLEAR 0xC8 78 #define EXYNOS5260_EMUL_CON 0x100 79 80 /* Exynos4412 specific */ 81 #define EXYNOS4412_MUX_ADDR_VALUE 6 82 #define EXYNOS4412_MUX_ADDR_SHIFT 20 83 84 /* Exynos5433 specific registers */ 85 #define EXYNOS5433_THD_TEMP_RISE3_0 0x050 86 #define EXYNOS5433_THD_TEMP_RISE7_4 0x054 87 #define EXYNOS5433_THD_TEMP_FALL3_0 0x060 88 #define EXYNOS5433_THD_TEMP_FALL7_4 0x064 89 #define EXYNOS5433_TMU_REG_INTEN 0x0c0 90 #define EXYNOS5433_TMU_REG_INTPEND 0x0c8 91 #define EXYNOS5433_TMU_EMUL_CON 0x110 92 #define EXYNOS5433_TMU_PD_DET_EN 0x130 93 94 #define EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT 16 95 #define EXYNOS5433_TRIMINFO_CALIB_SEL_SHIFT 23 96 #define EXYNOS5433_TRIMINFO_SENSOR_ID_MASK \ 97 (0xf << EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT) 98 #define EXYNOS5433_TRIMINFO_CALIB_SEL_MASK BIT(23) 99 100 #define EXYNOS5433_TRIMINFO_ONE_POINT_TRIMMING 0 101 #define EXYNOS5433_TRIMINFO_TWO_POINT_TRIMMING 1 102 103 #define EXYNOS5433_PD_DET_EN 1 104 105 #define EXYNOS5433_G3D_BASE 0x10070000 106 107 /* Exynos7 specific registers */ 108 #define EXYNOS7_THD_TEMP_RISE7_6 0x50 109 #define EXYNOS7_THD_TEMP_FALL7_6 0x60 110 #define EXYNOS7_TMU_REG_INTEN 0x110 111 #define EXYNOS7_TMU_REG_INTPEND 0x118 112 #define EXYNOS7_TMU_REG_EMUL_CON 0x160 113 114 #define EXYNOS7_TMU_TEMP_MASK 0x1ff 115 #define EXYNOS7_PD_DET_EN_SHIFT 23 116 #define EXYNOS7_TMU_INTEN_RISE0_SHIFT 0 117 #define EXYNOS7_EMUL_DATA_SHIFT 7 118 #define EXYNOS7_EMUL_DATA_MASK 0x1ff 119 120 #define EXYNOS_FIRST_POINT_TRIM 25 121 #define EXYNOS_SECOND_POINT_TRIM 85 122 123 #define EXYNOS_NOISE_CANCEL_MODE 4 124 125 #define MCELSIUS 1000 126 127 enum soc_type { 128 SOC_ARCH_EXYNOS3250 = 1, 129 SOC_ARCH_EXYNOS4210, 130 SOC_ARCH_EXYNOS4412, 131 SOC_ARCH_EXYNOS5250, 132 SOC_ARCH_EXYNOS5260, 133 SOC_ARCH_EXYNOS5420, 134 SOC_ARCH_EXYNOS5420_TRIMINFO, 135 SOC_ARCH_EXYNOS5433, 136 SOC_ARCH_EXYNOS7, 137 }; 138 139 /** 140 * struct exynos_tmu_data : A structure to hold the private data of the TMU 141 driver 142 * @id: identifier of the one instance of the TMU controller. 143 * @base: base address of the single instance of the TMU controller. 144 * @base_second: base address of the common registers of the TMU controller. 145 * @irq: irq number of the TMU controller. 146 * @soc: id of the SOC type. 147 * @irq_work: pointer to the irq work structure. 148 * @lock: lock to implement synchronization. 149 * @clk: pointer to the clock structure. 150 * @clk_sec: pointer to the clock structure for accessing the base_second. 151 * @sclk: pointer to the clock structure for accessing the tmu special clk. 152 * @cal_type: calibration type for temperature 153 * @efuse_value: SoC defined fuse value 154 * @min_efuse_value: minimum valid trimming data 155 * @max_efuse_value: maximum valid trimming data 156 * @temp_error1: fused value of the first point trim. 157 * @temp_error2: fused value of the second point trim. 158 * @gain: gain of amplifier in the positive-TC generator block 159 * 0 < gain <= 15 160 * @reference_voltage: reference voltage of amplifier 161 * in the positive-TC generator block 162 * 0 < reference_voltage <= 31 163 * @regulator: pointer to the TMU regulator structure. 164 * @reg_conf: pointer to structure to register with core thermal. 165 * @ntrip: number of supported trip points. 166 * @enabled: current status of TMU device 167 * @tmu_initialize: SoC specific TMU initialization method 168 * @tmu_control: SoC specific TMU control method 169 * @tmu_read: SoC specific TMU temperature read method 170 * @tmu_set_emulation: SoC specific TMU emulation setting method 171 * @tmu_clear_irqs: SoC specific TMU interrupts clearing method 172 */ 173 struct exynos_tmu_data { 174 int id; 175 void __iomem *base; 176 void __iomem *base_second; 177 int irq; 178 enum soc_type soc; 179 struct work_struct irq_work; 180 struct mutex lock; 181 struct clk *clk, *clk_sec, *sclk; 182 u32 cal_type; 183 u32 efuse_value; 184 u32 min_efuse_value; 185 u32 max_efuse_value; 186 u16 temp_error1, temp_error2; 187 u8 gain; 188 u8 reference_voltage; 189 struct regulator *regulator; 190 struct thermal_zone_device *tzd; 191 unsigned int ntrip; 192 bool enabled; 193 194 void (*tmu_set_trip_temp)(struct exynos_tmu_data *data, int trip, 195 u8 temp); 196 void (*tmu_set_trip_hyst)(struct exynos_tmu_data *data, int trip, 197 u8 temp, u8 hyst); 198 void (*tmu_initialize)(struct platform_device *pdev); 199 void (*tmu_control)(struct platform_device *pdev, bool on); 200 int (*tmu_read)(struct exynos_tmu_data *data); 201 void (*tmu_set_emulation)(struct exynos_tmu_data *data, int temp); 202 void (*tmu_clear_irqs)(struct exynos_tmu_data *data); 203 }; 204 205 /* 206 * TMU treats temperature as a mapped temperature code. 207 * The temperature is converted differently depending on the calibration type. 208 */ 209 static int temp_to_code(struct exynos_tmu_data *data, u8 temp) 210 { 211 if (data->cal_type == TYPE_ONE_POINT_TRIMMING) 212 return temp + data->temp_error1 - EXYNOS_FIRST_POINT_TRIM; 213 214 return (temp - EXYNOS_FIRST_POINT_TRIM) * 215 (data->temp_error2 - data->temp_error1) / 216 (EXYNOS_SECOND_POINT_TRIM - EXYNOS_FIRST_POINT_TRIM) + 217 data->temp_error1; 218 } 219 220 /* 221 * Calculate a temperature value from a temperature code. 222 * The unit of the temperature is degree Celsius. 223 */ 224 static int code_to_temp(struct exynos_tmu_data *data, u16 temp_code) 225 { 226 if (data->cal_type == TYPE_ONE_POINT_TRIMMING) 227 return temp_code - data->temp_error1 + EXYNOS_FIRST_POINT_TRIM; 228 229 return (temp_code - data->temp_error1) * 230 (EXYNOS_SECOND_POINT_TRIM - EXYNOS_FIRST_POINT_TRIM) / 231 (data->temp_error2 - data->temp_error1) + 232 EXYNOS_FIRST_POINT_TRIM; 233 } 234 235 static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_info) 236 { 237 u16 tmu_temp_mask = 238 (data->soc == SOC_ARCH_EXYNOS7) ? EXYNOS7_TMU_TEMP_MASK 239 : EXYNOS_TMU_TEMP_MASK; 240 241 data->temp_error1 = trim_info & tmu_temp_mask; 242 data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) & 243 EXYNOS_TMU_TEMP_MASK); 244 245 if (!data->temp_error1 || 246 (data->min_efuse_value > data->temp_error1) || 247 (data->temp_error1 > data->max_efuse_value)) 248 data->temp_error1 = data->efuse_value & EXYNOS_TMU_TEMP_MASK; 249 250 if (!data->temp_error2) 251 data->temp_error2 = 252 (data->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) & 253 EXYNOS_TMU_TEMP_MASK; 254 } 255 256 static int exynos_tmu_initialize(struct platform_device *pdev) 257 { 258 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 259 struct thermal_zone_device *tzd = data->tzd; 260 const struct thermal_trip * const trips = 261 of_thermal_get_trip_points(tzd); 262 unsigned int status; 263 int ret = 0, temp, hyst; 264 265 if (!trips) { 266 dev_err(&pdev->dev, 267 "Cannot get trip points from device tree!\n"); 268 return -ENODEV; 269 } 270 271 if (data->soc != SOC_ARCH_EXYNOS5433) /* FIXME */ 272 ret = tzd->ops->get_crit_temp(tzd, &temp); 273 if (ret) { 274 dev_err(&pdev->dev, 275 "No CRITICAL trip point defined in device tree!\n"); 276 goto out; 277 } 278 279 if (of_thermal_get_ntrips(tzd) > data->ntrip) { 280 dev_info(&pdev->dev, 281 "More trip points than supported by this TMU.\n"); 282 dev_info(&pdev->dev, 283 "%d trip points should be configured in polling mode.\n", 284 (of_thermal_get_ntrips(tzd) - data->ntrip)); 285 } 286 287 mutex_lock(&data->lock); 288 clk_enable(data->clk); 289 if (!IS_ERR(data->clk_sec)) 290 clk_enable(data->clk_sec); 291 292 status = readb(data->base + EXYNOS_TMU_REG_STATUS); 293 if (!status) { 294 ret = -EBUSY; 295 } else { 296 int i, ntrips = 297 min_t(int, of_thermal_get_ntrips(tzd), data->ntrip); 298 299 data->tmu_initialize(pdev); 300 301 /* Write temperature code for rising and falling threshold */ 302 for (i = 0; i < ntrips; i++) { 303 /* Write temperature code for rising threshold */ 304 ret = tzd->ops->get_trip_temp(tzd, i, &temp); 305 if (ret) 306 goto err; 307 temp /= MCELSIUS; 308 data->tmu_set_trip_temp(data, i, temp); 309 310 /* Write temperature code for falling threshold */ 311 ret = tzd->ops->get_trip_hyst(tzd, i, &hyst); 312 if (ret) 313 goto err; 314 hyst /= MCELSIUS; 315 data->tmu_set_trip_hyst(data, i, temp, hyst); 316 } 317 318 data->tmu_clear_irqs(data); 319 } 320 err: 321 clk_disable(data->clk); 322 mutex_unlock(&data->lock); 323 if (!IS_ERR(data->clk_sec)) 324 clk_disable(data->clk_sec); 325 out: 326 return ret; 327 } 328 329 static u32 get_con_reg(struct exynos_tmu_data *data, u32 con) 330 { 331 if (data->soc == SOC_ARCH_EXYNOS4412 || 332 data->soc == SOC_ARCH_EXYNOS3250) 333 con |= (EXYNOS4412_MUX_ADDR_VALUE << EXYNOS4412_MUX_ADDR_SHIFT); 334 335 con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK << EXYNOS_TMU_REF_VOLTAGE_SHIFT); 336 con |= data->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT; 337 338 con &= ~(EXYNOS_TMU_BUF_SLOPE_SEL_MASK << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT); 339 con |= (data->gain << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT); 340 341 con &= ~(EXYNOS_TMU_TRIP_MODE_MASK << EXYNOS_TMU_TRIP_MODE_SHIFT); 342 con |= (EXYNOS_NOISE_CANCEL_MODE << EXYNOS_TMU_TRIP_MODE_SHIFT); 343 344 return con; 345 } 346 347 static void exynos_tmu_control(struct platform_device *pdev, bool on) 348 { 349 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 350 351 mutex_lock(&data->lock); 352 clk_enable(data->clk); 353 data->tmu_control(pdev, on); 354 data->enabled = on; 355 clk_disable(data->clk); 356 mutex_unlock(&data->lock); 357 } 358 359 static void exynos4210_tmu_set_trip_temp(struct exynos_tmu_data *data, 360 int trip, u8 temp) 361 { 362 const struct thermal_trip * const trips = 363 of_thermal_get_trip_points(data->tzd); 364 u8 ref, th_code; 365 366 ref = trips[0].temperature / MCELSIUS; 367 368 if (trip == 0) { 369 th_code = temp_to_code(data, ref); 370 writeb(th_code, data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP); 371 } 372 373 temp -= ref; 374 writeb(temp, data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL0 + trip * 4); 375 } 376 377 /* failing thresholds are not supported on Exynos4210 */ 378 static void exynos4210_tmu_set_trip_hyst(struct exynos_tmu_data *data, 379 int trip, u8 temp, u8 hyst) 380 { 381 } 382 383 static void exynos4210_tmu_initialize(struct platform_device *pdev) 384 { 385 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 386 387 sanitize_temp_error(data, readl(data->base + EXYNOS_TMU_REG_TRIMINFO)); 388 } 389 390 static void exynos4412_tmu_set_trip_temp(struct exynos_tmu_data *data, 391 int trip, u8 temp) 392 { 393 u32 th, con; 394 395 th = readl(data->base + EXYNOS_THD_TEMP_RISE); 396 th &= ~(0xff << 8 * trip); 397 th |= temp_to_code(data, temp) << 8 * trip; 398 writel(th, data->base + EXYNOS_THD_TEMP_RISE); 399 400 if (trip == 3) { 401 con = readl(data->base + EXYNOS_TMU_REG_CONTROL); 402 con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT); 403 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 404 } 405 } 406 407 static void exynos4412_tmu_set_trip_hyst(struct exynos_tmu_data *data, 408 int trip, u8 temp, u8 hyst) 409 { 410 u32 th; 411 412 th = readl(data->base + EXYNOS_THD_TEMP_FALL); 413 th &= ~(0xff << 8 * trip); 414 if (hyst) 415 th |= temp_to_code(data, temp - hyst) << 8 * trip; 416 writel(th, data->base + EXYNOS_THD_TEMP_FALL); 417 } 418 419 static void exynos4412_tmu_initialize(struct platform_device *pdev) 420 { 421 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 422 unsigned int trim_info, ctrl; 423 424 if (data->soc == SOC_ARCH_EXYNOS3250 || 425 data->soc == SOC_ARCH_EXYNOS4412 || 426 data->soc == SOC_ARCH_EXYNOS5250) { 427 if (data->soc == SOC_ARCH_EXYNOS3250) { 428 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON1); 429 ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE; 430 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON1); 431 } 432 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON2); 433 ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE; 434 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON2); 435 } 436 437 /* On exynos5420 the triminfo register is in the shared space */ 438 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) 439 trim_info = readl(data->base_second + EXYNOS_TMU_REG_TRIMINFO); 440 else 441 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); 442 443 sanitize_temp_error(data, trim_info); 444 } 445 446 static void exynos5433_tmu_set_trip_temp(struct exynos_tmu_data *data, 447 int trip, u8 temp) 448 { 449 unsigned int reg_off, j; 450 u32 th; 451 452 if (trip > 3) { 453 reg_off = EXYNOS5433_THD_TEMP_RISE7_4; 454 j = trip - 4; 455 } else { 456 reg_off = EXYNOS5433_THD_TEMP_RISE3_0; 457 j = trip; 458 } 459 460 th = readl(data->base + reg_off); 461 th &= ~(0xff << j * 8); 462 th |= (temp_to_code(data, temp) << j * 8); 463 writel(th, data->base + reg_off); 464 } 465 466 static void exynos5433_tmu_set_trip_hyst(struct exynos_tmu_data *data, 467 int trip, u8 temp, u8 hyst) 468 { 469 unsigned int reg_off, j; 470 u32 th; 471 472 if (trip > 3) { 473 reg_off = EXYNOS5433_THD_TEMP_FALL7_4; 474 j = trip - 4; 475 } else { 476 reg_off = EXYNOS5433_THD_TEMP_FALL3_0; 477 j = trip; 478 } 479 480 th = readl(data->base + reg_off); 481 th &= ~(0xff << j * 8); 482 th |= (temp_to_code(data, temp - hyst) << j * 8); 483 writel(th, data->base + reg_off); 484 } 485 486 static void exynos5433_tmu_initialize(struct platform_device *pdev) 487 { 488 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 489 unsigned int trim_info; 490 int sensor_id, cal_type; 491 492 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); 493 sanitize_temp_error(data, trim_info); 494 495 /* Read the temperature sensor id */ 496 sensor_id = (trim_info & EXYNOS5433_TRIMINFO_SENSOR_ID_MASK) 497 >> EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT; 498 dev_info(&pdev->dev, "Temperature sensor ID: 0x%x\n", sensor_id); 499 500 /* Read the calibration mode */ 501 writel(trim_info, data->base + EXYNOS_TMU_REG_TRIMINFO); 502 cal_type = (trim_info & EXYNOS5433_TRIMINFO_CALIB_SEL_MASK) 503 >> EXYNOS5433_TRIMINFO_CALIB_SEL_SHIFT; 504 505 switch (cal_type) { 506 case EXYNOS5433_TRIMINFO_TWO_POINT_TRIMMING: 507 data->cal_type = TYPE_TWO_POINT_TRIMMING; 508 break; 509 case EXYNOS5433_TRIMINFO_ONE_POINT_TRIMMING: 510 default: 511 data->cal_type = TYPE_ONE_POINT_TRIMMING; 512 break; 513 } 514 515 dev_info(&pdev->dev, "Calibration type is %d-point calibration\n", 516 cal_type ? 2 : 1); 517 } 518 519 static void exynos7_tmu_set_trip_temp(struct exynos_tmu_data *data, 520 int trip, u8 temp) 521 { 522 unsigned int reg_off, bit_off; 523 u32 th; 524 525 reg_off = ((7 - trip) / 2) * 4; 526 bit_off = ((8 - trip) % 2); 527 528 th = readl(data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off); 529 th &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off)); 530 th |= temp_to_code(data, temp) << (16 * bit_off); 531 writel(th, data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off); 532 } 533 534 static void exynos7_tmu_set_trip_hyst(struct exynos_tmu_data *data, 535 int trip, u8 temp, u8 hyst) 536 { 537 unsigned int reg_off, bit_off; 538 u32 th; 539 540 reg_off = ((7 - trip) / 2) * 4; 541 bit_off = ((8 - trip) % 2); 542 543 th = readl(data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off); 544 th &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off)); 545 th |= temp_to_code(data, temp - hyst) << (16 * bit_off); 546 writel(th, data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off); 547 } 548 549 static void exynos7_tmu_initialize(struct platform_device *pdev) 550 { 551 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 552 unsigned int trim_info; 553 554 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); 555 sanitize_temp_error(data, trim_info); 556 } 557 558 static void exynos4210_tmu_control(struct platform_device *pdev, bool on) 559 { 560 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 561 struct thermal_zone_device *tz = data->tzd; 562 unsigned int con, interrupt_en = 0, i; 563 564 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); 565 566 if (on) { 567 for (i = 0; i < data->ntrip; i++) { 568 if (!of_thermal_is_trip_valid(tz, i)) 569 continue; 570 571 interrupt_en |= 572 (1 << (EXYNOS_TMU_INTEN_RISE0_SHIFT + i * 4)); 573 } 574 575 if (data->soc != SOC_ARCH_EXYNOS4210) 576 interrupt_en |= 577 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; 578 579 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); 580 } else { 581 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); 582 } 583 584 writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN); 585 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 586 } 587 588 static void exynos5433_tmu_control(struct platform_device *pdev, bool on) 589 { 590 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 591 struct thermal_zone_device *tz = data->tzd; 592 unsigned int con, interrupt_en = 0, pd_det_en, i; 593 594 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); 595 596 if (on) { 597 for (i = 0; i < data->ntrip; i++) { 598 if (!of_thermal_is_trip_valid(tz, i)) 599 continue; 600 601 interrupt_en |= 602 (1 << (EXYNOS7_TMU_INTEN_RISE0_SHIFT + i)); 603 } 604 605 interrupt_en |= 606 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; 607 608 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); 609 } else 610 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); 611 612 pd_det_en = on ? EXYNOS5433_PD_DET_EN : 0; 613 614 writel(pd_det_en, data->base + EXYNOS5433_TMU_PD_DET_EN); 615 writel(interrupt_en, data->base + EXYNOS5433_TMU_REG_INTEN); 616 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 617 } 618 619 static void exynos7_tmu_control(struct platform_device *pdev, bool on) 620 { 621 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 622 struct thermal_zone_device *tz = data->tzd; 623 unsigned int con, interrupt_en = 0, i; 624 625 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); 626 627 if (on) { 628 for (i = 0; i < data->ntrip; i++) { 629 if (!of_thermal_is_trip_valid(tz, i)) 630 continue; 631 632 interrupt_en |= 633 (1 << (EXYNOS7_TMU_INTEN_RISE0_SHIFT + i)); 634 } 635 636 interrupt_en |= 637 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; 638 639 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); 640 con |= (1 << EXYNOS7_PD_DET_EN_SHIFT); 641 } else { 642 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); 643 con &= ~(1 << EXYNOS7_PD_DET_EN_SHIFT); 644 } 645 646 writel(interrupt_en, data->base + EXYNOS7_TMU_REG_INTEN); 647 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 648 } 649 650 static int exynos_get_temp(void *p, int *temp) 651 { 652 struct exynos_tmu_data *data = p; 653 int value, ret = 0; 654 655 if (!data || !data->tmu_read) 656 return -EINVAL; 657 else if (!data->enabled) 658 /* 659 * Called too early, probably 660 * from thermal_zone_of_sensor_register(). 661 */ 662 return -EAGAIN; 663 664 mutex_lock(&data->lock); 665 clk_enable(data->clk); 666 667 value = data->tmu_read(data); 668 if (value < 0) 669 ret = value; 670 else 671 *temp = code_to_temp(data, value) * MCELSIUS; 672 673 clk_disable(data->clk); 674 mutex_unlock(&data->lock); 675 676 return ret; 677 } 678 679 #ifdef CONFIG_THERMAL_EMULATION 680 static u32 get_emul_con_reg(struct exynos_tmu_data *data, unsigned int val, 681 int temp) 682 { 683 if (temp) { 684 temp /= MCELSIUS; 685 686 val &= ~(EXYNOS_EMUL_TIME_MASK << EXYNOS_EMUL_TIME_SHIFT); 687 val |= (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT); 688 if (data->soc == SOC_ARCH_EXYNOS7) { 689 val &= ~(EXYNOS7_EMUL_DATA_MASK << 690 EXYNOS7_EMUL_DATA_SHIFT); 691 val |= (temp_to_code(data, temp) << 692 EXYNOS7_EMUL_DATA_SHIFT) | 693 EXYNOS_EMUL_ENABLE; 694 } else { 695 val &= ~(EXYNOS_EMUL_DATA_MASK << 696 EXYNOS_EMUL_DATA_SHIFT); 697 val |= (temp_to_code(data, temp) << 698 EXYNOS_EMUL_DATA_SHIFT) | 699 EXYNOS_EMUL_ENABLE; 700 } 701 } else { 702 val &= ~EXYNOS_EMUL_ENABLE; 703 } 704 705 return val; 706 } 707 708 static void exynos4412_tmu_set_emulation(struct exynos_tmu_data *data, 709 int temp) 710 { 711 unsigned int val; 712 u32 emul_con; 713 714 if (data->soc == SOC_ARCH_EXYNOS5260) 715 emul_con = EXYNOS5260_EMUL_CON; 716 else if (data->soc == SOC_ARCH_EXYNOS5433) 717 emul_con = EXYNOS5433_TMU_EMUL_CON; 718 else if (data->soc == SOC_ARCH_EXYNOS7) 719 emul_con = EXYNOS7_TMU_REG_EMUL_CON; 720 else 721 emul_con = EXYNOS_EMUL_CON; 722 723 val = readl(data->base + emul_con); 724 val = get_emul_con_reg(data, val, temp); 725 writel(val, data->base + emul_con); 726 } 727 728 static int exynos_tmu_set_emulation(void *drv_data, int temp) 729 { 730 struct exynos_tmu_data *data = drv_data; 731 int ret = -EINVAL; 732 733 if (data->soc == SOC_ARCH_EXYNOS4210) 734 goto out; 735 736 if (temp && temp < MCELSIUS) 737 goto out; 738 739 mutex_lock(&data->lock); 740 clk_enable(data->clk); 741 data->tmu_set_emulation(data, temp); 742 clk_disable(data->clk); 743 mutex_unlock(&data->lock); 744 return 0; 745 out: 746 return ret; 747 } 748 #else 749 #define exynos4412_tmu_set_emulation NULL 750 static int exynos_tmu_set_emulation(void *drv_data, int temp) 751 { return -EINVAL; } 752 #endif /* CONFIG_THERMAL_EMULATION */ 753 754 static int exynos4210_tmu_read(struct exynos_tmu_data *data) 755 { 756 int ret = readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP); 757 758 /* "temp_code" should range between 75 and 175 */ 759 return (ret < 75 || ret > 175) ? -ENODATA : ret; 760 } 761 762 static int exynos4412_tmu_read(struct exynos_tmu_data *data) 763 { 764 return readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP); 765 } 766 767 static int exynos7_tmu_read(struct exynos_tmu_data *data) 768 { 769 return readw(data->base + EXYNOS_TMU_REG_CURRENT_TEMP) & 770 EXYNOS7_TMU_TEMP_MASK; 771 } 772 773 static void exynos_tmu_work(struct work_struct *work) 774 { 775 struct exynos_tmu_data *data = container_of(work, 776 struct exynos_tmu_data, irq_work); 777 778 thermal_zone_device_update(data->tzd, THERMAL_EVENT_UNSPECIFIED); 779 780 mutex_lock(&data->lock); 781 clk_enable(data->clk); 782 783 /* TODO: take action based on particular interrupt */ 784 data->tmu_clear_irqs(data); 785 786 clk_disable(data->clk); 787 mutex_unlock(&data->lock); 788 enable_irq(data->irq); 789 } 790 791 static void exynos4210_tmu_clear_irqs(struct exynos_tmu_data *data) 792 { 793 unsigned int val_irq; 794 u32 tmu_intstat, tmu_intclear; 795 796 if (data->soc == SOC_ARCH_EXYNOS5260) { 797 tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT; 798 tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR; 799 } else if (data->soc == SOC_ARCH_EXYNOS7) { 800 tmu_intstat = EXYNOS7_TMU_REG_INTPEND; 801 tmu_intclear = EXYNOS7_TMU_REG_INTPEND; 802 } else if (data->soc == SOC_ARCH_EXYNOS5433) { 803 tmu_intstat = EXYNOS5433_TMU_REG_INTPEND; 804 tmu_intclear = EXYNOS5433_TMU_REG_INTPEND; 805 } else { 806 tmu_intstat = EXYNOS_TMU_REG_INTSTAT; 807 tmu_intclear = EXYNOS_TMU_REG_INTCLEAR; 808 } 809 810 val_irq = readl(data->base + tmu_intstat); 811 /* 812 * Clear the interrupts. Please note that the documentation for 813 * Exynos3250, Exynos4412, Exynos5250 and Exynos5260 incorrectly 814 * states that INTCLEAR register has a different placing of bits 815 * responsible for FALL IRQs than INTSTAT register. Exynos5420 816 * and Exynos5440 documentation is correct (Exynos4210 doesn't 817 * support FALL IRQs at all). 818 */ 819 writel(val_irq, data->base + tmu_intclear); 820 } 821 822 static irqreturn_t exynos_tmu_irq(int irq, void *id) 823 { 824 struct exynos_tmu_data *data = id; 825 826 disable_irq_nosync(irq); 827 schedule_work(&data->irq_work); 828 829 return IRQ_HANDLED; 830 } 831 832 static const struct of_device_id exynos_tmu_match[] = { 833 { 834 .compatible = "samsung,exynos3250-tmu", 835 .data = (const void *)SOC_ARCH_EXYNOS3250, 836 }, { 837 .compatible = "samsung,exynos4210-tmu", 838 .data = (const void *)SOC_ARCH_EXYNOS4210, 839 }, { 840 .compatible = "samsung,exynos4412-tmu", 841 .data = (const void *)SOC_ARCH_EXYNOS4412, 842 }, { 843 .compatible = "samsung,exynos5250-tmu", 844 .data = (const void *)SOC_ARCH_EXYNOS5250, 845 }, { 846 .compatible = "samsung,exynos5260-tmu", 847 .data = (const void *)SOC_ARCH_EXYNOS5260, 848 }, { 849 .compatible = "samsung,exynos5420-tmu", 850 .data = (const void *)SOC_ARCH_EXYNOS5420, 851 }, { 852 .compatible = "samsung,exynos5420-tmu-ext-triminfo", 853 .data = (const void *)SOC_ARCH_EXYNOS5420_TRIMINFO, 854 }, { 855 .compatible = "samsung,exynos5433-tmu", 856 .data = (const void *)SOC_ARCH_EXYNOS5433, 857 }, { 858 .compatible = "samsung,exynos7-tmu", 859 .data = (const void *)SOC_ARCH_EXYNOS7, 860 }, 861 { }, 862 }; 863 MODULE_DEVICE_TABLE(of, exynos_tmu_match); 864 865 static int exynos_map_dt_data(struct platform_device *pdev) 866 { 867 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 868 struct resource res; 869 870 if (!data || !pdev->dev.of_node) 871 return -ENODEV; 872 873 data->id = of_alias_get_id(pdev->dev.of_node, "tmuctrl"); 874 if (data->id < 0) 875 data->id = 0; 876 877 data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 878 if (data->irq <= 0) { 879 dev_err(&pdev->dev, "failed to get IRQ\n"); 880 return -ENODEV; 881 } 882 883 if (of_address_to_resource(pdev->dev.of_node, 0, &res)) { 884 dev_err(&pdev->dev, "failed to get Resource 0\n"); 885 return -ENODEV; 886 } 887 888 data->base = devm_ioremap(&pdev->dev, res.start, resource_size(&res)); 889 if (!data->base) { 890 dev_err(&pdev->dev, "Failed to ioremap memory\n"); 891 return -EADDRNOTAVAIL; 892 } 893 894 data->soc = (enum soc_type)of_device_get_match_data(&pdev->dev); 895 896 switch (data->soc) { 897 case SOC_ARCH_EXYNOS4210: 898 data->tmu_set_trip_temp = exynos4210_tmu_set_trip_temp; 899 data->tmu_set_trip_hyst = exynos4210_tmu_set_trip_hyst; 900 data->tmu_initialize = exynos4210_tmu_initialize; 901 data->tmu_control = exynos4210_tmu_control; 902 data->tmu_read = exynos4210_tmu_read; 903 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; 904 data->ntrip = 4; 905 data->gain = 15; 906 data->reference_voltage = 7; 907 data->efuse_value = 55; 908 data->min_efuse_value = 40; 909 data->max_efuse_value = 100; 910 break; 911 case SOC_ARCH_EXYNOS3250: 912 case SOC_ARCH_EXYNOS4412: 913 case SOC_ARCH_EXYNOS5250: 914 case SOC_ARCH_EXYNOS5260: 915 case SOC_ARCH_EXYNOS5420: 916 case SOC_ARCH_EXYNOS5420_TRIMINFO: 917 data->tmu_set_trip_temp = exynos4412_tmu_set_trip_temp; 918 data->tmu_set_trip_hyst = exynos4412_tmu_set_trip_hyst; 919 data->tmu_initialize = exynos4412_tmu_initialize; 920 data->tmu_control = exynos4210_tmu_control; 921 data->tmu_read = exynos4412_tmu_read; 922 data->tmu_set_emulation = exynos4412_tmu_set_emulation; 923 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; 924 data->ntrip = 4; 925 data->gain = 8; 926 data->reference_voltage = 16; 927 data->efuse_value = 55; 928 if (data->soc != SOC_ARCH_EXYNOS5420 && 929 data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO) 930 data->min_efuse_value = 40; 931 else 932 data->min_efuse_value = 0; 933 data->max_efuse_value = 100; 934 break; 935 case SOC_ARCH_EXYNOS5433: 936 data->tmu_set_trip_temp = exynos5433_tmu_set_trip_temp; 937 data->tmu_set_trip_hyst = exynos5433_tmu_set_trip_hyst; 938 data->tmu_initialize = exynos5433_tmu_initialize; 939 data->tmu_control = exynos5433_tmu_control; 940 data->tmu_read = exynos4412_tmu_read; 941 data->tmu_set_emulation = exynos4412_tmu_set_emulation; 942 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; 943 data->ntrip = 8; 944 data->gain = 8; 945 if (res.start == EXYNOS5433_G3D_BASE) 946 data->reference_voltage = 23; 947 else 948 data->reference_voltage = 16; 949 data->efuse_value = 75; 950 data->min_efuse_value = 40; 951 data->max_efuse_value = 150; 952 break; 953 case SOC_ARCH_EXYNOS7: 954 data->tmu_set_trip_temp = exynos7_tmu_set_trip_temp; 955 data->tmu_set_trip_hyst = exynos7_tmu_set_trip_hyst; 956 data->tmu_initialize = exynos7_tmu_initialize; 957 data->tmu_control = exynos7_tmu_control; 958 data->tmu_read = exynos7_tmu_read; 959 data->tmu_set_emulation = exynos4412_tmu_set_emulation; 960 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; 961 data->ntrip = 8; 962 data->gain = 9; 963 data->reference_voltage = 17; 964 data->efuse_value = 75; 965 data->min_efuse_value = 15; 966 data->max_efuse_value = 100; 967 break; 968 default: 969 dev_err(&pdev->dev, "Platform not supported\n"); 970 return -EINVAL; 971 } 972 973 data->cal_type = TYPE_ONE_POINT_TRIMMING; 974 975 /* 976 * Check if the TMU shares some registers and then try to map the 977 * memory of common registers. 978 */ 979 if (data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO) 980 return 0; 981 982 if (of_address_to_resource(pdev->dev.of_node, 1, &res)) { 983 dev_err(&pdev->dev, "failed to get Resource 1\n"); 984 return -ENODEV; 985 } 986 987 data->base_second = devm_ioremap(&pdev->dev, res.start, 988 resource_size(&res)); 989 if (!data->base_second) { 990 dev_err(&pdev->dev, "Failed to ioremap memory\n"); 991 return -ENOMEM; 992 } 993 994 return 0; 995 } 996 997 static const struct thermal_zone_of_device_ops exynos_sensor_ops = { 998 .get_temp = exynos_get_temp, 999 .set_emul_temp = exynos_tmu_set_emulation, 1000 }; 1001 1002 static int exynos_tmu_probe(struct platform_device *pdev) 1003 { 1004 struct exynos_tmu_data *data; 1005 int ret; 1006 1007 data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data), 1008 GFP_KERNEL); 1009 if (!data) 1010 return -ENOMEM; 1011 1012 platform_set_drvdata(pdev, data); 1013 mutex_init(&data->lock); 1014 1015 /* 1016 * Try enabling the regulator if found 1017 * TODO: Add regulator as an SOC feature, so that regulator enable 1018 * is a compulsory call. 1019 */ 1020 data->regulator = devm_regulator_get_optional(&pdev->dev, "vtmu"); 1021 if (!IS_ERR(data->regulator)) { 1022 ret = regulator_enable(data->regulator); 1023 if (ret) { 1024 dev_err(&pdev->dev, "failed to enable vtmu\n"); 1025 return ret; 1026 } 1027 } else { 1028 if (PTR_ERR(data->regulator) == -EPROBE_DEFER) 1029 return -EPROBE_DEFER; 1030 dev_info(&pdev->dev, "Regulator node (vtmu) not found\n"); 1031 } 1032 1033 ret = exynos_map_dt_data(pdev); 1034 if (ret) 1035 goto err_sensor; 1036 1037 INIT_WORK(&data->irq_work, exynos_tmu_work); 1038 1039 data->clk = devm_clk_get(&pdev->dev, "tmu_apbif"); 1040 if (IS_ERR(data->clk)) { 1041 dev_err(&pdev->dev, "Failed to get clock\n"); 1042 ret = PTR_ERR(data->clk); 1043 goto err_sensor; 1044 } 1045 1046 data->clk_sec = devm_clk_get(&pdev->dev, "tmu_triminfo_apbif"); 1047 if (IS_ERR(data->clk_sec)) { 1048 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) { 1049 dev_err(&pdev->dev, "Failed to get triminfo clock\n"); 1050 ret = PTR_ERR(data->clk_sec); 1051 goto err_sensor; 1052 } 1053 } else { 1054 ret = clk_prepare(data->clk_sec); 1055 if (ret) { 1056 dev_err(&pdev->dev, "Failed to get clock\n"); 1057 goto err_sensor; 1058 } 1059 } 1060 1061 ret = clk_prepare(data->clk); 1062 if (ret) { 1063 dev_err(&pdev->dev, "Failed to get clock\n"); 1064 goto err_clk_sec; 1065 } 1066 1067 switch (data->soc) { 1068 case SOC_ARCH_EXYNOS5433: 1069 case SOC_ARCH_EXYNOS7: 1070 data->sclk = devm_clk_get(&pdev->dev, "tmu_sclk"); 1071 if (IS_ERR(data->sclk)) { 1072 dev_err(&pdev->dev, "Failed to get sclk\n"); 1073 goto err_clk; 1074 } else { 1075 ret = clk_prepare_enable(data->sclk); 1076 if (ret) { 1077 dev_err(&pdev->dev, "Failed to enable sclk\n"); 1078 goto err_clk; 1079 } 1080 } 1081 break; 1082 default: 1083 break; 1084 } 1085 1086 /* 1087 * data->tzd must be registered before calling exynos_tmu_initialize(), 1088 * requesting irq and calling exynos_tmu_control(). 1089 */ 1090 data->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, data, 1091 &exynos_sensor_ops); 1092 if (IS_ERR(data->tzd)) { 1093 ret = PTR_ERR(data->tzd); 1094 dev_err(&pdev->dev, "Failed to register sensor: %d\n", ret); 1095 goto err_sclk; 1096 } 1097 1098 ret = exynos_tmu_initialize(pdev); 1099 if (ret) { 1100 dev_err(&pdev->dev, "Failed to initialize TMU\n"); 1101 goto err_thermal; 1102 } 1103 1104 ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq, 1105 IRQF_TRIGGER_RISING | IRQF_SHARED, dev_name(&pdev->dev), data); 1106 if (ret) { 1107 dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq); 1108 goto err_thermal; 1109 } 1110 1111 exynos_tmu_control(pdev, true); 1112 return 0; 1113 1114 err_thermal: 1115 thermal_zone_of_sensor_unregister(&pdev->dev, data->tzd); 1116 err_sclk: 1117 clk_disable_unprepare(data->sclk); 1118 err_clk: 1119 clk_unprepare(data->clk); 1120 err_clk_sec: 1121 if (!IS_ERR(data->clk_sec)) 1122 clk_unprepare(data->clk_sec); 1123 err_sensor: 1124 if (!IS_ERR(data->regulator)) 1125 regulator_disable(data->regulator); 1126 1127 return ret; 1128 } 1129 1130 static int exynos_tmu_remove(struct platform_device *pdev) 1131 { 1132 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 1133 struct thermal_zone_device *tzd = data->tzd; 1134 1135 thermal_zone_of_sensor_unregister(&pdev->dev, tzd); 1136 exynos_tmu_control(pdev, false); 1137 1138 clk_disable_unprepare(data->sclk); 1139 clk_unprepare(data->clk); 1140 if (!IS_ERR(data->clk_sec)) 1141 clk_unprepare(data->clk_sec); 1142 1143 if (!IS_ERR(data->regulator)) 1144 regulator_disable(data->regulator); 1145 1146 return 0; 1147 } 1148 1149 #ifdef CONFIG_PM_SLEEP 1150 static int exynos_tmu_suspend(struct device *dev) 1151 { 1152 exynos_tmu_control(to_platform_device(dev), false); 1153 1154 return 0; 1155 } 1156 1157 static int exynos_tmu_resume(struct device *dev) 1158 { 1159 struct platform_device *pdev = to_platform_device(dev); 1160 1161 exynos_tmu_initialize(pdev); 1162 exynos_tmu_control(pdev, true); 1163 1164 return 0; 1165 } 1166 1167 static SIMPLE_DEV_PM_OPS(exynos_tmu_pm, 1168 exynos_tmu_suspend, exynos_tmu_resume); 1169 #define EXYNOS_TMU_PM (&exynos_tmu_pm) 1170 #else 1171 #define EXYNOS_TMU_PM NULL 1172 #endif 1173 1174 static struct platform_driver exynos_tmu_driver = { 1175 .driver = { 1176 .name = "exynos-tmu", 1177 .pm = EXYNOS_TMU_PM, 1178 .of_match_table = exynos_tmu_match, 1179 }, 1180 .probe = exynos_tmu_probe, 1181 .remove = exynos_tmu_remove, 1182 }; 1183 1184 module_platform_driver(exynos_tmu_driver); 1185 1186 MODULE_DESCRIPTION("EXYNOS TMU Driver"); 1187 MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>"); 1188 MODULE_LICENSE("GPL"); 1189 MODULE_ALIAS("platform:exynos-tmu"); 1190