1 /* 2 * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit) 3 * 4 * Copyright (C) 2014 Samsung Electronics 5 * Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> 6 * Lukasz Majewski <l.majewski@samsung.com> 7 * 8 * Copyright (C) 2011 Samsung Electronics 9 * Donggeun Kim <dg77.kim@samsung.com> 10 * Amit Daniel Kachhap <amit.kachhap@linaro.org> 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 * 26 */ 27 28 #include <linux/clk.h> 29 #include <linux/io.h> 30 #include <linux/interrupt.h> 31 #include <linux/module.h> 32 #include <linux/of_device.h> 33 #include <linux/of_address.h> 34 #include <linux/of_irq.h> 35 #include <linux/platform_device.h> 36 #include <linux/regulator/consumer.h> 37 38 #include <dt-bindings/thermal/thermal_exynos.h> 39 40 #include "../thermal_core.h" 41 42 /* Exynos generic registers */ 43 #define EXYNOS_TMU_REG_TRIMINFO 0x0 44 #define EXYNOS_TMU_REG_CONTROL 0x20 45 #define EXYNOS_TMU_REG_STATUS 0x28 46 #define EXYNOS_TMU_REG_CURRENT_TEMP 0x40 47 #define EXYNOS_TMU_REG_INTEN 0x70 48 #define EXYNOS_TMU_REG_INTSTAT 0x74 49 #define EXYNOS_TMU_REG_INTCLEAR 0x78 50 51 #define EXYNOS_TMU_TEMP_MASK 0xff 52 #define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24 53 #define EXYNOS_TMU_REF_VOLTAGE_MASK 0x1f 54 #define EXYNOS_TMU_BUF_SLOPE_SEL_MASK 0xf 55 #define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT 8 56 #define EXYNOS_TMU_CORE_EN_SHIFT 0 57 58 /* Exynos3250 specific registers */ 59 #define EXYNOS_TMU_TRIMINFO_CON1 0x10 60 61 /* Exynos4210 specific registers */ 62 #define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44 63 #define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50 64 65 /* Exynos5250, Exynos4412, Exynos3250 specific registers */ 66 #define EXYNOS_TMU_TRIMINFO_CON2 0x14 67 #define EXYNOS_THD_TEMP_RISE 0x50 68 #define EXYNOS_THD_TEMP_FALL 0x54 69 #define EXYNOS_EMUL_CON 0x80 70 71 #define EXYNOS_TRIMINFO_RELOAD_ENABLE 1 72 #define EXYNOS_TRIMINFO_25_SHIFT 0 73 #define EXYNOS_TRIMINFO_85_SHIFT 8 74 #define EXYNOS_TMU_TRIP_MODE_SHIFT 13 75 #define EXYNOS_TMU_TRIP_MODE_MASK 0x7 76 #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12 77 78 #define EXYNOS_TMU_INTEN_RISE0_SHIFT 0 79 #define EXYNOS_TMU_INTEN_RISE1_SHIFT 4 80 #define EXYNOS_TMU_INTEN_RISE2_SHIFT 8 81 #define EXYNOS_TMU_INTEN_RISE3_SHIFT 12 82 #define EXYNOS_TMU_INTEN_FALL0_SHIFT 16 83 84 #define EXYNOS_EMUL_TIME 0x57F0 85 #define EXYNOS_EMUL_TIME_MASK 0xffff 86 #define EXYNOS_EMUL_TIME_SHIFT 16 87 #define EXYNOS_EMUL_DATA_SHIFT 8 88 #define EXYNOS_EMUL_DATA_MASK 0xFF 89 #define EXYNOS_EMUL_ENABLE 0x1 90 91 /* Exynos5260 specific */ 92 #define EXYNOS5260_TMU_REG_INTEN 0xC0 93 #define EXYNOS5260_TMU_REG_INTSTAT 0xC4 94 #define EXYNOS5260_TMU_REG_INTCLEAR 0xC8 95 #define EXYNOS5260_EMUL_CON 0x100 96 97 /* Exynos4412 specific */ 98 #define EXYNOS4412_MUX_ADDR_VALUE 6 99 #define EXYNOS4412_MUX_ADDR_SHIFT 20 100 101 /* Exynos5433 specific registers */ 102 #define EXYNOS5433_TMU_REG_CONTROL1 0x024 103 #define EXYNOS5433_TMU_SAMPLING_INTERVAL 0x02c 104 #define EXYNOS5433_TMU_COUNTER_VALUE0 0x030 105 #define EXYNOS5433_TMU_COUNTER_VALUE1 0x034 106 #define EXYNOS5433_TMU_REG_CURRENT_TEMP1 0x044 107 #define EXYNOS5433_THD_TEMP_RISE3_0 0x050 108 #define EXYNOS5433_THD_TEMP_RISE7_4 0x054 109 #define EXYNOS5433_THD_TEMP_FALL3_0 0x060 110 #define EXYNOS5433_THD_TEMP_FALL7_4 0x064 111 #define EXYNOS5433_TMU_REG_INTEN 0x0c0 112 #define EXYNOS5433_TMU_REG_INTPEND 0x0c8 113 #define EXYNOS5433_TMU_EMUL_CON 0x110 114 #define EXYNOS5433_TMU_PD_DET_EN 0x130 115 116 #define EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT 16 117 #define EXYNOS5433_TRIMINFO_CALIB_SEL_SHIFT 23 118 #define EXYNOS5433_TRIMINFO_SENSOR_ID_MASK \ 119 (0xf << EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT) 120 #define EXYNOS5433_TRIMINFO_CALIB_SEL_MASK BIT(23) 121 122 #define EXYNOS5433_TRIMINFO_ONE_POINT_TRIMMING 0 123 #define EXYNOS5433_TRIMINFO_TWO_POINT_TRIMMING 1 124 125 #define EXYNOS5433_PD_DET_EN 1 126 127 #define EXYNOS5433_G3D_BASE 0x10070000 128 129 /* Exynos7 specific registers */ 130 #define EXYNOS7_THD_TEMP_RISE7_6 0x50 131 #define EXYNOS7_THD_TEMP_FALL7_6 0x60 132 #define EXYNOS7_TMU_REG_INTEN 0x110 133 #define EXYNOS7_TMU_REG_INTPEND 0x118 134 #define EXYNOS7_TMU_REG_EMUL_CON 0x160 135 136 #define EXYNOS7_TMU_TEMP_MASK 0x1ff 137 #define EXYNOS7_PD_DET_EN_SHIFT 23 138 #define EXYNOS7_TMU_INTEN_RISE0_SHIFT 0 139 #define EXYNOS7_TMU_INTEN_RISE1_SHIFT 1 140 #define EXYNOS7_TMU_INTEN_RISE2_SHIFT 2 141 #define EXYNOS7_TMU_INTEN_RISE3_SHIFT 3 142 #define EXYNOS7_TMU_INTEN_RISE4_SHIFT 4 143 #define EXYNOS7_TMU_INTEN_RISE5_SHIFT 5 144 #define EXYNOS7_TMU_INTEN_RISE6_SHIFT 6 145 #define EXYNOS7_TMU_INTEN_RISE7_SHIFT 7 146 #define EXYNOS7_EMUL_DATA_SHIFT 7 147 #define EXYNOS7_EMUL_DATA_MASK 0x1ff 148 149 #define EXYNOS_FIRST_POINT_TRIM 25 150 #define EXYNOS_SECOND_POINT_TRIM 85 151 152 #define EXYNOS_NOISE_CANCEL_MODE 4 153 154 #define MCELSIUS 1000 155 156 enum soc_type { 157 SOC_ARCH_EXYNOS3250 = 1, 158 SOC_ARCH_EXYNOS4210, 159 SOC_ARCH_EXYNOS4412, 160 SOC_ARCH_EXYNOS5250, 161 SOC_ARCH_EXYNOS5260, 162 SOC_ARCH_EXYNOS5420, 163 SOC_ARCH_EXYNOS5420_TRIMINFO, 164 SOC_ARCH_EXYNOS5433, 165 SOC_ARCH_EXYNOS7, 166 }; 167 168 /** 169 * struct exynos_tmu_data : A structure to hold the private data of the TMU 170 driver 171 * @id: identifier of the one instance of the TMU controller. 172 * @base: base address of the single instance of the TMU controller. 173 * @base_second: base address of the common registers of the TMU controller. 174 * @irq: irq number of the TMU controller. 175 * @soc: id of the SOC type. 176 * @irq_work: pointer to the irq work structure. 177 * @lock: lock to implement synchronization. 178 * @clk: pointer to the clock structure. 179 * @clk_sec: pointer to the clock structure for accessing the base_second. 180 * @sclk: pointer to the clock structure for accessing the tmu special clk. 181 * @cal_type: calibration type for temperature 182 * @efuse_value: SoC defined fuse value 183 * @min_efuse_value: minimum valid trimming data 184 * @max_efuse_value: maximum valid trimming data 185 * @temp_error1: fused value of the first point trim. 186 * @temp_error2: fused value of the second point trim. 187 * @gain: gain of amplifier in the positive-TC generator block 188 * 0 < gain <= 15 189 * @reference_voltage: reference voltage of amplifier 190 * in the positive-TC generator block 191 * 0 < reference_voltage <= 31 192 * @regulator: pointer to the TMU regulator structure. 193 * @reg_conf: pointer to structure to register with core thermal. 194 * @ntrip: number of supported trip points. 195 * @enabled: current status of TMU device 196 * @tmu_initialize: SoC specific TMU initialization method 197 * @tmu_control: SoC specific TMU control method 198 * @tmu_read: SoC specific TMU temperature read method 199 * @tmu_set_emulation: SoC specific TMU emulation setting method 200 * @tmu_clear_irqs: SoC specific TMU interrupts clearing method 201 */ 202 struct exynos_tmu_data { 203 int id; 204 void __iomem *base; 205 void __iomem *base_second; 206 int irq; 207 enum soc_type soc; 208 struct work_struct irq_work; 209 struct mutex lock; 210 struct clk *clk, *clk_sec, *sclk; 211 u32 cal_type; 212 u32 efuse_value; 213 u32 min_efuse_value; 214 u32 max_efuse_value; 215 u16 temp_error1, temp_error2; 216 u8 gain; 217 u8 reference_voltage; 218 struct regulator *regulator; 219 struct thermal_zone_device *tzd; 220 unsigned int ntrip; 221 bool enabled; 222 223 void (*tmu_set_trip_temp)(struct exynos_tmu_data *data, int trip, 224 u8 temp); 225 void (*tmu_set_trip_hyst)(struct exynos_tmu_data *data, int trip, 226 u8 temp, u8 hyst); 227 void (*tmu_initialize)(struct platform_device *pdev); 228 void (*tmu_control)(struct platform_device *pdev, bool on); 229 int (*tmu_read)(struct exynos_tmu_data *data); 230 void (*tmu_set_emulation)(struct exynos_tmu_data *data, int temp); 231 void (*tmu_clear_irqs)(struct exynos_tmu_data *data); 232 }; 233 234 static void exynos_report_trigger(struct exynos_tmu_data *p) 235 { 236 char data[10], *envp[] = { data, NULL }; 237 struct thermal_zone_device *tz = p->tzd; 238 int temp; 239 unsigned int i; 240 241 if (!tz) { 242 pr_err("No thermal zone device defined\n"); 243 return; 244 } 245 246 thermal_zone_device_update(tz, THERMAL_EVENT_UNSPECIFIED); 247 248 mutex_lock(&tz->lock); 249 /* Find the level for which trip happened */ 250 for (i = 0; i < of_thermal_get_ntrips(tz); i++) { 251 tz->ops->get_trip_temp(tz, i, &temp); 252 if (tz->last_temperature < temp) 253 break; 254 } 255 256 snprintf(data, sizeof(data), "%u", i); 257 kobject_uevent_env(&tz->device.kobj, KOBJ_CHANGE, envp); 258 mutex_unlock(&tz->lock); 259 } 260 261 /* 262 * TMU treats temperature as a mapped temperature code. 263 * The temperature is converted differently depending on the calibration type. 264 */ 265 static int temp_to_code(struct exynos_tmu_data *data, u8 temp) 266 { 267 if (data->cal_type == TYPE_ONE_POINT_TRIMMING) 268 return temp + data->temp_error1 - EXYNOS_FIRST_POINT_TRIM; 269 270 return (temp - EXYNOS_FIRST_POINT_TRIM) * 271 (data->temp_error2 - data->temp_error1) / 272 (EXYNOS_SECOND_POINT_TRIM - EXYNOS_FIRST_POINT_TRIM) + 273 data->temp_error1; 274 } 275 276 /* 277 * Calculate a temperature value from a temperature code. 278 * The unit of the temperature is degree Celsius. 279 */ 280 static int code_to_temp(struct exynos_tmu_data *data, u16 temp_code) 281 { 282 if (data->cal_type == TYPE_ONE_POINT_TRIMMING) 283 return temp_code - data->temp_error1 + EXYNOS_FIRST_POINT_TRIM; 284 285 return (temp_code - data->temp_error1) * 286 (EXYNOS_SECOND_POINT_TRIM - EXYNOS_FIRST_POINT_TRIM) / 287 (data->temp_error2 - data->temp_error1) + 288 EXYNOS_FIRST_POINT_TRIM; 289 } 290 291 static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_info) 292 { 293 u16 tmu_temp_mask = 294 (data->soc == SOC_ARCH_EXYNOS7) ? EXYNOS7_TMU_TEMP_MASK 295 : EXYNOS_TMU_TEMP_MASK; 296 297 data->temp_error1 = trim_info & tmu_temp_mask; 298 data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) & 299 EXYNOS_TMU_TEMP_MASK); 300 301 if (!data->temp_error1 || 302 (data->min_efuse_value > data->temp_error1) || 303 (data->temp_error1 > data->max_efuse_value)) 304 data->temp_error1 = data->efuse_value & EXYNOS_TMU_TEMP_MASK; 305 306 if (!data->temp_error2) 307 data->temp_error2 = 308 (data->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) & 309 EXYNOS_TMU_TEMP_MASK; 310 } 311 312 static int exynos_tmu_initialize(struct platform_device *pdev) 313 { 314 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 315 struct thermal_zone_device *tzd = data->tzd; 316 const struct thermal_trip * const trips = 317 of_thermal_get_trip_points(tzd); 318 unsigned int status; 319 int ret = 0, temp, hyst; 320 321 if (!trips) { 322 dev_err(&pdev->dev, 323 "Cannot get trip points from device tree!\n"); 324 return -ENODEV; 325 } 326 327 if (data->soc != SOC_ARCH_EXYNOS5433) /* FIXME */ 328 ret = tzd->ops->get_crit_temp(tzd, &temp); 329 if (ret) { 330 dev_err(&pdev->dev, 331 "No CRITICAL trip point defined in device tree!\n"); 332 goto out; 333 } 334 335 if (of_thermal_get_ntrips(tzd) > data->ntrip) { 336 dev_info(&pdev->dev, 337 "More trip points than supported by this TMU.\n"); 338 dev_info(&pdev->dev, 339 "%d trip points should be configured in polling mode.\n", 340 (of_thermal_get_ntrips(tzd) - data->ntrip)); 341 } 342 343 mutex_lock(&data->lock); 344 clk_enable(data->clk); 345 if (!IS_ERR(data->clk_sec)) 346 clk_enable(data->clk_sec); 347 348 status = readb(data->base + EXYNOS_TMU_REG_STATUS); 349 if (!status) { 350 ret = -EBUSY; 351 } else { 352 int i, ntrips = 353 min_t(int, of_thermal_get_ntrips(tzd), data->ntrip); 354 355 data->tmu_initialize(pdev); 356 357 /* Write temperature code for rising and falling threshold */ 358 for (i = 0; i < ntrips; i++) { 359 /* Write temperature code for rising threshold */ 360 ret = tzd->ops->get_trip_temp(tzd, i, &temp); 361 if (ret) 362 goto err; 363 temp /= MCELSIUS; 364 data->tmu_set_trip_temp(data, i, temp); 365 366 /* Write temperature code for falling threshold */ 367 ret = tzd->ops->get_trip_hyst(tzd, i, &hyst); 368 if (ret) 369 goto err; 370 hyst /= MCELSIUS; 371 data->tmu_set_trip_hyst(data, i, temp, hyst); 372 } 373 374 data->tmu_clear_irqs(data); 375 } 376 err: 377 clk_disable(data->clk); 378 mutex_unlock(&data->lock); 379 if (!IS_ERR(data->clk_sec)) 380 clk_disable(data->clk_sec); 381 out: 382 return ret; 383 } 384 385 static u32 get_con_reg(struct exynos_tmu_data *data, u32 con) 386 { 387 if (data->soc == SOC_ARCH_EXYNOS4412 || 388 data->soc == SOC_ARCH_EXYNOS3250) 389 con |= (EXYNOS4412_MUX_ADDR_VALUE << EXYNOS4412_MUX_ADDR_SHIFT); 390 391 con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK << EXYNOS_TMU_REF_VOLTAGE_SHIFT); 392 con |= data->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT; 393 394 con &= ~(EXYNOS_TMU_BUF_SLOPE_SEL_MASK << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT); 395 con |= (data->gain << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT); 396 397 con &= ~(EXYNOS_TMU_TRIP_MODE_MASK << EXYNOS_TMU_TRIP_MODE_SHIFT); 398 con |= (EXYNOS_NOISE_CANCEL_MODE << EXYNOS_TMU_TRIP_MODE_SHIFT); 399 400 return con; 401 } 402 403 static void exynos_tmu_control(struct platform_device *pdev, bool on) 404 { 405 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 406 407 mutex_lock(&data->lock); 408 clk_enable(data->clk); 409 data->tmu_control(pdev, on); 410 data->enabled = on; 411 clk_disable(data->clk); 412 mutex_unlock(&data->lock); 413 } 414 415 static void exynos4210_tmu_set_trip_temp(struct exynos_tmu_data *data, 416 int trip, u8 temp) 417 { 418 const struct thermal_trip * const trips = 419 of_thermal_get_trip_points(data->tzd); 420 u8 ref, th_code; 421 422 ref = trips[0].temperature / MCELSIUS; 423 424 if (trip == 0) { 425 th_code = temp_to_code(data, ref); 426 writeb(th_code, data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP); 427 } 428 429 temp -= ref; 430 writeb(temp, data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL0 + trip * 4); 431 } 432 433 /* failing thresholds are not supported on Exynos4210 */ 434 static void exynos4210_tmu_set_trip_hyst(struct exynos_tmu_data *data, 435 int trip, u8 temp, u8 hyst) 436 { 437 } 438 439 static void exynos4210_tmu_initialize(struct platform_device *pdev) 440 { 441 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 442 443 sanitize_temp_error(data, readl(data->base + EXYNOS_TMU_REG_TRIMINFO)); 444 } 445 446 static void exynos4412_tmu_set_trip_temp(struct exynos_tmu_data *data, 447 int trip, u8 temp) 448 { 449 u32 th, con; 450 451 th = readl(data->base + EXYNOS_THD_TEMP_RISE); 452 th &= ~(0xff << 8 * trip); 453 th |= temp_to_code(data, temp) << 8 * trip; 454 writel(th, data->base + EXYNOS_THD_TEMP_RISE); 455 456 if (trip == 3) { 457 con = readl(data->base + EXYNOS_TMU_REG_CONTROL); 458 con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT); 459 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 460 } 461 } 462 463 static void exynos4412_tmu_set_trip_hyst(struct exynos_tmu_data *data, 464 int trip, u8 temp, u8 hyst) 465 { 466 u32 th; 467 468 th = readl(data->base + EXYNOS_THD_TEMP_FALL); 469 th &= ~(0xff << 8 * trip); 470 if (hyst) 471 th |= temp_to_code(data, temp - hyst) << 8 * trip; 472 writel(th, data->base + EXYNOS_THD_TEMP_FALL); 473 } 474 475 static void exynos4412_tmu_initialize(struct platform_device *pdev) 476 { 477 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 478 unsigned int trim_info, ctrl; 479 480 if (data->soc == SOC_ARCH_EXYNOS3250 || 481 data->soc == SOC_ARCH_EXYNOS4412 || 482 data->soc == SOC_ARCH_EXYNOS5250) { 483 if (data->soc == SOC_ARCH_EXYNOS3250) { 484 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON1); 485 ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE; 486 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON1); 487 } 488 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON2); 489 ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE; 490 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON2); 491 } 492 493 /* On exynos5420 the triminfo register is in the shared space */ 494 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) 495 trim_info = readl(data->base_second + EXYNOS_TMU_REG_TRIMINFO); 496 else 497 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); 498 499 sanitize_temp_error(data, trim_info); 500 } 501 502 static void exynos5433_tmu_set_trip_temp(struct exynos_tmu_data *data, 503 int trip, u8 temp) 504 { 505 unsigned int reg_off, j; 506 u32 th; 507 508 if (trip > 3) { 509 reg_off = EXYNOS5433_THD_TEMP_RISE7_4; 510 j = trip - 4; 511 } else { 512 reg_off = EXYNOS5433_THD_TEMP_RISE3_0; 513 j = trip; 514 } 515 516 th = readl(data->base + reg_off); 517 th &= ~(0xff << j * 8); 518 th |= (temp_to_code(data, temp) << j * 8); 519 writel(th, data->base + reg_off); 520 } 521 522 static void exynos5433_tmu_set_trip_hyst(struct exynos_tmu_data *data, 523 int trip, u8 temp, u8 hyst) 524 { 525 unsigned int reg_off, j; 526 u32 th; 527 528 if (trip > 3) { 529 reg_off = EXYNOS5433_THD_TEMP_FALL7_4; 530 j = trip - 4; 531 } else { 532 reg_off = EXYNOS5433_THD_TEMP_FALL3_0; 533 j = trip; 534 } 535 536 th = readl(data->base + reg_off); 537 th &= ~(0xff << j * 8); 538 th |= (temp_to_code(data, temp - hyst) << j * 8); 539 writel(th, data->base + reg_off); 540 } 541 542 static void exynos5433_tmu_initialize(struct platform_device *pdev) 543 { 544 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 545 unsigned int trim_info; 546 int sensor_id, cal_type; 547 548 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); 549 sanitize_temp_error(data, trim_info); 550 551 /* Read the temperature sensor id */ 552 sensor_id = (trim_info & EXYNOS5433_TRIMINFO_SENSOR_ID_MASK) 553 >> EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT; 554 dev_info(&pdev->dev, "Temperature sensor ID: 0x%x\n", sensor_id); 555 556 /* Read the calibration mode */ 557 writel(trim_info, data->base + EXYNOS_TMU_REG_TRIMINFO); 558 cal_type = (trim_info & EXYNOS5433_TRIMINFO_CALIB_SEL_MASK) 559 >> EXYNOS5433_TRIMINFO_CALIB_SEL_SHIFT; 560 561 switch (cal_type) { 562 case EXYNOS5433_TRIMINFO_TWO_POINT_TRIMMING: 563 data->cal_type = TYPE_TWO_POINT_TRIMMING; 564 break; 565 case EXYNOS5433_TRIMINFO_ONE_POINT_TRIMMING: 566 default: 567 data->cal_type = TYPE_ONE_POINT_TRIMMING; 568 break; 569 } 570 571 dev_info(&pdev->dev, "Calibration type is %d-point calibration\n", 572 cal_type ? 2 : 1); 573 } 574 575 static void exynos7_tmu_set_trip_temp(struct exynos_tmu_data *data, 576 int trip, u8 temp) 577 { 578 unsigned int reg_off, bit_off; 579 u32 th; 580 581 reg_off = ((7 - trip) / 2) * 4; 582 bit_off = ((8 - trip) % 2); 583 584 th = readl(data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off); 585 th &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off)); 586 th |= temp_to_code(data, temp) << (16 * bit_off); 587 writel(th, data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off); 588 } 589 590 static void exynos7_tmu_set_trip_hyst(struct exynos_tmu_data *data, 591 int trip, u8 temp, u8 hyst) 592 { 593 unsigned int reg_off, bit_off; 594 u32 th; 595 596 reg_off = ((7 - trip) / 2) * 4; 597 bit_off = ((8 - trip) % 2); 598 599 th = readl(data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off); 600 th &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off)); 601 th |= temp_to_code(data, temp - hyst) << (16 * bit_off); 602 writel(th, data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off); 603 } 604 605 static void exynos7_tmu_initialize(struct platform_device *pdev) 606 { 607 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 608 unsigned int trim_info; 609 610 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); 611 sanitize_temp_error(data, trim_info); 612 } 613 614 static void exynos4210_tmu_control(struct platform_device *pdev, bool on) 615 { 616 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 617 struct thermal_zone_device *tz = data->tzd; 618 unsigned int con, interrupt_en; 619 620 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); 621 622 if (on) { 623 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); 624 interrupt_en = 625 (of_thermal_is_trip_valid(tz, 3) 626 << EXYNOS_TMU_INTEN_RISE3_SHIFT) | 627 (of_thermal_is_trip_valid(tz, 2) 628 << EXYNOS_TMU_INTEN_RISE2_SHIFT) | 629 (of_thermal_is_trip_valid(tz, 1) 630 << EXYNOS_TMU_INTEN_RISE1_SHIFT) | 631 (of_thermal_is_trip_valid(tz, 0) 632 << EXYNOS_TMU_INTEN_RISE0_SHIFT); 633 634 if (data->soc != SOC_ARCH_EXYNOS4210) 635 interrupt_en |= 636 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; 637 } else { 638 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); 639 interrupt_en = 0; /* Disable all interrupts */ 640 } 641 writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN); 642 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 643 } 644 645 static void exynos5433_tmu_control(struct platform_device *pdev, bool on) 646 { 647 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 648 struct thermal_zone_device *tz = data->tzd; 649 unsigned int con, interrupt_en, pd_det_en; 650 651 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); 652 653 if (on) { 654 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); 655 interrupt_en = 656 (of_thermal_is_trip_valid(tz, 7) 657 << EXYNOS7_TMU_INTEN_RISE7_SHIFT) | 658 (of_thermal_is_trip_valid(tz, 6) 659 << EXYNOS7_TMU_INTEN_RISE6_SHIFT) | 660 (of_thermal_is_trip_valid(tz, 5) 661 << EXYNOS7_TMU_INTEN_RISE5_SHIFT) | 662 (of_thermal_is_trip_valid(tz, 4) 663 << EXYNOS7_TMU_INTEN_RISE4_SHIFT) | 664 (of_thermal_is_trip_valid(tz, 3) 665 << EXYNOS7_TMU_INTEN_RISE3_SHIFT) | 666 (of_thermal_is_trip_valid(tz, 2) 667 << EXYNOS7_TMU_INTEN_RISE2_SHIFT) | 668 (of_thermal_is_trip_valid(tz, 1) 669 << EXYNOS7_TMU_INTEN_RISE1_SHIFT) | 670 (of_thermal_is_trip_valid(tz, 0) 671 << EXYNOS7_TMU_INTEN_RISE0_SHIFT); 672 673 interrupt_en |= 674 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; 675 } else { 676 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); 677 interrupt_en = 0; /* Disable all interrupts */ 678 } 679 680 pd_det_en = on ? EXYNOS5433_PD_DET_EN : 0; 681 682 writel(pd_det_en, data->base + EXYNOS5433_TMU_PD_DET_EN); 683 writel(interrupt_en, data->base + EXYNOS5433_TMU_REG_INTEN); 684 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 685 } 686 687 static void exynos7_tmu_control(struct platform_device *pdev, bool on) 688 { 689 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 690 struct thermal_zone_device *tz = data->tzd; 691 unsigned int con, interrupt_en; 692 693 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); 694 695 if (on) { 696 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); 697 con |= (1 << EXYNOS7_PD_DET_EN_SHIFT); 698 interrupt_en = 699 (of_thermal_is_trip_valid(tz, 7) 700 << EXYNOS7_TMU_INTEN_RISE7_SHIFT) | 701 (of_thermal_is_trip_valid(tz, 6) 702 << EXYNOS7_TMU_INTEN_RISE6_SHIFT) | 703 (of_thermal_is_trip_valid(tz, 5) 704 << EXYNOS7_TMU_INTEN_RISE5_SHIFT) | 705 (of_thermal_is_trip_valid(tz, 4) 706 << EXYNOS7_TMU_INTEN_RISE4_SHIFT) | 707 (of_thermal_is_trip_valid(tz, 3) 708 << EXYNOS7_TMU_INTEN_RISE3_SHIFT) | 709 (of_thermal_is_trip_valid(tz, 2) 710 << EXYNOS7_TMU_INTEN_RISE2_SHIFT) | 711 (of_thermal_is_trip_valid(tz, 1) 712 << EXYNOS7_TMU_INTEN_RISE1_SHIFT) | 713 (of_thermal_is_trip_valid(tz, 0) 714 << EXYNOS7_TMU_INTEN_RISE0_SHIFT); 715 716 interrupt_en |= 717 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; 718 } else { 719 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); 720 con &= ~(1 << EXYNOS7_PD_DET_EN_SHIFT); 721 interrupt_en = 0; /* Disable all interrupts */ 722 } 723 724 writel(interrupt_en, data->base + EXYNOS7_TMU_REG_INTEN); 725 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 726 } 727 728 static int exynos_get_temp(void *p, int *temp) 729 { 730 struct exynos_tmu_data *data = p; 731 int value, ret = 0; 732 733 if (!data || !data->tmu_read || !data->enabled) 734 return -EINVAL; 735 736 mutex_lock(&data->lock); 737 clk_enable(data->clk); 738 739 value = data->tmu_read(data); 740 if (value < 0) 741 ret = value; 742 else 743 *temp = code_to_temp(data, value) * MCELSIUS; 744 745 clk_disable(data->clk); 746 mutex_unlock(&data->lock); 747 748 return ret; 749 } 750 751 #ifdef CONFIG_THERMAL_EMULATION 752 static u32 get_emul_con_reg(struct exynos_tmu_data *data, unsigned int val, 753 int temp) 754 { 755 if (temp) { 756 temp /= MCELSIUS; 757 758 val &= ~(EXYNOS_EMUL_TIME_MASK << EXYNOS_EMUL_TIME_SHIFT); 759 val |= (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT); 760 if (data->soc == SOC_ARCH_EXYNOS7) { 761 val &= ~(EXYNOS7_EMUL_DATA_MASK << 762 EXYNOS7_EMUL_DATA_SHIFT); 763 val |= (temp_to_code(data, temp) << 764 EXYNOS7_EMUL_DATA_SHIFT) | 765 EXYNOS_EMUL_ENABLE; 766 } else { 767 val &= ~(EXYNOS_EMUL_DATA_MASK << 768 EXYNOS_EMUL_DATA_SHIFT); 769 val |= (temp_to_code(data, temp) << 770 EXYNOS_EMUL_DATA_SHIFT) | 771 EXYNOS_EMUL_ENABLE; 772 } 773 } else { 774 val &= ~EXYNOS_EMUL_ENABLE; 775 } 776 777 return val; 778 } 779 780 static void exynos4412_tmu_set_emulation(struct exynos_tmu_data *data, 781 int temp) 782 { 783 unsigned int val; 784 u32 emul_con; 785 786 if (data->soc == SOC_ARCH_EXYNOS5260) 787 emul_con = EXYNOS5260_EMUL_CON; 788 else if (data->soc == SOC_ARCH_EXYNOS5433) 789 emul_con = EXYNOS5433_TMU_EMUL_CON; 790 else if (data->soc == SOC_ARCH_EXYNOS7) 791 emul_con = EXYNOS7_TMU_REG_EMUL_CON; 792 else 793 emul_con = EXYNOS_EMUL_CON; 794 795 val = readl(data->base + emul_con); 796 val = get_emul_con_reg(data, val, temp); 797 writel(val, data->base + emul_con); 798 } 799 800 static int exynos_tmu_set_emulation(void *drv_data, int temp) 801 { 802 struct exynos_tmu_data *data = drv_data; 803 int ret = -EINVAL; 804 805 if (data->soc == SOC_ARCH_EXYNOS4210) 806 goto out; 807 808 if (temp && temp < MCELSIUS) 809 goto out; 810 811 mutex_lock(&data->lock); 812 clk_enable(data->clk); 813 data->tmu_set_emulation(data, temp); 814 clk_disable(data->clk); 815 mutex_unlock(&data->lock); 816 return 0; 817 out: 818 return ret; 819 } 820 #else 821 #define exynos4412_tmu_set_emulation NULL 822 static int exynos_tmu_set_emulation(void *drv_data, int temp) 823 { return -EINVAL; } 824 #endif /* CONFIG_THERMAL_EMULATION */ 825 826 static int exynos4210_tmu_read(struct exynos_tmu_data *data) 827 { 828 int ret = readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP); 829 830 /* "temp_code" should range between 75 and 175 */ 831 return (ret < 75 || ret > 175) ? -ENODATA : ret; 832 } 833 834 static int exynos4412_tmu_read(struct exynos_tmu_data *data) 835 { 836 return readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP); 837 } 838 839 static int exynos7_tmu_read(struct exynos_tmu_data *data) 840 { 841 return readw(data->base + EXYNOS_TMU_REG_CURRENT_TEMP) & 842 EXYNOS7_TMU_TEMP_MASK; 843 } 844 845 static void exynos_tmu_work(struct work_struct *work) 846 { 847 struct exynos_tmu_data *data = container_of(work, 848 struct exynos_tmu_data, irq_work); 849 850 if (!IS_ERR(data->clk_sec)) 851 clk_enable(data->clk_sec); 852 if (!IS_ERR(data->clk_sec)) 853 clk_disable(data->clk_sec); 854 855 exynos_report_trigger(data); 856 mutex_lock(&data->lock); 857 clk_enable(data->clk); 858 859 /* TODO: take action based on particular interrupt */ 860 data->tmu_clear_irqs(data); 861 862 clk_disable(data->clk); 863 mutex_unlock(&data->lock); 864 enable_irq(data->irq); 865 } 866 867 static void exynos4210_tmu_clear_irqs(struct exynos_tmu_data *data) 868 { 869 unsigned int val_irq; 870 u32 tmu_intstat, tmu_intclear; 871 872 if (data->soc == SOC_ARCH_EXYNOS5260) { 873 tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT; 874 tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR; 875 } else if (data->soc == SOC_ARCH_EXYNOS7) { 876 tmu_intstat = EXYNOS7_TMU_REG_INTPEND; 877 tmu_intclear = EXYNOS7_TMU_REG_INTPEND; 878 } else if (data->soc == SOC_ARCH_EXYNOS5433) { 879 tmu_intstat = EXYNOS5433_TMU_REG_INTPEND; 880 tmu_intclear = EXYNOS5433_TMU_REG_INTPEND; 881 } else { 882 tmu_intstat = EXYNOS_TMU_REG_INTSTAT; 883 tmu_intclear = EXYNOS_TMU_REG_INTCLEAR; 884 } 885 886 val_irq = readl(data->base + tmu_intstat); 887 /* 888 * Clear the interrupts. Please note that the documentation for 889 * Exynos3250, Exynos4412, Exynos5250 and Exynos5260 incorrectly 890 * states that INTCLEAR register has a different placing of bits 891 * responsible for FALL IRQs than INTSTAT register. Exynos5420 892 * and Exynos5440 documentation is correct (Exynos4210 doesn't 893 * support FALL IRQs at all). 894 */ 895 writel(val_irq, data->base + tmu_intclear); 896 } 897 898 static irqreturn_t exynos_tmu_irq(int irq, void *id) 899 { 900 struct exynos_tmu_data *data = id; 901 902 disable_irq_nosync(irq); 903 schedule_work(&data->irq_work); 904 905 return IRQ_HANDLED; 906 } 907 908 static const struct of_device_id exynos_tmu_match[] = { 909 { 910 .compatible = "samsung,exynos3250-tmu", 911 .data = (const void *)SOC_ARCH_EXYNOS3250, 912 }, { 913 .compatible = "samsung,exynos4210-tmu", 914 .data = (const void *)SOC_ARCH_EXYNOS4210, 915 }, { 916 .compatible = "samsung,exynos4412-tmu", 917 .data = (const void *)SOC_ARCH_EXYNOS4412, 918 }, { 919 .compatible = "samsung,exynos5250-tmu", 920 .data = (const void *)SOC_ARCH_EXYNOS5250, 921 }, { 922 .compatible = "samsung,exynos5260-tmu", 923 .data = (const void *)SOC_ARCH_EXYNOS5260, 924 }, { 925 .compatible = "samsung,exynos5420-tmu", 926 .data = (const void *)SOC_ARCH_EXYNOS5420, 927 }, { 928 .compatible = "samsung,exynos5420-tmu-ext-triminfo", 929 .data = (const void *)SOC_ARCH_EXYNOS5420_TRIMINFO, 930 }, { 931 .compatible = "samsung,exynos5433-tmu", 932 .data = (const void *)SOC_ARCH_EXYNOS5433, 933 }, { 934 .compatible = "samsung,exynos7-tmu", 935 .data = (const void *)SOC_ARCH_EXYNOS7, 936 }, 937 { }, 938 }; 939 MODULE_DEVICE_TABLE(of, exynos_tmu_match); 940 941 static int exynos_map_dt_data(struct platform_device *pdev) 942 { 943 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 944 struct resource res; 945 946 if (!data || !pdev->dev.of_node) 947 return -ENODEV; 948 949 data->id = of_alias_get_id(pdev->dev.of_node, "tmuctrl"); 950 if (data->id < 0) 951 data->id = 0; 952 953 data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 954 if (data->irq <= 0) { 955 dev_err(&pdev->dev, "failed to get IRQ\n"); 956 return -ENODEV; 957 } 958 959 if (of_address_to_resource(pdev->dev.of_node, 0, &res)) { 960 dev_err(&pdev->dev, "failed to get Resource 0\n"); 961 return -ENODEV; 962 } 963 964 data->base = devm_ioremap(&pdev->dev, res.start, resource_size(&res)); 965 if (!data->base) { 966 dev_err(&pdev->dev, "Failed to ioremap memory\n"); 967 return -EADDRNOTAVAIL; 968 } 969 970 data->soc = (enum soc_type)of_device_get_match_data(&pdev->dev); 971 972 switch (data->soc) { 973 case SOC_ARCH_EXYNOS4210: 974 data->tmu_set_trip_temp = exynos4210_tmu_set_trip_temp; 975 data->tmu_set_trip_hyst = exynos4210_tmu_set_trip_hyst; 976 data->tmu_initialize = exynos4210_tmu_initialize; 977 data->tmu_control = exynos4210_tmu_control; 978 data->tmu_read = exynos4210_tmu_read; 979 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; 980 data->ntrip = 4; 981 data->gain = 15; 982 data->reference_voltage = 7; 983 data->efuse_value = 55; 984 data->min_efuse_value = 40; 985 data->max_efuse_value = 100; 986 break; 987 case SOC_ARCH_EXYNOS3250: 988 case SOC_ARCH_EXYNOS4412: 989 case SOC_ARCH_EXYNOS5250: 990 case SOC_ARCH_EXYNOS5260: 991 case SOC_ARCH_EXYNOS5420: 992 case SOC_ARCH_EXYNOS5420_TRIMINFO: 993 data->tmu_set_trip_temp = exynos4412_tmu_set_trip_temp; 994 data->tmu_set_trip_hyst = exynos4412_tmu_set_trip_hyst; 995 data->tmu_initialize = exynos4412_tmu_initialize; 996 data->tmu_control = exynos4210_tmu_control; 997 data->tmu_read = exynos4412_tmu_read; 998 data->tmu_set_emulation = exynos4412_tmu_set_emulation; 999 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; 1000 data->ntrip = 4; 1001 data->gain = 8; 1002 data->reference_voltage = 16; 1003 data->efuse_value = 55; 1004 if (data->soc != SOC_ARCH_EXYNOS5420 && 1005 data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO) 1006 data->min_efuse_value = 40; 1007 else 1008 data->min_efuse_value = 0; 1009 data->max_efuse_value = 100; 1010 break; 1011 case SOC_ARCH_EXYNOS5433: 1012 data->tmu_set_trip_temp = exynos5433_tmu_set_trip_temp; 1013 data->tmu_set_trip_hyst = exynos5433_tmu_set_trip_hyst; 1014 data->tmu_initialize = exynos5433_tmu_initialize; 1015 data->tmu_control = exynos5433_tmu_control; 1016 data->tmu_read = exynos4412_tmu_read; 1017 data->tmu_set_emulation = exynos4412_tmu_set_emulation; 1018 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; 1019 data->ntrip = 8; 1020 data->gain = 8; 1021 if (res.start == EXYNOS5433_G3D_BASE) 1022 data->reference_voltage = 23; 1023 else 1024 data->reference_voltage = 16; 1025 data->efuse_value = 75; 1026 data->min_efuse_value = 40; 1027 data->max_efuse_value = 150; 1028 break; 1029 case SOC_ARCH_EXYNOS7: 1030 data->tmu_set_trip_temp = exynos7_tmu_set_trip_temp; 1031 data->tmu_set_trip_hyst = exynos7_tmu_set_trip_hyst; 1032 data->tmu_initialize = exynos7_tmu_initialize; 1033 data->tmu_control = exynos7_tmu_control; 1034 data->tmu_read = exynos7_tmu_read; 1035 data->tmu_set_emulation = exynos4412_tmu_set_emulation; 1036 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; 1037 data->ntrip = 8; 1038 data->gain = 9; 1039 data->reference_voltage = 17; 1040 data->efuse_value = 75; 1041 data->min_efuse_value = 15; 1042 data->max_efuse_value = 100; 1043 break; 1044 default: 1045 dev_err(&pdev->dev, "Platform not supported\n"); 1046 return -EINVAL; 1047 } 1048 1049 data->cal_type = TYPE_ONE_POINT_TRIMMING; 1050 1051 /* 1052 * Check if the TMU shares some registers and then try to map the 1053 * memory of common registers. 1054 */ 1055 if (data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO) 1056 return 0; 1057 1058 if (of_address_to_resource(pdev->dev.of_node, 1, &res)) { 1059 dev_err(&pdev->dev, "failed to get Resource 1\n"); 1060 return -ENODEV; 1061 } 1062 1063 data->base_second = devm_ioremap(&pdev->dev, res.start, 1064 resource_size(&res)); 1065 if (!data->base_second) { 1066 dev_err(&pdev->dev, "Failed to ioremap memory\n"); 1067 return -ENOMEM; 1068 } 1069 1070 return 0; 1071 } 1072 1073 static const struct thermal_zone_of_device_ops exynos_sensor_ops = { 1074 .get_temp = exynos_get_temp, 1075 .set_emul_temp = exynos_tmu_set_emulation, 1076 }; 1077 1078 static int exynos_tmu_probe(struct platform_device *pdev) 1079 { 1080 struct exynos_tmu_data *data; 1081 int ret; 1082 1083 data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data), 1084 GFP_KERNEL); 1085 if (!data) 1086 return -ENOMEM; 1087 1088 platform_set_drvdata(pdev, data); 1089 mutex_init(&data->lock); 1090 1091 /* 1092 * Try enabling the regulator if found 1093 * TODO: Add regulator as an SOC feature, so that regulator enable 1094 * is a compulsory call. 1095 */ 1096 data->regulator = devm_regulator_get_optional(&pdev->dev, "vtmu"); 1097 if (!IS_ERR(data->regulator)) { 1098 ret = regulator_enable(data->regulator); 1099 if (ret) { 1100 dev_err(&pdev->dev, "failed to enable vtmu\n"); 1101 return ret; 1102 } 1103 } else { 1104 if (PTR_ERR(data->regulator) == -EPROBE_DEFER) 1105 return -EPROBE_DEFER; 1106 dev_info(&pdev->dev, "Regulator node (vtmu) not found\n"); 1107 } 1108 1109 ret = exynos_map_dt_data(pdev); 1110 if (ret) 1111 goto err_sensor; 1112 1113 INIT_WORK(&data->irq_work, exynos_tmu_work); 1114 1115 data->clk = devm_clk_get(&pdev->dev, "tmu_apbif"); 1116 if (IS_ERR(data->clk)) { 1117 dev_err(&pdev->dev, "Failed to get clock\n"); 1118 ret = PTR_ERR(data->clk); 1119 goto err_sensor; 1120 } 1121 1122 data->clk_sec = devm_clk_get(&pdev->dev, "tmu_triminfo_apbif"); 1123 if (IS_ERR(data->clk_sec)) { 1124 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) { 1125 dev_err(&pdev->dev, "Failed to get triminfo clock\n"); 1126 ret = PTR_ERR(data->clk_sec); 1127 goto err_sensor; 1128 } 1129 } else { 1130 ret = clk_prepare(data->clk_sec); 1131 if (ret) { 1132 dev_err(&pdev->dev, "Failed to get clock\n"); 1133 goto err_sensor; 1134 } 1135 } 1136 1137 ret = clk_prepare(data->clk); 1138 if (ret) { 1139 dev_err(&pdev->dev, "Failed to get clock\n"); 1140 goto err_clk_sec; 1141 } 1142 1143 switch (data->soc) { 1144 case SOC_ARCH_EXYNOS5433: 1145 case SOC_ARCH_EXYNOS7: 1146 data->sclk = devm_clk_get(&pdev->dev, "tmu_sclk"); 1147 if (IS_ERR(data->sclk)) { 1148 dev_err(&pdev->dev, "Failed to get sclk\n"); 1149 goto err_clk; 1150 } else { 1151 ret = clk_prepare_enable(data->sclk); 1152 if (ret) { 1153 dev_err(&pdev->dev, "Failed to enable sclk\n"); 1154 goto err_clk; 1155 } 1156 } 1157 break; 1158 default: 1159 break; 1160 } 1161 1162 /* 1163 * data->tzd must be registered before calling exynos_tmu_initialize(), 1164 * requesting irq and calling exynos_tmu_control(). 1165 */ 1166 data->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, data, 1167 &exynos_sensor_ops); 1168 if (IS_ERR(data->tzd)) { 1169 ret = PTR_ERR(data->tzd); 1170 dev_err(&pdev->dev, "Failed to register sensor: %d\n", ret); 1171 goto err_sclk; 1172 } 1173 1174 ret = exynos_tmu_initialize(pdev); 1175 if (ret) { 1176 dev_err(&pdev->dev, "Failed to initialize TMU\n"); 1177 goto err_thermal; 1178 } 1179 1180 ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq, 1181 IRQF_TRIGGER_RISING | IRQF_SHARED, dev_name(&pdev->dev), data); 1182 if (ret) { 1183 dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq); 1184 goto err_thermal; 1185 } 1186 1187 exynos_tmu_control(pdev, true); 1188 return 0; 1189 1190 err_thermal: 1191 thermal_zone_of_sensor_unregister(&pdev->dev, data->tzd); 1192 err_sclk: 1193 clk_disable_unprepare(data->sclk); 1194 err_clk: 1195 clk_unprepare(data->clk); 1196 err_clk_sec: 1197 if (!IS_ERR(data->clk_sec)) 1198 clk_unprepare(data->clk_sec); 1199 err_sensor: 1200 if (!IS_ERR(data->regulator)) 1201 regulator_disable(data->regulator); 1202 1203 return ret; 1204 } 1205 1206 static int exynos_tmu_remove(struct platform_device *pdev) 1207 { 1208 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 1209 struct thermal_zone_device *tzd = data->tzd; 1210 1211 thermal_zone_of_sensor_unregister(&pdev->dev, tzd); 1212 exynos_tmu_control(pdev, false); 1213 1214 clk_disable_unprepare(data->sclk); 1215 clk_unprepare(data->clk); 1216 if (!IS_ERR(data->clk_sec)) 1217 clk_unprepare(data->clk_sec); 1218 1219 if (!IS_ERR(data->regulator)) 1220 regulator_disable(data->regulator); 1221 1222 return 0; 1223 } 1224 1225 #ifdef CONFIG_PM_SLEEP 1226 static int exynos_tmu_suspend(struct device *dev) 1227 { 1228 exynos_tmu_control(to_platform_device(dev), false); 1229 1230 return 0; 1231 } 1232 1233 static int exynos_tmu_resume(struct device *dev) 1234 { 1235 struct platform_device *pdev = to_platform_device(dev); 1236 1237 exynos_tmu_initialize(pdev); 1238 exynos_tmu_control(pdev, true); 1239 1240 return 0; 1241 } 1242 1243 static SIMPLE_DEV_PM_OPS(exynos_tmu_pm, 1244 exynos_tmu_suspend, exynos_tmu_resume); 1245 #define EXYNOS_TMU_PM (&exynos_tmu_pm) 1246 #else 1247 #define EXYNOS_TMU_PM NULL 1248 #endif 1249 1250 static struct platform_driver exynos_tmu_driver = { 1251 .driver = { 1252 .name = "exynos-tmu", 1253 .pm = EXYNOS_TMU_PM, 1254 .of_match_table = exynos_tmu_match, 1255 }, 1256 .probe = exynos_tmu_probe, 1257 .remove = exynos_tmu_remove, 1258 }; 1259 1260 module_platform_driver(exynos_tmu_driver); 1261 1262 MODULE_DESCRIPTION("EXYNOS TMU Driver"); 1263 MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>"); 1264 MODULE_LICENSE("GPL"); 1265 MODULE_ALIAS("platform:exynos-tmu"); 1266