1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * exynos_tmu.c - Samsung Exynos TMU (Thermal Management Unit) 4 * 5 * Copyright (C) 2014 Samsung Electronics 6 * Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> 7 * Lukasz Majewski <l.majewski@samsung.com> 8 * 9 * Copyright (C) 2011 Samsung Electronics 10 * Donggeun Kim <dg77.kim@samsung.com> 11 * Amit Daniel Kachhap <amit.kachhap@linaro.org> 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/io.h> 16 #include <linux/interrupt.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/of_address.h> 20 #include <linux/of_irq.h> 21 #include <linux/platform_device.h> 22 #include <linux/regulator/consumer.h> 23 #include <linux/thermal.h> 24 25 #include <dt-bindings/thermal/thermal_exynos.h> 26 27 /* Exynos generic registers */ 28 #define EXYNOS_TMU_REG_TRIMINFO 0x0 29 #define EXYNOS_TMU_REG_CONTROL 0x20 30 #define EXYNOS_TMU_REG_STATUS 0x28 31 #define EXYNOS_TMU_REG_CURRENT_TEMP 0x40 32 #define EXYNOS_TMU_REG_INTEN 0x70 33 #define EXYNOS_TMU_REG_INTSTAT 0x74 34 #define EXYNOS_TMU_REG_INTCLEAR 0x78 35 36 #define EXYNOS_TMU_TEMP_MASK 0xff 37 #define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24 38 #define EXYNOS_TMU_REF_VOLTAGE_MASK 0x1f 39 #define EXYNOS_TMU_BUF_SLOPE_SEL_MASK 0xf 40 #define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT 8 41 #define EXYNOS_TMU_CORE_EN_SHIFT 0 42 43 /* Exynos3250 specific registers */ 44 #define EXYNOS_TMU_TRIMINFO_CON1 0x10 45 46 /* Exynos4210 specific registers */ 47 #define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44 48 #define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50 49 50 /* Exynos5250, Exynos4412, Exynos3250 specific registers */ 51 #define EXYNOS_TMU_TRIMINFO_CON2 0x14 52 #define EXYNOS_THD_TEMP_RISE 0x50 53 #define EXYNOS_THD_TEMP_FALL 0x54 54 #define EXYNOS_EMUL_CON 0x80 55 56 #define EXYNOS_TRIMINFO_RELOAD_ENABLE 1 57 #define EXYNOS_TRIMINFO_25_SHIFT 0 58 #define EXYNOS_TRIMINFO_85_SHIFT 8 59 #define EXYNOS_TMU_TRIP_MODE_SHIFT 13 60 #define EXYNOS_TMU_TRIP_MODE_MASK 0x7 61 #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12 62 63 #define EXYNOS_TMU_INTEN_RISE0_SHIFT 0 64 #define EXYNOS_TMU_INTEN_FALL0_SHIFT 16 65 66 #define EXYNOS_EMUL_TIME 0x57F0 67 #define EXYNOS_EMUL_TIME_MASK 0xffff 68 #define EXYNOS_EMUL_TIME_SHIFT 16 69 #define EXYNOS_EMUL_DATA_SHIFT 8 70 #define EXYNOS_EMUL_DATA_MASK 0xFF 71 #define EXYNOS_EMUL_ENABLE 0x1 72 73 /* Exynos5260 specific */ 74 #define EXYNOS5260_TMU_REG_INTEN 0xC0 75 #define EXYNOS5260_TMU_REG_INTSTAT 0xC4 76 #define EXYNOS5260_TMU_REG_INTCLEAR 0xC8 77 #define EXYNOS5260_EMUL_CON 0x100 78 79 /* Exynos4412 specific */ 80 #define EXYNOS4412_MUX_ADDR_VALUE 6 81 #define EXYNOS4412_MUX_ADDR_SHIFT 20 82 83 /* Exynos5433 specific registers */ 84 #define EXYNOS5433_THD_TEMP_RISE3_0 0x050 85 #define EXYNOS5433_THD_TEMP_RISE7_4 0x054 86 #define EXYNOS5433_THD_TEMP_FALL3_0 0x060 87 #define EXYNOS5433_THD_TEMP_FALL7_4 0x064 88 #define EXYNOS5433_TMU_REG_INTEN 0x0c0 89 #define EXYNOS5433_TMU_REG_INTPEND 0x0c8 90 #define EXYNOS5433_TMU_EMUL_CON 0x110 91 #define EXYNOS5433_TMU_PD_DET_EN 0x130 92 93 #define EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT 16 94 #define EXYNOS5433_TRIMINFO_CALIB_SEL_SHIFT 23 95 #define EXYNOS5433_TRIMINFO_SENSOR_ID_MASK \ 96 (0xf << EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT) 97 #define EXYNOS5433_TRIMINFO_CALIB_SEL_MASK BIT(23) 98 99 #define EXYNOS5433_TRIMINFO_ONE_POINT_TRIMMING 0 100 #define EXYNOS5433_TRIMINFO_TWO_POINT_TRIMMING 1 101 102 #define EXYNOS5433_PD_DET_EN 1 103 104 #define EXYNOS5433_G3D_BASE 0x10070000 105 106 /* Exynos7 specific registers */ 107 #define EXYNOS7_THD_TEMP_RISE7_6 0x50 108 #define EXYNOS7_THD_TEMP_FALL7_6 0x60 109 #define EXYNOS7_TMU_REG_INTEN 0x110 110 #define EXYNOS7_TMU_REG_INTPEND 0x118 111 #define EXYNOS7_TMU_REG_EMUL_CON 0x160 112 113 #define EXYNOS7_TMU_TEMP_MASK 0x1ff 114 #define EXYNOS7_PD_DET_EN_SHIFT 23 115 #define EXYNOS7_TMU_INTEN_RISE0_SHIFT 0 116 #define EXYNOS7_EMUL_DATA_SHIFT 7 117 #define EXYNOS7_EMUL_DATA_MASK 0x1ff 118 119 #define EXYNOS_FIRST_POINT_TRIM 25 120 #define EXYNOS_SECOND_POINT_TRIM 85 121 122 #define EXYNOS_NOISE_CANCEL_MODE 4 123 124 #define MCELSIUS 1000 125 126 enum soc_type { 127 SOC_ARCH_EXYNOS3250 = 1, 128 SOC_ARCH_EXYNOS4210, 129 SOC_ARCH_EXYNOS4412, 130 SOC_ARCH_EXYNOS5250, 131 SOC_ARCH_EXYNOS5260, 132 SOC_ARCH_EXYNOS5420, 133 SOC_ARCH_EXYNOS5420_TRIMINFO, 134 SOC_ARCH_EXYNOS5433, 135 SOC_ARCH_EXYNOS7, 136 }; 137 138 /** 139 * struct exynos_tmu_data : A structure to hold the private data of the TMU 140 * driver 141 * @base: base address of the single instance of the TMU controller. 142 * @base_second: base address of the common registers of the TMU controller. 143 * @irq: irq number of the TMU controller. 144 * @soc: id of the SOC type. 145 * @lock: lock to implement synchronization. 146 * @clk: pointer to the clock structure. 147 * @clk_sec: pointer to the clock structure for accessing the base_second. 148 * @sclk: pointer to the clock structure for accessing the tmu special clk. 149 * @cal_type: calibration type for temperature 150 * @efuse_value: SoC defined fuse value 151 * @min_efuse_value: minimum valid trimming data 152 * @max_efuse_value: maximum valid trimming data 153 * @temp_error1: fused value of the first point trim. 154 * @temp_error2: fused value of the second point trim. 155 * @gain: gain of amplifier in the positive-TC generator block 156 * 0 < gain <= 15 157 * @reference_voltage: reference voltage of amplifier 158 * in the positive-TC generator block 159 * 0 < reference_voltage <= 31 160 * @tzd: pointer to thermal_zone_device structure 161 * @ntrip: number of supported trip points. 162 * @enabled: current status of TMU device 163 * @tmu_set_trip_temp: SoC specific method to set trip (rising threshold) 164 * @tmu_set_trip_hyst: SoC specific to set hysteresis (falling threshold) 165 * @tmu_initialize: SoC specific TMU initialization method 166 * @tmu_control: SoC specific TMU control method 167 * @tmu_read: SoC specific TMU temperature read method 168 * @tmu_set_emulation: SoC specific TMU emulation setting method 169 * @tmu_clear_irqs: SoC specific TMU interrupts clearing method 170 */ 171 struct exynos_tmu_data { 172 void __iomem *base; 173 void __iomem *base_second; 174 int irq; 175 enum soc_type soc; 176 struct mutex lock; 177 struct clk *clk, *clk_sec, *sclk; 178 u32 cal_type; 179 u32 efuse_value; 180 u32 min_efuse_value; 181 u32 max_efuse_value; 182 u16 temp_error1, temp_error2; 183 u8 gain; 184 u8 reference_voltage; 185 struct thermal_zone_device *tzd; 186 unsigned int ntrip; 187 bool enabled; 188 189 void (*tmu_set_trip_temp)(struct exynos_tmu_data *data, int trip, 190 u8 temp); 191 void (*tmu_set_trip_hyst)(struct exynos_tmu_data *data, int trip, 192 u8 temp, u8 hyst); 193 void (*tmu_initialize)(struct platform_device *pdev); 194 void (*tmu_control)(struct platform_device *pdev, bool on); 195 int (*tmu_read)(struct exynos_tmu_data *data); 196 void (*tmu_set_emulation)(struct exynos_tmu_data *data, int temp); 197 void (*tmu_clear_irqs)(struct exynos_tmu_data *data); 198 }; 199 200 /* 201 * TMU treats temperature as a mapped temperature code. 202 * The temperature is converted differently depending on the calibration type. 203 */ 204 static int temp_to_code(struct exynos_tmu_data *data, u8 temp) 205 { 206 if (data->cal_type == TYPE_ONE_POINT_TRIMMING) 207 return temp + data->temp_error1 - EXYNOS_FIRST_POINT_TRIM; 208 209 return (temp - EXYNOS_FIRST_POINT_TRIM) * 210 (data->temp_error2 - data->temp_error1) / 211 (EXYNOS_SECOND_POINT_TRIM - EXYNOS_FIRST_POINT_TRIM) + 212 data->temp_error1; 213 } 214 215 /* 216 * Calculate a temperature value from a temperature code. 217 * The unit of the temperature is degree Celsius. 218 */ 219 static int code_to_temp(struct exynos_tmu_data *data, u16 temp_code) 220 { 221 if (data->cal_type == TYPE_ONE_POINT_TRIMMING) 222 return temp_code - data->temp_error1 + EXYNOS_FIRST_POINT_TRIM; 223 224 return (temp_code - data->temp_error1) * 225 (EXYNOS_SECOND_POINT_TRIM - EXYNOS_FIRST_POINT_TRIM) / 226 (data->temp_error2 - data->temp_error1) + 227 EXYNOS_FIRST_POINT_TRIM; 228 } 229 230 static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_info) 231 { 232 u16 tmu_temp_mask = 233 (data->soc == SOC_ARCH_EXYNOS7) ? EXYNOS7_TMU_TEMP_MASK 234 : EXYNOS_TMU_TEMP_MASK; 235 236 data->temp_error1 = trim_info & tmu_temp_mask; 237 data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) & 238 EXYNOS_TMU_TEMP_MASK); 239 240 if (!data->temp_error1 || 241 (data->min_efuse_value > data->temp_error1) || 242 (data->temp_error1 > data->max_efuse_value)) 243 data->temp_error1 = data->efuse_value & EXYNOS_TMU_TEMP_MASK; 244 245 if (!data->temp_error2) 246 data->temp_error2 = 247 (data->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) & 248 EXYNOS_TMU_TEMP_MASK; 249 } 250 251 static int exynos_tmu_initialize(struct platform_device *pdev) 252 { 253 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 254 struct thermal_zone_device *tzd = data->tzd; 255 int num_trips = thermal_zone_get_num_trips(tzd); 256 unsigned int status; 257 int ret = 0, temp; 258 259 ret = thermal_zone_get_crit_temp(tzd, &temp); 260 if (ret && data->soc != SOC_ARCH_EXYNOS5433) { /* FIXME */ 261 dev_err(&pdev->dev, 262 "No CRITICAL trip point defined in device tree!\n"); 263 goto out; 264 } 265 266 if (num_trips > data->ntrip) { 267 dev_info(&pdev->dev, 268 "More trip points than supported by this TMU.\n"); 269 dev_info(&pdev->dev, 270 "%d trip points should be configured in polling mode.\n", 271 num_trips - data->ntrip); 272 } 273 274 mutex_lock(&data->lock); 275 clk_enable(data->clk); 276 if (!IS_ERR(data->clk_sec)) 277 clk_enable(data->clk_sec); 278 279 status = readb(data->base + EXYNOS_TMU_REG_STATUS); 280 if (!status) { 281 ret = -EBUSY; 282 } else { 283 int i, ntrips = 284 min_t(int, num_trips, data->ntrip); 285 286 data->tmu_initialize(pdev); 287 288 /* Write temperature code for rising and falling threshold */ 289 for (i = 0; i < ntrips; i++) { 290 291 struct thermal_trip trip; 292 293 ret = thermal_zone_get_trip(tzd, i, &trip); 294 if (ret) 295 goto err; 296 297 data->tmu_set_trip_temp(data, i, trip.temperature / MCELSIUS); 298 data->tmu_set_trip_hyst(data, i, trip.temperature / MCELSIUS, 299 trip.hysteresis / MCELSIUS); 300 } 301 302 data->tmu_clear_irqs(data); 303 } 304 err: 305 clk_disable(data->clk); 306 mutex_unlock(&data->lock); 307 if (!IS_ERR(data->clk_sec)) 308 clk_disable(data->clk_sec); 309 out: 310 return ret; 311 } 312 313 static u32 get_con_reg(struct exynos_tmu_data *data, u32 con) 314 { 315 if (data->soc == SOC_ARCH_EXYNOS4412 || 316 data->soc == SOC_ARCH_EXYNOS3250) 317 con |= (EXYNOS4412_MUX_ADDR_VALUE << EXYNOS4412_MUX_ADDR_SHIFT); 318 319 con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK << EXYNOS_TMU_REF_VOLTAGE_SHIFT); 320 con |= data->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT; 321 322 con &= ~(EXYNOS_TMU_BUF_SLOPE_SEL_MASK << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT); 323 con |= (data->gain << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT); 324 325 con &= ~(EXYNOS_TMU_TRIP_MODE_MASK << EXYNOS_TMU_TRIP_MODE_SHIFT); 326 con |= (EXYNOS_NOISE_CANCEL_MODE << EXYNOS_TMU_TRIP_MODE_SHIFT); 327 328 return con; 329 } 330 331 static void exynos_tmu_control(struct platform_device *pdev, bool on) 332 { 333 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 334 335 mutex_lock(&data->lock); 336 clk_enable(data->clk); 337 data->tmu_control(pdev, on); 338 data->enabled = on; 339 clk_disable(data->clk); 340 mutex_unlock(&data->lock); 341 } 342 343 static void exynos4210_tmu_set_trip_temp(struct exynos_tmu_data *data, 344 int trip_id, u8 temp) 345 { 346 struct thermal_trip trip; 347 u8 ref, th_code; 348 349 if (thermal_zone_get_trip(data->tzd, 0, &trip)) 350 return; 351 352 ref = trip.temperature / MCELSIUS; 353 354 if (trip_id == 0) { 355 th_code = temp_to_code(data, ref); 356 writeb(th_code, data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP); 357 } 358 359 temp -= ref; 360 writeb(temp, data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL0 + trip_id * 4); 361 } 362 363 /* failing thresholds are not supported on Exynos4210 */ 364 static void exynos4210_tmu_set_trip_hyst(struct exynos_tmu_data *data, 365 int trip, u8 temp, u8 hyst) 366 { 367 } 368 369 static void exynos4210_tmu_initialize(struct platform_device *pdev) 370 { 371 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 372 373 sanitize_temp_error(data, readl(data->base + EXYNOS_TMU_REG_TRIMINFO)); 374 } 375 376 static void exynos4412_tmu_set_trip_temp(struct exynos_tmu_data *data, 377 int trip, u8 temp) 378 { 379 u32 th, con; 380 381 th = readl(data->base + EXYNOS_THD_TEMP_RISE); 382 th &= ~(0xff << 8 * trip); 383 th |= temp_to_code(data, temp) << 8 * trip; 384 writel(th, data->base + EXYNOS_THD_TEMP_RISE); 385 386 if (trip == 3) { 387 con = readl(data->base + EXYNOS_TMU_REG_CONTROL); 388 con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT); 389 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 390 } 391 } 392 393 static void exynos4412_tmu_set_trip_hyst(struct exynos_tmu_data *data, 394 int trip, u8 temp, u8 hyst) 395 { 396 u32 th; 397 398 th = readl(data->base + EXYNOS_THD_TEMP_FALL); 399 th &= ~(0xff << 8 * trip); 400 if (hyst) 401 th |= temp_to_code(data, temp - hyst) << 8 * trip; 402 writel(th, data->base + EXYNOS_THD_TEMP_FALL); 403 } 404 405 static void exynos4412_tmu_initialize(struct platform_device *pdev) 406 { 407 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 408 unsigned int trim_info, ctrl; 409 410 if (data->soc == SOC_ARCH_EXYNOS3250 || 411 data->soc == SOC_ARCH_EXYNOS4412 || 412 data->soc == SOC_ARCH_EXYNOS5250) { 413 if (data->soc == SOC_ARCH_EXYNOS3250) { 414 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON1); 415 ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE; 416 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON1); 417 } 418 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON2); 419 ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE; 420 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON2); 421 } 422 423 /* On exynos5420 the triminfo register is in the shared space */ 424 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) 425 trim_info = readl(data->base_second + EXYNOS_TMU_REG_TRIMINFO); 426 else 427 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); 428 429 sanitize_temp_error(data, trim_info); 430 } 431 432 static void exynos5433_tmu_set_trip_temp(struct exynos_tmu_data *data, 433 int trip, u8 temp) 434 { 435 unsigned int reg_off, j; 436 u32 th; 437 438 if (trip > 3) { 439 reg_off = EXYNOS5433_THD_TEMP_RISE7_4; 440 j = trip - 4; 441 } else { 442 reg_off = EXYNOS5433_THD_TEMP_RISE3_0; 443 j = trip; 444 } 445 446 th = readl(data->base + reg_off); 447 th &= ~(0xff << j * 8); 448 th |= (temp_to_code(data, temp) << j * 8); 449 writel(th, data->base + reg_off); 450 } 451 452 static void exynos5433_tmu_set_trip_hyst(struct exynos_tmu_data *data, 453 int trip, u8 temp, u8 hyst) 454 { 455 unsigned int reg_off, j; 456 u32 th; 457 458 if (trip > 3) { 459 reg_off = EXYNOS5433_THD_TEMP_FALL7_4; 460 j = trip - 4; 461 } else { 462 reg_off = EXYNOS5433_THD_TEMP_FALL3_0; 463 j = trip; 464 } 465 466 th = readl(data->base + reg_off); 467 th &= ~(0xff << j * 8); 468 th |= (temp_to_code(data, temp - hyst) << j * 8); 469 writel(th, data->base + reg_off); 470 } 471 472 static void exynos5433_tmu_initialize(struct platform_device *pdev) 473 { 474 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 475 unsigned int trim_info; 476 int sensor_id, cal_type; 477 478 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); 479 sanitize_temp_error(data, trim_info); 480 481 /* Read the temperature sensor id */ 482 sensor_id = (trim_info & EXYNOS5433_TRIMINFO_SENSOR_ID_MASK) 483 >> EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT; 484 dev_info(&pdev->dev, "Temperature sensor ID: 0x%x\n", sensor_id); 485 486 /* Read the calibration mode */ 487 writel(trim_info, data->base + EXYNOS_TMU_REG_TRIMINFO); 488 cal_type = (trim_info & EXYNOS5433_TRIMINFO_CALIB_SEL_MASK) 489 >> EXYNOS5433_TRIMINFO_CALIB_SEL_SHIFT; 490 491 switch (cal_type) { 492 case EXYNOS5433_TRIMINFO_TWO_POINT_TRIMMING: 493 data->cal_type = TYPE_TWO_POINT_TRIMMING; 494 break; 495 case EXYNOS5433_TRIMINFO_ONE_POINT_TRIMMING: 496 default: 497 data->cal_type = TYPE_ONE_POINT_TRIMMING; 498 break; 499 } 500 501 dev_info(&pdev->dev, "Calibration type is %d-point calibration\n", 502 cal_type ? 2 : 1); 503 } 504 505 static void exynos7_tmu_set_trip_temp(struct exynos_tmu_data *data, 506 int trip, u8 temp) 507 { 508 unsigned int reg_off, bit_off; 509 u32 th; 510 511 reg_off = ((7 - trip) / 2) * 4; 512 bit_off = ((8 - trip) % 2); 513 514 th = readl(data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off); 515 th &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off)); 516 th |= temp_to_code(data, temp) << (16 * bit_off); 517 writel(th, data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off); 518 } 519 520 static void exynos7_tmu_set_trip_hyst(struct exynos_tmu_data *data, 521 int trip, u8 temp, u8 hyst) 522 { 523 unsigned int reg_off, bit_off; 524 u32 th; 525 526 reg_off = ((7 - trip) / 2) * 4; 527 bit_off = ((8 - trip) % 2); 528 529 th = readl(data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off); 530 th &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off)); 531 th |= temp_to_code(data, temp - hyst) << (16 * bit_off); 532 writel(th, data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off); 533 } 534 535 static void exynos7_tmu_initialize(struct platform_device *pdev) 536 { 537 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 538 unsigned int trim_info; 539 540 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); 541 sanitize_temp_error(data, trim_info); 542 } 543 544 static void exynos4210_tmu_control(struct platform_device *pdev, bool on) 545 { 546 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 547 struct thermal_zone_device *tz = data->tzd; 548 struct thermal_trip trip; 549 unsigned int con, interrupt_en = 0, i; 550 551 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); 552 553 if (on) { 554 for (i = 0; i < data->ntrip; i++) { 555 if (thermal_zone_get_trip(tz, i, &trip)) 556 continue; 557 558 interrupt_en |= 559 (1 << (EXYNOS_TMU_INTEN_RISE0_SHIFT + i * 4)); 560 } 561 562 if (data->soc != SOC_ARCH_EXYNOS4210) 563 interrupt_en |= 564 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; 565 566 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); 567 } else { 568 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); 569 } 570 571 writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN); 572 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 573 } 574 575 static void exynos5433_tmu_control(struct platform_device *pdev, bool on) 576 { 577 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 578 struct thermal_zone_device *tz = data->tzd; 579 struct thermal_trip trip; 580 unsigned int con, interrupt_en = 0, pd_det_en, i; 581 582 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); 583 584 if (on) { 585 for (i = 0; i < data->ntrip; i++) { 586 if (thermal_zone_get_trip(tz, i, &trip)) 587 continue; 588 589 interrupt_en |= 590 (1 << (EXYNOS7_TMU_INTEN_RISE0_SHIFT + i)); 591 } 592 593 interrupt_en |= 594 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; 595 596 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); 597 } else 598 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); 599 600 pd_det_en = on ? EXYNOS5433_PD_DET_EN : 0; 601 602 writel(pd_det_en, data->base + EXYNOS5433_TMU_PD_DET_EN); 603 writel(interrupt_en, data->base + EXYNOS5433_TMU_REG_INTEN); 604 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 605 } 606 607 static void exynos7_tmu_control(struct platform_device *pdev, bool on) 608 { 609 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 610 struct thermal_zone_device *tz = data->tzd; 611 struct thermal_trip trip; 612 unsigned int con, interrupt_en = 0, i; 613 614 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); 615 616 if (on) { 617 for (i = 0; i < data->ntrip; i++) { 618 if (thermal_zone_get_trip(tz, i, &trip)) 619 continue; 620 621 interrupt_en |= 622 (1 << (EXYNOS7_TMU_INTEN_RISE0_SHIFT + i)); 623 } 624 625 interrupt_en |= 626 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; 627 628 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); 629 con |= (1 << EXYNOS7_PD_DET_EN_SHIFT); 630 } else { 631 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); 632 con &= ~(1 << EXYNOS7_PD_DET_EN_SHIFT); 633 } 634 635 writel(interrupt_en, data->base + EXYNOS7_TMU_REG_INTEN); 636 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 637 } 638 639 static int exynos_get_temp(struct thermal_zone_device *tz, int *temp) 640 { 641 struct exynos_tmu_data *data = thermal_zone_device_priv(tz); 642 int value, ret = 0; 643 644 if (!data || !data->tmu_read) 645 return -EINVAL; 646 else if (!data->enabled) 647 /* 648 * Called too early, probably 649 * from thermal_zone_of_sensor_register(). 650 */ 651 return -EAGAIN; 652 653 mutex_lock(&data->lock); 654 clk_enable(data->clk); 655 656 value = data->tmu_read(data); 657 if (value < 0) 658 ret = value; 659 else 660 *temp = code_to_temp(data, value) * MCELSIUS; 661 662 clk_disable(data->clk); 663 mutex_unlock(&data->lock); 664 665 return ret; 666 } 667 668 #ifdef CONFIG_THERMAL_EMULATION 669 static u32 get_emul_con_reg(struct exynos_tmu_data *data, unsigned int val, 670 int temp) 671 { 672 if (temp) { 673 temp /= MCELSIUS; 674 675 val &= ~(EXYNOS_EMUL_TIME_MASK << EXYNOS_EMUL_TIME_SHIFT); 676 val |= (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT); 677 if (data->soc == SOC_ARCH_EXYNOS7) { 678 val &= ~(EXYNOS7_EMUL_DATA_MASK << 679 EXYNOS7_EMUL_DATA_SHIFT); 680 val |= (temp_to_code(data, temp) << 681 EXYNOS7_EMUL_DATA_SHIFT) | 682 EXYNOS_EMUL_ENABLE; 683 } else { 684 val &= ~(EXYNOS_EMUL_DATA_MASK << 685 EXYNOS_EMUL_DATA_SHIFT); 686 val |= (temp_to_code(data, temp) << 687 EXYNOS_EMUL_DATA_SHIFT) | 688 EXYNOS_EMUL_ENABLE; 689 } 690 } else { 691 val &= ~EXYNOS_EMUL_ENABLE; 692 } 693 694 return val; 695 } 696 697 static void exynos4412_tmu_set_emulation(struct exynos_tmu_data *data, 698 int temp) 699 { 700 unsigned int val; 701 u32 emul_con; 702 703 if (data->soc == SOC_ARCH_EXYNOS5260) 704 emul_con = EXYNOS5260_EMUL_CON; 705 else if (data->soc == SOC_ARCH_EXYNOS5433) 706 emul_con = EXYNOS5433_TMU_EMUL_CON; 707 else if (data->soc == SOC_ARCH_EXYNOS7) 708 emul_con = EXYNOS7_TMU_REG_EMUL_CON; 709 else 710 emul_con = EXYNOS_EMUL_CON; 711 712 val = readl(data->base + emul_con); 713 val = get_emul_con_reg(data, val, temp); 714 writel(val, data->base + emul_con); 715 } 716 717 static int exynos_tmu_set_emulation(struct thermal_zone_device *tz, int temp) 718 { 719 struct exynos_tmu_data *data = thermal_zone_device_priv(tz); 720 int ret = -EINVAL; 721 722 if (data->soc == SOC_ARCH_EXYNOS4210) 723 goto out; 724 725 if (temp && temp < MCELSIUS) 726 goto out; 727 728 mutex_lock(&data->lock); 729 clk_enable(data->clk); 730 data->tmu_set_emulation(data, temp); 731 clk_disable(data->clk); 732 mutex_unlock(&data->lock); 733 return 0; 734 out: 735 return ret; 736 } 737 #else 738 #define exynos4412_tmu_set_emulation NULL 739 static int exynos_tmu_set_emulation(struct thermal_zone_device *tz, int temp) 740 { return -EINVAL; } 741 #endif /* CONFIG_THERMAL_EMULATION */ 742 743 static int exynos4210_tmu_read(struct exynos_tmu_data *data) 744 { 745 int ret = readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP); 746 747 /* "temp_code" should range between 75 and 175 */ 748 return (ret < 75 || ret > 175) ? -ENODATA : ret; 749 } 750 751 static int exynos4412_tmu_read(struct exynos_tmu_data *data) 752 { 753 return readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP); 754 } 755 756 static int exynos7_tmu_read(struct exynos_tmu_data *data) 757 { 758 return readw(data->base + EXYNOS_TMU_REG_CURRENT_TEMP) & 759 EXYNOS7_TMU_TEMP_MASK; 760 } 761 762 static irqreturn_t exynos_tmu_threaded_irq(int irq, void *id) 763 { 764 struct exynos_tmu_data *data = id; 765 766 thermal_zone_device_update(data->tzd, THERMAL_EVENT_UNSPECIFIED); 767 768 mutex_lock(&data->lock); 769 clk_enable(data->clk); 770 771 /* TODO: take action based on particular interrupt */ 772 data->tmu_clear_irqs(data); 773 774 clk_disable(data->clk); 775 mutex_unlock(&data->lock); 776 777 return IRQ_HANDLED; 778 } 779 780 static void exynos4210_tmu_clear_irqs(struct exynos_tmu_data *data) 781 { 782 unsigned int val_irq; 783 u32 tmu_intstat, tmu_intclear; 784 785 if (data->soc == SOC_ARCH_EXYNOS5260) { 786 tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT; 787 tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR; 788 } else if (data->soc == SOC_ARCH_EXYNOS7) { 789 tmu_intstat = EXYNOS7_TMU_REG_INTPEND; 790 tmu_intclear = EXYNOS7_TMU_REG_INTPEND; 791 } else if (data->soc == SOC_ARCH_EXYNOS5433) { 792 tmu_intstat = EXYNOS5433_TMU_REG_INTPEND; 793 tmu_intclear = EXYNOS5433_TMU_REG_INTPEND; 794 } else { 795 tmu_intstat = EXYNOS_TMU_REG_INTSTAT; 796 tmu_intclear = EXYNOS_TMU_REG_INTCLEAR; 797 } 798 799 val_irq = readl(data->base + tmu_intstat); 800 /* 801 * Clear the interrupts. Please note that the documentation for 802 * Exynos3250, Exynos4412, Exynos5250 and Exynos5260 incorrectly 803 * states that INTCLEAR register has a different placing of bits 804 * responsible for FALL IRQs than INTSTAT register. Exynos5420 805 * and Exynos5440 documentation is correct (Exynos4210 doesn't 806 * support FALL IRQs at all). 807 */ 808 writel(val_irq, data->base + tmu_intclear); 809 } 810 811 static const struct of_device_id exynos_tmu_match[] = { 812 { 813 .compatible = "samsung,exynos3250-tmu", 814 .data = (const void *)SOC_ARCH_EXYNOS3250, 815 }, { 816 .compatible = "samsung,exynos4210-tmu", 817 .data = (const void *)SOC_ARCH_EXYNOS4210, 818 }, { 819 .compatible = "samsung,exynos4412-tmu", 820 .data = (const void *)SOC_ARCH_EXYNOS4412, 821 }, { 822 .compatible = "samsung,exynos5250-tmu", 823 .data = (const void *)SOC_ARCH_EXYNOS5250, 824 }, { 825 .compatible = "samsung,exynos5260-tmu", 826 .data = (const void *)SOC_ARCH_EXYNOS5260, 827 }, { 828 .compatible = "samsung,exynos5420-tmu", 829 .data = (const void *)SOC_ARCH_EXYNOS5420, 830 }, { 831 .compatible = "samsung,exynos5420-tmu-ext-triminfo", 832 .data = (const void *)SOC_ARCH_EXYNOS5420_TRIMINFO, 833 }, { 834 .compatible = "samsung,exynos5433-tmu", 835 .data = (const void *)SOC_ARCH_EXYNOS5433, 836 }, { 837 .compatible = "samsung,exynos7-tmu", 838 .data = (const void *)SOC_ARCH_EXYNOS7, 839 }, 840 { }, 841 }; 842 MODULE_DEVICE_TABLE(of, exynos_tmu_match); 843 844 static int exynos_map_dt_data(struct platform_device *pdev) 845 { 846 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 847 struct resource res; 848 849 if (!data || !pdev->dev.of_node) 850 return -ENODEV; 851 852 data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 853 if (data->irq <= 0) { 854 dev_err(&pdev->dev, "failed to get IRQ\n"); 855 return -ENODEV; 856 } 857 858 if (of_address_to_resource(pdev->dev.of_node, 0, &res)) { 859 dev_err(&pdev->dev, "failed to get Resource 0\n"); 860 return -ENODEV; 861 } 862 863 data->base = devm_ioremap(&pdev->dev, res.start, resource_size(&res)); 864 if (!data->base) { 865 dev_err(&pdev->dev, "Failed to ioremap memory\n"); 866 return -EADDRNOTAVAIL; 867 } 868 869 data->soc = (uintptr_t)of_device_get_match_data(&pdev->dev); 870 871 switch (data->soc) { 872 case SOC_ARCH_EXYNOS4210: 873 data->tmu_set_trip_temp = exynos4210_tmu_set_trip_temp; 874 data->tmu_set_trip_hyst = exynos4210_tmu_set_trip_hyst; 875 data->tmu_initialize = exynos4210_tmu_initialize; 876 data->tmu_control = exynos4210_tmu_control; 877 data->tmu_read = exynos4210_tmu_read; 878 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; 879 data->ntrip = 4; 880 data->gain = 15; 881 data->reference_voltage = 7; 882 data->efuse_value = 55; 883 data->min_efuse_value = 40; 884 data->max_efuse_value = 100; 885 break; 886 case SOC_ARCH_EXYNOS3250: 887 case SOC_ARCH_EXYNOS4412: 888 case SOC_ARCH_EXYNOS5250: 889 case SOC_ARCH_EXYNOS5260: 890 case SOC_ARCH_EXYNOS5420: 891 case SOC_ARCH_EXYNOS5420_TRIMINFO: 892 data->tmu_set_trip_temp = exynos4412_tmu_set_trip_temp; 893 data->tmu_set_trip_hyst = exynos4412_tmu_set_trip_hyst; 894 data->tmu_initialize = exynos4412_tmu_initialize; 895 data->tmu_control = exynos4210_tmu_control; 896 data->tmu_read = exynos4412_tmu_read; 897 data->tmu_set_emulation = exynos4412_tmu_set_emulation; 898 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; 899 data->ntrip = 4; 900 data->gain = 8; 901 data->reference_voltage = 16; 902 data->efuse_value = 55; 903 if (data->soc != SOC_ARCH_EXYNOS5420 && 904 data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO) 905 data->min_efuse_value = 40; 906 else 907 data->min_efuse_value = 0; 908 data->max_efuse_value = 100; 909 break; 910 case SOC_ARCH_EXYNOS5433: 911 data->tmu_set_trip_temp = exynos5433_tmu_set_trip_temp; 912 data->tmu_set_trip_hyst = exynos5433_tmu_set_trip_hyst; 913 data->tmu_initialize = exynos5433_tmu_initialize; 914 data->tmu_control = exynos5433_tmu_control; 915 data->tmu_read = exynos4412_tmu_read; 916 data->tmu_set_emulation = exynos4412_tmu_set_emulation; 917 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; 918 data->ntrip = 8; 919 data->gain = 8; 920 if (res.start == EXYNOS5433_G3D_BASE) 921 data->reference_voltage = 23; 922 else 923 data->reference_voltage = 16; 924 data->efuse_value = 75; 925 data->min_efuse_value = 40; 926 data->max_efuse_value = 150; 927 break; 928 case SOC_ARCH_EXYNOS7: 929 data->tmu_set_trip_temp = exynos7_tmu_set_trip_temp; 930 data->tmu_set_trip_hyst = exynos7_tmu_set_trip_hyst; 931 data->tmu_initialize = exynos7_tmu_initialize; 932 data->tmu_control = exynos7_tmu_control; 933 data->tmu_read = exynos7_tmu_read; 934 data->tmu_set_emulation = exynos4412_tmu_set_emulation; 935 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; 936 data->ntrip = 8; 937 data->gain = 9; 938 data->reference_voltage = 17; 939 data->efuse_value = 75; 940 data->min_efuse_value = 15; 941 data->max_efuse_value = 100; 942 break; 943 default: 944 dev_err(&pdev->dev, "Platform not supported\n"); 945 return -EINVAL; 946 } 947 948 data->cal_type = TYPE_ONE_POINT_TRIMMING; 949 950 /* 951 * Check if the TMU shares some registers and then try to map the 952 * memory of common registers. 953 */ 954 if (data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO) 955 return 0; 956 957 if (of_address_to_resource(pdev->dev.of_node, 1, &res)) { 958 dev_err(&pdev->dev, "failed to get Resource 1\n"); 959 return -ENODEV; 960 } 961 962 data->base_second = devm_ioremap(&pdev->dev, res.start, 963 resource_size(&res)); 964 if (!data->base_second) { 965 dev_err(&pdev->dev, "Failed to ioremap memory\n"); 966 return -ENOMEM; 967 } 968 969 return 0; 970 } 971 972 static const struct thermal_zone_device_ops exynos_sensor_ops = { 973 .get_temp = exynos_get_temp, 974 .set_emul_temp = exynos_tmu_set_emulation, 975 }; 976 977 static int exynos_tmu_probe(struct platform_device *pdev) 978 { 979 struct exynos_tmu_data *data; 980 int ret; 981 982 data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data), 983 GFP_KERNEL); 984 if (!data) 985 return -ENOMEM; 986 987 platform_set_drvdata(pdev, data); 988 mutex_init(&data->lock); 989 990 /* 991 * Try enabling the regulator if found 992 * TODO: Add regulator as an SOC feature, so that regulator enable 993 * is a compulsory call. 994 */ 995 ret = devm_regulator_get_enable_optional(&pdev->dev, "vtmu"); 996 switch (ret) { 997 case 0: 998 case -ENODEV: 999 break; 1000 case -EPROBE_DEFER: 1001 return -EPROBE_DEFER; 1002 default: 1003 dev_err(&pdev->dev, "Failed to get enabled regulator: %d\n", 1004 ret); 1005 return ret; 1006 } 1007 1008 ret = exynos_map_dt_data(pdev); 1009 if (ret) 1010 return ret; 1011 1012 data->clk = devm_clk_get(&pdev->dev, "tmu_apbif"); 1013 if (IS_ERR(data->clk)) { 1014 dev_err(&pdev->dev, "Failed to get clock\n"); 1015 return PTR_ERR(data->clk); 1016 } 1017 1018 data->clk_sec = devm_clk_get(&pdev->dev, "tmu_triminfo_apbif"); 1019 if (IS_ERR(data->clk_sec)) { 1020 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) { 1021 dev_err(&pdev->dev, "Failed to get triminfo clock\n"); 1022 return PTR_ERR(data->clk_sec); 1023 } 1024 } else { 1025 ret = clk_prepare(data->clk_sec); 1026 if (ret) { 1027 dev_err(&pdev->dev, "Failed to get clock\n"); 1028 return ret; 1029 } 1030 } 1031 1032 ret = clk_prepare(data->clk); 1033 if (ret) { 1034 dev_err(&pdev->dev, "Failed to get clock\n"); 1035 goto err_clk_sec; 1036 } 1037 1038 switch (data->soc) { 1039 case SOC_ARCH_EXYNOS5433: 1040 case SOC_ARCH_EXYNOS7: 1041 data->sclk = devm_clk_get(&pdev->dev, "tmu_sclk"); 1042 if (IS_ERR(data->sclk)) { 1043 dev_err(&pdev->dev, "Failed to get sclk\n"); 1044 ret = PTR_ERR(data->sclk); 1045 goto err_clk; 1046 } else { 1047 ret = clk_prepare_enable(data->sclk); 1048 if (ret) { 1049 dev_err(&pdev->dev, "Failed to enable sclk\n"); 1050 goto err_clk; 1051 } 1052 } 1053 break; 1054 default: 1055 break; 1056 } 1057 1058 /* 1059 * data->tzd must be registered before calling exynos_tmu_initialize(), 1060 * requesting irq and calling exynos_tmu_control(). 1061 */ 1062 data->tzd = devm_thermal_of_zone_register(&pdev->dev, 0, data, 1063 &exynos_sensor_ops); 1064 if (IS_ERR(data->tzd)) { 1065 ret = PTR_ERR(data->tzd); 1066 if (ret != -EPROBE_DEFER) 1067 dev_err(&pdev->dev, "Failed to register sensor: %d\n", 1068 ret); 1069 goto err_sclk; 1070 } 1071 1072 ret = exynos_tmu_initialize(pdev); 1073 if (ret) { 1074 dev_err(&pdev->dev, "Failed to initialize TMU\n"); 1075 goto err_sclk; 1076 } 1077 1078 ret = devm_request_threaded_irq(&pdev->dev, data->irq, NULL, 1079 exynos_tmu_threaded_irq, 1080 IRQF_TRIGGER_RISING 1081 | IRQF_SHARED | IRQF_ONESHOT, 1082 dev_name(&pdev->dev), data); 1083 if (ret) { 1084 dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq); 1085 goto err_sclk; 1086 } 1087 1088 exynos_tmu_control(pdev, true); 1089 return 0; 1090 1091 err_sclk: 1092 clk_disable_unprepare(data->sclk); 1093 err_clk: 1094 clk_unprepare(data->clk); 1095 err_clk_sec: 1096 if (!IS_ERR(data->clk_sec)) 1097 clk_unprepare(data->clk_sec); 1098 return ret; 1099 } 1100 1101 static void exynos_tmu_remove(struct platform_device *pdev) 1102 { 1103 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 1104 1105 exynos_tmu_control(pdev, false); 1106 1107 clk_disable_unprepare(data->sclk); 1108 clk_unprepare(data->clk); 1109 if (!IS_ERR(data->clk_sec)) 1110 clk_unprepare(data->clk_sec); 1111 } 1112 1113 #ifdef CONFIG_PM_SLEEP 1114 static int exynos_tmu_suspend(struct device *dev) 1115 { 1116 exynos_tmu_control(to_platform_device(dev), false); 1117 1118 return 0; 1119 } 1120 1121 static int exynos_tmu_resume(struct device *dev) 1122 { 1123 struct platform_device *pdev = to_platform_device(dev); 1124 1125 exynos_tmu_initialize(pdev); 1126 exynos_tmu_control(pdev, true); 1127 1128 return 0; 1129 } 1130 1131 static SIMPLE_DEV_PM_OPS(exynos_tmu_pm, 1132 exynos_tmu_suspend, exynos_tmu_resume); 1133 #define EXYNOS_TMU_PM (&exynos_tmu_pm) 1134 #else 1135 #define EXYNOS_TMU_PM NULL 1136 #endif 1137 1138 static struct platform_driver exynos_tmu_driver = { 1139 .driver = { 1140 .name = "exynos-tmu", 1141 .pm = EXYNOS_TMU_PM, 1142 .of_match_table = exynos_tmu_match, 1143 }, 1144 .probe = exynos_tmu_probe, 1145 .remove_new = exynos_tmu_remove, 1146 }; 1147 1148 module_platform_driver(exynos_tmu_driver); 1149 1150 MODULE_DESCRIPTION("Exynos TMU Driver"); 1151 MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>"); 1152 MODULE_LICENSE("GPL"); 1153 MODULE_ALIAS("platform:exynos-tmu"); 1154