1 /* 2 * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit) 3 * 4 * Copyright (C) 2014 Samsung Electronics 5 * Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> 6 * Lukasz Majewski <l.majewski@samsung.com> 7 * 8 * Copyright (C) 2011 Samsung Electronics 9 * Donggeun Kim <dg77.kim@samsung.com> 10 * Amit Daniel Kachhap <amit.kachhap@linaro.org> 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 * 26 */ 27 28 #include <linux/clk.h> 29 #include <linux/io.h> 30 #include <linux/interrupt.h> 31 #include <linux/module.h> 32 #include <linux/of_device.h> 33 #include <linux/of_address.h> 34 #include <linux/of_irq.h> 35 #include <linux/platform_device.h> 36 #include <linux/regulator/consumer.h> 37 38 #include <dt-bindings/thermal/thermal_exynos.h> 39 40 #include "../thermal_core.h" 41 42 /* Exynos generic registers */ 43 #define EXYNOS_TMU_REG_TRIMINFO 0x0 44 #define EXYNOS_TMU_REG_CONTROL 0x20 45 #define EXYNOS_TMU_REG_STATUS 0x28 46 #define EXYNOS_TMU_REG_CURRENT_TEMP 0x40 47 #define EXYNOS_TMU_REG_INTEN 0x70 48 #define EXYNOS_TMU_REG_INTSTAT 0x74 49 #define EXYNOS_TMU_REG_INTCLEAR 0x78 50 51 #define EXYNOS_TMU_TEMP_MASK 0xff 52 #define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24 53 #define EXYNOS_TMU_REF_VOLTAGE_MASK 0x1f 54 #define EXYNOS_TMU_BUF_SLOPE_SEL_MASK 0xf 55 #define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT 8 56 #define EXYNOS_TMU_CORE_EN_SHIFT 0 57 58 /* Exynos3250 specific registers */ 59 #define EXYNOS_TMU_TRIMINFO_CON1 0x10 60 61 /* Exynos4210 specific registers */ 62 #define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44 63 #define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50 64 65 /* Exynos5250, Exynos4412, Exynos3250 specific registers */ 66 #define EXYNOS_TMU_TRIMINFO_CON2 0x14 67 #define EXYNOS_THD_TEMP_RISE 0x50 68 #define EXYNOS_THD_TEMP_FALL 0x54 69 #define EXYNOS_EMUL_CON 0x80 70 71 #define EXYNOS_TRIMINFO_RELOAD_ENABLE 1 72 #define EXYNOS_TRIMINFO_25_SHIFT 0 73 #define EXYNOS_TRIMINFO_85_SHIFT 8 74 #define EXYNOS_TMU_TRIP_MODE_SHIFT 13 75 #define EXYNOS_TMU_TRIP_MODE_MASK 0x7 76 #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12 77 78 #define EXYNOS_TMU_INTEN_RISE0_SHIFT 0 79 #define EXYNOS_TMU_INTEN_FALL0_SHIFT 16 80 81 #define EXYNOS_EMUL_TIME 0x57F0 82 #define EXYNOS_EMUL_TIME_MASK 0xffff 83 #define EXYNOS_EMUL_TIME_SHIFT 16 84 #define EXYNOS_EMUL_DATA_SHIFT 8 85 #define EXYNOS_EMUL_DATA_MASK 0xFF 86 #define EXYNOS_EMUL_ENABLE 0x1 87 88 /* Exynos5260 specific */ 89 #define EXYNOS5260_TMU_REG_INTEN 0xC0 90 #define EXYNOS5260_TMU_REG_INTSTAT 0xC4 91 #define EXYNOS5260_TMU_REG_INTCLEAR 0xC8 92 #define EXYNOS5260_EMUL_CON 0x100 93 94 /* Exynos4412 specific */ 95 #define EXYNOS4412_MUX_ADDR_VALUE 6 96 #define EXYNOS4412_MUX_ADDR_SHIFT 20 97 98 /* Exynos5433 specific registers */ 99 #define EXYNOS5433_THD_TEMP_RISE3_0 0x050 100 #define EXYNOS5433_THD_TEMP_RISE7_4 0x054 101 #define EXYNOS5433_THD_TEMP_FALL3_0 0x060 102 #define EXYNOS5433_THD_TEMP_FALL7_4 0x064 103 #define EXYNOS5433_TMU_REG_INTEN 0x0c0 104 #define EXYNOS5433_TMU_REG_INTPEND 0x0c8 105 #define EXYNOS5433_TMU_EMUL_CON 0x110 106 #define EXYNOS5433_TMU_PD_DET_EN 0x130 107 108 #define EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT 16 109 #define EXYNOS5433_TRIMINFO_CALIB_SEL_SHIFT 23 110 #define EXYNOS5433_TRIMINFO_SENSOR_ID_MASK \ 111 (0xf << EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT) 112 #define EXYNOS5433_TRIMINFO_CALIB_SEL_MASK BIT(23) 113 114 #define EXYNOS5433_TRIMINFO_ONE_POINT_TRIMMING 0 115 #define EXYNOS5433_TRIMINFO_TWO_POINT_TRIMMING 1 116 117 #define EXYNOS5433_PD_DET_EN 1 118 119 #define EXYNOS5433_G3D_BASE 0x10070000 120 121 /* Exynos7 specific registers */ 122 #define EXYNOS7_THD_TEMP_RISE7_6 0x50 123 #define EXYNOS7_THD_TEMP_FALL7_6 0x60 124 #define EXYNOS7_TMU_REG_INTEN 0x110 125 #define EXYNOS7_TMU_REG_INTPEND 0x118 126 #define EXYNOS7_TMU_REG_EMUL_CON 0x160 127 128 #define EXYNOS7_TMU_TEMP_MASK 0x1ff 129 #define EXYNOS7_PD_DET_EN_SHIFT 23 130 #define EXYNOS7_TMU_INTEN_RISE0_SHIFT 0 131 #define EXYNOS7_EMUL_DATA_SHIFT 7 132 #define EXYNOS7_EMUL_DATA_MASK 0x1ff 133 134 #define EXYNOS_FIRST_POINT_TRIM 25 135 #define EXYNOS_SECOND_POINT_TRIM 85 136 137 #define EXYNOS_NOISE_CANCEL_MODE 4 138 139 #define MCELSIUS 1000 140 141 enum soc_type { 142 SOC_ARCH_EXYNOS3250 = 1, 143 SOC_ARCH_EXYNOS4210, 144 SOC_ARCH_EXYNOS4412, 145 SOC_ARCH_EXYNOS5250, 146 SOC_ARCH_EXYNOS5260, 147 SOC_ARCH_EXYNOS5420, 148 SOC_ARCH_EXYNOS5420_TRIMINFO, 149 SOC_ARCH_EXYNOS5433, 150 SOC_ARCH_EXYNOS7, 151 }; 152 153 /** 154 * struct exynos_tmu_data : A structure to hold the private data of the TMU 155 driver 156 * @id: identifier of the one instance of the TMU controller. 157 * @base: base address of the single instance of the TMU controller. 158 * @base_second: base address of the common registers of the TMU controller. 159 * @irq: irq number of the TMU controller. 160 * @soc: id of the SOC type. 161 * @irq_work: pointer to the irq work structure. 162 * @lock: lock to implement synchronization. 163 * @clk: pointer to the clock structure. 164 * @clk_sec: pointer to the clock structure for accessing the base_second. 165 * @sclk: pointer to the clock structure for accessing the tmu special clk. 166 * @cal_type: calibration type for temperature 167 * @efuse_value: SoC defined fuse value 168 * @min_efuse_value: minimum valid trimming data 169 * @max_efuse_value: maximum valid trimming data 170 * @temp_error1: fused value of the first point trim. 171 * @temp_error2: fused value of the second point trim. 172 * @gain: gain of amplifier in the positive-TC generator block 173 * 0 < gain <= 15 174 * @reference_voltage: reference voltage of amplifier 175 * in the positive-TC generator block 176 * 0 < reference_voltage <= 31 177 * @regulator: pointer to the TMU regulator structure. 178 * @reg_conf: pointer to structure to register with core thermal. 179 * @ntrip: number of supported trip points. 180 * @enabled: current status of TMU device 181 * @tmu_initialize: SoC specific TMU initialization method 182 * @tmu_control: SoC specific TMU control method 183 * @tmu_read: SoC specific TMU temperature read method 184 * @tmu_set_emulation: SoC specific TMU emulation setting method 185 * @tmu_clear_irqs: SoC specific TMU interrupts clearing method 186 */ 187 struct exynos_tmu_data { 188 int id; 189 void __iomem *base; 190 void __iomem *base_second; 191 int irq; 192 enum soc_type soc; 193 struct work_struct irq_work; 194 struct mutex lock; 195 struct clk *clk, *clk_sec, *sclk; 196 u32 cal_type; 197 u32 efuse_value; 198 u32 min_efuse_value; 199 u32 max_efuse_value; 200 u16 temp_error1, temp_error2; 201 u8 gain; 202 u8 reference_voltage; 203 struct regulator *regulator; 204 struct thermal_zone_device *tzd; 205 unsigned int ntrip; 206 bool enabled; 207 208 void (*tmu_set_trip_temp)(struct exynos_tmu_data *data, int trip, 209 u8 temp); 210 void (*tmu_set_trip_hyst)(struct exynos_tmu_data *data, int trip, 211 u8 temp, u8 hyst); 212 void (*tmu_initialize)(struct platform_device *pdev); 213 void (*tmu_control)(struct platform_device *pdev, bool on); 214 int (*tmu_read)(struct exynos_tmu_data *data); 215 void (*tmu_set_emulation)(struct exynos_tmu_data *data, int temp); 216 void (*tmu_clear_irqs)(struct exynos_tmu_data *data); 217 }; 218 219 static void exynos_report_trigger(struct exynos_tmu_data *p) 220 { 221 char data[10], *envp[] = { data, NULL }; 222 struct thermal_zone_device *tz = p->tzd; 223 int temp; 224 unsigned int i; 225 226 if (!tz) { 227 pr_err("No thermal zone device defined\n"); 228 return; 229 } 230 231 thermal_zone_device_update(tz, THERMAL_EVENT_UNSPECIFIED); 232 233 mutex_lock(&tz->lock); 234 /* Find the level for which trip happened */ 235 for (i = 0; i < of_thermal_get_ntrips(tz); i++) { 236 tz->ops->get_trip_temp(tz, i, &temp); 237 if (tz->last_temperature < temp) 238 break; 239 } 240 241 snprintf(data, sizeof(data), "%u", i); 242 kobject_uevent_env(&tz->device.kobj, KOBJ_CHANGE, envp); 243 mutex_unlock(&tz->lock); 244 } 245 246 /* 247 * TMU treats temperature as a mapped temperature code. 248 * The temperature is converted differently depending on the calibration type. 249 */ 250 static int temp_to_code(struct exynos_tmu_data *data, u8 temp) 251 { 252 if (data->cal_type == TYPE_ONE_POINT_TRIMMING) 253 return temp + data->temp_error1 - EXYNOS_FIRST_POINT_TRIM; 254 255 return (temp - EXYNOS_FIRST_POINT_TRIM) * 256 (data->temp_error2 - data->temp_error1) / 257 (EXYNOS_SECOND_POINT_TRIM - EXYNOS_FIRST_POINT_TRIM) + 258 data->temp_error1; 259 } 260 261 /* 262 * Calculate a temperature value from a temperature code. 263 * The unit of the temperature is degree Celsius. 264 */ 265 static int code_to_temp(struct exynos_tmu_data *data, u16 temp_code) 266 { 267 if (data->cal_type == TYPE_ONE_POINT_TRIMMING) 268 return temp_code - data->temp_error1 + EXYNOS_FIRST_POINT_TRIM; 269 270 return (temp_code - data->temp_error1) * 271 (EXYNOS_SECOND_POINT_TRIM - EXYNOS_FIRST_POINT_TRIM) / 272 (data->temp_error2 - data->temp_error1) + 273 EXYNOS_FIRST_POINT_TRIM; 274 } 275 276 static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_info) 277 { 278 u16 tmu_temp_mask = 279 (data->soc == SOC_ARCH_EXYNOS7) ? EXYNOS7_TMU_TEMP_MASK 280 : EXYNOS_TMU_TEMP_MASK; 281 282 data->temp_error1 = trim_info & tmu_temp_mask; 283 data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) & 284 EXYNOS_TMU_TEMP_MASK); 285 286 if (!data->temp_error1 || 287 (data->min_efuse_value > data->temp_error1) || 288 (data->temp_error1 > data->max_efuse_value)) 289 data->temp_error1 = data->efuse_value & EXYNOS_TMU_TEMP_MASK; 290 291 if (!data->temp_error2) 292 data->temp_error2 = 293 (data->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) & 294 EXYNOS_TMU_TEMP_MASK; 295 } 296 297 static int exynos_tmu_initialize(struct platform_device *pdev) 298 { 299 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 300 struct thermal_zone_device *tzd = data->tzd; 301 const struct thermal_trip * const trips = 302 of_thermal_get_trip_points(tzd); 303 unsigned int status; 304 int ret = 0, temp, hyst; 305 306 if (!trips) { 307 dev_err(&pdev->dev, 308 "Cannot get trip points from device tree!\n"); 309 return -ENODEV; 310 } 311 312 if (data->soc != SOC_ARCH_EXYNOS5433) /* FIXME */ 313 ret = tzd->ops->get_crit_temp(tzd, &temp); 314 if (ret) { 315 dev_err(&pdev->dev, 316 "No CRITICAL trip point defined in device tree!\n"); 317 goto out; 318 } 319 320 if (of_thermal_get_ntrips(tzd) > data->ntrip) { 321 dev_info(&pdev->dev, 322 "More trip points than supported by this TMU.\n"); 323 dev_info(&pdev->dev, 324 "%d trip points should be configured in polling mode.\n", 325 (of_thermal_get_ntrips(tzd) - data->ntrip)); 326 } 327 328 mutex_lock(&data->lock); 329 clk_enable(data->clk); 330 if (!IS_ERR(data->clk_sec)) 331 clk_enable(data->clk_sec); 332 333 status = readb(data->base + EXYNOS_TMU_REG_STATUS); 334 if (!status) { 335 ret = -EBUSY; 336 } else { 337 int i, ntrips = 338 min_t(int, of_thermal_get_ntrips(tzd), data->ntrip); 339 340 data->tmu_initialize(pdev); 341 342 /* Write temperature code for rising and falling threshold */ 343 for (i = 0; i < ntrips; i++) { 344 /* Write temperature code for rising threshold */ 345 ret = tzd->ops->get_trip_temp(tzd, i, &temp); 346 if (ret) 347 goto err; 348 temp /= MCELSIUS; 349 data->tmu_set_trip_temp(data, i, temp); 350 351 /* Write temperature code for falling threshold */ 352 ret = tzd->ops->get_trip_hyst(tzd, i, &hyst); 353 if (ret) 354 goto err; 355 hyst /= MCELSIUS; 356 data->tmu_set_trip_hyst(data, i, temp, hyst); 357 } 358 359 data->tmu_clear_irqs(data); 360 } 361 err: 362 clk_disable(data->clk); 363 mutex_unlock(&data->lock); 364 if (!IS_ERR(data->clk_sec)) 365 clk_disable(data->clk_sec); 366 out: 367 return ret; 368 } 369 370 static u32 get_con_reg(struct exynos_tmu_data *data, u32 con) 371 { 372 if (data->soc == SOC_ARCH_EXYNOS4412 || 373 data->soc == SOC_ARCH_EXYNOS3250) 374 con |= (EXYNOS4412_MUX_ADDR_VALUE << EXYNOS4412_MUX_ADDR_SHIFT); 375 376 con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK << EXYNOS_TMU_REF_VOLTAGE_SHIFT); 377 con |= data->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT; 378 379 con &= ~(EXYNOS_TMU_BUF_SLOPE_SEL_MASK << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT); 380 con |= (data->gain << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT); 381 382 con &= ~(EXYNOS_TMU_TRIP_MODE_MASK << EXYNOS_TMU_TRIP_MODE_SHIFT); 383 con |= (EXYNOS_NOISE_CANCEL_MODE << EXYNOS_TMU_TRIP_MODE_SHIFT); 384 385 return con; 386 } 387 388 static void exynos_tmu_control(struct platform_device *pdev, bool on) 389 { 390 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 391 392 mutex_lock(&data->lock); 393 clk_enable(data->clk); 394 data->tmu_control(pdev, on); 395 data->enabled = on; 396 clk_disable(data->clk); 397 mutex_unlock(&data->lock); 398 } 399 400 static void exynos4210_tmu_set_trip_temp(struct exynos_tmu_data *data, 401 int trip, u8 temp) 402 { 403 const struct thermal_trip * const trips = 404 of_thermal_get_trip_points(data->tzd); 405 u8 ref, th_code; 406 407 ref = trips[0].temperature / MCELSIUS; 408 409 if (trip == 0) { 410 th_code = temp_to_code(data, ref); 411 writeb(th_code, data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP); 412 } 413 414 temp -= ref; 415 writeb(temp, data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL0 + trip * 4); 416 } 417 418 /* failing thresholds are not supported on Exynos4210 */ 419 static void exynos4210_tmu_set_trip_hyst(struct exynos_tmu_data *data, 420 int trip, u8 temp, u8 hyst) 421 { 422 } 423 424 static void exynos4210_tmu_initialize(struct platform_device *pdev) 425 { 426 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 427 428 sanitize_temp_error(data, readl(data->base + EXYNOS_TMU_REG_TRIMINFO)); 429 } 430 431 static void exynos4412_tmu_set_trip_temp(struct exynos_tmu_data *data, 432 int trip, u8 temp) 433 { 434 u32 th, con; 435 436 th = readl(data->base + EXYNOS_THD_TEMP_RISE); 437 th &= ~(0xff << 8 * trip); 438 th |= temp_to_code(data, temp) << 8 * trip; 439 writel(th, data->base + EXYNOS_THD_TEMP_RISE); 440 441 if (trip == 3) { 442 con = readl(data->base + EXYNOS_TMU_REG_CONTROL); 443 con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT); 444 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 445 } 446 } 447 448 static void exynos4412_tmu_set_trip_hyst(struct exynos_tmu_data *data, 449 int trip, u8 temp, u8 hyst) 450 { 451 u32 th; 452 453 th = readl(data->base + EXYNOS_THD_TEMP_FALL); 454 th &= ~(0xff << 8 * trip); 455 if (hyst) 456 th |= temp_to_code(data, temp - hyst) << 8 * trip; 457 writel(th, data->base + EXYNOS_THD_TEMP_FALL); 458 } 459 460 static void exynos4412_tmu_initialize(struct platform_device *pdev) 461 { 462 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 463 unsigned int trim_info, ctrl; 464 465 if (data->soc == SOC_ARCH_EXYNOS3250 || 466 data->soc == SOC_ARCH_EXYNOS4412 || 467 data->soc == SOC_ARCH_EXYNOS5250) { 468 if (data->soc == SOC_ARCH_EXYNOS3250) { 469 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON1); 470 ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE; 471 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON1); 472 } 473 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON2); 474 ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE; 475 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON2); 476 } 477 478 /* On exynos5420 the triminfo register is in the shared space */ 479 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) 480 trim_info = readl(data->base_second + EXYNOS_TMU_REG_TRIMINFO); 481 else 482 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); 483 484 sanitize_temp_error(data, trim_info); 485 } 486 487 static void exynos5433_tmu_set_trip_temp(struct exynos_tmu_data *data, 488 int trip, u8 temp) 489 { 490 unsigned int reg_off, j; 491 u32 th; 492 493 if (trip > 3) { 494 reg_off = EXYNOS5433_THD_TEMP_RISE7_4; 495 j = trip - 4; 496 } else { 497 reg_off = EXYNOS5433_THD_TEMP_RISE3_0; 498 j = trip; 499 } 500 501 th = readl(data->base + reg_off); 502 th &= ~(0xff << j * 8); 503 th |= (temp_to_code(data, temp) << j * 8); 504 writel(th, data->base + reg_off); 505 } 506 507 static void exynos5433_tmu_set_trip_hyst(struct exynos_tmu_data *data, 508 int trip, u8 temp, u8 hyst) 509 { 510 unsigned int reg_off, j; 511 u32 th; 512 513 if (trip > 3) { 514 reg_off = EXYNOS5433_THD_TEMP_FALL7_4; 515 j = trip - 4; 516 } else { 517 reg_off = EXYNOS5433_THD_TEMP_FALL3_0; 518 j = trip; 519 } 520 521 th = readl(data->base + reg_off); 522 th &= ~(0xff << j * 8); 523 th |= (temp_to_code(data, temp - hyst) << j * 8); 524 writel(th, data->base + reg_off); 525 } 526 527 static void exynos5433_tmu_initialize(struct platform_device *pdev) 528 { 529 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 530 unsigned int trim_info; 531 int sensor_id, cal_type; 532 533 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); 534 sanitize_temp_error(data, trim_info); 535 536 /* Read the temperature sensor id */ 537 sensor_id = (trim_info & EXYNOS5433_TRIMINFO_SENSOR_ID_MASK) 538 >> EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT; 539 dev_info(&pdev->dev, "Temperature sensor ID: 0x%x\n", sensor_id); 540 541 /* Read the calibration mode */ 542 writel(trim_info, data->base + EXYNOS_TMU_REG_TRIMINFO); 543 cal_type = (trim_info & EXYNOS5433_TRIMINFO_CALIB_SEL_MASK) 544 >> EXYNOS5433_TRIMINFO_CALIB_SEL_SHIFT; 545 546 switch (cal_type) { 547 case EXYNOS5433_TRIMINFO_TWO_POINT_TRIMMING: 548 data->cal_type = TYPE_TWO_POINT_TRIMMING; 549 break; 550 case EXYNOS5433_TRIMINFO_ONE_POINT_TRIMMING: 551 default: 552 data->cal_type = TYPE_ONE_POINT_TRIMMING; 553 break; 554 } 555 556 dev_info(&pdev->dev, "Calibration type is %d-point calibration\n", 557 cal_type ? 2 : 1); 558 } 559 560 static void exynos7_tmu_set_trip_temp(struct exynos_tmu_data *data, 561 int trip, u8 temp) 562 { 563 unsigned int reg_off, bit_off; 564 u32 th; 565 566 reg_off = ((7 - trip) / 2) * 4; 567 bit_off = ((8 - trip) % 2); 568 569 th = readl(data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off); 570 th &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off)); 571 th |= temp_to_code(data, temp) << (16 * bit_off); 572 writel(th, data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off); 573 } 574 575 static void exynos7_tmu_set_trip_hyst(struct exynos_tmu_data *data, 576 int trip, u8 temp, u8 hyst) 577 { 578 unsigned int reg_off, bit_off; 579 u32 th; 580 581 reg_off = ((7 - trip) / 2) * 4; 582 bit_off = ((8 - trip) % 2); 583 584 th = readl(data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off); 585 th &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off)); 586 th |= temp_to_code(data, temp - hyst) << (16 * bit_off); 587 writel(th, data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off); 588 } 589 590 static void exynos7_tmu_initialize(struct platform_device *pdev) 591 { 592 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 593 unsigned int trim_info; 594 595 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); 596 sanitize_temp_error(data, trim_info); 597 } 598 599 static void exynos4210_tmu_control(struct platform_device *pdev, bool on) 600 { 601 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 602 struct thermal_zone_device *tz = data->tzd; 603 unsigned int con, interrupt_en = 0, i; 604 605 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); 606 607 if (on) { 608 for (i = 0; i < data->ntrip; i++) { 609 if (!of_thermal_is_trip_valid(tz, i)) 610 continue; 611 612 interrupt_en |= 613 (1 << (EXYNOS_TMU_INTEN_RISE0_SHIFT + i * 4)); 614 } 615 616 if (data->soc != SOC_ARCH_EXYNOS4210) 617 interrupt_en |= 618 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; 619 620 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); 621 } else { 622 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); 623 } 624 625 writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN); 626 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 627 } 628 629 static void exynos5433_tmu_control(struct platform_device *pdev, bool on) 630 { 631 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 632 struct thermal_zone_device *tz = data->tzd; 633 unsigned int con, interrupt_en = 0, pd_det_en, i; 634 635 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); 636 637 if (on) { 638 for (i = 0; i < data->ntrip; i++) { 639 if (!of_thermal_is_trip_valid(tz, i)) 640 continue; 641 642 interrupt_en |= 643 (1 << (EXYNOS7_TMU_INTEN_RISE0_SHIFT + i)); 644 } 645 646 interrupt_en |= 647 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; 648 649 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); 650 } else 651 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); 652 653 pd_det_en = on ? EXYNOS5433_PD_DET_EN : 0; 654 655 writel(pd_det_en, data->base + EXYNOS5433_TMU_PD_DET_EN); 656 writel(interrupt_en, data->base + EXYNOS5433_TMU_REG_INTEN); 657 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 658 } 659 660 static void exynos7_tmu_control(struct platform_device *pdev, bool on) 661 { 662 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 663 struct thermal_zone_device *tz = data->tzd; 664 unsigned int con, interrupt_en = 0, i; 665 666 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); 667 668 if (on) { 669 for (i = 0; i < data->ntrip; i++) { 670 if (!of_thermal_is_trip_valid(tz, i)) 671 continue; 672 673 interrupt_en |= 674 (1 << (EXYNOS7_TMU_INTEN_RISE0_SHIFT + i)); 675 } 676 677 interrupt_en |= 678 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; 679 680 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); 681 con |= (1 << EXYNOS7_PD_DET_EN_SHIFT); 682 } else { 683 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); 684 con &= ~(1 << EXYNOS7_PD_DET_EN_SHIFT); 685 } 686 687 writel(interrupt_en, data->base + EXYNOS7_TMU_REG_INTEN); 688 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 689 } 690 691 static int exynos_get_temp(void *p, int *temp) 692 { 693 struct exynos_tmu_data *data = p; 694 int value, ret = 0; 695 696 if (!data || !data->tmu_read || !data->enabled) 697 return -EINVAL; 698 699 mutex_lock(&data->lock); 700 clk_enable(data->clk); 701 702 value = data->tmu_read(data); 703 if (value < 0) 704 ret = value; 705 else 706 *temp = code_to_temp(data, value) * MCELSIUS; 707 708 clk_disable(data->clk); 709 mutex_unlock(&data->lock); 710 711 return ret; 712 } 713 714 #ifdef CONFIG_THERMAL_EMULATION 715 static u32 get_emul_con_reg(struct exynos_tmu_data *data, unsigned int val, 716 int temp) 717 { 718 if (temp) { 719 temp /= MCELSIUS; 720 721 val &= ~(EXYNOS_EMUL_TIME_MASK << EXYNOS_EMUL_TIME_SHIFT); 722 val |= (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT); 723 if (data->soc == SOC_ARCH_EXYNOS7) { 724 val &= ~(EXYNOS7_EMUL_DATA_MASK << 725 EXYNOS7_EMUL_DATA_SHIFT); 726 val |= (temp_to_code(data, temp) << 727 EXYNOS7_EMUL_DATA_SHIFT) | 728 EXYNOS_EMUL_ENABLE; 729 } else { 730 val &= ~(EXYNOS_EMUL_DATA_MASK << 731 EXYNOS_EMUL_DATA_SHIFT); 732 val |= (temp_to_code(data, temp) << 733 EXYNOS_EMUL_DATA_SHIFT) | 734 EXYNOS_EMUL_ENABLE; 735 } 736 } else { 737 val &= ~EXYNOS_EMUL_ENABLE; 738 } 739 740 return val; 741 } 742 743 static void exynos4412_tmu_set_emulation(struct exynos_tmu_data *data, 744 int temp) 745 { 746 unsigned int val; 747 u32 emul_con; 748 749 if (data->soc == SOC_ARCH_EXYNOS5260) 750 emul_con = EXYNOS5260_EMUL_CON; 751 else if (data->soc == SOC_ARCH_EXYNOS5433) 752 emul_con = EXYNOS5433_TMU_EMUL_CON; 753 else if (data->soc == SOC_ARCH_EXYNOS7) 754 emul_con = EXYNOS7_TMU_REG_EMUL_CON; 755 else 756 emul_con = EXYNOS_EMUL_CON; 757 758 val = readl(data->base + emul_con); 759 val = get_emul_con_reg(data, val, temp); 760 writel(val, data->base + emul_con); 761 } 762 763 static int exynos_tmu_set_emulation(void *drv_data, int temp) 764 { 765 struct exynos_tmu_data *data = drv_data; 766 int ret = -EINVAL; 767 768 if (data->soc == SOC_ARCH_EXYNOS4210) 769 goto out; 770 771 if (temp && temp < MCELSIUS) 772 goto out; 773 774 mutex_lock(&data->lock); 775 clk_enable(data->clk); 776 data->tmu_set_emulation(data, temp); 777 clk_disable(data->clk); 778 mutex_unlock(&data->lock); 779 return 0; 780 out: 781 return ret; 782 } 783 #else 784 #define exynos4412_tmu_set_emulation NULL 785 static int exynos_tmu_set_emulation(void *drv_data, int temp) 786 { return -EINVAL; } 787 #endif /* CONFIG_THERMAL_EMULATION */ 788 789 static int exynos4210_tmu_read(struct exynos_tmu_data *data) 790 { 791 int ret = readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP); 792 793 /* "temp_code" should range between 75 and 175 */ 794 return (ret < 75 || ret > 175) ? -ENODATA : ret; 795 } 796 797 static int exynos4412_tmu_read(struct exynos_tmu_data *data) 798 { 799 return readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP); 800 } 801 802 static int exynos7_tmu_read(struct exynos_tmu_data *data) 803 { 804 return readw(data->base + EXYNOS_TMU_REG_CURRENT_TEMP) & 805 EXYNOS7_TMU_TEMP_MASK; 806 } 807 808 static void exynos_tmu_work(struct work_struct *work) 809 { 810 struct exynos_tmu_data *data = container_of(work, 811 struct exynos_tmu_data, irq_work); 812 813 if (!IS_ERR(data->clk_sec)) 814 clk_enable(data->clk_sec); 815 if (!IS_ERR(data->clk_sec)) 816 clk_disable(data->clk_sec); 817 818 exynos_report_trigger(data); 819 mutex_lock(&data->lock); 820 clk_enable(data->clk); 821 822 /* TODO: take action based on particular interrupt */ 823 data->tmu_clear_irqs(data); 824 825 clk_disable(data->clk); 826 mutex_unlock(&data->lock); 827 enable_irq(data->irq); 828 } 829 830 static void exynos4210_tmu_clear_irqs(struct exynos_tmu_data *data) 831 { 832 unsigned int val_irq; 833 u32 tmu_intstat, tmu_intclear; 834 835 if (data->soc == SOC_ARCH_EXYNOS5260) { 836 tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT; 837 tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR; 838 } else if (data->soc == SOC_ARCH_EXYNOS7) { 839 tmu_intstat = EXYNOS7_TMU_REG_INTPEND; 840 tmu_intclear = EXYNOS7_TMU_REG_INTPEND; 841 } else if (data->soc == SOC_ARCH_EXYNOS5433) { 842 tmu_intstat = EXYNOS5433_TMU_REG_INTPEND; 843 tmu_intclear = EXYNOS5433_TMU_REG_INTPEND; 844 } else { 845 tmu_intstat = EXYNOS_TMU_REG_INTSTAT; 846 tmu_intclear = EXYNOS_TMU_REG_INTCLEAR; 847 } 848 849 val_irq = readl(data->base + tmu_intstat); 850 /* 851 * Clear the interrupts. Please note that the documentation for 852 * Exynos3250, Exynos4412, Exynos5250 and Exynos5260 incorrectly 853 * states that INTCLEAR register has a different placing of bits 854 * responsible for FALL IRQs than INTSTAT register. Exynos5420 855 * and Exynos5440 documentation is correct (Exynos4210 doesn't 856 * support FALL IRQs at all). 857 */ 858 writel(val_irq, data->base + tmu_intclear); 859 } 860 861 static irqreturn_t exynos_tmu_irq(int irq, void *id) 862 { 863 struct exynos_tmu_data *data = id; 864 865 disable_irq_nosync(irq); 866 schedule_work(&data->irq_work); 867 868 return IRQ_HANDLED; 869 } 870 871 static const struct of_device_id exynos_tmu_match[] = { 872 { 873 .compatible = "samsung,exynos3250-tmu", 874 .data = (const void *)SOC_ARCH_EXYNOS3250, 875 }, { 876 .compatible = "samsung,exynos4210-tmu", 877 .data = (const void *)SOC_ARCH_EXYNOS4210, 878 }, { 879 .compatible = "samsung,exynos4412-tmu", 880 .data = (const void *)SOC_ARCH_EXYNOS4412, 881 }, { 882 .compatible = "samsung,exynos5250-tmu", 883 .data = (const void *)SOC_ARCH_EXYNOS5250, 884 }, { 885 .compatible = "samsung,exynos5260-tmu", 886 .data = (const void *)SOC_ARCH_EXYNOS5260, 887 }, { 888 .compatible = "samsung,exynos5420-tmu", 889 .data = (const void *)SOC_ARCH_EXYNOS5420, 890 }, { 891 .compatible = "samsung,exynos5420-tmu-ext-triminfo", 892 .data = (const void *)SOC_ARCH_EXYNOS5420_TRIMINFO, 893 }, { 894 .compatible = "samsung,exynos5433-tmu", 895 .data = (const void *)SOC_ARCH_EXYNOS5433, 896 }, { 897 .compatible = "samsung,exynos7-tmu", 898 .data = (const void *)SOC_ARCH_EXYNOS7, 899 }, 900 { }, 901 }; 902 MODULE_DEVICE_TABLE(of, exynos_tmu_match); 903 904 static int exynos_map_dt_data(struct platform_device *pdev) 905 { 906 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 907 struct resource res; 908 909 if (!data || !pdev->dev.of_node) 910 return -ENODEV; 911 912 data->id = of_alias_get_id(pdev->dev.of_node, "tmuctrl"); 913 if (data->id < 0) 914 data->id = 0; 915 916 data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 917 if (data->irq <= 0) { 918 dev_err(&pdev->dev, "failed to get IRQ\n"); 919 return -ENODEV; 920 } 921 922 if (of_address_to_resource(pdev->dev.of_node, 0, &res)) { 923 dev_err(&pdev->dev, "failed to get Resource 0\n"); 924 return -ENODEV; 925 } 926 927 data->base = devm_ioremap(&pdev->dev, res.start, resource_size(&res)); 928 if (!data->base) { 929 dev_err(&pdev->dev, "Failed to ioremap memory\n"); 930 return -EADDRNOTAVAIL; 931 } 932 933 data->soc = (enum soc_type)of_device_get_match_data(&pdev->dev); 934 935 switch (data->soc) { 936 case SOC_ARCH_EXYNOS4210: 937 data->tmu_set_trip_temp = exynos4210_tmu_set_trip_temp; 938 data->tmu_set_trip_hyst = exynos4210_tmu_set_trip_hyst; 939 data->tmu_initialize = exynos4210_tmu_initialize; 940 data->tmu_control = exynos4210_tmu_control; 941 data->tmu_read = exynos4210_tmu_read; 942 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; 943 data->ntrip = 4; 944 data->gain = 15; 945 data->reference_voltage = 7; 946 data->efuse_value = 55; 947 data->min_efuse_value = 40; 948 data->max_efuse_value = 100; 949 break; 950 case SOC_ARCH_EXYNOS3250: 951 case SOC_ARCH_EXYNOS4412: 952 case SOC_ARCH_EXYNOS5250: 953 case SOC_ARCH_EXYNOS5260: 954 case SOC_ARCH_EXYNOS5420: 955 case SOC_ARCH_EXYNOS5420_TRIMINFO: 956 data->tmu_set_trip_temp = exynos4412_tmu_set_trip_temp; 957 data->tmu_set_trip_hyst = exynos4412_tmu_set_trip_hyst; 958 data->tmu_initialize = exynos4412_tmu_initialize; 959 data->tmu_control = exynos4210_tmu_control; 960 data->tmu_read = exynos4412_tmu_read; 961 data->tmu_set_emulation = exynos4412_tmu_set_emulation; 962 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; 963 data->ntrip = 4; 964 data->gain = 8; 965 data->reference_voltage = 16; 966 data->efuse_value = 55; 967 if (data->soc != SOC_ARCH_EXYNOS5420 && 968 data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO) 969 data->min_efuse_value = 40; 970 else 971 data->min_efuse_value = 0; 972 data->max_efuse_value = 100; 973 break; 974 case SOC_ARCH_EXYNOS5433: 975 data->tmu_set_trip_temp = exynos5433_tmu_set_trip_temp; 976 data->tmu_set_trip_hyst = exynos5433_tmu_set_trip_hyst; 977 data->tmu_initialize = exynos5433_tmu_initialize; 978 data->tmu_control = exynos5433_tmu_control; 979 data->tmu_read = exynos4412_tmu_read; 980 data->tmu_set_emulation = exynos4412_tmu_set_emulation; 981 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; 982 data->ntrip = 8; 983 data->gain = 8; 984 if (res.start == EXYNOS5433_G3D_BASE) 985 data->reference_voltage = 23; 986 else 987 data->reference_voltage = 16; 988 data->efuse_value = 75; 989 data->min_efuse_value = 40; 990 data->max_efuse_value = 150; 991 break; 992 case SOC_ARCH_EXYNOS7: 993 data->tmu_set_trip_temp = exynos7_tmu_set_trip_temp; 994 data->tmu_set_trip_hyst = exynos7_tmu_set_trip_hyst; 995 data->tmu_initialize = exynos7_tmu_initialize; 996 data->tmu_control = exynos7_tmu_control; 997 data->tmu_read = exynos7_tmu_read; 998 data->tmu_set_emulation = exynos4412_tmu_set_emulation; 999 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; 1000 data->ntrip = 8; 1001 data->gain = 9; 1002 data->reference_voltage = 17; 1003 data->efuse_value = 75; 1004 data->min_efuse_value = 15; 1005 data->max_efuse_value = 100; 1006 break; 1007 default: 1008 dev_err(&pdev->dev, "Platform not supported\n"); 1009 return -EINVAL; 1010 } 1011 1012 data->cal_type = TYPE_ONE_POINT_TRIMMING; 1013 1014 /* 1015 * Check if the TMU shares some registers and then try to map the 1016 * memory of common registers. 1017 */ 1018 if (data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO) 1019 return 0; 1020 1021 if (of_address_to_resource(pdev->dev.of_node, 1, &res)) { 1022 dev_err(&pdev->dev, "failed to get Resource 1\n"); 1023 return -ENODEV; 1024 } 1025 1026 data->base_second = devm_ioremap(&pdev->dev, res.start, 1027 resource_size(&res)); 1028 if (!data->base_second) { 1029 dev_err(&pdev->dev, "Failed to ioremap memory\n"); 1030 return -ENOMEM; 1031 } 1032 1033 return 0; 1034 } 1035 1036 static const struct thermal_zone_of_device_ops exynos_sensor_ops = { 1037 .get_temp = exynos_get_temp, 1038 .set_emul_temp = exynos_tmu_set_emulation, 1039 }; 1040 1041 static int exynos_tmu_probe(struct platform_device *pdev) 1042 { 1043 struct exynos_tmu_data *data; 1044 int ret; 1045 1046 data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data), 1047 GFP_KERNEL); 1048 if (!data) 1049 return -ENOMEM; 1050 1051 platform_set_drvdata(pdev, data); 1052 mutex_init(&data->lock); 1053 1054 /* 1055 * Try enabling the regulator if found 1056 * TODO: Add regulator as an SOC feature, so that regulator enable 1057 * is a compulsory call. 1058 */ 1059 data->regulator = devm_regulator_get_optional(&pdev->dev, "vtmu"); 1060 if (!IS_ERR(data->regulator)) { 1061 ret = regulator_enable(data->regulator); 1062 if (ret) { 1063 dev_err(&pdev->dev, "failed to enable vtmu\n"); 1064 return ret; 1065 } 1066 } else { 1067 if (PTR_ERR(data->regulator) == -EPROBE_DEFER) 1068 return -EPROBE_DEFER; 1069 dev_info(&pdev->dev, "Regulator node (vtmu) not found\n"); 1070 } 1071 1072 ret = exynos_map_dt_data(pdev); 1073 if (ret) 1074 goto err_sensor; 1075 1076 INIT_WORK(&data->irq_work, exynos_tmu_work); 1077 1078 data->clk = devm_clk_get(&pdev->dev, "tmu_apbif"); 1079 if (IS_ERR(data->clk)) { 1080 dev_err(&pdev->dev, "Failed to get clock\n"); 1081 ret = PTR_ERR(data->clk); 1082 goto err_sensor; 1083 } 1084 1085 data->clk_sec = devm_clk_get(&pdev->dev, "tmu_triminfo_apbif"); 1086 if (IS_ERR(data->clk_sec)) { 1087 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) { 1088 dev_err(&pdev->dev, "Failed to get triminfo clock\n"); 1089 ret = PTR_ERR(data->clk_sec); 1090 goto err_sensor; 1091 } 1092 } else { 1093 ret = clk_prepare(data->clk_sec); 1094 if (ret) { 1095 dev_err(&pdev->dev, "Failed to get clock\n"); 1096 goto err_sensor; 1097 } 1098 } 1099 1100 ret = clk_prepare(data->clk); 1101 if (ret) { 1102 dev_err(&pdev->dev, "Failed to get clock\n"); 1103 goto err_clk_sec; 1104 } 1105 1106 switch (data->soc) { 1107 case SOC_ARCH_EXYNOS5433: 1108 case SOC_ARCH_EXYNOS7: 1109 data->sclk = devm_clk_get(&pdev->dev, "tmu_sclk"); 1110 if (IS_ERR(data->sclk)) { 1111 dev_err(&pdev->dev, "Failed to get sclk\n"); 1112 goto err_clk; 1113 } else { 1114 ret = clk_prepare_enable(data->sclk); 1115 if (ret) { 1116 dev_err(&pdev->dev, "Failed to enable sclk\n"); 1117 goto err_clk; 1118 } 1119 } 1120 break; 1121 default: 1122 break; 1123 } 1124 1125 /* 1126 * data->tzd must be registered before calling exynos_tmu_initialize(), 1127 * requesting irq and calling exynos_tmu_control(). 1128 */ 1129 data->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, data, 1130 &exynos_sensor_ops); 1131 if (IS_ERR(data->tzd)) { 1132 ret = PTR_ERR(data->tzd); 1133 dev_err(&pdev->dev, "Failed to register sensor: %d\n", ret); 1134 goto err_sclk; 1135 } 1136 1137 ret = exynos_tmu_initialize(pdev); 1138 if (ret) { 1139 dev_err(&pdev->dev, "Failed to initialize TMU\n"); 1140 goto err_thermal; 1141 } 1142 1143 ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq, 1144 IRQF_TRIGGER_RISING | IRQF_SHARED, dev_name(&pdev->dev), data); 1145 if (ret) { 1146 dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq); 1147 goto err_thermal; 1148 } 1149 1150 exynos_tmu_control(pdev, true); 1151 return 0; 1152 1153 err_thermal: 1154 thermal_zone_of_sensor_unregister(&pdev->dev, data->tzd); 1155 err_sclk: 1156 clk_disable_unprepare(data->sclk); 1157 err_clk: 1158 clk_unprepare(data->clk); 1159 err_clk_sec: 1160 if (!IS_ERR(data->clk_sec)) 1161 clk_unprepare(data->clk_sec); 1162 err_sensor: 1163 if (!IS_ERR(data->regulator)) 1164 regulator_disable(data->regulator); 1165 1166 return ret; 1167 } 1168 1169 static int exynos_tmu_remove(struct platform_device *pdev) 1170 { 1171 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 1172 struct thermal_zone_device *tzd = data->tzd; 1173 1174 thermal_zone_of_sensor_unregister(&pdev->dev, tzd); 1175 exynos_tmu_control(pdev, false); 1176 1177 clk_disable_unprepare(data->sclk); 1178 clk_unprepare(data->clk); 1179 if (!IS_ERR(data->clk_sec)) 1180 clk_unprepare(data->clk_sec); 1181 1182 if (!IS_ERR(data->regulator)) 1183 regulator_disable(data->regulator); 1184 1185 return 0; 1186 } 1187 1188 #ifdef CONFIG_PM_SLEEP 1189 static int exynos_tmu_suspend(struct device *dev) 1190 { 1191 exynos_tmu_control(to_platform_device(dev), false); 1192 1193 return 0; 1194 } 1195 1196 static int exynos_tmu_resume(struct device *dev) 1197 { 1198 struct platform_device *pdev = to_platform_device(dev); 1199 1200 exynos_tmu_initialize(pdev); 1201 exynos_tmu_control(pdev, true); 1202 1203 return 0; 1204 } 1205 1206 static SIMPLE_DEV_PM_OPS(exynos_tmu_pm, 1207 exynos_tmu_suspend, exynos_tmu_resume); 1208 #define EXYNOS_TMU_PM (&exynos_tmu_pm) 1209 #else 1210 #define EXYNOS_TMU_PM NULL 1211 #endif 1212 1213 static struct platform_driver exynos_tmu_driver = { 1214 .driver = { 1215 .name = "exynos-tmu", 1216 .pm = EXYNOS_TMU_PM, 1217 .of_match_table = exynos_tmu_match, 1218 }, 1219 .probe = exynos_tmu_probe, 1220 .remove = exynos_tmu_remove, 1221 }; 1222 1223 module_platform_driver(exynos_tmu_driver); 1224 1225 MODULE_DESCRIPTION("EXYNOS TMU Driver"); 1226 MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>"); 1227 MODULE_LICENSE("GPL"); 1228 MODULE_ALIAS("platform:exynos-tmu"); 1229