1 /* 2 * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit) 3 * 4 * Copyright (C) 2014 Samsung Electronics 5 * Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> 6 * Lukasz Majewski <l.majewski@samsung.com> 7 * 8 * Copyright (C) 2011 Samsung Electronics 9 * Donggeun Kim <dg77.kim@samsung.com> 10 * Amit Daniel Kachhap <amit.kachhap@linaro.org> 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 * 26 */ 27 28 #include <linux/clk.h> 29 #include <linux/io.h> 30 #include <linux/interrupt.h> 31 #include <linux/module.h> 32 #include <linux/of_device.h> 33 #include <linux/of_address.h> 34 #include <linux/of_irq.h> 35 #include <linux/platform_device.h> 36 #include <linux/regulator/consumer.h> 37 38 #include "exynos_tmu.h" 39 #include "../thermal_core.h" 40 41 /* Exynos generic registers */ 42 #define EXYNOS_TMU_REG_TRIMINFO 0x0 43 #define EXYNOS_TMU_REG_CONTROL 0x20 44 #define EXYNOS_TMU_REG_STATUS 0x28 45 #define EXYNOS_TMU_REG_CURRENT_TEMP 0x40 46 #define EXYNOS_TMU_REG_INTEN 0x70 47 #define EXYNOS_TMU_REG_INTSTAT 0x74 48 #define EXYNOS_TMU_REG_INTCLEAR 0x78 49 50 #define EXYNOS_TMU_TEMP_MASK 0xff 51 #define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24 52 #define EXYNOS_TMU_REF_VOLTAGE_MASK 0x1f 53 #define EXYNOS_TMU_BUF_SLOPE_SEL_MASK 0xf 54 #define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT 8 55 #define EXYNOS_TMU_CORE_EN_SHIFT 0 56 57 /* Exynos3250 specific registers */ 58 #define EXYNOS_TMU_TRIMINFO_CON1 0x10 59 60 /* Exynos4210 specific registers */ 61 #define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44 62 #define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50 63 64 /* Exynos5250, Exynos4412, Exynos3250 specific registers */ 65 #define EXYNOS_TMU_TRIMINFO_CON2 0x14 66 #define EXYNOS_THD_TEMP_RISE 0x50 67 #define EXYNOS_THD_TEMP_FALL 0x54 68 #define EXYNOS_EMUL_CON 0x80 69 70 #define EXYNOS_TRIMINFO_RELOAD_ENABLE 1 71 #define EXYNOS_TRIMINFO_25_SHIFT 0 72 #define EXYNOS_TRIMINFO_85_SHIFT 8 73 #define EXYNOS_TMU_TRIP_MODE_SHIFT 13 74 #define EXYNOS_TMU_TRIP_MODE_MASK 0x7 75 #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12 76 77 #define EXYNOS_TMU_INTEN_RISE0_SHIFT 0 78 #define EXYNOS_TMU_INTEN_RISE1_SHIFT 4 79 #define EXYNOS_TMU_INTEN_RISE2_SHIFT 8 80 #define EXYNOS_TMU_INTEN_RISE3_SHIFT 12 81 #define EXYNOS_TMU_INTEN_FALL0_SHIFT 16 82 83 #define EXYNOS_EMUL_TIME 0x57F0 84 #define EXYNOS_EMUL_TIME_MASK 0xffff 85 #define EXYNOS_EMUL_TIME_SHIFT 16 86 #define EXYNOS_EMUL_DATA_SHIFT 8 87 #define EXYNOS_EMUL_DATA_MASK 0xFF 88 #define EXYNOS_EMUL_ENABLE 0x1 89 90 /* Exynos5260 specific */ 91 #define EXYNOS5260_TMU_REG_INTEN 0xC0 92 #define EXYNOS5260_TMU_REG_INTSTAT 0xC4 93 #define EXYNOS5260_TMU_REG_INTCLEAR 0xC8 94 #define EXYNOS5260_EMUL_CON 0x100 95 96 /* Exynos4412 specific */ 97 #define EXYNOS4412_MUX_ADDR_VALUE 6 98 #define EXYNOS4412_MUX_ADDR_SHIFT 20 99 100 /* Exynos5433 specific registers */ 101 #define EXYNOS5433_TMU_REG_CONTROL1 0x024 102 #define EXYNOS5433_TMU_SAMPLING_INTERVAL 0x02c 103 #define EXYNOS5433_TMU_COUNTER_VALUE0 0x030 104 #define EXYNOS5433_TMU_COUNTER_VALUE1 0x034 105 #define EXYNOS5433_TMU_REG_CURRENT_TEMP1 0x044 106 #define EXYNOS5433_THD_TEMP_RISE3_0 0x050 107 #define EXYNOS5433_THD_TEMP_RISE7_4 0x054 108 #define EXYNOS5433_THD_TEMP_FALL3_0 0x060 109 #define EXYNOS5433_THD_TEMP_FALL7_4 0x064 110 #define EXYNOS5433_TMU_REG_INTEN 0x0c0 111 #define EXYNOS5433_TMU_REG_INTPEND 0x0c8 112 #define EXYNOS5433_TMU_EMUL_CON 0x110 113 #define EXYNOS5433_TMU_PD_DET_EN 0x130 114 115 #define EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT 16 116 #define EXYNOS5433_TRIMINFO_CALIB_SEL_SHIFT 23 117 #define EXYNOS5433_TRIMINFO_SENSOR_ID_MASK \ 118 (0xf << EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT) 119 #define EXYNOS5433_TRIMINFO_CALIB_SEL_MASK BIT(23) 120 121 #define EXYNOS5433_TRIMINFO_ONE_POINT_TRIMMING 0 122 #define EXYNOS5433_TRIMINFO_TWO_POINT_TRIMMING 1 123 124 #define EXYNOS5433_PD_DET_EN 1 125 126 #define EXYNOS5433_G3D_BASE 0x10070000 127 128 /*exynos5440 specific registers*/ 129 #define EXYNOS5440_TMU_S0_7_TRIM 0x000 130 #define EXYNOS5440_TMU_S0_7_CTRL 0x020 131 #define EXYNOS5440_TMU_S0_7_DEBUG 0x040 132 #define EXYNOS5440_TMU_S0_7_TEMP 0x0f0 133 #define EXYNOS5440_TMU_S0_7_TH0 0x110 134 #define EXYNOS5440_TMU_S0_7_TH1 0x130 135 #define EXYNOS5440_TMU_S0_7_TH2 0x150 136 #define EXYNOS5440_TMU_S0_7_IRQEN 0x210 137 #define EXYNOS5440_TMU_S0_7_IRQ 0x230 138 /* exynos5440 common registers */ 139 #define EXYNOS5440_TMU_IRQ_STATUS 0x000 140 #define EXYNOS5440_TMU_PMIN 0x004 141 142 #define EXYNOS5440_TMU_INTEN_RISE0_SHIFT 0 143 #define EXYNOS5440_TMU_INTEN_RISE1_SHIFT 1 144 #define EXYNOS5440_TMU_INTEN_RISE2_SHIFT 2 145 #define EXYNOS5440_TMU_INTEN_RISE3_SHIFT 3 146 #define EXYNOS5440_TMU_INTEN_FALL0_SHIFT 4 147 #define EXYNOS5440_TMU_TH_RISE4_SHIFT 24 148 #define EXYNOS5440_EFUSE_SWAP_OFFSET 8 149 150 /* Exynos7 specific registers */ 151 #define EXYNOS7_THD_TEMP_RISE7_6 0x50 152 #define EXYNOS7_THD_TEMP_FALL7_6 0x60 153 #define EXYNOS7_TMU_REG_INTEN 0x110 154 #define EXYNOS7_TMU_REG_INTPEND 0x118 155 #define EXYNOS7_TMU_REG_EMUL_CON 0x160 156 157 #define EXYNOS7_TMU_TEMP_MASK 0x1ff 158 #define EXYNOS7_PD_DET_EN_SHIFT 23 159 #define EXYNOS7_TMU_INTEN_RISE0_SHIFT 0 160 #define EXYNOS7_TMU_INTEN_RISE1_SHIFT 1 161 #define EXYNOS7_TMU_INTEN_RISE2_SHIFT 2 162 #define EXYNOS7_TMU_INTEN_RISE3_SHIFT 3 163 #define EXYNOS7_TMU_INTEN_RISE4_SHIFT 4 164 #define EXYNOS7_TMU_INTEN_RISE5_SHIFT 5 165 #define EXYNOS7_TMU_INTEN_RISE6_SHIFT 6 166 #define EXYNOS7_TMU_INTEN_RISE7_SHIFT 7 167 #define EXYNOS7_EMUL_DATA_SHIFT 7 168 #define EXYNOS7_EMUL_DATA_MASK 0x1ff 169 170 #define EXYNOS_FIRST_POINT_TRIM 25 171 #define EXYNOS_SECOND_POINT_TRIM 85 172 173 #define EXYNOS_NOISE_CANCEL_MODE 4 174 175 #define MCELSIUS 1000 176 /** 177 * struct exynos_tmu_data : A structure to hold the private data of the TMU 178 driver 179 * @id: identifier of the one instance of the TMU controller. 180 * @base: base address of the single instance of the TMU controller. 181 * @base_second: base address of the common registers of the TMU controller. 182 * @irq: irq number of the TMU controller. 183 * @soc: id of the SOC type. 184 * @irq_work: pointer to the irq work structure. 185 * @lock: lock to implement synchronization. 186 * @clk: pointer to the clock structure. 187 * @clk_sec: pointer to the clock structure for accessing the base_second. 188 * @sclk: pointer to the clock structure for accessing the tmu special clk. 189 * @cal_type: calibration type for temperature 190 * @efuse_value: SoC defined fuse value 191 * @min_efuse_value: minimum valid trimming data 192 * @max_efuse_value: maximum valid trimming data 193 * @temp_error1: fused value of the first point trim. 194 * @temp_error2: fused value of the second point trim. 195 * @gain: gain of amplifier in the positive-TC generator block 196 * 0 < gain <= 15 197 * @reference_voltage: reference voltage of amplifier 198 * in the positive-TC generator block 199 * 0 < reference_voltage <= 31 200 * @regulator: pointer to the TMU regulator structure. 201 * @reg_conf: pointer to structure to register with core thermal. 202 * @ntrip: number of supported trip points. 203 * @enabled: current status of TMU device 204 * @tmu_initialize: SoC specific TMU initialization method 205 * @tmu_control: SoC specific TMU control method 206 * @tmu_read: SoC specific TMU temperature read method 207 * @tmu_set_emulation: SoC specific TMU emulation setting method 208 * @tmu_clear_irqs: SoC specific TMU interrupts clearing method 209 */ 210 struct exynos_tmu_data { 211 int id; 212 void __iomem *base; 213 void __iomem *base_second; 214 int irq; 215 enum soc_type soc; 216 struct work_struct irq_work; 217 struct mutex lock; 218 struct clk *clk, *clk_sec, *sclk; 219 u32 cal_type; 220 u32 efuse_value; 221 u32 min_efuse_value; 222 u32 max_efuse_value; 223 u16 temp_error1, temp_error2; 224 u8 gain; 225 u8 reference_voltage; 226 struct regulator *regulator; 227 struct thermal_zone_device *tzd; 228 unsigned int ntrip; 229 bool enabled; 230 231 int (*tmu_initialize)(struct platform_device *pdev); 232 void (*tmu_control)(struct platform_device *pdev, bool on); 233 int (*tmu_read)(struct exynos_tmu_data *data); 234 void (*tmu_set_emulation)(struct exynos_tmu_data *data, int temp); 235 void (*tmu_clear_irqs)(struct exynos_tmu_data *data); 236 }; 237 238 static void exynos_report_trigger(struct exynos_tmu_data *p) 239 { 240 char data[10], *envp[] = { data, NULL }; 241 struct thermal_zone_device *tz = p->tzd; 242 int temp; 243 unsigned int i; 244 245 if (!tz) { 246 pr_err("No thermal zone device defined\n"); 247 return; 248 } 249 250 thermal_zone_device_update(tz, THERMAL_EVENT_UNSPECIFIED); 251 252 mutex_lock(&tz->lock); 253 /* Find the level for which trip happened */ 254 for (i = 0; i < of_thermal_get_ntrips(tz); i++) { 255 tz->ops->get_trip_temp(tz, i, &temp); 256 if (tz->last_temperature < temp) 257 break; 258 } 259 260 snprintf(data, sizeof(data), "%u", i); 261 kobject_uevent_env(&tz->device.kobj, KOBJ_CHANGE, envp); 262 mutex_unlock(&tz->lock); 263 } 264 265 /* 266 * TMU treats temperature as a mapped temperature code. 267 * The temperature is converted differently depending on the calibration type. 268 */ 269 static int temp_to_code(struct exynos_tmu_data *data, u8 temp) 270 { 271 if (data->cal_type == TYPE_ONE_POINT_TRIMMING) 272 return temp + data->temp_error1 - EXYNOS_FIRST_POINT_TRIM; 273 274 return (temp - EXYNOS_FIRST_POINT_TRIM) * 275 (data->temp_error2 - data->temp_error1) / 276 (EXYNOS_SECOND_POINT_TRIM - EXYNOS_FIRST_POINT_TRIM) + 277 data->temp_error1; 278 } 279 280 /* 281 * Calculate a temperature value from a temperature code. 282 * The unit of the temperature is degree Celsius. 283 */ 284 static int code_to_temp(struct exynos_tmu_data *data, u16 temp_code) 285 { 286 if (data->cal_type == TYPE_ONE_POINT_TRIMMING) 287 return temp_code - data->temp_error1 + EXYNOS_FIRST_POINT_TRIM; 288 289 return (temp_code - data->temp_error1) * 290 (EXYNOS_SECOND_POINT_TRIM - EXYNOS_FIRST_POINT_TRIM) / 291 (data->temp_error2 - data->temp_error1) + 292 EXYNOS_FIRST_POINT_TRIM; 293 } 294 295 static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_info) 296 { 297 data->temp_error1 = trim_info & EXYNOS_TMU_TEMP_MASK; 298 data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) & 299 EXYNOS_TMU_TEMP_MASK); 300 301 if (!data->temp_error1 || 302 (data->min_efuse_value > data->temp_error1) || 303 (data->temp_error1 > data->max_efuse_value)) 304 data->temp_error1 = data->efuse_value & EXYNOS_TMU_TEMP_MASK; 305 306 if (!data->temp_error2) 307 data->temp_error2 = 308 (data->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) & 309 EXYNOS_TMU_TEMP_MASK; 310 } 311 312 static u32 get_th_reg(struct exynos_tmu_data *data, u32 threshold, bool falling) 313 { 314 struct thermal_zone_device *tz = data->tzd; 315 const struct thermal_trip * const trips = 316 of_thermal_get_trip_points(tz); 317 unsigned long temp; 318 int i; 319 320 if (!trips) { 321 pr_err("%s: Cannot get trip points from of-thermal.c!\n", 322 __func__); 323 return 0; 324 } 325 326 for (i = 0; i < of_thermal_get_ntrips(tz); i++) { 327 if (trips[i].type == THERMAL_TRIP_CRITICAL) 328 continue; 329 330 temp = trips[i].temperature / MCELSIUS; 331 if (falling) 332 temp -= (trips[i].hysteresis / MCELSIUS); 333 else 334 threshold &= ~(0xff << 8 * i); 335 336 threshold |= temp_to_code(data, temp) << 8 * i; 337 } 338 339 return threshold; 340 } 341 342 static int exynos_tmu_initialize(struct platform_device *pdev) 343 { 344 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 345 int ret; 346 347 if (of_thermal_get_ntrips(data->tzd) > data->ntrip) { 348 dev_info(&pdev->dev, 349 "More trip points than supported by this TMU.\n"); 350 dev_info(&pdev->dev, 351 "%d trip points should be configured in polling mode.\n", 352 (of_thermal_get_ntrips(data->tzd) - data->ntrip)); 353 } 354 355 mutex_lock(&data->lock); 356 clk_enable(data->clk); 357 if (!IS_ERR(data->clk_sec)) 358 clk_enable(data->clk_sec); 359 ret = data->tmu_initialize(pdev); 360 clk_disable(data->clk); 361 mutex_unlock(&data->lock); 362 if (!IS_ERR(data->clk_sec)) 363 clk_disable(data->clk_sec); 364 365 return ret; 366 } 367 368 static u32 get_con_reg(struct exynos_tmu_data *data, u32 con) 369 { 370 if (data->soc == SOC_ARCH_EXYNOS4412 || 371 data->soc == SOC_ARCH_EXYNOS3250) 372 con |= (EXYNOS4412_MUX_ADDR_VALUE << EXYNOS4412_MUX_ADDR_SHIFT); 373 374 con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK << EXYNOS_TMU_REF_VOLTAGE_SHIFT); 375 con |= data->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT; 376 377 con &= ~(EXYNOS_TMU_BUF_SLOPE_SEL_MASK << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT); 378 con |= (data->gain << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT); 379 380 con &= ~(EXYNOS_TMU_TRIP_MODE_MASK << EXYNOS_TMU_TRIP_MODE_SHIFT); 381 con |= (EXYNOS_NOISE_CANCEL_MODE << EXYNOS_TMU_TRIP_MODE_SHIFT); 382 383 return con; 384 } 385 386 static void exynos_tmu_control(struct platform_device *pdev, bool on) 387 { 388 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 389 390 mutex_lock(&data->lock); 391 clk_enable(data->clk); 392 data->tmu_control(pdev, on); 393 data->enabled = on; 394 clk_disable(data->clk); 395 mutex_unlock(&data->lock); 396 } 397 398 static int exynos4210_tmu_initialize(struct platform_device *pdev) 399 { 400 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 401 struct thermal_zone_device *tz = data->tzd; 402 const struct thermal_trip * const trips = 403 of_thermal_get_trip_points(tz); 404 int ret = 0, threshold_code, i; 405 unsigned long reference, temp; 406 unsigned int status; 407 408 if (!trips) { 409 pr_err("%s: Cannot get trip points from of-thermal.c!\n", 410 __func__); 411 ret = -ENODEV; 412 goto out; 413 } 414 415 status = readb(data->base + EXYNOS_TMU_REG_STATUS); 416 if (!status) { 417 ret = -EBUSY; 418 goto out; 419 } 420 421 sanitize_temp_error(data, readl(data->base + EXYNOS_TMU_REG_TRIMINFO)); 422 423 /* Write temperature code for threshold */ 424 reference = trips[0].temperature / MCELSIUS; 425 threshold_code = temp_to_code(data, reference); 426 if (threshold_code < 0) { 427 ret = threshold_code; 428 goto out; 429 } 430 writeb(threshold_code, data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP); 431 432 for (i = 0; i < of_thermal_get_ntrips(tz); i++) { 433 temp = trips[i].temperature / MCELSIUS; 434 writeb(temp - reference, data->base + 435 EXYNOS4210_TMU_REG_TRIG_LEVEL0 + i * 4); 436 } 437 438 data->tmu_clear_irqs(data); 439 out: 440 return ret; 441 } 442 443 static int exynos4412_tmu_initialize(struct platform_device *pdev) 444 { 445 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 446 const struct thermal_trip * const trips = 447 of_thermal_get_trip_points(data->tzd); 448 unsigned int status, trim_info, con, ctrl, rising_threshold; 449 int ret = 0, threshold_code, i; 450 unsigned long crit_temp = 0; 451 452 status = readb(data->base + EXYNOS_TMU_REG_STATUS); 453 if (!status) { 454 ret = -EBUSY; 455 goto out; 456 } 457 458 if (data->soc == SOC_ARCH_EXYNOS3250 || 459 data->soc == SOC_ARCH_EXYNOS4412 || 460 data->soc == SOC_ARCH_EXYNOS5250) { 461 if (data->soc == SOC_ARCH_EXYNOS3250) { 462 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON1); 463 ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE; 464 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON1); 465 } 466 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON2); 467 ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE; 468 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON2); 469 } 470 471 /* On exynos5420 the triminfo register is in the shared space */ 472 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) 473 trim_info = readl(data->base_second + EXYNOS_TMU_REG_TRIMINFO); 474 else 475 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); 476 477 sanitize_temp_error(data, trim_info); 478 479 /* Write temperature code for rising and falling threshold */ 480 rising_threshold = readl(data->base + EXYNOS_THD_TEMP_RISE); 481 rising_threshold = get_th_reg(data, rising_threshold, false); 482 writel(rising_threshold, data->base + EXYNOS_THD_TEMP_RISE); 483 writel(get_th_reg(data, 0, true), data->base + EXYNOS_THD_TEMP_FALL); 484 485 data->tmu_clear_irqs(data); 486 487 /* if last threshold limit is also present */ 488 for (i = 0; i < of_thermal_get_ntrips(data->tzd); i++) { 489 if (trips[i].type == THERMAL_TRIP_CRITICAL) { 490 crit_temp = trips[i].temperature; 491 break; 492 } 493 } 494 495 if (i == of_thermal_get_ntrips(data->tzd)) { 496 pr_err("%s: No CRITICAL trip point defined at of-thermal.c!\n", 497 __func__); 498 ret = -EINVAL; 499 goto out; 500 } 501 502 threshold_code = temp_to_code(data, crit_temp / MCELSIUS); 503 /* 1-4 level to be assigned in th0 reg */ 504 rising_threshold &= ~(0xff << 8 * i); 505 rising_threshold |= threshold_code << 8 * i; 506 writel(rising_threshold, data->base + EXYNOS_THD_TEMP_RISE); 507 con = readl(data->base + EXYNOS_TMU_REG_CONTROL); 508 con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT); 509 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 510 511 out: 512 return ret; 513 } 514 515 static int exynos5433_tmu_initialize(struct platform_device *pdev) 516 { 517 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 518 struct thermal_zone_device *tz = data->tzd; 519 unsigned int status, trim_info; 520 unsigned int rising_threshold = 0, falling_threshold = 0; 521 int temp, temp_hist; 522 int ret = 0, threshold_code, i, sensor_id, cal_type; 523 524 status = readb(data->base + EXYNOS_TMU_REG_STATUS); 525 if (!status) { 526 ret = -EBUSY; 527 goto out; 528 } 529 530 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); 531 sanitize_temp_error(data, trim_info); 532 533 /* Read the temperature sensor id */ 534 sensor_id = (trim_info & EXYNOS5433_TRIMINFO_SENSOR_ID_MASK) 535 >> EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT; 536 dev_info(&pdev->dev, "Temperature sensor ID: 0x%x\n", sensor_id); 537 538 /* Read the calibration mode */ 539 writel(trim_info, data->base + EXYNOS_TMU_REG_TRIMINFO); 540 cal_type = (trim_info & EXYNOS5433_TRIMINFO_CALIB_SEL_MASK) 541 >> EXYNOS5433_TRIMINFO_CALIB_SEL_SHIFT; 542 543 switch (cal_type) { 544 case EXYNOS5433_TRIMINFO_TWO_POINT_TRIMMING: 545 data->cal_type = TYPE_TWO_POINT_TRIMMING; 546 break; 547 case EXYNOS5433_TRIMINFO_ONE_POINT_TRIMMING: 548 default: 549 data->cal_type = TYPE_ONE_POINT_TRIMMING; 550 break; 551 } 552 553 dev_info(&pdev->dev, "Calibration type is %d-point calibration\n", 554 cal_type ? 2 : 1); 555 556 /* Write temperature code for rising and falling threshold */ 557 for (i = 0; i < of_thermal_get_ntrips(tz); i++) { 558 int rising_reg_offset, falling_reg_offset; 559 int j = 0; 560 561 switch (i) { 562 case 0: 563 case 1: 564 case 2: 565 case 3: 566 rising_reg_offset = EXYNOS5433_THD_TEMP_RISE3_0; 567 falling_reg_offset = EXYNOS5433_THD_TEMP_FALL3_0; 568 j = i; 569 break; 570 case 4: 571 case 5: 572 case 6: 573 case 7: 574 rising_reg_offset = EXYNOS5433_THD_TEMP_RISE7_4; 575 falling_reg_offset = EXYNOS5433_THD_TEMP_FALL7_4; 576 j = i - 4; 577 break; 578 default: 579 continue; 580 } 581 582 /* Write temperature code for rising threshold */ 583 tz->ops->get_trip_temp(tz, i, &temp); 584 temp /= MCELSIUS; 585 threshold_code = temp_to_code(data, temp); 586 587 rising_threshold = readl(data->base + rising_reg_offset); 588 rising_threshold |= (threshold_code << j * 8); 589 writel(rising_threshold, data->base + rising_reg_offset); 590 591 /* Write temperature code for falling threshold */ 592 tz->ops->get_trip_hyst(tz, i, &temp_hist); 593 temp_hist = temp - (temp_hist / MCELSIUS); 594 threshold_code = temp_to_code(data, temp_hist); 595 596 falling_threshold = readl(data->base + falling_reg_offset); 597 falling_threshold &= ~(0xff << j * 8); 598 falling_threshold |= (threshold_code << j * 8); 599 writel(falling_threshold, data->base + falling_reg_offset); 600 } 601 602 data->tmu_clear_irqs(data); 603 out: 604 return ret; 605 } 606 607 static int exynos5440_tmu_initialize(struct platform_device *pdev) 608 { 609 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 610 unsigned int trim_info = 0, con, rising_threshold; 611 int threshold_code; 612 int crit_temp = 0; 613 614 /* 615 * For exynos5440 soc triminfo value is swapped between TMU0 and 616 * TMU2, so the below logic is needed. 617 */ 618 switch (data->id) { 619 case 0: 620 trim_info = readl(data->base + EXYNOS5440_EFUSE_SWAP_OFFSET + 621 EXYNOS5440_TMU_S0_7_TRIM); 622 break; 623 case 1: 624 trim_info = readl(data->base + EXYNOS5440_TMU_S0_7_TRIM); 625 break; 626 case 2: 627 trim_info = readl(data->base - EXYNOS5440_EFUSE_SWAP_OFFSET + 628 EXYNOS5440_TMU_S0_7_TRIM); 629 } 630 sanitize_temp_error(data, trim_info); 631 632 /* Write temperature code for rising and falling threshold */ 633 rising_threshold = readl(data->base + EXYNOS5440_TMU_S0_7_TH0); 634 rising_threshold = get_th_reg(data, rising_threshold, false); 635 writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH0); 636 writel(0, data->base + EXYNOS5440_TMU_S0_7_TH1); 637 638 data->tmu_clear_irqs(data); 639 640 /* if last threshold limit is also present */ 641 if (!data->tzd->ops->get_crit_temp(data->tzd, &crit_temp)) { 642 threshold_code = temp_to_code(data, crit_temp / MCELSIUS); 643 /* 5th level to be assigned in th2 reg */ 644 rising_threshold = 645 threshold_code << EXYNOS5440_TMU_TH_RISE4_SHIFT; 646 writel(rising_threshold, data->base + EXYNOS5440_TMU_S0_7_TH2); 647 con = readl(data->base + EXYNOS5440_TMU_S0_7_CTRL); 648 con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT); 649 writel(con, data->base + EXYNOS5440_TMU_S0_7_CTRL); 650 } 651 /* Clear the PMIN in the common TMU register */ 652 if (!data->id) 653 writel(0, data->base_second + EXYNOS5440_TMU_PMIN); 654 655 return 0; 656 } 657 658 static int exynos7_tmu_initialize(struct platform_device *pdev) 659 { 660 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 661 struct thermal_zone_device *tz = data->tzd; 662 unsigned int status, trim_info; 663 unsigned int rising_threshold = 0, falling_threshold = 0; 664 int ret = 0, threshold_code, i; 665 int temp, temp_hist; 666 unsigned int reg_off, bit_off; 667 668 status = readb(data->base + EXYNOS_TMU_REG_STATUS); 669 if (!status) { 670 ret = -EBUSY; 671 goto out; 672 } 673 674 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); 675 676 data->temp_error1 = trim_info & EXYNOS7_TMU_TEMP_MASK; 677 if (!data->temp_error1 || 678 (data->min_efuse_value > data->temp_error1) || 679 (data->temp_error1 > data->max_efuse_value)) 680 data->temp_error1 = data->efuse_value & EXYNOS_TMU_TEMP_MASK; 681 682 /* Write temperature code for rising and falling threshold */ 683 for (i = (of_thermal_get_ntrips(tz) - 1); i >= 0; i--) { 684 /* 685 * On exynos7 there are 4 rising and 4 falling threshold 686 * registers (0x50-0x5c and 0x60-0x6c respectively). Each 687 * register holds the value of two threshold levels (at bit 688 * offsets 0 and 16). Based on the fact that there are atmost 689 * eight possible trigger levels, calculate the register and 690 * bit offsets where the threshold levels are to be written. 691 * 692 * e.g. EXYNOS7_THD_TEMP_RISE7_6 (0x50) 693 * [24:16] - Threshold level 7 694 * [8:0] - Threshold level 6 695 * e.g. EXYNOS7_THD_TEMP_RISE5_4 (0x54) 696 * [24:16] - Threshold level 5 697 * [8:0] - Threshold level 4 698 * 699 * and similarly for falling thresholds. 700 * 701 * Based on the above, calculate the register and bit offsets 702 * for rising/falling threshold levels and populate them. 703 */ 704 reg_off = ((7 - i) / 2) * 4; 705 bit_off = ((8 - i) % 2); 706 707 tz->ops->get_trip_temp(tz, i, &temp); 708 temp /= MCELSIUS; 709 710 tz->ops->get_trip_hyst(tz, i, &temp_hist); 711 temp_hist = temp - (temp_hist / MCELSIUS); 712 713 /* Set 9-bit temperature code for rising threshold levels */ 714 threshold_code = temp_to_code(data, temp); 715 rising_threshold = readl(data->base + 716 EXYNOS7_THD_TEMP_RISE7_6 + reg_off); 717 rising_threshold &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off)); 718 rising_threshold |= threshold_code << (16 * bit_off); 719 writel(rising_threshold, 720 data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off); 721 722 /* Set 9-bit temperature code for falling threshold levels */ 723 threshold_code = temp_to_code(data, temp_hist); 724 falling_threshold &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off)); 725 falling_threshold |= threshold_code << (16 * bit_off); 726 writel(falling_threshold, 727 data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off); 728 } 729 730 data->tmu_clear_irqs(data); 731 out: 732 return ret; 733 } 734 735 static void exynos4210_tmu_control(struct platform_device *pdev, bool on) 736 { 737 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 738 struct thermal_zone_device *tz = data->tzd; 739 unsigned int con, interrupt_en; 740 741 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); 742 743 if (on) { 744 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); 745 interrupt_en = 746 (of_thermal_is_trip_valid(tz, 3) 747 << EXYNOS_TMU_INTEN_RISE3_SHIFT) | 748 (of_thermal_is_trip_valid(tz, 2) 749 << EXYNOS_TMU_INTEN_RISE2_SHIFT) | 750 (of_thermal_is_trip_valid(tz, 1) 751 << EXYNOS_TMU_INTEN_RISE1_SHIFT) | 752 (of_thermal_is_trip_valid(tz, 0) 753 << EXYNOS_TMU_INTEN_RISE0_SHIFT); 754 755 if (data->soc != SOC_ARCH_EXYNOS4210) 756 interrupt_en |= 757 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; 758 } else { 759 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); 760 interrupt_en = 0; /* Disable all interrupts */ 761 } 762 writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN); 763 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 764 } 765 766 static void exynos5433_tmu_control(struct platform_device *pdev, bool on) 767 { 768 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 769 struct thermal_zone_device *tz = data->tzd; 770 unsigned int con, interrupt_en, pd_det_en; 771 772 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); 773 774 if (on) { 775 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); 776 interrupt_en = 777 (of_thermal_is_trip_valid(tz, 7) 778 << EXYNOS7_TMU_INTEN_RISE7_SHIFT) | 779 (of_thermal_is_trip_valid(tz, 6) 780 << EXYNOS7_TMU_INTEN_RISE6_SHIFT) | 781 (of_thermal_is_trip_valid(tz, 5) 782 << EXYNOS7_TMU_INTEN_RISE5_SHIFT) | 783 (of_thermal_is_trip_valid(tz, 4) 784 << EXYNOS7_TMU_INTEN_RISE4_SHIFT) | 785 (of_thermal_is_trip_valid(tz, 3) 786 << EXYNOS7_TMU_INTEN_RISE3_SHIFT) | 787 (of_thermal_is_trip_valid(tz, 2) 788 << EXYNOS7_TMU_INTEN_RISE2_SHIFT) | 789 (of_thermal_is_trip_valid(tz, 1) 790 << EXYNOS7_TMU_INTEN_RISE1_SHIFT) | 791 (of_thermal_is_trip_valid(tz, 0) 792 << EXYNOS7_TMU_INTEN_RISE0_SHIFT); 793 794 interrupt_en |= 795 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; 796 } else { 797 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); 798 interrupt_en = 0; /* Disable all interrupts */ 799 } 800 801 pd_det_en = on ? EXYNOS5433_PD_DET_EN : 0; 802 803 writel(pd_det_en, data->base + EXYNOS5433_TMU_PD_DET_EN); 804 writel(interrupt_en, data->base + EXYNOS5433_TMU_REG_INTEN); 805 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 806 } 807 808 static void exynos5440_tmu_control(struct platform_device *pdev, bool on) 809 { 810 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 811 struct thermal_zone_device *tz = data->tzd; 812 unsigned int con, interrupt_en; 813 814 con = get_con_reg(data, readl(data->base + EXYNOS5440_TMU_S0_7_CTRL)); 815 816 if (on) { 817 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); 818 interrupt_en = 819 (of_thermal_is_trip_valid(tz, 3) 820 << EXYNOS5440_TMU_INTEN_RISE3_SHIFT) | 821 (of_thermal_is_trip_valid(tz, 2) 822 << EXYNOS5440_TMU_INTEN_RISE2_SHIFT) | 823 (of_thermal_is_trip_valid(tz, 1) 824 << EXYNOS5440_TMU_INTEN_RISE1_SHIFT) | 825 (of_thermal_is_trip_valid(tz, 0) 826 << EXYNOS5440_TMU_INTEN_RISE0_SHIFT); 827 interrupt_en |= 828 interrupt_en << EXYNOS5440_TMU_INTEN_FALL0_SHIFT; 829 } else { 830 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); 831 interrupt_en = 0; /* Disable all interrupts */ 832 } 833 writel(interrupt_en, data->base + EXYNOS5440_TMU_S0_7_IRQEN); 834 writel(con, data->base + EXYNOS5440_TMU_S0_7_CTRL); 835 } 836 837 static void exynos7_tmu_control(struct platform_device *pdev, bool on) 838 { 839 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 840 struct thermal_zone_device *tz = data->tzd; 841 unsigned int con, interrupt_en; 842 843 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); 844 845 if (on) { 846 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); 847 con |= (1 << EXYNOS7_PD_DET_EN_SHIFT); 848 interrupt_en = 849 (of_thermal_is_trip_valid(tz, 7) 850 << EXYNOS7_TMU_INTEN_RISE7_SHIFT) | 851 (of_thermal_is_trip_valid(tz, 6) 852 << EXYNOS7_TMU_INTEN_RISE6_SHIFT) | 853 (of_thermal_is_trip_valid(tz, 5) 854 << EXYNOS7_TMU_INTEN_RISE5_SHIFT) | 855 (of_thermal_is_trip_valid(tz, 4) 856 << EXYNOS7_TMU_INTEN_RISE4_SHIFT) | 857 (of_thermal_is_trip_valid(tz, 3) 858 << EXYNOS7_TMU_INTEN_RISE3_SHIFT) | 859 (of_thermal_is_trip_valid(tz, 2) 860 << EXYNOS7_TMU_INTEN_RISE2_SHIFT) | 861 (of_thermal_is_trip_valid(tz, 1) 862 << EXYNOS7_TMU_INTEN_RISE1_SHIFT) | 863 (of_thermal_is_trip_valid(tz, 0) 864 << EXYNOS7_TMU_INTEN_RISE0_SHIFT); 865 866 interrupt_en |= 867 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; 868 } else { 869 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); 870 con &= ~(1 << EXYNOS7_PD_DET_EN_SHIFT); 871 interrupt_en = 0; /* Disable all interrupts */ 872 } 873 874 writel(interrupt_en, data->base + EXYNOS7_TMU_REG_INTEN); 875 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 876 } 877 878 static int exynos_get_temp(void *p, int *temp) 879 { 880 struct exynos_tmu_data *data = p; 881 int value, ret = 0; 882 883 if (!data || !data->tmu_read || !data->enabled) 884 return -EINVAL; 885 886 mutex_lock(&data->lock); 887 clk_enable(data->clk); 888 889 value = data->tmu_read(data); 890 if (value < 0) 891 ret = value; 892 else 893 *temp = code_to_temp(data, value) * MCELSIUS; 894 895 clk_disable(data->clk); 896 mutex_unlock(&data->lock); 897 898 return ret; 899 } 900 901 #ifdef CONFIG_THERMAL_EMULATION 902 static u32 get_emul_con_reg(struct exynos_tmu_data *data, unsigned int val, 903 int temp) 904 { 905 if (temp) { 906 temp /= MCELSIUS; 907 908 if (data->soc != SOC_ARCH_EXYNOS5440) { 909 val &= ~(EXYNOS_EMUL_TIME_MASK << EXYNOS_EMUL_TIME_SHIFT); 910 val |= (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT); 911 } 912 if (data->soc == SOC_ARCH_EXYNOS7) { 913 val &= ~(EXYNOS7_EMUL_DATA_MASK << 914 EXYNOS7_EMUL_DATA_SHIFT); 915 val |= (temp_to_code(data, temp) << 916 EXYNOS7_EMUL_DATA_SHIFT) | 917 EXYNOS_EMUL_ENABLE; 918 } else { 919 val &= ~(EXYNOS_EMUL_DATA_MASK << 920 EXYNOS_EMUL_DATA_SHIFT); 921 val |= (temp_to_code(data, temp) << 922 EXYNOS_EMUL_DATA_SHIFT) | 923 EXYNOS_EMUL_ENABLE; 924 } 925 } else { 926 val &= ~EXYNOS_EMUL_ENABLE; 927 } 928 929 return val; 930 } 931 932 static void exynos4412_tmu_set_emulation(struct exynos_tmu_data *data, 933 int temp) 934 { 935 unsigned int val; 936 u32 emul_con; 937 938 if (data->soc == SOC_ARCH_EXYNOS5260) 939 emul_con = EXYNOS5260_EMUL_CON; 940 else if (data->soc == SOC_ARCH_EXYNOS5433) 941 emul_con = EXYNOS5433_TMU_EMUL_CON; 942 else if (data->soc == SOC_ARCH_EXYNOS7) 943 emul_con = EXYNOS7_TMU_REG_EMUL_CON; 944 else 945 emul_con = EXYNOS_EMUL_CON; 946 947 val = readl(data->base + emul_con); 948 val = get_emul_con_reg(data, val, temp); 949 writel(val, data->base + emul_con); 950 } 951 952 static void exynos5440_tmu_set_emulation(struct exynos_tmu_data *data, 953 int temp) 954 { 955 unsigned int val; 956 957 val = readl(data->base + EXYNOS5440_TMU_S0_7_DEBUG); 958 val = get_emul_con_reg(data, val, temp); 959 writel(val, data->base + EXYNOS5440_TMU_S0_7_DEBUG); 960 } 961 962 static int exynos_tmu_set_emulation(void *drv_data, int temp) 963 { 964 struct exynos_tmu_data *data = drv_data; 965 int ret = -EINVAL; 966 967 if (data->soc == SOC_ARCH_EXYNOS4210) 968 goto out; 969 970 if (temp && temp < MCELSIUS) 971 goto out; 972 973 mutex_lock(&data->lock); 974 clk_enable(data->clk); 975 data->tmu_set_emulation(data, temp); 976 clk_disable(data->clk); 977 mutex_unlock(&data->lock); 978 return 0; 979 out: 980 return ret; 981 } 982 #else 983 #define exynos4412_tmu_set_emulation NULL 984 #define exynos5440_tmu_set_emulation NULL 985 static int exynos_tmu_set_emulation(void *drv_data, int temp) 986 { return -EINVAL; } 987 #endif /* CONFIG_THERMAL_EMULATION */ 988 989 static int exynos4210_tmu_read(struct exynos_tmu_data *data) 990 { 991 int ret = readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP); 992 993 /* "temp_code" should range between 75 and 175 */ 994 return (ret < 75 || ret > 175) ? -ENODATA : ret; 995 } 996 997 static int exynos4412_tmu_read(struct exynos_tmu_data *data) 998 { 999 return readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP); 1000 } 1001 1002 static int exynos5440_tmu_read(struct exynos_tmu_data *data) 1003 { 1004 return readb(data->base + EXYNOS5440_TMU_S0_7_TEMP); 1005 } 1006 1007 static int exynos7_tmu_read(struct exynos_tmu_data *data) 1008 { 1009 return readw(data->base + EXYNOS_TMU_REG_CURRENT_TEMP) & 1010 EXYNOS7_TMU_TEMP_MASK; 1011 } 1012 1013 static void exynos_tmu_work(struct work_struct *work) 1014 { 1015 struct exynos_tmu_data *data = container_of(work, 1016 struct exynos_tmu_data, irq_work); 1017 unsigned int val_type; 1018 1019 if (!IS_ERR(data->clk_sec)) 1020 clk_enable(data->clk_sec); 1021 /* Find which sensor generated this interrupt */ 1022 if (data->soc == SOC_ARCH_EXYNOS5440) { 1023 val_type = readl(data->base_second + EXYNOS5440_TMU_IRQ_STATUS); 1024 if (!((val_type >> data->id) & 0x1)) 1025 goto out; 1026 } 1027 if (!IS_ERR(data->clk_sec)) 1028 clk_disable(data->clk_sec); 1029 1030 exynos_report_trigger(data); 1031 mutex_lock(&data->lock); 1032 clk_enable(data->clk); 1033 1034 /* TODO: take action based on particular interrupt */ 1035 data->tmu_clear_irqs(data); 1036 1037 clk_disable(data->clk); 1038 mutex_unlock(&data->lock); 1039 out: 1040 enable_irq(data->irq); 1041 } 1042 1043 static void exynos4210_tmu_clear_irqs(struct exynos_tmu_data *data) 1044 { 1045 unsigned int val_irq; 1046 u32 tmu_intstat, tmu_intclear; 1047 1048 if (data->soc == SOC_ARCH_EXYNOS5260) { 1049 tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT; 1050 tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR; 1051 } else if (data->soc == SOC_ARCH_EXYNOS7) { 1052 tmu_intstat = EXYNOS7_TMU_REG_INTPEND; 1053 tmu_intclear = EXYNOS7_TMU_REG_INTPEND; 1054 } else if (data->soc == SOC_ARCH_EXYNOS5433) { 1055 tmu_intstat = EXYNOS5433_TMU_REG_INTPEND; 1056 tmu_intclear = EXYNOS5433_TMU_REG_INTPEND; 1057 } else { 1058 tmu_intstat = EXYNOS_TMU_REG_INTSTAT; 1059 tmu_intclear = EXYNOS_TMU_REG_INTCLEAR; 1060 } 1061 1062 val_irq = readl(data->base + tmu_intstat); 1063 /* 1064 * Clear the interrupts. Please note that the documentation for 1065 * Exynos3250, Exynos4412, Exynos5250 and Exynos5260 incorrectly 1066 * states that INTCLEAR register has a different placing of bits 1067 * responsible for FALL IRQs than INTSTAT register. Exynos5420 1068 * and Exynos5440 documentation is correct (Exynos4210 doesn't 1069 * support FALL IRQs at all). 1070 */ 1071 writel(val_irq, data->base + tmu_intclear); 1072 } 1073 1074 static void exynos5440_tmu_clear_irqs(struct exynos_tmu_data *data) 1075 { 1076 unsigned int val_irq; 1077 1078 val_irq = readl(data->base + EXYNOS5440_TMU_S0_7_IRQ); 1079 /* clear the interrupts */ 1080 writel(val_irq, data->base + EXYNOS5440_TMU_S0_7_IRQ); 1081 } 1082 1083 static irqreturn_t exynos_tmu_irq(int irq, void *id) 1084 { 1085 struct exynos_tmu_data *data = id; 1086 1087 disable_irq_nosync(irq); 1088 schedule_work(&data->irq_work); 1089 1090 return IRQ_HANDLED; 1091 } 1092 1093 static const struct of_device_id exynos_tmu_match[] = { 1094 { 1095 .compatible = "samsung,exynos3250-tmu", 1096 .data = (const void *)SOC_ARCH_EXYNOS3250, 1097 }, { 1098 .compatible = "samsung,exynos4210-tmu", 1099 .data = (const void *)SOC_ARCH_EXYNOS4210, 1100 }, { 1101 .compatible = "samsung,exynos4412-tmu", 1102 .data = (const void *)SOC_ARCH_EXYNOS4412, 1103 }, { 1104 .compatible = "samsung,exynos5250-tmu", 1105 .data = (const void *)SOC_ARCH_EXYNOS5250, 1106 }, { 1107 .compatible = "samsung,exynos5260-tmu", 1108 .data = (const void *)SOC_ARCH_EXYNOS5260, 1109 }, { 1110 .compatible = "samsung,exynos5420-tmu", 1111 .data = (const void *)SOC_ARCH_EXYNOS5420, 1112 }, { 1113 .compatible = "samsung,exynos5420-tmu-ext-triminfo", 1114 .data = (const void *)SOC_ARCH_EXYNOS5420_TRIMINFO, 1115 }, { 1116 .compatible = "samsung,exynos5433-tmu", 1117 .data = (const void *)SOC_ARCH_EXYNOS5433, 1118 }, { 1119 .compatible = "samsung,exynos5440-tmu", 1120 .data = (const void *)SOC_ARCH_EXYNOS5440, 1121 }, { 1122 .compatible = "samsung,exynos7-tmu", 1123 .data = (const void *)SOC_ARCH_EXYNOS7, 1124 }, 1125 { }, 1126 }; 1127 MODULE_DEVICE_TABLE(of, exynos_tmu_match); 1128 1129 static int exynos_map_dt_data(struct platform_device *pdev) 1130 { 1131 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 1132 struct resource res; 1133 1134 if (!data || !pdev->dev.of_node) 1135 return -ENODEV; 1136 1137 data->id = of_alias_get_id(pdev->dev.of_node, "tmuctrl"); 1138 if (data->id < 0) 1139 data->id = 0; 1140 1141 data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 1142 if (data->irq <= 0) { 1143 dev_err(&pdev->dev, "failed to get IRQ\n"); 1144 return -ENODEV; 1145 } 1146 1147 if (of_address_to_resource(pdev->dev.of_node, 0, &res)) { 1148 dev_err(&pdev->dev, "failed to get Resource 0\n"); 1149 return -ENODEV; 1150 } 1151 1152 data->base = devm_ioremap(&pdev->dev, res.start, resource_size(&res)); 1153 if (!data->base) { 1154 dev_err(&pdev->dev, "Failed to ioremap memory\n"); 1155 return -EADDRNOTAVAIL; 1156 } 1157 1158 data->soc = (enum soc_type)of_device_get_match_data(&pdev->dev); 1159 1160 switch (data->soc) { 1161 case SOC_ARCH_EXYNOS4210: 1162 data->tmu_initialize = exynos4210_tmu_initialize; 1163 data->tmu_control = exynos4210_tmu_control; 1164 data->tmu_read = exynos4210_tmu_read; 1165 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; 1166 data->ntrip = 4; 1167 data->gain = 15; 1168 data->reference_voltage = 7; 1169 data->efuse_value = 55; 1170 data->min_efuse_value = 40; 1171 data->max_efuse_value = 100; 1172 break; 1173 case SOC_ARCH_EXYNOS3250: 1174 case SOC_ARCH_EXYNOS4412: 1175 case SOC_ARCH_EXYNOS5250: 1176 case SOC_ARCH_EXYNOS5260: 1177 case SOC_ARCH_EXYNOS5420: 1178 case SOC_ARCH_EXYNOS5420_TRIMINFO: 1179 data->tmu_initialize = exynos4412_tmu_initialize; 1180 data->tmu_control = exynos4210_tmu_control; 1181 data->tmu_read = exynos4412_tmu_read; 1182 data->tmu_set_emulation = exynos4412_tmu_set_emulation; 1183 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; 1184 data->ntrip = 4; 1185 data->gain = 8; 1186 data->reference_voltage = 16; 1187 data->efuse_value = 55; 1188 if (data->soc != SOC_ARCH_EXYNOS5420 && 1189 data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO) 1190 data->min_efuse_value = 40; 1191 else 1192 data->min_efuse_value = 0; 1193 data->max_efuse_value = 100; 1194 break; 1195 case SOC_ARCH_EXYNOS5433: 1196 data->tmu_initialize = exynos5433_tmu_initialize; 1197 data->tmu_control = exynos5433_tmu_control; 1198 data->tmu_read = exynos4412_tmu_read; 1199 data->tmu_set_emulation = exynos4412_tmu_set_emulation; 1200 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; 1201 data->ntrip = 8; 1202 data->gain = 8; 1203 if (res.start == EXYNOS5433_G3D_BASE) 1204 data->reference_voltage = 23; 1205 else 1206 data->reference_voltage = 16; 1207 data->efuse_value = 75; 1208 data->min_efuse_value = 40; 1209 data->max_efuse_value = 150; 1210 break; 1211 case SOC_ARCH_EXYNOS5440: 1212 data->tmu_initialize = exynos5440_tmu_initialize; 1213 data->tmu_control = exynos5440_tmu_control; 1214 data->tmu_read = exynos5440_tmu_read; 1215 data->tmu_set_emulation = exynos5440_tmu_set_emulation; 1216 data->tmu_clear_irqs = exynos5440_tmu_clear_irqs; 1217 data->ntrip = 4; 1218 data->gain = 5; 1219 data->reference_voltage = 16; 1220 data->efuse_value = 0x5d2d; 1221 data->min_efuse_value = 16; 1222 data->max_efuse_value = 76; 1223 break; 1224 case SOC_ARCH_EXYNOS7: 1225 data->tmu_initialize = exynos7_tmu_initialize; 1226 data->tmu_control = exynos7_tmu_control; 1227 data->tmu_read = exynos7_tmu_read; 1228 data->tmu_set_emulation = exynos4412_tmu_set_emulation; 1229 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; 1230 data->ntrip = 8; 1231 data->gain = 9; 1232 data->reference_voltage = 17; 1233 data->efuse_value = 75; 1234 data->min_efuse_value = 15; 1235 data->max_efuse_value = 100; 1236 break; 1237 default: 1238 dev_err(&pdev->dev, "Platform not supported\n"); 1239 return -EINVAL; 1240 } 1241 1242 data->cal_type = TYPE_ONE_POINT_TRIMMING; 1243 1244 /* 1245 * Check if the TMU shares some registers and then try to map the 1246 * memory of common registers. 1247 */ 1248 if (data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO && 1249 data->soc != SOC_ARCH_EXYNOS5440) 1250 return 0; 1251 1252 if (of_address_to_resource(pdev->dev.of_node, 1, &res)) { 1253 dev_err(&pdev->dev, "failed to get Resource 1\n"); 1254 return -ENODEV; 1255 } 1256 1257 data->base_second = devm_ioremap(&pdev->dev, res.start, 1258 resource_size(&res)); 1259 if (!data->base_second) { 1260 dev_err(&pdev->dev, "Failed to ioremap memory\n"); 1261 return -ENOMEM; 1262 } 1263 1264 return 0; 1265 } 1266 1267 static const struct thermal_zone_of_device_ops exynos_sensor_ops = { 1268 .get_temp = exynos_get_temp, 1269 .set_emul_temp = exynos_tmu_set_emulation, 1270 }; 1271 1272 static int exynos_tmu_probe(struct platform_device *pdev) 1273 { 1274 struct exynos_tmu_data *data; 1275 int ret; 1276 1277 data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data), 1278 GFP_KERNEL); 1279 if (!data) 1280 return -ENOMEM; 1281 1282 platform_set_drvdata(pdev, data); 1283 mutex_init(&data->lock); 1284 1285 /* 1286 * Try enabling the regulator if found 1287 * TODO: Add regulator as an SOC feature, so that regulator enable 1288 * is a compulsory call. 1289 */ 1290 data->regulator = devm_regulator_get_optional(&pdev->dev, "vtmu"); 1291 if (!IS_ERR(data->regulator)) { 1292 ret = regulator_enable(data->regulator); 1293 if (ret) { 1294 dev_err(&pdev->dev, "failed to enable vtmu\n"); 1295 return ret; 1296 } 1297 } else { 1298 if (PTR_ERR(data->regulator) == -EPROBE_DEFER) 1299 return -EPROBE_DEFER; 1300 dev_info(&pdev->dev, "Regulator node (vtmu) not found\n"); 1301 } 1302 1303 ret = exynos_map_dt_data(pdev); 1304 if (ret) 1305 goto err_sensor; 1306 1307 INIT_WORK(&data->irq_work, exynos_tmu_work); 1308 1309 data->clk = devm_clk_get(&pdev->dev, "tmu_apbif"); 1310 if (IS_ERR(data->clk)) { 1311 dev_err(&pdev->dev, "Failed to get clock\n"); 1312 ret = PTR_ERR(data->clk); 1313 goto err_sensor; 1314 } 1315 1316 data->clk_sec = devm_clk_get(&pdev->dev, "tmu_triminfo_apbif"); 1317 if (IS_ERR(data->clk_sec)) { 1318 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) { 1319 dev_err(&pdev->dev, "Failed to get triminfo clock\n"); 1320 ret = PTR_ERR(data->clk_sec); 1321 goto err_sensor; 1322 } 1323 } else { 1324 ret = clk_prepare(data->clk_sec); 1325 if (ret) { 1326 dev_err(&pdev->dev, "Failed to get clock\n"); 1327 goto err_sensor; 1328 } 1329 } 1330 1331 ret = clk_prepare(data->clk); 1332 if (ret) { 1333 dev_err(&pdev->dev, "Failed to get clock\n"); 1334 goto err_clk_sec; 1335 } 1336 1337 switch (data->soc) { 1338 case SOC_ARCH_EXYNOS5433: 1339 case SOC_ARCH_EXYNOS7: 1340 data->sclk = devm_clk_get(&pdev->dev, "tmu_sclk"); 1341 if (IS_ERR(data->sclk)) { 1342 dev_err(&pdev->dev, "Failed to get sclk\n"); 1343 goto err_clk; 1344 } else { 1345 ret = clk_prepare_enable(data->sclk); 1346 if (ret) { 1347 dev_err(&pdev->dev, "Failed to enable sclk\n"); 1348 goto err_clk; 1349 } 1350 } 1351 break; 1352 default: 1353 break; 1354 } 1355 1356 /* 1357 * data->tzd must be registered before calling exynos_tmu_initialize(), 1358 * requesting irq and calling exynos_tmu_control(). 1359 */ 1360 data->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, data, 1361 &exynos_sensor_ops); 1362 if (IS_ERR(data->tzd)) { 1363 ret = PTR_ERR(data->tzd); 1364 dev_err(&pdev->dev, "Failed to register sensor: %d\n", ret); 1365 goto err_sclk; 1366 } 1367 1368 ret = exynos_tmu_initialize(pdev); 1369 if (ret) { 1370 dev_err(&pdev->dev, "Failed to initialize TMU\n"); 1371 goto err_thermal; 1372 } 1373 1374 ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq, 1375 IRQF_TRIGGER_RISING | IRQF_SHARED, dev_name(&pdev->dev), data); 1376 if (ret) { 1377 dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq); 1378 goto err_thermal; 1379 } 1380 1381 exynos_tmu_control(pdev, true); 1382 return 0; 1383 1384 err_thermal: 1385 thermal_zone_of_sensor_unregister(&pdev->dev, data->tzd); 1386 err_sclk: 1387 clk_disable_unprepare(data->sclk); 1388 err_clk: 1389 clk_unprepare(data->clk); 1390 err_clk_sec: 1391 if (!IS_ERR(data->clk_sec)) 1392 clk_unprepare(data->clk_sec); 1393 err_sensor: 1394 if (!IS_ERR(data->regulator)) 1395 regulator_disable(data->regulator); 1396 1397 return ret; 1398 } 1399 1400 static int exynos_tmu_remove(struct platform_device *pdev) 1401 { 1402 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 1403 struct thermal_zone_device *tzd = data->tzd; 1404 1405 thermal_zone_of_sensor_unregister(&pdev->dev, tzd); 1406 exynos_tmu_control(pdev, false); 1407 1408 clk_disable_unprepare(data->sclk); 1409 clk_unprepare(data->clk); 1410 if (!IS_ERR(data->clk_sec)) 1411 clk_unprepare(data->clk_sec); 1412 1413 if (!IS_ERR(data->regulator)) 1414 regulator_disable(data->regulator); 1415 1416 return 0; 1417 } 1418 1419 #ifdef CONFIG_PM_SLEEP 1420 static int exynos_tmu_suspend(struct device *dev) 1421 { 1422 exynos_tmu_control(to_platform_device(dev), false); 1423 1424 return 0; 1425 } 1426 1427 static int exynos_tmu_resume(struct device *dev) 1428 { 1429 struct platform_device *pdev = to_platform_device(dev); 1430 1431 exynos_tmu_initialize(pdev); 1432 exynos_tmu_control(pdev, true); 1433 1434 return 0; 1435 } 1436 1437 static SIMPLE_DEV_PM_OPS(exynos_tmu_pm, 1438 exynos_tmu_suspend, exynos_tmu_resume); 1439 #define EXYNOS_TMU_PM (&exynos_tmu_pm) 1440 #else 1441 #define EXYNOS_TMU_PM NULL 1442 #endif 1443 1444 static struct platform_driver exynos_tmu_driver = { 1445 .driver = { 1446 .name = "exynos-tmu", 1447 .pm = EXYNOS_TMU_PM, 1448 .of_match_table = exynos_tmu_match, 1449 }, 1450 .probe = exynos_tmu_probe, 1451 .remove = exynos_tmu_remove, 1452 }; 1453 1454 module_platform_driver(exynos_tmu_driver); 1455 1456 MODULE_DESCRIPTION("EXYNOS TMU Driver"); 1457 MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>"); 1458 MODULE_LICENSE("GPL"); 1459 MODULE_ALIAS("platform:exynos-tmu"); 1460