1 /* 2 * exynos_tmu.c - Samsung EXYNOS TMU (Thermal Management Unit) 3 * 4 * Copyright (C) 2014 Samsung Electronics 5 * Bartlomiej Zolnierkiewicz <b.zolnierkie@samsung.com> 6 * Lukasz Majewski <l.majewski@samsung.com> 7 * 8 * Copyright (C) 2011 Samsung Electronics 9 * Donggeun Kim <dg77.kim@samsung.com> 10 * Amit Daniel Kachhap <amit.kachhap@linaro.org> 11 * 12 * This program is free software; you can redistribute it and/or modify 13 * it under the terms of the GNU General Public License as published by 14 * the Free Software Foundation; either version 2 of the License, or 15 * (at your option) any later version. 16 * 17 * This program is distributed in the hope that it will be useful, 18 * but WITHOUT ANY WARRANTY; without even the implied warranty of 19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 20 * GNU General Public License for more details. 21 * 22 * You should have received a copy of the GNU General Public License 23 * along with this program; if not, write to the Free Software 24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA 25 * 26 */ 27 28 #include <linux/clk.h> 29 #include <linux/io.h> 30 #include <linux/interrupt.h> 31 #include <linux/module.h> 32 #include <linux/of_device.h> 33 #include <linux/of_address.h> 34 #include <linux/of_irq.h> 35 #include <linux/platform_device.h> 36 #include <linux/regulator/consumer.h> 37 38 #include <dt-bindings/thermal/thermal_exynos.h> 39 40 #include "../thermal_core.h" 41 42 /* Exynos generic registers */ 43 #define EXYNOS_TMU_REG_TRIMINFO 0x0 44 #define EXYNOS_TMU_REG_CONTROL 0x20 45 #define EXYNOS_TMU_REG_STATUS 0x28 46 #define EXYNOS_TMU_REG_CURRENT_TEMP 0x40 47 #define EXYNOS_TMU_REG_INTEN 0x70 48 #define EXYNOS_TMU_REG_INTSTAT 0x74 49 #define EXYNOS_TMU_REG_INTCLEAR 0x78 50 51 #define EXYNOS_TMU_TEMP_MASK 0xff 52 #define EXYNOS_TMU_REF_VOLTAGE_SHIFT 24 53 #define EXYNOS_TMU_REF_VOLTAGE_MASK 0x1f 54 #define EXYNOS_TMU_BUF_SLOPE_SEL_MASK 0xf 55 #define EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT 8 56 #define EXYNOS_TMU_CORE_EN_SHIFT 0 57 58 /* Exynos3250 specific registers */ 59 #define EXYNOS_TMU_TRIMINFO_CON1 0x10 60 61 /* Exynos4210 specific registers */ 62 #define EXYNOS4210_TMU_REG_THRESHOLD_TEMP 0x44 63 #define EXYNOS4210_TMU_REG_TRIG_LEVEL0 0x50 64 65 /* Exynos5250, Exynos4412, Exynos3250 specific registers */ 66 #define EXYNOS_TMU_TRIMINFO_CON2 0x14 67 #define EXYNOS_THD_TEMP_RISE 0x50 68 #define EXYNOS_THD_TEMP_FALL 0x54 69 #define EXYNOS_EMUL_CON 0x80 70 71 #define EXYNOS_TRIMINFO_RELOAD_ENABLE 1 72 #define EXYNOS_TRIMINFO_25_SHIFT 0 73 #define EXYNOS_TRIMINFO_85_SHIFT 8 74 #define EXYNOS_TMU_TRIP_MODE_SHIFT 13 75 #define EXYNOS_TMU_TRIP_MODE_MASK 0x7 76 #define EXYNOS_TMU_THERM_TRIP_EN_SHIFT 12 77 78 #define EXYNOS_TMU_INTEN_RISE0_SHIFT 0 79 #define EXYNOS_TMU_INTEN_RISE1_SHIFT 4 80 #define EXYNOS_TMU_INTEN_RISE2_SHIFT 8 81 #define EXYNOS_TMU_INTEN_RISE3_SHIFT 12 82 #define EXYNOS_TMU_INTEN_FALL0_SHIFT 16 83 84 #define EXYNOS_EMUL_TIME 0x57F0 85 #define EXYNOS_EMUL_TIME_MASK 0xffff 86 #define EXYNOS_EMUL_TIME_SHIFT 16 87 #define EXYNOS_EMUL_DATA_SHIFT 8 88 #define EXYNOS_EMUL_DATA_MASK 0xFF 89 #define EXYNOS_EMUL_ENABLE 0x1 90 91 /* Exynos5260 specific */ 92 #define EXYNOS5260_TMU_REG_INTEN 0xC0 93 #define EXYNOS5260_TMU_REG_INTSTAT 0xC4 94 #define EXYNOS5260_TMU_REG_INTCLEAR 0xC8 95 #define EXYNOS5260_EMUL_CON 0x100 96 97 /* Exynos4412 specific */ 98 #define EXYNOS4412_MUX_ADDR_VALUE 6 99 #define EXYNOS4412_MUX_ADDR_SHIFT 20 100 101 /* Exynos5433 specific registers */ 102 #define EXYNOS5433_TMU_REG_CONTROL1 0x024 103 #define EXYNOS5433_TMU_SAMPLING_INTERVAL 0x02c 104 #define EXYNOS5433_TMU_COUNTER_VALUE0 0x030 105 #define EXYNOS5433_TMU_COUNTER_VALUE1 0x034 106 #define EXYNOS5433_TMU_REG_CURRENT_TEMP1 0x044 107 #define EXYNOS5433_THD_TEMP_RISE3_0 0x050 108 #define EXYNOS5433_THD_TEMP_RISE7_4 0x054 109 #define EXYNOS5433_THD_TEMP_FALL3_0 0x060 110 #define EXYNOS5433_THD_TEMP_FALL7_4 0x064 111 #define EXYNOS5433_TMU_REG_INTEN 0x0c0 112 #define EXYNOS5433_TMU_REG_INTPEND 0x0c8 113 #define EXYNOS5433_TMU_EMUL_CON 0x110 114 #define EXYNOS5433_TMU_PD_DET_EN 0x130 115 116 #define EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT 16 117 #define EXYNOS5433_TRIMINFO_CALIB_SEL_SHIFT 23 118 #define EXYNOS5433_TRIMINFO_SENSOR_ID_MASK \ 119 (0xf << EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT) 120 #define EXYNOS5433_TRIMINFO_CALIB_SEL_MASK BIT(23) 121 122 #define EXYNOS5433_TRIMINFO_ONE_POINT_TRIMMING 0 123 #define EXYNOS5433_TRIMINFO_TWO_POINT_TRIMMING 1 124 125 #define EXYNOS5433_PD_DET_EN 1 126 127 #define EXYNOS5433_G3D_BASE 0x10070000 128 129 /* Exynos7 specific registers */ 130 #define EXYNOS7_THD_TEMP_RISE7_6 0x50 131 #define EXYNOS7_THD_TEMP_FALL7_6 0x60 132 #define EXYNOS7_TMU_REG_INTEN 0x110 133 #define EXYNOS7_TMU_REG_INTPEND 0x118 134 #define EXYNOS7_TMU_REG_EMUL_CON 0x160 135 136 #define EXYNOS7_TMU_TEMP_MASK 0x1ff 137 #define EXYNOS7_PD_DET_EN_SHIFT 23 138 #define EXYNOS7_TMU_INTEN_RISE0_SHIFT 0 139 #define EXYNOS7_TMU_INTEN_RISE1_SHIFT 1 140 #define EXYNOS7_TMU_INTEN_RISE2_SHIFT 2 141 #define EXYNOS7_TMU_INTEN_RISE3_SHIFT 3 142 #define EXYNOS7_TMU_INTEN_RISE4_SHIFT 4 143 #define EXYNOS7_TMU_INTEN_RISE5_SHIFT 5 144 #define EXYNOS7_TMU_INTEN_RISE6_SHIFT 6 145 #define EXYNOS7_TMU_INTEN_RISE7_SHIFT 7 146 #define EXYNOS7_EMUL_DATA_SHIFT 7 147 #define EXYNOS7_EMUL_DATA_MASK 0x1ff 148 149 #define EXYNOS_FIRST_POINT_TRIM 25 150 #define EXYNOS_SECOND_POINT_TRIM 85 151 152 #define EXYNOS_NOISE_CANCEL_MODE 4 153 154 #define MCELSIUS 1000 155 156 enum soc_type { 157 SOC_ARCH_EXYNOS3250 = 1, 158 SOC_ARCH_EXYNOS4210, 159 SOC_ARCH_EXYNOS4412, 160 SOC_ARCH_EXYNOS5250, 161 SOC_ARCH_EXYNOS5260, 162 SOC_ARCH_EXYNOS5420, 163 SOC_ARCH_EXYNOS5420_TRIMINFO, 164 SOC_ARCH_EXYNOS5433, 165 SOC_ARCH_EXYNOS7, 166 }; 167 168 /** 169 * struct exynos_tmu_data : A structure to hold the private data of the TMU 170 driver 171 * @id: identifier of the one instance of the TMU controller. 172 * @base: base address of the single instance of the TMU controller. 173 * @base_second: base address of the common registers of the TMU controller. 174 * @irq: irq number of the TMU controller. 175 * @soc: id of the SOC type. 176 * @irq_work: pointer to the irq work structure. 177 * @lock: lock to implement synchronization. 178 * @clk: pointer to the clock structure. 179 * @clk_sec: pointer to the clock structure for accessing the base_second. 180 * @sclk: pointer to the clock structure for accessing the tmu special clk. 181 * @cal_type: calibration type for temperature 182 * @efuse_value: SoC defined fuse value 183 * @min_efuse_value: minimum valid trimming data 184 * @max_efuse_value: maximum valid trimming data 185 * @temp_error1: fused value of the first point trim. 186 * @temp_error2: fused value of the second point trim. 187 * @gain: gain of amplifier in the positive-TC generator block 188 * 0 < gain <= 15 189 * @reference_voltage: reference voltage of amplifier 190 * in the positive-TC generator block 191 * 0 < reference_voltage <= 31 192 * @regulator: pointer to the TMU regulator structure. 193 * @reg_conf: pointer to structure to register with core thermal. 194 * @ntrip: number of supported trip points. 195 * @enabled: current status of TMU device 196 * @tmu_initialize: SoC specific TMU initialization method 197 * @tmu_control: SoC specific TMU control method 198 * @tmu_read: SoC specific TMU temperature read method 199 * @tmu_set_emulation: SoC specific TMU emulation setting method 200 * @tmu_clear_irqs: SoC specific TMU interrupts clearing method 201 */ 202 struct exynos_tmu_data { 203 int id; 204 void __iomem *base; 205 void __iomem *base_second; 206 int irq; 207 enum soc_type soc; 208 struct work_struct irq_work; 209 struct mutex lock; 210 struct clk *clk, *clk_sec, *sclk; 211 u32 cal_type; 212 u32 efuse_value; 213 u32 min_efuse_value; 214 u32 max_efuse_value; 215 u16 temp_error1, temp_error2; 216 u8 gain; 217 u8 reference_voltage; 218 struct regulator *regulator; 219 struct thermal_zone_device *tzd; 220 unsigned int ntrip; 221 bool enabled; 222 223 void (*tmu_initialize)(struct platform_device *pdev); 224 void (*tmu_control)(struct platform_device *pdev, bool on); 225 int (*tmu_read)(struct exynos_tmu_data *data); 226 void (*tmu_set_emulation)(struct exynos_tmu_data *data, int temp); 227 void (*tmu_clear_irqs)(struct exynos_tmu_data *data); 228 }; 229 230 static void exynos_report_trigger(struct exynos_tmu_data *p) 231 { 232 char data[10], *envp[] = { data, NULL }; 233 struct thermal_zone_device *tz = p->tzd; 234 int temp; 235 unsigned int i; 236 237 if (!tz) { 238 pr_err("No thermal zone device defined\n"); 239 return; 240 } 241 242 thermal_zone_device_update(tz, THERMAL_EVENT_UNSPECIFIED); 243 244 mutex_lock(&tz->lock); 245 /* Find the level for which trip happened */ 246 for (i = 0; i < of_thermal_get_ntrips(tz); i++) { 247 tz->ops->get_trip_temp(tz, i, &temp); 248 if (tz->last_temperature < temp) 249 break; 250 } 251 252 snprintf(data, sizeof(data), "%u", i); 253 kobject_uevent_env(&tz->device.kobj, KOBJ_CHANGE, envp); 254 mutex_unlock(&tz->lock); 255 } 256 257 /* 258 * TMU treats temperature as a mapped temperature code. 259 * The temperature is converted differently depending on the calibration type. 260 */ 261 static int temp_to_code(struct exynos_tmu_data *data, u8 temp) 262 { 263 if (data->cal_type == TYPE_ONE_POINT_TRIMMING) 264 return temp + data->temp_error1 - EXYNOS_FIRST_POINT_TRIM; 265 266 return (temp - EXYNOS_FIRST_POINT_TRIM) * 267 (data->temp_error2 - data->temp_error1) / 268 (EXYNOS_SECOND_POINT_TRIM - EXYNOS_FIRST_POINT_TRIM) + 269 data->temp_error1; 270 } 271 272 /* 273 * Calculate a temperature value from a temperature code. 274 * The unit of the temperature is degree Celsius. 275 */ 276 static int code_to_temp(struct exynos_tmu_data *data, u16 temp_code) 277 { 278 if (data->cal_type == TYPE_ONE_POINT_TRIMMING) 279 return temp_code - data->temp_error1 + EXYNOS_FIRST_POINT_TRIM; 280 281 return (temp_code - data->temp_error1) * 282 (EXYNOS_SECOND_POINT_TRIM - EXYNOS_FIRST_POINT_TRIM) / 283 (data->temp_error2 - data->temp_error1) + 284 EXYNOS_FIRST_POINT_TRIM; 285 } 286 287 static void sanitize_temp_error(struct exynos_tmu_data *data, u32 trim_info) 288 { 289 u16 tmu_temp_mask = 290 (data->soc == SOC_ARCH_EXYNOS7) ? EXYNOS7_TMU_TEMP_MASK 291 : EXYNOS_TMU_TEMP_MASK; 292 293 data->temp_error1 = trim_info & tmu_temp_mask; 294 data->temp_error2 = ((trim_info >> EXYNOS_TRIMINFO_85_SHIFT) & 295 EXYNOS_TMU_TEMP_MASK); 296 297 if (!data->temp_error1 || 298 (data->min_efuse_value > data->temp_error1) || 299 (data->temp_error1 > data->max_efuse_value)) 300 data->temp_error1 = data->efuse_value & EXYNOS_TMU_TEMP_MASK; 301 302 if (!data->temp_error2) 303 data->temp_error2 = 304 (data->efuse_value >> EXYNOS_TRIMINFO_85_SHIFT) & 305 EXYNOS_TMU_TEMP_MASK; 306 } 307 308 static int exynos_tmu_initialize(struct platform_device *pdev) 309 { 310 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 311 struct thermal_zone_device *tzd = data->tzd; 312 const struct thermal_trip * const trips = 313 of_thermal_get_trip_points(tzd); 314 unsigned int status; 315 int ret = 0, temp; 316 317 if (!trips) { 318 dev_err(&pdev->dev, 319 "Cannot get trip points from device tree!\n"); 320 return -ENODEV; 321 } 322 323 if (data->soc != SOC_ARCH_EXYNOS5433) /* FIXME */ 324 ret = tzd->ops->get_crit_temp(tzd, &temp); 325 if (ret) { 326 dev_err(&pdev->dev, 327 "No CRITICAL trip point defined in device tree!\n"); 328 goto out; 329 } 330 331 if (of_thermal_get_ntrips(tzd) > data->ntrip) { 332 dev_info(&pdev->dev, 333 "More trip points than supported by this TMU.\n"); 334 dev_info(&pdev->dev, 335 "%d trip points should be configured in polling mode.\n", 336 (of_thermal_get_ntrips(tzd) - data->ntrip)); 337 } 338 339 mutex_lock(&data->lock); 340 clk_enable(data->clk); 341 if (!IS_ERR(data->clk_sec)) 342 clk_enable(data->clk_sec); 343 344 status = readb(data->base + EXYNOS_TMU_REG_STATUS); 345 if (!status) { 346 ret = -EBUSY; 347 } else { 348 data->tmu_initialize(pdev); 349 data->tmu_clear_irqs(data); 350 } 351 352 clk_disable(data->clk); 353 mutex_unlock(&data->lock); 354 if (!IS_ERR(data->clk_sec)) 355 clk_disable(data->clk_sec); 356 out: 357 return ret; 358 } 359 360 static u32 get_con_reg(struct exynos_tmu_data *data, u32 con) 361 { 362 if (data->soc == SOC_ARCH_EXYNOS4412 || 363 data->soc == SOC_ARCH_EXYNOS3250) 364 con |= (EXYNOS4412_MUX_ADDR_VALUE << EXYNOS4412_MUX_ADDR_SHIFT); 365 366 con &= ~(EXYNOS_TMU_REF_VOLTAGE_MASK << EXYNOS_TMU_REF_VOLTAGE_SHIFT); 367 con |= data->reference_voltage << EXYNOS_TMU_REF_VOLTAGE_SHIFT; 368 369 con &= ~(EXYNOS_TMU_BUF_SLOPE_SEL_MASK << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT); 370 con |= (data->gain << EXYNOS_TMU_BUF_SLOPE_SEL_SHIFT); 371 372 con &= ~(EXYNOS_TMU_TRIP_MODE_MASK << EXYNOS_TMU_TRIP_MODE_SHIFT); 373 con |= (EXYNOS_NOISE_CANCEL_MODE << EXYNOS_TMU_TRIP_MODE_SHIFT); 374 375 return con; 376 } 377 378 static void exynos_tmu_control(struct platform_device *pdev, bool on) 379 { 380 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 381 382 mutex_lock(&data->lock); 383 clk_enable(data->clk); 384 data->tmu_control(pdev, on); 385 data->enabled = on; 386 clk_disable(data->clk); 387 mutex_unlock(&data->lock); 388 } 389 390 static void exynos4210_tmu_set_trip_temp(struct exynos_tmu_data *data, 391 int trip, u8 temp) 392 { 393 const struct thermal_trip * const trips = 394 of_thermal_get_trip_points(data->tzd); 395 u8 ref, th_code; 396 397 ref = trips[0].temperature / MCELSIUS; 398 399 if (trip == 0) { 400 th_code = temp_to_code(data, ref); 401 writeb(th_code, data->base + EXYNOS4210_TMU_REG_THRESHOLD_TEMP); 402 } 403 404 temp -= ref; 405 writeb(temp, data->base + EXYNOS4210_TMU_REG_TRIG_LEVEL0 + trip * 4); 406 } 407 408 static void exynos4210_tmu_initialize(struct platform_device *pdev) 409 { 410 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 411 struct thermal_zone_device *tz = data->tzd; 412 int i, temp; 413 414 sanitize_temp_error(data, readl(data->base + EXYNOS_TMU_REG_TRIMINFO)); 415 416 for (i = 0; i < of_thermal_get_ntrips(tz); i++) { 417 tz->ops->get_trip_temp(tz, i, &temp); 418 temp /= MCELSIUS; 419 exynos4210_tmu_set_trip_temp(data, i, temp); 420 } 421 } 422 423 static void exynos4412_tmu_set_trip_temp(struct exynos_tmu_data *data, 424 int trip, u8 temp) 425 { 426 u32 th, con; 427 428 th = readl(data->base + EXYNOS_THD_TEMP_RISE); 429 th &= ~(0xff << 8 * trip); 430 th |= temp_to_code(data, temp) << 8 * trip; 431 writel(th, data->base + EXYNOS_THD_TEMP_RISE); 432 433 if (trip == 3) { 434 con = readl(data->base + EXYNOS_TMU_REG_CONTROL); 435 con |= (1 << EXYNOS_TMU_THERM_TRIP_EN_SHIFT); 436 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 437 } 438 } 439 440 static void exynos4412_tmu_set_trip_hyst(struct exynos_tmu_data *data, 441 int trip, u8 temp, u8 hyst) 442 { 443 u32 th; 444 445 th = readl(data->base + EXYNOS_THD_TEMP_FALL); 446 th &= ~(0xff << 8 * trip); 447 if (hyst) 448 th |= temp_to_code(data, temp - hyst) << 8 * trip; 449 writel(th, data->base + EXYNOS_THD_TEMP_FALL); 450 } 451 452 static void exynos4412_tmu_initialize(struct platform_device *pdev) 453 { 454 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 455 struct thermal_zone_device *tz = data->tzd; 456 unsigned int trim_info, ctrl; 457 int i, ntrips = min_t(int, of_thermal_get_ntrips(tz), data->ntrip); 458 int temp, hyst; 459 460 if (data->soc == SOC_ARCH_EXYNOS3250 || 461 data->soc == SOC_ARCH_EXYNOS4412 || 462 data->soc == SOC_ARCH_EXYNOS5250) { 463 if (data->soc == SOC_ARCH_EXYNOS3250) { 464 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON1); 465 ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE; 466 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON1); 467 } 468 ctrl = readl(data->base + EXYNOS_TMU_TRIMINFO_CON2); 469 ctrl |= EXYNOS_TRIMINFO_RELOAD_ENABLE; 470 writel(ctrl, data->base + EXYNOS_TMU_TRIMINFO_CON2); 471 } 472 473 /* On exynos5420 the triminfo register is in the shared space */ 474 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) 475 trim_info = readl(data->base_second + EXYNOS_TMU_REG_TRIMINFO); 476 else 477 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); 478 479 sanitize_temp_error(data, trim_info); 480 481 /* Write temperature code for rising and falling threshold */ 482 for (i = 0; i < ntrips; i++) { 483 tz->ops->get_trip_temp(tz, i, &temp); 484 temp /= MCELSIUS; 485 exynos4412_tmu_set_trip_temp(data, i, temp); 486 487 tz->ops->get_trip_hyst(tz, i, &hyst); 488 hyst /= MCELSIUS; 489 exynos4412_tmu_set_trip_hyst(data, i, temp, hyst); 490 } 491 } 492 493 static void exynos5433_tmu_set_trip_temp(struct exynos_tmu_data *data, 494 int trip, u8 temp) 495 { 496 unsigned int reg_off, j; 497 u32 th; 498 499 if (trip > 3) { 500 reg_off = EXYNOS5433_THD_TEMP_RISE7_4; 501 j = trip - 4; 502 } else { 503 reg_off = EXYNOS5433_THD_TEMP_RISE3_0; 504 j = trip; 505 } 506 507 th = readl(data->base + reg_off); 508 th &= ~(0xff << j * 8); 509 th |= (temp_to_code(data, temp) << j * 8); 510 writel(th, data->base + reg_off); 511 } 512 513 static void exynos5433_tmu_set_trip_hyst(struct exynos_tmu_data *data, 514 int trip, u8 temp, u8 hyst) 515 { 516 unsigned int reg_off, j; 517 u32 th; 518 519 if (trip > 3) { 520 reg_off = EXYNOS5433_THD_TEMP_FALL7_4; 521 j = trip - 4; 522 } else { 523 reg_off = EXYNOS5433_THD_TEMP_FALL3_0; 524 j = trip; 525 } 526 527 th = readl(data->base + reg_off); 528 th &= ~(0xff << j * 8); 529 th |= (temp_to_code(data, temp - hyst) << j * 8); 530 writel(th, data->base + reg_off); 531 } 532 533 static void exynos5433_tmu_initialize(struct platform_device *pdev) 534 { 535 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 536 struct thermal_zone_device *tz = data->tzd; 537 unsigned int trim_info; 538 int sensor_id, cal_type, i, temp, hyst; 539 540 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); 541 sanitize_temp_error(data, trim_info); 542 543 /* Read the temperature sensor id */ 544 sensor_id = (trim_info & EXYNOS5433_TRIMINFO_SENSOR_ID_MASK) 545 >> EXYNOS5433_TRIMINFO_SENSOR_ID_SHIFT; 546 dev_info(&pdev->dev, "Temperature sensor ID: 0x%x\n", sensor_id); 547 548 /* Read the calibration mode */ 549 writel(trim_info, data->base + EXYNOS_TMU_REG_TRIMINFO); 550 cal_type = (trim_info & EXYNOS5433_TRIMINFO_CALIB_SEL_MASK) 551 >> EXYNOS5433_TRIMINFO_CALIB_SEL_SHIFT; 552 553 switch (cal_type) { 554 case EXYNOS5433_TRIMINFO_TWO_POINT_TRIMMING: 555 data->cal_type = TYPE_TWO_POINT_TRIMMING; 556 break; 557 case EXYNOS5433_TRIMINFO_ONE_POINT_TRIMMING: 558 default: 559 data->cal_type = TYPE_ONE_POINT_TRIMMING; 560 break; 561 } 562 563 dev_info(&pdev->dev, "Calibration type is %d-point calibration\n", 564 cal_type ? 2 : 1); 565 566 /* Write temperature code for rising and falling threshold */ 567 for (i = 0; i < of_thermal_get_ntrips(tz); i++) { 568 /* Write temperature code for rising threshold */ 569 tz->ops->get_trip_temp(tz, i, &temp); 570 temp /= MCELSIUS; 571 exynos5433_tmu_set_trip_temp(data, i, temp); 572 573 /* Write temperature code for falling threshold */ 574 tz->ops->get_trip_hyst(tz, i, &hyst); 575 hyst /= MCELSIUS; 576 exynos5433_tmu_set_trip_hyst(data, i, temp, hyst); 577 } 578 } 579 580 static void exynos7_tmu_set_trip_temp(struct exynos_tmu_data *data, 581 int trip, u8 temp) 582 { 583 unsigned int reg_off, bit_off; 584 u32 th; 585 586 reg_off = ((7 - trip) / 2) * 4; 587 bit_off = ((8 - trip) % 2); 588 589 th = readl(data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off); 590 th &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off)); 591 th |= temp_to_code(data, temp) << (16 * bit_off); 592 writel(th, data->base + EXYNOS7_THD_TEMP_RISE7_6 + reg_off); 593 } 594 595 static void exynos7_tmu_set_trip_hyst(struct exynos_tmu_data *data, 596 int trip, u8 temp, u8 hyst) 597 { 598 unsigned int reg_off, bit_off; 599 u32 th; 600 601 reg_off = ((7 - trip) / 2) * 4; 602 bit_off = ((8 - trip) % 2); 603 604 th = readl(data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off); 605 th &= ~(EXYNOS7_TMU_TEMP_MASK << (16 * bit_off)); 606 th |= temp_to_code(data, temp - hyst) << (16 * bit_off); 607 writel(th, data->base + EXYNOS7_THD_TEMP_FALL7_6 + reg_off); 608 } 609 610 static void exynos7_tmu_initialize(struct platform_device *pdev) 611 { 612 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 613 struct thermal_zone_device *tz = data->tzd; 614 unsigned int trim_info; 615 int i, temp, hyst; 616 617 trim_info = readl(data->base + EXYNOS_TMU_REG_TRIMINFO); 618 sanitize_temp_error(data, trim_info); 619 620 /* Write temperature code for rising and falling threshold */ 621 for (i = 0; i < of_thermal_get_ntrips(tz); i++) { 622 tz->ops->get_trip_temp(tz, i, &temp); 623 temp /= MCELSIUS; 624 exynos7_tmu_set_trip_temp(data, i, temp); 625 626 tz->ops->get_trip_hyst(tz, i, &hyst); 627 hyst /= MCELSIUS; 628 exynos7_tmu_set_trip_hyst(data, i, temp, hyst); 629 } 630 } 631 632 static void exynos4210_tmu_control(struct platform_device *pdev, bool on) 633 { 634 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 635 struct thermal_zone_device *tz = data->tzd; 636 unsigned int con, interrupt_en; 637 638 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); 639 640 if (on) { 641 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); 642 interrupt_en = 643 (of_thermal_is_trip_valid(tz, 3) 644 << EXYNOS_TMU_INTEN_RISE3_SHIFT) | 645 (of_thermal_is_trip_valid(tz, 2) 646 << EXYNOS_TMU_INTEN_RISE2_SHIFT) | 647 (of_thermal_is_trip_valid(tz, 1) 648 << EXYNOS_TMU_INTEN_RISE1_SHIFT) | 649 (of_thermal_is_trip_valid(tz, 0) 650 << EXYNOS_TMU_INTEN_RISE0_SHIFT); 651 652 if (data->soc != SOC_ARCH_EXYNOS4210) 653 interrupt_en |= 654 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; 655 } else { 656 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); 657 interrupt_en = 0; /* Disable all interrupts */ 658 } 659 writel(interrupt_en, data->base + EXYNOS_TMU_REG_INTEN); 660 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 661 } 662 663 static void exynos5433_tmu_control(struct platform_device *pdev, bool on) 664 { 665 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 666 struct thermal_zone_device *tz = data->tzd; 667 unsigned int con, interrupt_en, pd_det_en; 668 669 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); 670 671 if (on) { 672 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); 673 interrupt_en = 674 (of_thermal_is_trip_valid(tz, 7) 675 << EXYNOS7_TMU_INTEN_RISE7_SHIFT) | 676 (of_thermal_is_trip_valid(tz, 6) 677 << EXYNOS7_TMU_INTEN_RISE6_SHIFT) | 678 (of_thermal_is_trip_valid(tz, 5) 679 << EXYNOS7_TMU_INTEN_RISE5_SHIFT) | 680 (of_thermal_is_trip_valid(tz, 4) 681 << EXYNOS7_TMU_INTEN_RISE4_SHIFT) | 682 (of_thermal_is_trip_valid(tz, 3) 683 << EXYNOS7_TMU_INTEN_RISE3_SHIFT) | 684 (of_thermal_is_trip_valid(tz, 2) 685 << EXYNOS7_TMU_INTEN_RISE2_SHIFT) | 686 (of_thermal_is_trip_valid(tz, 1) 687 << EXYNOS7_TMU_INTEN_RISE1_SHIFT) | 688 (of_thermal_is_trip_valid(tz, 0) 689 << EXYNOS7_TMU_INTEN_RISE0_SHIFT); 690 691 interrupt_en |= 692 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; 693 } else { 694 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); 695 interrupt_en = 0; /* Disable all interrupts */ 696 } 697 698 pd_det_en = on ? EXYNOS5433_PD_DET_EN : 0; 699 700 writel(pd_det_en, data->base + EXYNOS5433_TMU_PD_DET_EN); 701 writel(interrupt_en, data->base + EXYNOS5433_TMU_REG_INTEN); 702 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 703 } 704 705 static void exynos7_tmu_control(struct platform_device *pdev, bool on) 706 { 707 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 708 struct thermal_zone_device *tz = data->tzd; 709 unsigned int con, interrupt_en; 710 711 con = get_con_reg(data, readl(data->base + EXYNOS_TMU_REG_CONTROL)); 712 713 if (on) { 714 con |= (1 << EXYNOS_TMU_CORE_EN_SHIFT); 715 con |= (1 << EXYNOS7_PD_DET_EN_SHIFT); 716 interrupt_en = 717 (of_thermal_is_trip_valid(tz, 7) 718 << EXYNOS7_TMU_INTEN_RISE7_SHIFT) | 719 (of_thermal_is_trip_valid(tz, 6) 720 << EXYNOS7_TMU_INTEN_RISE6_SHIFT) | 721 (of_thermal_is_trip_valid(tz, 5) 722 << EXYNOS7_TMU_INTEN_RISE5_SHIFT) | 723 (of_thermal_is_trip_valid(tz, 4) 724 << EXYNOS7_TMU_INTEN_RISE4_SHIFT) | 725 (of_thermal_is_trip_valid(tz, 3) 726 << EXYNOS7_TMU_INTEN_RISE3_SHIFT) | 727 (of_thermal_is_trip_valid(tz, 2) 728 << EXYNOS7_TMU_INTEN_RISE2_SHIFT) | 729 (of_thermal_is_trip_valid(tz, 1) 730 << EXYNOS7_TMU_INTEN_RISE1_SHIFT) | 731 (of_thermal_is_trip_valid(tz, 0) 732 << EXYNOS7_TMU_INTEN_RISE0_SHIFT); 733 734 interrupt_en |= 735 interrupt_en << EXYNOS_TMU_INTEN_FALL0_SHIFT; 736 } else { 737 con &= ~(1 << EXYNOS_TMU_CORE_EN_SHIFT); 738 con &= ~(1 << EXYNOS7_PD_DET_EN_SHIFT); 739 interrupt_en = 0; /* Disable all interrupts */ 740 } 741 742 writel(interrupt_en, data->base + EXYNOS7_TMU_REG_INTEN); 743 writel(con, data->base + EXYNOS_TMU_REG_CONTROL); 744 } 745 746 static int exynos_get_temp(void *p, int *temp) 747 { 748 struct exynos_tmu_data *data = p; 749 int value, ret = 0; 750 751 if (!data || !data->tmu_read || !data->enabled) 752 return -EINVAL; 753 754 mutex_lock(&data->lock); 755 clk_enable(data->clk); 756 757 value = data->tmu_read(data); 758 if (value < 0) 759 ret = value; 760 else 761 *temp = code_to_temp(data, value) * MCELSIUS; 762 763 clk_disable(data->clk); 764 mutex_unlock(&data->lock); 765 766 return ret; 767 } 768 769 #ifdef CONFIG_THERMAL_EMULATION 770 static u32 get_emul_con_reg(struct exynos_tmu_data *data, unsigned int val, 771 int temp) 772 { 773 if (temp) { 774 temp /= MCELSIUS; 775 776 val &= ~(EXYNOS_EMUL_TIME_MASK << EXYNOS_EMUL_TIME_SHIFT); 777 val |= (EXYNOS_EMUL_TIME << EXYNOS_EMUL_TIME_SHIFT); 778 if (data->soc == SOC_ARCH_EXYNOS7) { 779 val &= ~(EXYNOS7_EMUL_DATA_MASK << 780 EXYNOS7_EMUL_DATA_SHIFT); 781 val |= (temp_to_code(data, temp) << 782 EXYNOS7_EMUL_DATA_SHIFT) | 783 EXYNOS_EMUL_ENABLE; 784 } else { 785 val &= ~(EXYNOS_EMUL_DATA_MASK << 786 EXYNOS_EMUL_DATA_SHIFT); 787 val |= (temp_to_code(data, temp) << 788 EXYNOS_EMUL_DATA_SHIFT) | 789 EXYNOS_EMUL_ENABLE; 790 } 791 } else { 792 val &= ~EXYNOS_EMUL_ENABLE; 793 } 794 795 return val; 796 } 797 798 static void exynos4412_tmu_set_emulation(struct exynos_tmu_data *data, 799 int temp) 800 { 801 unsigned int val; 802 u32 emul_con; 803 804 if (data->soc == SOC_ARCH_EXYNOS5260) 805 emul_con = EXYNOS5260_EMUL_CON; 806 else if (data->soc == SOC_ARCH_EXYNOS5433) 807 emul_con = EXYNOS5433_TMU_EMUL_CON; 808 else if (data->soc == SOC_ARCH_EXYNOS7) 809 emul_con = EXYNOS7_TMU_REG_EMUL_CON; 810 else 811 emul_con = EXYNOS_EMUL_CON; 812 813 val = readl(data->base + emul_con); 814 val = get_emul_con_reg(data, val, temp); 815 writel(val, data->base + emul_con); 816 } 817 818 static int exynos_tmu_set_emulation(void *drv_data, int temp) 819 { 820 struct exynos_tmu_data *data = drv_data; 821 int ret = -EINVAL; 822 823 if (data->soc == SOC_ARCH_EXYNOS4210) 824 goto out; 825 826 if (temp && temp < MCELSIUS) 827 goto out; 828 829 mutex_lock(&data->lock); 830 clk_enable(data->clk); 831 data->tmu_set_emulation(data, temp); 832 clk_disable(data->clk); 833 mutex_unlock(&data->lock); 834 return 0; 835 out: 836 return ret; 837 } 838 #else 839 #define exynos4412_tmu_set_emulation NULL 840 static int exynos_tmu_set_emulation(void *drv_data, int temp) 841 { return -EINVAL; } 842 #endif /* CONFIG_THERMAL_EMULATION */ 843 844 static int exynos4210_tmu_read(struct exynos_tmu_data *data) 845 { 846 int ret = readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP); 847 848 /* "temp_code" should range between 75 and 175 */ 849 return (ret < 75 || ret > 175) ? -ENODATA : ret; 850 } 851 852 static int exynos4412_tmu_read(struct exynos_tmu_data *data) 853 { 854 return readb(data->base + EXYNOS_TMU_REG_CURRENT_TEMP); 855 } 856 857 static int exynos7_tmu_read(struct exynos_tmu_data *data) 858 { 859 return readw(data->base + EXYNOS_TMU_REG_CURRENT_TEMP) & 860 EXYNOS7_TMU_TEMP_MASK; 861 } 862 863 static void exynos_tmu_work(struct work_struct *work) 864 { 865 struct exynos_tmu_data *data = container_of(work, 866 struct exynos_tmu_data, irq_work); 867 868 if (!IS_ERR(data->clk_sec)) 869 clk_enable(data->clk_sec); 870 if (!IS_ERR(data->clk_sec)) 871 clk_disable(data->clk_sec); 872 873 exynos_report_trigger(data); 874 mutex_lock(&data->lock); 875 clk_enable(data->clk); 876 877 /* TODO: take action based on particular interrupt */ 878 data->tmu_clear_irqs(data); 879 880 clk_disable(data->clk); 881 mutex_unlock(&data->lock); 882 enable_irq(data->irq); 883 } 884 885 static void exynos4210_tmu_clear_irqs(struct exynos_tmu_data *data) 886 { 887 unsigned int val_irq; 888 u32 tmu_intstat, tmu_intclear; 889 890 if (data->soc == SOC_ARCH_EXYNOS5260) { 891 tmu_intstat = EXYNOS5260_TMU_REG_INTSTAT; 892 tmu_intclear = EXYNOS5260_TMU_REG_INTCLEAR; 893 } else if (data->soc == SOC_ARCH_EXYNOS7) { 894 tmu_intstat = EXYNOS7_TMU_REG_INTPEND; 895 tmu_intclear = EXYNOS7_TMU_REG_INTPEND; 896 } else if (data->soc == SOC_ARCH_EXYNOS5433) { 897 tmu_intstat = EXYNOS5433_TMU_REG_INTPEND; 898 tmu_intclear = EXYNOS5433_TMU_REG_INTPEND; 899 } else { 900 tmu_intstat = EXYNOS_TMU_REG_INTSTAT; 901 tmu_intclear = EXYNOS_TMU_REG_INTCLEAR; 902 } 903 904 val_irq = readl(data->base + tmu_intstat); 905 /* 906 * Clear the interrupts. Please note that the documentation for 907 * Exynos3250, Exynos4412, Exynos5250 and Exynos5260 incorrectly 908 * states that INTCLEAR register has a different placing of bits 909 * responsible for FALL IRQs than INTSTAT register. Exynos5420 910 * and Exynos5440 documentation is correct (Exynos4210 doesn't 911 * support FALL IRQs at all). 912 */ 913 writel(val_irq, data->base + tmu_intclear); 914 } 915 916 static irqreturn_t exynos_tmu_irq(int irq, void *id) 917 { 918 struct exynos_tmu_data *data = id; 919 920 disable_irq_nosync(irq); 921 schedule_work(&data->irq_work); 922 923 return IRQ_HANDLED; 924 } 925 926 static const struct of_device_id exynos_tmu_match[] = { 927 { 928 .compatible = "samsung,exynos3250-tmu", 929 .data = (const void *)SOC_ARCH_EXYNOS3250, 930 }, { 931 .compatible = "samsung,exynos4210-tmu", 932 .data = (const void *)SOC_ARCH_EXYNOS4210, 933 }, { 934 .compatible = "samsung,exynos4412-tmu", 935 .data = (const void *)SOC_ARCH_EXYNOS4412, 936 }, { 937 .compatible = "samsung,exynos5250-tmu", 938 .data = (const void *)SOC_ARCH_EXYNOS5250, 939 }, { 940 .compatible = "samsung,exynos5260-tmu", 941 .data = (const void *)SOC_ARCH_EXYNOS5260, 942 }, { 943 .compatible = "samsung,exynos5420-tmu", 944 .data = (const void *)SOC_ARCH_EXYNOS5420, 945 }, { 946 .compatible = "samsung,exynos5420-tmu-ext-triminfo", 947 .data = (const void *)SOC_ARCH_EXYNOS5420_TRIMINFO, 948 }, { 949 .compatible = "samsung,exynos5433-tmu", 950 .data = (const void *)SOC_ARCH_EXYNOS5433, 951 }, { 952 .compatible = "samsung,exynos7-tmu", 953 .data = (const void *)SOC_ARCH_EXYNOS7, 954 }, 955 { }, 956 }; 957 MODULE_DEVICE_TABLE(of, exynos_tmu_match); 958 959 static int exynos_map_dt_data(struct platform_device *pdev) 960 { 961 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 962 struct resource res; 963 964 if (!data || !pdev->dev.of_node) 965 return -ENODEV; 966 967 data->id = of_alias_get_id(pdev->dev.of_node, "tmuctrl"); 968 if (data->id < 0) 969 data->id = 0; 970 971 data->irq = irq_of_parse_and_map(pdev->dev.of_node, 0); 972 if (data->irq <= 0) { 973 dev_err(&pdev->dev, "failed to get IRQ\n"); 974 return -ENODEV; 975 } 976 977 if (of_address_to_resource(pdev->dev.of_node, 0, &res)) { 978 dev_err(&pdev->dev, "failed to get Resource 0\n"); 979 return -ENODEV; 980 } 981 982 data->base = devm_ioremap(&pdev->dev, res.start, resource_size(&res)); 983 if (!data->base) { 984 dev_err(&pdev->dev, "Failed to ioremap memory\n"); 985 return -EADDRNOTAVAIL; 986 } 987 988 data->soc = (enum soc_type)of_device_get_match_data(&pdev->dev); 989 990 switch (data->soc) { 991 case SOC_ARCH_EXYNOS4210: 992 data->tmu_initialize = exynos4210_tmu_initialize; 993 data->tmu_control = exynos4210_tmu_control; 994 data->tmu_read = exynos4210_tmu_read; 995 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; 996 data->ntrip = 4; 997 data->gain = 15; 998 data->reference_voltage = 7; 999 data->efuse_value = 55; 1000 data->min_efuse_value = 40; 1001 data->max_efuse_value = 100; 1002 break; 1003 case SOC_ARCH_EXYNOS3250: 1004 case SOC_ARCH_EXYNOS4412: 1005 case SOC_ARCH_EXYNOS5250: 1006 case SOC_ARCH_EXYNOS5260: 1007 case SOC_ARCH_EXYNOS5420: 1008 case SOC_ARCH_EXYNOS5420_TRIMINFO: 1009 data->tmu_initialize = exynos4412_tmu_initialize; 1010 data->tmu_control = exynos4210_tmu_control; 1011 data->tmu_read = exynos4412_tmu_read; 1012 data->tmu_set_emulation = exynos4412_tmu_set_emulation; 1013 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; 1014 data->ntrip = 4; 1015 data->gain = 8; 1016 data->reference_voltage = 16; 1017 data->efuse_value = 55; 1018 if (data->soc != SOC_ARCH_EXYNOS5420 && 1019 data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO) 1020 data->min_efuse_value = 40; 1021 else 1022 data->min_efuse_value = 0; 1023 data->max_efuse_value = 100; 1024 break; 1025 case SOC_ARCH_EXYNOS5433: 1026 data->tmu_initialize = exynos5433_tmu_initialize; 1027 data->tmu_control = exynos5433_tmu_control; 1028 data->tmu_read = exynos4412_tmu_read; 1029 data->tmu_set_emulation = exynos4412_tmu_set_emulation; 1030 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; 1031 data->ntrip = 8; 1032 data->gain = 8; 1033 if (res.start == EXYNOS5433_G3D_BASE) 1034 data->reference_voltage = 23; 1035 else 1036 data->reference_voltage = 16; 1037 data->efuse_value = 75; 1038 data->min_efuse_value = 40; 1039 data->max_efuse_value = 150; 1040 break; 1041 case SOC_ARCH_EXYNOS7: 1042 data->tmu_initialize = exynos7_tmu_initialize; 1043 data->tmu_control = exynos7_tmu_control; 1044 data->tmu_read = exynos7_tmu_read; 1045 data->tmu_set_emulation = exynos4412_tmu_set_emulation; 1046 data->tmu_clear_irqs = exynos4210_tmu_clear_irqs; 1047 data->ntrip = 8; 1048 data->gain = 9; 1049 data->reference_voltage = 17; 1050 data->efuse_value = 75; 1051 data->min_efuse_value = 15; 1052 data->max_efuse_value = 100; 1053 break; 1054 default: 1055 dev_err(&pdev->dev, "Platform not supported\n"); 1056 return -EINVAL; 1057 } 1058 1059 data->cal_type = TYPE_ONE_POINT_TRIMMING; 1060 1061 /* 1062 * Check if the TMU shares some registers and then try to map the 1063 * memory of common registers. 1064 */ 1065 if (data->soc != SOC_ARCH_EXYNOS5420_TRIMINFO) 1066 return 0; 1067 1068 if (of_address_to_resource(pdev->dev.of_node, 1, &res)) { 1069 dev_err(&pdev->dev, "failed to get Resource 1\n"); 1070 return -ENODEV; 1071 } 1072 1073 data->base_second = devm_ioremap(&pdev->dev, res.start, 1074 resource_size(&res)); 1075 if (!data->base_second) { 1076 dev_err(&pdev->dev, "Failed to ioremap memory\n"); 1077 return -ENOMEM; 1078 } 1079 1080 return 0; 1081 } 1082 1083 static const struct thermal_zone_of_device_ops exynos_sensor_ops = { 1084 .get_temp = exynos_get_temp, 1085 .set_emul_temp = exynos_tmu_set_emulation, 1086 }; 1087 1088 static int exynos_tmu_probe(struct platform_device *pdev) 1089 { 1090 struct exynos_tmu_data *data; 1091 int ret; 1092 1093 data = devm_kzalloc(&pdev->dev, sizeof(struct exynos_tmu_data), 1094 GFP_KERNEL); 1095 if (!data) 1096 return -ENOMEM; 1097 1098 platform_set_drvdata(pdev, data); 1099 mutex_init(&data->lock); 1100 1101 /* 1102 * Try enabling the regulator if found 1103 * TODO: Add regulator as an SOC feature, so that regulator enable 1104 * is a compulsory call. 1105 */ 1106 data->regulator = devm_regulator_get_optional(&pdev->dev, "vtmu"); 1107 if (!IS_ERR(data->regulator)) { 1108 ret = regulator_enable(data->regulator); 1109 if (ret) { 1110 dev_err(&pdev->dev, "failed to enable vtmu\n"); 1111 return ret; 1112 } 1113 } else { 1114 if (PTR_ERR(data->regulator) == -EPROBE_DEFER) 1115 return -EPROBE_DEFER; 1116 dev_info(&pdev->dev, "Regulator node (vtmu) not found\n"); 1117 } 1118 1119 ret = exynos_map_dt_data(pdev); 1120 if (ret) 1121 goto err_sensor; 1122 1123 INIT_WORK(&data->irq_work, exynos_tmu_work); 1124 1125 data->clk = devm_clk_get(&pdev->dev, "tmu_apbif"); 1126 if (IS_ERR(data->clk)) { 1127 dev_err(&pdev->dev, "Failed to get clock\n"); 1128 ret = PTR_ERR(data->clk); 1129 goto err_sensor; 1130 } 1131 1132 data->clk_sec = devm_clk_get(&pdev->dev, "tmu_triminfo_apbif"); 1133 if (IS_ERR(data->clk_sec)) { 1134 if (data->soc == SOC_ARCH_EXYNOS5420_TRIMINFO) { 1135 dev_err(&pdev->dev, "Failed to get triminfo clock\n"); 1136 ret = PTR_ERR(data->clk_sec); 1137 goto err_sensor; 1138 } 1139 } else { 1140 ret = clk_prepare(data->clk_sec); 1141 if (ret) { 1142 dev_err(&pdev->dev, "Failed to get clock\n"); 1143 goto err_sensor; 1144 } 1145 } 1146 1147 ret = clk_prepare(data->clk); 1148 if (ret) { 1149 dev_err(&pdev->dev, "Failed to get clock\n"); 1150 goto err_clk_sec; 1151 } 1152 1153 switch (data->soc) { 1154 case SOC_ARCH_EXYNOS5433: 1155 case SOC_ARCH_EXYNOS7: 1156 data->sclk = devm_clk_get(&pdev->dev, "tmu_sclk"); 1157 if (IS_ERR(data->sclk)) { 1158 dev_err(&pdev->dev, "Failed to get sclk\n"); 1159 goto err_clk; 1160 } else { 1161 ret = clk_prepare_enable(data->sclk); 1162 if (ret) { 1163 dev_err(&pdev->dev, "Failed to enable sclk\n"); 1164 goto err_clk; 1165 } 1166 } 1167 break; 1168 default: 1169 break; 1170 } 1171 1172 /* 1173 * data->tzd must be registered before calling exynos_tmu_initialize(), 1174 * requesting irq and calling exynos_tmu_control(). 1175 */ 1176 data->tzd = thermal_zone_of_sensor_register(&pdev->dev, 0, data, 1177 &exynos_sensor_ops); 1178 if (IS_ERR(data->tzd)) { 1179 ret = PTR_ERR(data->tzd); 1180 dev_err(&pdev->dev, "Failed to register sensor: %d\n", ret); 1181 goto err_sclk; 1182 } 1183 1184 ret = exynos_tmu_initialize(pdev); 1185 if (ret) { 1186 dev_err(&pdev->dev, "Failed to initialize TMU\n"); 1187 goto err_thermal; 1188 } 1189 1190 ret = devm_request_irq(&pdev->dev, data->irq, exynos_tmu_irq, 1191 IRQF_TRIGGER_RISING | IRQF_SHARED, dev_name(&pdev->dev), data); 1192 if (ret) { 1193 dev_err(&pdev->dev, "Failed to request irq: %d\n", data->irq); 1194 goto err_thermal; 1195 } 1196 1197 exynos_tmu_control(pdev, true); 1198 return 0; 1199 1200 err_thermal: 1201 thermal_zone_of_sensor_unregister(&pdev->dev, data->tzd); 1202 err_sclk: 1203 clk_disable_unprepare(data->sclk); 1204 err_clk: 1205 clk_unprepare(data->clk); 1206 err_clk_sec: 1207 if (!IS_ERR(data->clk_sec)) 1208 clk_unprepare(data->clk_sec); 1209 err_sensor: 1210 if (!IS_ERR(data->regulator)) 1211 regulator_disable(data->regulator); 1212 1213 return ret; 1214 } 1215 1216 static int exynos_tmu_remove(struct platform_device *pdev) 1217 { 1218 struct exynos_tmu_data *data = platform_get_drvdata(pdev); 1219 struct thermal_zone_device *tzd = data->tzd; 1220 1221 thermal_zone_of_sensor_unregister(&pdev->dev, tzd); 1222 exynos_tmu_control(pdev, false); 1223 1224 clk_disable_unprepare(data->sclk); 1225 clk_unprepare(data->clk); 1226 if (!IS_ERR(data->clk_sec)) 1227 clk_unprepare(data->clk_sec); 1228 1229 if (!IS_ERR(data->regulator)) 1230 regulator_disable(data->regulator); 1231 1232 return 0; 1233 } 1234 1235 #ifdef CONFIG_PM_SLEEP 1236 static int exynos_tmu_suspend(struct device *dev) 1237 { 1238 exynos_tmu_control(to_platform_device(dev), false); 1239 1240 return 0; 1241 } 1242 1243 static int exynos_tmu_resume(struct device *dev) 1244 { 1245 struct platform_device *pdev = to_platform_device(dev); 1246 1247 exynos_tmu_initialize(pdev); 1248 exynos_tmu_control(pdev, true); 1249 1250 return 0; 1251 } 1252 1253 static SIMPLE_DEV_PM_OPS(exynos_tmu_pm, 1254 exynos_tmu_suspend, exynos_tmu_resume); 1255 #define EXYNOS_TMU_PM (&exynos_tmu_pm) 1256 #else 1257 #define EXYNOS_TMU_PM NULL 1258 #endif 1259 1260 static struct platform_driver exynos_tmu_driver = { 1261 .driver = { 1262 .name = "exynos-tmu", 1263 .pm = EXYNOS_TMU_PM, 1264 .of_match_table = exynos_tmu_match, 1265 }, 1266 .probe = exynos_tmu_probe, 1267 .remove = exynos_tmu_remove, 1268 }; 1269 1270 module_platform_driver(exynos_tmu_driver); 1271 1272 MODULE_DESCRIPTION("EXYNOS TMU Driver"); 1273 MODULE_AUTHOR("Donggeun Kim <dg77.kim@samsung.com>"); 1274 MODULE_LICENSE("GPL"); 1275 MODULE_ALIAS("platform:exynos-tmu"); 1276