1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Copyright 2016 Freescale Semiconductor, Inc. 4 5 #include <linux/clk.h> 6 #include <linux/err.h> 7 #include <linux/io.h> 8 #include <linux/module.h> 9 #include <linux/of.h> 10 #include <linux/platform_device.h> 11 #include <linux/regmap.h> 12 #include <linux/sizes.h> 13 #include <linux/thermal.h> 14 #include <linux/units.h> 15 16 #include "thermal_hwmon.h" 17 18 #define SITES_MAX 16 19 #define TMR_DISABLE 0x0 20 #define TMR_ME 0x80000000 21 #define TMR_CMD BIT(29) 22 #define TMR_ALPF 0x0c000000 23 #define TMR_ALPF_V2 0x03000000 24 #define TMTMIR_DEFAULT 0x0000000f 25 #define TIER_DISABLE 0x0 26 #define TEUMR0_V2 0x51009c00 27 #define TMSARA_V2 0xe 28 #define TMU_VER1 0x1 29 #define TMU_VER2 0x2 30 31 #define REGS_TMR 0x000 /* Mode Register */ 32 #define TMR_DISABLE 0x0 33 #define TMR_ME 0x80000000 34 #define TMR_ALPF 0x0c000000 35 36 #define REGS_TMTMIR 0x008 /* Temperature measurement interval Register */ 37 #define TMTMIR_DEFAULT 0x0000000f 38 39 #define REGS_V2_TMSR 0x008 /* monitor site register */ 40 41 #define REGS_V2_TMTMIR 0x00c /* Temperature measurement interval Register */ 42 43 #define REGS_TIER 0x020 /* Interrupt Enable Register */ 44 #define TIER_DISABLE 0x0 45 46 47 #define REGS_TTCFGR 0x080 /* Temperature Configuration Register */ 48 #define REGS_TSCFGR 0x084 /* Sensor Configuration Register */ 49 50 #define REGS_TRITSR(n) (0x100 + 16 * (n)) /* Immediate Temperature 51 * Site Register 52 */ 53 #define TRITSR_V BIT(31) 54 #define TRITSR_TP5 BIT(9) 55 #define REGS_V2_TMSAR(n) (0x304 + 16 * (n)) /* TMU monitoring 56 * site adjustment register 57 */ 58 #define REGS_TTRnCR(n) (0xf10 + 4 * (n)) /* Temperature Range n 59 * Control Register 60 */ 61 #define NUM_TTRCR_V1 4 62 #define NUM_TTRCR_MAX 16 63 64 #define REGS_IPBRR(n) (0xbf8 + 4 * (n)) /* IP Block Revision 65 * Register n 66 */ 67 #define REGS_V2_TEUMR(n) (0xf00 + 4 * (n)) 68 69 /* 70 * Thermal zone data 71 */ 72 struct qoriq_sensor { 73 int id; 74 }; 75 76 struct qoriq_tmu_data { 77 int ver; 78 u32 ttrcr[NUM_TTRCR_MAX]; 79 struct regmap *regmap; 80 struct clk *clk; 81 struct qoriq_sensor sensor[SITES_MAX]; 82 }; 83 84 static struct qoriq_tmu_data *qoriq_sensor_to_data(struct qoriq_sensor *s) 85 { 86 return container_of(s, struct qoriq_tmu_data, sensor[s->id]); 87 } 88 89 static int tmu_get_temp(struct thermal_zone_device *tz, int *temp) 90 { 91 struct qoriq_sensor *qsensor = thermal_zone_device_priv(tz); 92 struct qoriq_tmu_data *qdata = qoriq_sensor_to_data(qsensor); 93 u32 val; 94 /* 95 * REGS_TRITSR(id) has the following layout: 96 * 97 * For TMU Rev1: 98 * 31 ... 7 6 5 4 3 2 1 0 99 * V TEMP 100 * 101 * Where V bit signifies if the measurement is ready and is 102 * within sensor range. TEMP is an 8 bit value representing 103 * temperature in Celsius. 104 105 * For TMU Rev2: 106 * 31 ... 8 7 6 5 4 3 2 1 0 107 * V TEMP 108 * 109 * Where V bit signifies if the measurement is ready and is 110 * within sensor range. TEMP is an 9 bit value representing 111 * temperature in KelVin. 112 */ 113 114 regmap_read(qdata->regmap, REGS_TMR, &val); 115 if (!(val & TMR_ME)) 116 return -EAGAIN; 117 118 if (regmap_read_poll_timeout(qdata->regmap, 119 REGS_TRITSR(qsensor->id), 120 val, 121 val & TRITSR_V, 122 USEC_PER_MSEC, 123 10 * USEC_PER_MSEC)) 124 return -ENODATA; 125 126 if (qdata->ver == TMU_VER1) { 127 *temp = (val & GENMASK(7, 0)) * MILLIDEGREE_PER_DEGREE; 128 } else { 129 if (val & TRITSR_TP5) 130 *temp = milli_kelvin_to_millicelsius((val & GENMASK(8, 0)) * 131 MILLIDEGREE_PER_DEGREE + 500); 132 else 133 *temp = kelvin_to_millicelsius(val & GENMASK(8, 0)); 134 } 135 136 return 0; 137 } 138 139 static const struct thermal_zone_device_ops tmu_tz_ops = { 140 .get_temp = tmu_get_temp, 141 }; 142 143 static int qoriq_tmu_register_tmu_zone(struct device *dev, 144 struct qoriq_tmu_data *qdata) 145 { 146 int id, sites = 0; 147 148 for (id = 0; id < SITES_MAX; id++) { 149 struct thermal_zone_device *tzd; 150 struct qoriq_sensor *sensor = &qdata->sensor[id]; 151 int ret; 152 153 sensor->id = id; 154 155 tzd = devm_thermal_of_zone_register(dev, id, 156 sensor, 157 &tmu_tz_ops); 158 ret = PTR_ERR_OR_ZERO(tzd); 159 if (ret) { 160 if (ret == -ENODEV) 161 continue; 162 163 return ret; 164 } 165 166 if (qdata->ver == TMU_VER1) 167 sites |= 0x1 << (15 - id); 168 else 169 sites |= 0x1 << id; 170 171 devm_thermal_add_hwmon_sysfs(dev, tzd); 172 } 173 174 if (sites) { 175 if (qdata->ver == TMU_VER1) { 176 regmap_write(qdata->regmap, REGS_TMR, TMR_ME | TMR_ALPF | sites); 177 } else { 178 regmap_write(qdata->regmap, REGS_V2_TMSR, sites); 179 regmap_write(qdata->regmap, REGS_TMR, TMR_ME | TMR_ALPF_V2); 180 } 181 } 182 183 return 0; 184 } 185 186 static int qoriq_tmu_calibration(struct device *dev, 187 struct qoriq_tmu_data *data) 188 { 189 int i, val, len; 190 const u32 *calibration; 191 struct device_node *np = dev->of_node; 192 193 len = of_property_count_u32_elems(np, "fsl,tmu-range"); 194 if (len < 0 || (data->ver == TMU_VER1 && len > NUM_TTRCR_V1) || 195 (data->ver > TMU_VER1 && len > NUM_TTRCR_MAX)) { 196 dev_err(dev, "invalid range data.\n"); 197 return len; 198 } 199 200 val = of_property_read_u32_array(np, "fsl,tmu-range", data->ttrcr, len); 201 if (val != 0) { 202 dev_err(dev, "failed to read range data.\n"); 203 return val; 204 } 205 206 /* Init temperature range registers */ 207 for (i = 0; i < len; i++) 208 regmap_write(data->regmap, REGS_TTRnCR(i), data->ttrcr[i]); 209 210 calibration = of_get_property(np, "fsl,tmu-calibration", &len); 211 if (calibration == NULL || len % 8) { 212 dev_err(dev, "invalid calibration data.\n"); 213 return -ENODEV; 214 } 215 216 for (i = 0; i < len; i += 8, calibration += 2) { 217 val = of_read_number(calibration, 1); 218 regmap_write(data->regmap, REGS_TTCFGR, val); 219 val = of_read_number(calibration + 1, 1); 220 regmap_write(data->regmap, REGS_TSCFGR, val); 221 } 222 223 return 0; 224 } 225 226 static void qoriq_tmu_init_device(struct qoriq_tmu_data *data) 227 { 228 /* Disable interrupt, using polling instead */ 229 regmap_write(data->regmap, REGS_TIER, TIER_DISABLE); 230 231 /* Set update_interval */ 232 233 if (data->ver == TMU_VER1) { 234 regmap_write(data->regmap, REGS_TMTMIR, TMTMIR_DEFAULT); 235 } else { 236 regmap_write(data->regmap, REGS_V2_TMTMIR, TMTMIR_DEFAULT); 237 regmap_write(data->regmap, REGS_V2_TEUMR(0), TEUMR0_V2); 238 } 239 240 /* Disable monitoring */ 241 regmap_write(data->regmap, REGS_TMR, TMR_DISABLE); 242 } 243 244 static const struct regmap_range qoriq_yes_ranges[] = { 245 regmap_reg_range(REGS_TMR, REGS_TSCFGR), 246 regmap_reg_range(REGS_TTRnCR(0), REGS_TTRnCR(15)), 247 regmap_reg_range(REGS_V2_TEUMR(0), REGS_V2_TEUMR(2)), 248 regmap_reg_range(REGS_V2_TMSAR(0), REGS_V2_TMSAR(15)), 249 regmap_reg_range(REGS_IPBRR(0), REGS_IPBRR(1)), 250 /* Read only registers below */ 251 regmap_reg_range(REGS_TRITSR(0), REGS_TRITSR(15)), 252 }; 253 254 static const struct regmap_access_table qoriq_wr_table = { 255 .yes_ranges = qoriq_yes_ranges, 256 .n_yes_ranges = ARRAY_SIZE(qoriq_yes_ranges) - 1, 257 }; 258 259 static const struct regmap_access_table qoriq_rd_table = { 260 .yes_ranges = qoriq_yes_ranges, 261 .n_yes_ranges = ARRAY_SIZE(qoriq_yes_ranges), 262 }; 263 264 static void qoriq_tmu_action(void *p) 265 { 266 struct qoriq_tmu_data *data = p; 267 268 regmap_write(data->regmap, REGS_TMR, TMR_DISABLE); 269 } 270 271 static int qoriq_tmu_probe(struct platform_device *pdev) 272 { 273 int ret; 274 u32 ver; 275 struct qoriq_tmu_data *data; 276 struct device_node *np = pdev->dev.of_node; 277 struct device *dev = &pdev->dev; 278 const bool little_endian = of_property_read_bool(np, "little-endian"); 279 const enum regmap_endian format_endian = 280 little_endian ? REGMAP_ENDIAN_LITTLE : REGMAP_ENDIAN_BIG; 281 const struct regmap_config regmap_config = { 282 .reg_bits = 32, 283 .val_bits = 32, 284 .reg_stride = 4, 285 .rd_table = &qoriq_rd_table, 286 .wr_table = &qoriq_wr_table, 287 .val_format_endian = format_endian, 288 .max_register = SZ_4K, 289 }; 290 void __iomem *base; 291 292 data = devm_kzalloc(dev, sizeof(struct qoriq_tmu_data), 293 GFP_KERNEL); 294 if (!data) 295 return -ENOMEM; 296 297 base = devm_platform_ioremap_resource(pdev, 0); 298 ret = PTR_ERR_OR_ZERO(base); 299 if (ret) 300 return dev_err_probe(dev, ret, "Failed to get memory region\n"); 301 302 data->regmap = devm_regmap_init_mmio(dev, base, ®map_config); 303 ret = PTR_ERR_OR_ZERO(data->regmap); 304 if (ret) 305 return dev_err_probe(dev, ret, "Failed to init regmap\n"); 306 307 data->clk = devm_clk_get_optional_enabled(dev, NULL); 308 if (IS_ERR(data->clk)) 309 return PTR_ERR(data->clk); 310 311 ret = devm_add_action_or_reset(dev, qoriq_tmu_action, data); 312 if (ret) 313 return ret; 314 315 /* version register offset at: 0xbf8 on both v1 and v2 */ 316 ret = regmap_read(data->regmap, REGS_IPBRR(0), &ver); 317 if (ret) 318 return dev_err_probe(dev, ret, "Failed to read IP block version\n"); 319 320 data->ver = (ver >> 8) & 0xff; 321 322 qoriq_tmu_init_device(data); /* TMU initialization */ 323 324 ret = qoriq_tmu_calibration(dev, data); /* TMU calibration */ 325 if (ret < 0) 326 return ret; 327 328 ret = qoriq_tmu_register_tmu_zone(dev, data); 329 if (ret < 0) 330 return dev_err_probe(dev, ret, "Failed to register sensors\n"); 331 332 platform_set_drvdata(pdev, data); 333 334 return 0; 335 } 336 337 static int qoriq_tmu_suspend(struct device *dev) 338 { 339 struct qoriq_tmu_data *data = dev_get_drvdata(dev); 340 int ret; 341 342 ret = regmap_update_bits(data->regmap, REGS_TMR, TMR_ME, 0); 343 if (ret) 344 return ret; 345 346 if (data->ver > TMU_VER1) { 347 ret = regmap_set_bits(data->regmap, REGS_TMR, TMR_CMD); 348 if (ret) 349 return ret; 350 } 351 352 clk_disable_unprepare(data->clk); 353 354 return 0; 355 } 356 357 static int qoriq_tmu_resume(struct device *dev) 358 { 359 int ret; 360 struct qoriq_tmu_data *data = dev_get_drvdata(dev); 361 362 ret = clk_prepare_enable(data->clk); 363 if (ret) 364 return ret; 365 366 if (data->ver > TMU_VER1) { 367 ret = regmap_clear_bits(data->regmap, REGS_TMR, TMR_CMD); 368 if (ret) 369 return ret; 370 } 371 372 /* Enable monitoring */ 373 return regmap_update_bits(data->regmap, REGS_TMR, TMR_ME, TMR_ME); 374 } 375 376 static DEFINE_SIMPLE_DEV_PM_OPS(qoriq_tmu_pm_ops, 377 qoriq_tmu_suspend, qoriq_tmu_resume); 378 379 static const struct of_device_id qoriq_tmu_match[] = { 380 { .compatible = "fsl,qoriq-tmu", }, 381 { .compatible = "fsl,imx8mq-tmu", }, 382 {}, 383 }; 384 MODULE_DEVICE_TABLE(of, qoriq_tmu_match); 385 386 static struct platform_driver qoriq_tmu = { 387 .driver = { 388 .name = "qoriq_thermal", 389 .pm = pm_sleep_ptr(&qoriq_tmu_pm_ops), 390 .of_match_table = qoriq_tmu_match, 391 }, 392 .probe = qoriq_tmu_probe, 393 }; 394 module_platform_driver(qoriq_tmu); 395 396 MODULE_AUTHOR("Jia Hongtao <hongtao.jia@nxp.com>"); 397 MODULE_DESCRIPTION("QorIQ Thermal Monitoring Unit driver"); 398 MODULE_LICENSE("GPL v2"); 399