1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2020 Linaro Limited 4 * 5 * Based on original driver: 6 * Copyright (c) 2012-2020, The Linux Foundation. All rights reserved. 7 */ 8 #include <linux/bitfield.h> 9 #include <linux/iio/adc/qcom-vadc-common.h> 10 #include <linux/iio/consumer.h> 11 #include <linux/interrupt.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_device.h> 15 #include <linux/platform_device.h> 16 #include <linux/regmap.h> 17 #include <linux/thermal.h> 18 19 /* 20 * Thermal monitoring block consists of 8 (ADC_TM5_NUM_CHANNELS) channels. Each 21 * channel is programmed to use one of ADC channels for voltage comparison. 22 * Voltages are programmed using ADC codes, so we have to convert temp to 23 * voltage and then to ADC code value. 24 * 25 * Configuration of TM channels must match configuration of corresponding ADC 26 * channels. 27 */ 28 29 #define ADC5_MAX_CHANNEL 0xc0 30 #define ADC_TM5_NUM_CHANNELS 8 31 32 #define ADC_TM5_STATUS_LOW 0x0a 33 34 #define ADC_TM5_STATUS_HIGH 0x0b 35 36 #define ADC_TM5_NUM_BTM 0x0f 37 38 #define ADC_TM5_ADC_DIG_PARAM 0x42 39 40 #define ADC_TM5_FAST_AVG_CTL (ADC_TM5_ADC_DIG_PARAM + 1) 41 #define ADC_TM5_FAST_AVG_EN BIT(7) 42 43 #define ADC_TM5_MEAS_INTERVAL_CTL (ADC_TM5_ADC_DIG_PARAM + 2) 44 #define ADC_TM5_TIMER1 3 /* 3.9ms */ 45 46 #define ADC_TM5_MEAS_INTERVAL_CTL2 (ADC_TM5_ADC_DIG_PARAM + 3) 47 #define ADC_TM5_MEAS_INTERVAL_CTL2_MASK 0xf0 48 #define ADC_TM5_TIMER2 10 /* 1 second */ 49 #define ADC_TM5_MEAS_INTERVAL_CTL3_MASK 0xf 50 #define ADC_TM5_TIMER3 4 /* 4 second */ 51 52 #define ADC_TM_EN_CTL1 0x46 53 #define ADC_TM_EN BIT(7) 54 #define ADC_TM_CONV_REQ 0x47 55 #define ADC_TM_CONV_REQ_EN BIT(7) 56 57 #define ADC_TM5_M_CHAN_BASE 0x60 58 59 #define ADC_TM5_M_ADC_CH_SEL_CTL(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 0) 60 #define ADC_TM5_M_LOW_THR0(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 1) 61 #define ADC_TM5_M_LOW_THR1(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 2) 62 #define ADC_TM5_M_HIGH_THR0(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 3) 63 #define ADC_TM5_M_HIGH_THR1(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 4) 64 #define ADC_TM5_M_MEAS_INTERVAL_CTL(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 5) 65 #define ADC_TM5_M_CTL(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 6) 66 #define ADC_TM5_M_CTL_HW_SETTLE_DELAY_MASK 0xf 67 #define ADC_TM5_M_CTL_CAL_SEL_MASK 0x30 68 #define ADC_TM5_M_CTL_CAL_VAL 0x40 69 #define ADC_TM5_M_EN(n) (ADC_TM5_M_CHAN_BASE + ((n) * 8) + 7) 70 #define ADC_TM5_M_MEAS_EN BIT(7) 71 #define ADC_TM5_M_HIGH_THR_INT_EN BIT(1) 72 #define ADC_TM5_M_LOW_THR_INT_EN BIT(0) 73 74 enum adc5_timer_select { 75 ADC5_TIMER_SEL_1 = 0, 76 ADC5_TIMER_SEL_2, 77 ADC5_TIMER_SEL_3, 78 ADC5_TIMER_SEL_NONE, 79 }; 80 81 struct adc_tm5_data { 82 const u32 full_scale_code_volt; 83 unsigned int *decimation; 84 unsigned int *hw_settle; 85 bool is_hc; 86 }; 87 88 enum adc_tm5_cal_method { 89 ADC_TM5_NO_CAL = 0, 90 ADC_TM5_RATIOMETRIC_CAL, 91 ADC_TM5_ABSOLUTE_CAL 92 }; 93 94 struct adc_tm5_chip; 95 96 /** 97 * struct adc_tm5_channel - ADC Thermal Monitoring channel data. 98 * @channel: channel number. 99 * @adc_channel: corresponding ADC channel number. 100 * @cal_method: calibration method. 101 * @prescale: channel scaling performed on the input signal. 102 * @hw_settle_time: the time between AMUX being configured and the 103 * start of conversion. 104 * @iio: IIO channel instance used by this channel. 105 * @chip: ADC TM chip instance. 106 * @tzd: thermal zone device used by this channel. 107 */ 108 struct adc_tm5_channel { 109 unsigned int channel; 110 unsigned int adc_channel; 111 enum adc_tm5_cal_method cal_method; 112 unsigned int prescale; 113 unsigned int hw_settle_time; 114 struct iio_channel *iio; 115 struct adc_tm5_chip *chip; 116 struct thermal_zone_device *tzd; 117 }; 118 119 /** 120 * struct adc_tm5_chip - ADC Thermal Monitoring properties 121 * @regmap: SPMI ADC5 Thermal Monitoring peripheral register map field. 122 * @dev: SPMI ADC5 device. 123 * @data: software configuration data. 124 * @channels: array of ADC TM channel data. 125 * @nchannels: amount of channels defined/allocated 126 * @decimation: sampling rate supported for the channel. 127 * @avg_samples: ability to provide single result from the ADC 128 * that is an average of multiple measurements. 129 * @base: base address of TM registers. 130 */ 131 struct adc_tm5_chip { 132 struct regmap *regmap; 133 struct device *dev; 134 const struct adc_tm5_data *data; 135 struct adc_tm5_channel *channels; 136 unsigned int nchannels; 137 unsigned int decimation; 138 unsigned int avg_samples; 139 u16 base; 140 }; 141 142 static const struct adc_tm5_data adc_tm5_data_pmic = { 143 .full_scale_code_volt = 0x70e4, 144 .decimation = (unsigned int []) { 250, 420, 840 }, 145 .hw_settle = (unsigned int []) { 15, 100, 200, 300, 400, 500, 600, 700, 146 1000, 2000, 4000, 8000, 16000, 32000, 147 64000, 128000 }, 148 }; 149 150 static const struct adc_tm5_data adc_tm_hc_data_pmic = { 151 .full_scale_code_volt = 0x70e4, 152 .decimation = (unsigned int []) { 256, 512, 1024 }, 153 .hw_settle = (unsigned int []) { 0, 100, 200, 300, 400, 500, 600, 700, 154 1000, 2000, 4000, 6000, 8000, 10000 }, 155 .is_hc = true, 156 }; 157 158 static int adc_tm5_read(struct adc_tm5_chip *adc_tm, u16 offset, u8 *data, int len) 159 { 160 return regmap_bulk_read(adc_tm->regmap, adc_tm->base + offset, data, len); 161 } 162 163 static int adc_tm5_write(struct adc_tm5_chip *adc_tm, u16 offset, u8 *data, int len) 164 { 165 return regmap_bulk_write(adc_tm->regmap, adc_tm->base + offset, data, len); 166 } 167 168 static int adc_tm5_reg_update(struct adc_tm5_chip *adc_tm, u16 offset, u8 mask, u8 val) 169 { 170 return regmap_write_bits(adc_tm->regmap, adc_tm->base + offset, mask, val); 171 } 172 173 static irqreturn_t adc_tm5_isr(int irq, void *data) 174 { 175 struct adc_tm5_chip *chip = data; 176 u8 status_low, status_high, ctl; 177 int ret, i; 178 179 ret = adc_tm5_read(chip, ADC_TM5_STATUS_LOW, &status_low, sizeof(status_low)); 180 if (unlikely(ret)) { 181 dev_err(chip->dev, "read status low failed: %d\n", ret); 182 return IRQ_HANDLED; 183 } 184 185 ret = adc_tm5_read(chip, ADC_TM5_STATUS_HIGH, &status_high, sizeof(status_high)); 186 if (unlikely(ret)) { 187 dev_err(chip->dev, "read status high failed: %d\n", ret); 188 return IRQ_HANDLED; 189 } 190 191 for (i = 0; i < chip->nchannels; i++) { 192 bool upper_set = false, lower_set = false; 193 unsigned int ch = chip->channels[i].channel; 194 195 /* No TZD, we warned at the boot time */ 196 if (!chip->channels[i].tzd) 197 continue; 198 199 ret = adc_tm5_read(chip, ADC_TM5_M_EN(ch), &ctl, sizeof(ctl)); 200 if (unlikely(ret)) { 201 dev_err(chip->dev, "ctl read failed: %d, channel %d\n", ret, i); 202 continue; 203 } 204 205 if (!(ctl & ADC_TM5_M_MEAS_EN)) 206 continue; 207 208 lower_set = (status_low & BIT(ch)) && 209 (ctl & ADC_TM5_M_LOW_THR_INT_EN); 210 211 upper_set = (status_high & BIT(ch)) && 212 (ctl & ADC_TM5_M_HIGH_THR_INT_EN); 213 214 if (upper_set || lower_set) 215 thermal_zone_device_update(chip->channels[i].tzd, 216 THERMAL_EVENT_UNSPECIFIED); 217 } 218 219 return IRQ_HANDLED; 220 } 221 222 static int adc_tm5_get_temp(void *data, int *temp) 223 { 224 struct adc_tm5_channel *channel = data; 225 int ret; 226 227 if (!channel || !channel->iio) 228 return -EINVAL; 229 230 ret = iio_read_channel_processed(channel->iio, temp); 231 if (ret < 0) 232 return ret; 233 234 if (ret != IIO_VAL_INT) 235 return -EINVAL; 236 237 return 0; 238 } 239 240 static int adc_tm5_disable_channel(struct adc_tm5_channel *channel) 241 { 242 struct adc_tm5_chip *chip = channel->chip; 243 unsigned int reg = ADC_TM5_M_EN(channel->channel); 244 245 return adc_tm5_reg_update(chip, reg, 246 ADC_TM5_M_MEAS_EN | 247 ADC_TM5_M_HIGH_THR_INT_EN | 248 ADC_TM5_M_LOW_THR_INT_EN, 249 0); 250 } 251 252 static int adc_tm5_enable(struct adc_tm5_chip *chip) 253 { 254 int ret; 255 u8 data; 256 257 data = ADC_TM_EN; 258 ret = adc_tm5_write(chip, ADC_TM_EN_CTL1, &data, sizeof(data)); 259 if (ret < 0) { 260 dev_err(chip->dev, "adc-tm enable failed\n"); 261 return ret; 262 } 263 264 data = ADC_TM_CONV_REQ_EN; 265 ret = adc_tm5_write(chip, ADC_TM_CONV_REQ, &data, sizeof(data)); 266 if (ret < 0) { 267 dev_err(chip->dev, "adc-tm request conversion failed\n"); 268 return ret; 269 } 270 271 return 0; 272 } 273 274 static int adc_tm5_configure(struct adc_tm5_channel *channel, int low, int high) 275 { 276 struct adc_tm5_chip *chip = channel->chip; 277 u8 buf[8]; 278 u16 reg = ADC_TM5_M_ADC_CH_SEL_CTL(channel->channel); 279 int ret; 280 281 ret = adc_tm5_read(chip, reg, buf, sizeof(buf)); 282 if (ret) { 283 dev_err(chip->dev, "channel %d params read failed: %d\n", channel->channel, ret); 284 return ret; 285 } 286 287 buf[0] = channel->adc_channel; 288 289 /* High temperature corresponds to low voltage threshold */ 290 if (high != INT_MAX) { 291 u16 adc_code = qcom_adc_tm5_temp_volt_scale(channel->prescale, 292 chip->data->full_scale_code_volt, high); 293 294 buf[1] = adc_code & 0xff; 295 buf[2] = adc_code >> 8; 296 buf[7] |= ADC_TM5_M_LOW_THR_INT_EN; 297 } else { 298 buf[7] &= ~ADC_TM5_M_LOW_THR_INT_EN; 299 } 300 301 /* Low temperature corresponds to high voltage threshold */ 302 if (low != -INT_MAX) { 303 u16 adc_code = qcom_adc_tm5_temp_volt_scale(channel->prescale, 304 chip->data->full_scale_code_volt, low); 305 306 buf[3] = adc_code & 0xff; 307 buf[4] = adc_code >> 8; 308 buf[7] |= ADC_TM5_M_HIGH_THR_INT_EN; 309 } else { 310 buf[7] &= ~ADC_TM5_M_HIGH_THR_INT_EN; 311 } 312 313 buf[5] = ADC5_TIMER_SEL_2; 314 315 /* Set calibration select, hw_settle delay */ 316 buf[6] &= ~ADC_TM5_M_CTL_HW_SETTLE_DELAY_MASK; 317 buf[6] |= FIELD_PREP(ADC_TM5_M_CTL_HW_SETTLE_DELAY_MASK, channel->hw_settle_time); 318 buf[6] &= ~ADC_TM5_M_CTL_CAL_SEL_MASK; 319 buf[6] |= FIELD_PREP(ADC_TM5_M_CTL_CAL_SEL_MASK, channel->cal_method); 320 321 buf[7] |= ADC_TM5_M_MEAS_EN; 322 323 ret = adc_tm5_write(chip, reg, buf, sizeof(buf)); 324 if (ret) { 325 dev_err(chip->dev, "channel %d params write failed: %d\n", channel->channel, ret); 326 return ret; 327 } 328 329 return adc_tm5_enable(chip); 330 } 331 332 static int adc_tm5_set_trips(void *data, int low, int high) 333 { 334 struct adc_tm5_channel *channel = data; 335 struct adc_tm5_chip *chip; 336 int ret; 337 338 if (!channel) 339 return -EINVAL; 340 341 chip = channel->chip; 342 dev_dbg(chip->dev, "%d:low(mdegC):%d, high(mdegC):%d\n", 343 channel->channel, low, high); 344 345 if (high == INT_MAX && low <= -INT_MAX) 346 ret = adc_tm5_disable_channel(channel); 347 else 348 ret = adc_tm5_configure(channel, low, high); 349 350 return ret; 351 } 352 353 static struct thermal_zone_of_device_ops adc_tm5_ops = { 354 .get_temp = adc_tm5_get_temp, 355 .set_trips = adc_tm5_set_trips, 356 }; 357 358 static int adc_tm5_register_tzd(struct adc_tm5_chip *adc_tm) 359 { 360 unsigned int i; 361 struct thermal_zone_device *tzd; 362 363 for (i = 0; i < adc_tm->nchannels; i++) { 364 adc_tm->channels[i].chip = adc_tm; 365 366 tzd = devm_thermal_zone_of_sensor_register(adc_tm->dev, 367 adc_tm->channels[i].channel, 368 &adc_tm->channels[i], 369 &adc_tm5_ops); 370 if (IS_ERR(tzd)) { 371 if (PTR_ERR(tzd) == -ENODEV) { 372 dev_warn(adc_tm->dev, "thermal sensor on channel %d is not used\n", 373 adc_tm->channels[i].channel); 374 continue; 375 } 376 377 dev_err(adc_tm->dev, "Error registering TZ zone for channel %d: %ld\n", 378 adc_tm->channels[i].channel, PTR_ERR(tzd)); 379 return PTR_ERR(tzd); 380 } 381 adc_tm->channels[i].tzd = tzd; 382 } 383 384 return 0; 385 } 386 387 static int adc_tm_hc_init(struct adc_tm5_chip *chip) 388 { 389 unsigned int i; 390 u8 buf[2]; 391 int ret; 392 393 for (i = 0; i < chip->nchannels; i++) { 394 if (chip->channels[i].channel >= ADC_TM5_NUM_CHANNELS) { 395 dev_err(chip->dev, "Invalid channel %d\n", chip->channels[i].channel); 396 return -EINVAL; 397 } 398 } 399 400 buf[0] = chip->decimation; 401 buf[1] = chip->avg_samples | ADC_TM5_FAST_AVG_EN; 402 403 ret = adc_tm5_write(chip, ADC_TM5_ADC_DIG_PARAM, buf, sizeof(buf)); 404 if (ret) 405 dev_err(chip->dev, "block write failed: %d\n", ret); 406 407 return ret; 408 } 409 410 static int adc_tm5_init(struct adc_tm5_chip *chip) 411 { 412 u8 buf[4], channels_available; 413 int ret; 414 unsigned int i; 415 416 ret = adc_tm5_read(chip, ADC_TM5_NUM_BTM, 417 &channels_available, sizeof(channels_available)); 418 if (ret) { 419 dev_err(chip->dev, "read failed for BTM channels\n"); 420 return ret; 421 } 422 423 for (i = 0; i < chip->nchannels; i++) { 424 if (chip->channels[i].channel >= channels_available) { 425 dev_err(chip->dev, "Invalid channel %d\n", chip->channels[i].channel); 426 return -EINVAL; 427 } 428 } 429 430 buf[0] = chip->decimation; 431 buf[1] = chip->avg_samples | ADC_TM5_FAST_AVG_EN; 432 buf[2] = ADC_TM5_TIMER1; 433 buf[3] = FIELD_PREP(ADC_TM5_MEAS_INTERVAL_CTL2_MASK, ADC_TM5_TIMER2) | 434 FIELD_PREP(ADC_TM5_MEAS_INTERVAL_CTL3_MASK, ADC_TM5_TIMER3); 435 436 ret = adc_tm5_write(chip, ADC_TM5_ADC_DIG_PARAM, buf, sizeof(buf)); 437 if (ret) { 438 dev_err(chip->dev, "block write failed: %d\n", ret); 439 return ret; 440 } 441 442 return ret; 443 } 444 445 static int adc_tm5_get_dt_channel_data(struct adc_tm5_chip *adc_tm, 446 struct adc_tm5_channel *channel, 447 struct device_node *node) 448 { 449 const char *name = node->name; 450 u32 chan, value, varr[2]; 451 int ret; 452 struct device *dev = adc_tm->dev; 453 struct of_phandle_args args; 454 455 ret = of_property_read_u32(node, "reg", &chan); 456 if (ret) { 457 dev_err(dev, "%s: invalid channel number %d\n", name, ret); 458 return ret; 459 } 460 461 if (chan >= ADC_TM5_NUM_CHANNELS) { 462 dev_err(dev, "%s: channel number too big: %d\n", name, chan); 463 return -EINVAL; 464 } 465 466 channel->channel = chan; 467 468 /* 469 * We are tied to PMIC's ADC controller, which always use single 470 * argument for channel number. So don't bother parsing 471 * #io-channel-cells, just enforce cell_count = 1. 472 */ 473 ret = of_parse_phandle_with_fixed_args(node, "io-channels", 1, 0, &args); 474 if (ret < 0) { 475 dev_err(dev, "%s: error parsing ADC channel number %d: %d\n", name, chan, ret); 476 return ret; 477 } 478 of_node_put(args.np); 479 480 if (args.args_count != 1 || args.args[0] >= ADC5_MAX_CHANNEL) { 481 dev_err(dev, "%s: invalid ADC channel number %d\n", name, chan); 482 return -EINVAL; 483 } 484 channel->adc_channel = args.args[0]; 485 486 channel->iio = devm_of_iio_channel_get_by_name(adc_tm->dev, node, NULL); 487 if (IS_ERR(channel->iio)) { 488 ret = PTR_ERR(channel->iio); 489 if (ret != -EPROBE_DEFER) 490 dev_err(dev, "%s: error getting channel: %d\n", name, ret); 491 return ret; 492 } 493 494 ret = of_property_read_u32_array(node, "qcom,pre-scaling", varr, 2); 495 if (!ret) { 496 ret = qcom_adc5_prescaling_from_dt(varr[0], varr[1]); 497 if (ret < 0) { 498 dev_err(dev, "%s: invalid pre-scaling <%d %d>\n", 499 name, varr[0], varr[1]); 500 return ret; 501 } 502 channel->prescale = ret; 503 } else { 504 /* 1:1 prescale is index 0 */ 505 channel->prescale = 0; 506 } 507 508 ret = of_property_read_u32(node, "qcom,hw-settle-time-us", &value); 509 if (!ret) { 510 ret = qcom_adc5_hw_settle_time_from_dt(value, adc_tm->data->hw_settle); 511 if (ret < 0) { 512 dev_err(dev, "%s invalid hw-settle-time-us %d us\n", 513 name, value); 514 return ret; 515 } 516 channel->hw_settle_time = ret; 517 } else { 518 channel->hw_settle_time = VADC_DEF_HW_SETTLE_TIME; 519 } 520 521 if (of_property_read_bool(node, "qcom,ratiometric")) 522 channel->cal_method = ADC_TM5_RATIOMETRIC_CAL; 523 else 524 channel->cal_method = ADC_TM5_ABSOLUTE_CAL; 525 526 return 0; 527 } 528 529 static int adc_tm5_get_dt_data(struct adc_tm5_chip *adc_tm, struct device_node *node) 530 { 531 struct adc_tm5_channel *channels; 532 struct device_node *child; 533 u32 value; 534 int ret; 535 struct device *dev = adc_tm->dev; 536 537 adc_tm->nchannels = of_get_available_child_count(node); 538 if (!adc_tm->nchannels) 539 return -EINVAL; 540 541 adc_tm->channels = devm_kcalloc(dev, adc_tm->nchannels, 542 sizeof(*adc_tm->channels), GFP_KERNEL); 543 if (!adc_tm->channels) 544 return -ENOMEM; 545 546 channels = adc_tm->channels; 547 548 adc_tm->data = of_device_get_match_data(dev); 549 if (!adc_tm->data) 550 adc_tm->data = &adc_tm5_data_pmic; 551 552 ret = of_property_read_u32(node, "qcom,decimation", &value); 553 if (!ret) { 554 ret = qcom_adc5_decimation_from_dt(value, adc_tm->data->decimation); 555 if (ret < 0) { 556 dev_err(dev, "invalid decimation %d\n", value); 557 return ret; 558 } 559 adc_tm->decimation = ret; 560 } else { 561 adc_tm->decimation = ADC5_DECIMATION_DEFAULT; 562 } 563 564 ret = of_property_read_u32(node, "qcom,avg-samples", &value); 565 if (!ret) { 566 ret = qcom_adc5_avg_samples_from_dt(value); 567 if (ret < 0) { 568 dev_err(dev, "invalid avg-samples %d\n", value); 569 return ret; 570 } 571 adc_tm->avg_samples = ret; 572 } else { 573 adc_tm->avg_samples = VADC_DEF_AVG_SAMPLES; 574 } 575 576 for_each_available_child_of_node(node, child) { 577 ret = adc_tm5_get_dt_channel_data(adc_tm, channels, child); 578 if (ret) { 579 of_node_put(child); 580 return ret; 581 } 582 583 channels++; 584 } 585 586 return 0; 587 } 588 589 static int adc_tm5_probe(struct platform_device *pdev) 590 { 591 struct device_node *node = pdev->dev.of_node; 592 struct device *dev = &pdev->dev; 593 struct adc_tm5_chip *adc_tm; 594 struct regmap *regmap; 595 int ret, irq; 596 u32 reg; 597 598 regmap = dev_get_regmap(dev->parent, NULL); 599 if (!regmap) 600 return -ENODEV; 601 602 ret = of_property_read_u32(node, "reg", ®); 603 if (ret) 604 return ret; 605 606 adc_tm = devm_kzalloc(&pdev->dev, sizeof(*adc_tm), GFP_KERNEL); 607 if (!adc_tm) 608 return -ENOMEM; 609 610 adc_tm->regmap = regmap; 611 adc_tm->dev = dev; 612 adc_tm->base = reg; 613 614 irq = platform_get_irq(pdev, 0); 615 if (irq < 0) { 616 dev_err(dev, "get_irq failed: %d\n", irq); 617 return irq; 618 } 619 620 ret = adc_tm5_get_dt_data(adc_tm, node); 621 if (ret) { 622 dev_err(dev, "get dt data failed: %d\n", ret); 623 return ret; 624 } 625 626 if (adc_tm->data->is_hc) 627 ret = adc_tm_hc_init(adc_tm); 628 else 629 ret = adc_tm5_init(adc_tm); 630 if (ret) { 631 dev_err(dev, "adc-tm init failed\n"); 632 return ret; 633 } 634 635 ret = adc_tm5_register_tzd(adc_tm); 636 if (ret) { 637 dev_err(dev, "tzd register failed\n"); 638 return ret; 639 } 640 641 return devm_request_threaded_irq(dev, irq, NULL, adc_tm5_isr, 642 IRQF_ONESHOT, "pm-adc-tm5", adc_tm); 643 } 644 645 static const struct of_device_id adc_tm5_match_table[] = { 646 { 647 .compatible = "qcom,spmi-adc-tm5", 648 .data = &adc_tm5_data_pmic, 649 }, 650 { 651 .compatible = "qcom,spmi-adc-tm-hc", 652 .data = &adc_tm_hc_data_pmic, 653 }, 654 { } 655 }; 656 MODULE_DEVICE_TABLE(of, adc_tm5_match_table); 657 658 static struct platform_driver adc_tm5_driver = { 659 .driver = { 660 .name = "qcom-spmi-adc-tm5", 661 .of_match_table = adc_tm5_match_table, 662 }, 663 .probe = adc_tm5_probe, 664 }; 665 module_platform_driver(adc_tm5_driver); 666 667 MODULE_DESCRIPTION("SPMI PMIC Thermal Monitor ADC driver"); 668 MODULE_LICENSE("GPL v2"); 669