1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2023 MediaTek Inc. 4 * Author: Balsam CHIHI <bchihi@baylibre.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/clk-provider.h> 9 #include <linux/delay.h> 10 #include <linux/debugfs.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/iopoll.h> 14 #include <linux/kernel.h> 15 #include <linux/nvmem-consumer.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/reset.h> 19 #include <linux/thermal.h> 20 #include <dt-bindings/thermal/mediatek,lvts-thermal.h> 21 22 #include "../thermal_hwmon.h" 23 24 #define LVTS_MONCTL0(__base) (__base + 0x0000) 25 #define LVTS_MONCTL1(__base) (__base + 0x0004) 26 #define LVTS_MONCTL2(__base) (__base + 0x0008) 27 #define LVTS_MONINT(__base) (__base + 0x000C) 28 #define LVTS_MONINTSTS(__base) (__base + 0x0010) 29 #define LVTS_MONIDET0(__base) (__base + 0x0014) 30 #define LVTS_MONIDET1(__base) (__base + 0x0018) 31 #define LVTS_MONIDET2(__base) (__base + 0x001C) 32 #define LVTS_MONIDET3(__base) (__base + 0x0020) 33 #define LVTS_H2NTHRE(__base) (__base + 0x0024) 34 #define LVTS_HTHRE(__base) (__base + 0x0028) 35 #define LVTS_OFFSETH(__base) (__base + 0x0030) 36 #define LVTS_OFFSETL(__base) (__base + 0x0034) 37 #define LVTS_MSRCTL0(__base) (__base + 0x0038) 38 #define LVTS_MSRCTL1(__base) (__base + 0x003C) 39 #define LVTS_TSSEL(__base) (__base + 0x0040) 40 #define LVTS_CALSCALE(__base) (__base + 0x0048) 41 #define LVTS_ID(__base) (__base + 0x004C) 42 #define LVTS_CONFIG(__base) (__base + 0x0050) 43 #define LVTS_EDATA00(__base) (__base + 0x0054) 44 #define LVTS_EDATA01(__base) (__base + 0x0058) 45 #define LVTS_EDATA02(__base) (__base + 0x005C) 46 #define LVTS_EDATA03(__base) (__base + 0x0060) 47 #define LVTS_MSR0(__base) (__base + 0x0090) 48 #define LVTS_MSR1(__base) (__base + 0x0094) 49 #define LVTS_MSR2(__base) (__base + 0x0098) 50 #define LVTS_MSR3(__base) (__base + 0x009C) 51 #define LVTS_IMMD0(__base) (__base + 0x00A0) 52 #define LVTS_IMMD1(__base) (__base + 0x00A4) 53 #define LVTS_IMMD2(__base) (__base + 0x00A8) 54 #define LVTS_IMMD3(__base) (__base + 0x00AC) 55 #define LVTS_PROTCTL(__base) (__base + 0x00C0) 56 #define LVTS_PROTTA(__base) (__base + 0x00C4) 57 #define LVTS_PROTTB(__base) (__base + 0x00C8) 58 #define LVTS_PROTTC(__base) (__base + 0x00CC) 59 #define LVTS_CLKEN(__base) (__base + 0x00E4) 60 61 #define LVTS_PERIOD_UNIT 0 62 #define LVTS_GROUP_INTERVAL 0 63 #define LVTS_FILTER_INTERVAL 0 64 #define LVTS_SENSOR_INTERVAL 0 65 #define LVTS_HW_FILTER 0x0 66 #define LVTS_TSSEL_CONF 0x13121110 67 #define LVTS_CALSCALE_CONF 0x300 68 #define LVTS_MONINT_CONF 0x8300318C 69 70 #define LVTS_MONINT_OFFSET_SENSOR0 0xC 71 #define LVTS_MONINT_OFFSET_SENSOR1 0x180 72 #define LVTS_MONINT_OFFSET_SENSOR2 0x3000 73 #define LVTS_MONINT_OFFSET_SENSOR3 0x3000000 74 75 #define LVTS_INT_SENSOR0 0x0009001F 76 #define LVTS_INT_SENSOR1 0x001203E0 77 #define LVTS_INT_SENSOR2 0x00247C00 78 #define LVTS_INT_SENSOR3 0x1FC00000 79 80 #define LVTS_SENSOR_MAX 4 81 #define LVTS_GOLDEN_TEMP_MAX 62 82 #define LVTS_GOLDEN_TEMP_DEFAULT 50 83 #define LVTS_COEFF_A_MT8195 -250460 84 #define LVTS_COEFF_B_MT8195 250460 85 #define LVTS_COEFF_A_MT7988 -204650 86 #define LVTS_COEFF_B_MT7988 204650 87 88 #define LVTS_MSR_IMMEDIATE_MODE 0 89 #define LVTS_MSR_FILTERED_MODE 1 90 91 #define LVTS_MSR_READ_TIMEOUT_US 400 92 #define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2) 93 94 #define LVTS_HW_TSHUT_TEMP 105000 95 96 #define LVTS_MINIMUM_THRESHOLD 20000 97 98 static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT; 99 static int golden_temp_offset; 100 101 struct lvts_sensor_data { 102 int dt_id; 103 u8 cal_offsets[3]; 104 }; 105 106 struct lvts_ctrl_data { 107 struct lvts_sensor_data lvts_sensor[LVTS_SENSOR_MAX]; 108 u8 valid_sensor_mask; 109 int offset; 110 int mode; 111 }; 112 113 #define VALID_SENSOR_MAP(s0, s1, s2, s3) \ 114 .valid_sensor_mask = (((s0) ? BIT(0) : 0) | \ 115 ((s1) ? BIT(1) : 0) | \ 116 ((s2) ? BIT(2) : 0) | \ 117 ((s3) ? BIT(3) : 0)) 118 119 #define lvts_for_each_valid_sensor(i, lvts_ctrl_data) \ 120 for ((i) = 0; (i) < LVTS_SENSOR_MAX; (i)++) \ 121 if (!((lvts_ctrl_data)->valid_sensor_mask & BIT(i))) \ 122 continue; \ 123 else 124 125 struct lvts_data { 126 const struct lvts_ctrl_data *lvts_ctrl; 127 int num_lvts_ctrl; 128 int temp_factor; 129 int temp_offset; 130 int gt_calib_bit_offset; 131 }; 132 133 struct lvts_sensor { 134 struct thermal_zone_device *tz; 135 void __iomem *msr; 136 void __iomem *base; 137 int id; 138 int dt_id; 139 int low_thresh; 140 int high_thresh; 141 }; 142 143 struct lvts_ctrl { 144 struct lvts_sensor sensors[LVTS_SENSOR_MAX]; 145 const struct lvts_data *lvts_data; 146 u32 calibration[LVTS_SENSOR_MAX]; 147 u32 hw_tshut_raw_temp; 148 int mode; 149 void __iomem *base; 150 int low_thresh; 151 int high_thresh; 152 }; 153 154 struct lvts_domain { 155 struct lvts_ctrl *lvts_ctrl; 156 struct reset_control *reset; 157 struct clk *clk; 158 int num_lvts_ctrl; 159 void __iomem *base; 160 size_t calib_len; 161 u8 *calib; 162 #ifdef CONFIG_DEBUG_FS 163 struct dentry *dom_dentry; 164 #endif 165 }; 166 167 #ifdef CONFIG_MTK_LVTS_THERMAL_DEBUGFS 168 169 #define LVTS_DEBUG_FS_REGS(__reg) \ 170 { \ 171 .name = __stringify(__reg), \ 172 .offset = __reg(0), \ 173 } 174 175 static const struct debugfs_reg32 lvts_regs[] = { 176 LVTS_DEBUG_FS_REGS(LVTS_MONCTL0), 177 LVTS_DEBUG_FS_REGS(LVTS_MONCTL1), 178 LVTS_DEBUG_FS_REGS(LVTS_MONCTL2), 179 LVTS_DEBUG_FS_REGS(LVTS_MONINT), 180 LVTS_DEBUG_FS_REGS(LVTS_MONINTSTS), 181 LVTS_DEBUG_FS_REGS(LVTS_MONIDET0), 182 LVTS_DEBUG_FS_REGS(LVTS_MONIDET1), 183 LVTS_DEBUG_FS_REGS(LVTS_MONIDET2), 184 LVTS_DEBUG_FS_REGS(LVTS_MONIDET3), 185 LVTS_DEBUG_FS_REGS(LVTS_H2NTHRE), 186 LVTS_DEBUG_FS_REGS(LVTS_HTHRE), 187 LVTS_DEBUG_FS_REGS(LVTS_OFFSETH), 188 LVTS_DEBUG_FS_REGS(LVTS_OFFSETL), 189 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL0), 190 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL1), 191 LVTS_DEBUG_FS_REGS(LVTS_TSSEL), 192 LVTS_DEBUG_FS_REGS(LVTS_CALSCALE), 193 LVTS_DEBUG_FS_REGS(LVTS_ID), 194 LVTS_DEBUG_FS_REGS(LVTS_CONFIG), 195 LVTS_DEBUG_FS_REGS(LVTS_EDATA00), 196 LVTS_DEBUG_FS_REGS(LVTS_EDATA01), 197 LVTS_DEBUG_FS_REGS(LVTS_EDATA02), 198 LVTS_DEBUG_FS_REGS(LVTS_EDATA03), 199 LVTS_DEBUG_FS_REGS(LVTS_MSR0), 200 LVTS_DEBUG_FS_REGS(LVTS_MSR1), 201 LVTS_DEBUG_FS_REGS(LVTS_MSR2), 202 LVTS_DEBUG_FS_REGS(LVTS_MSR3), 203 LVTS_DEBUG_FS_REGS(LVTS_IMMD0), 204 LVTS_DEBUG_FS_REGS(LVTS_IMMD1), 205 LVTS_DEBUG_FS_REGS(LVTS_IMMD2), 206 LVTS_DEBUG_FS_REGS(LVTS_IMMD3), 207 LVTS_DEBUG_FS_REGS(LVTS_PROTCTL), 208 LVTS_DEBUG_FS_REGS(LVTS_PROTTA), 209 LVTS_DEBUG_FS_REGS(LVTS_PROTTB), 210 LVTS_DEBUG_FS_REGS(LVTS_PROTTC), 211 LVTS_DEBUG_FS_REGS(LVTS_CLKEN), 212 }; 213 214 static int lvts_debugfs_init(struct device *dev, struct lvts_domain *lvts_td) 215 { 216 struct debugfs_regset32 *regset; 217 struct lvts_ctrl *lvts_ctrl; 218 struct dentry *dentry; 219 char name[64]; 220 int i; 221 222 lvts_td->dom_dentry = debugfs_create_dir(dev_name(dev), NULL); 223 if (IS_ERR(lvts_td->dom_dentry)) 224 return 0; 225 226 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 227 228 lvts_ctrl = &lvts_td->lvts_ctrl[i]; 229 230 sprintf(name, "controller%d", i); 231 dentry = debugfs_create_dir(name, lvts_td->dom_dentry); 232 if (IS_ERR(dentry)) 233 continue; 234 235 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 236 if (!regset) 237 continue; 238 239 regset->base = lvts_ctrl->base; 240 regset->regs = lvts_regs; 241 regset->nregs = ARRAY_SIZE(lvts_regs); 242 243 debugfs_create_regset32("registers", 0400, dentry, regset); 244 } 245 246 return 0; 247 } 248 249 static void lvts_debugfs_exit(struct lvts_domain *lvts_td) 250 { 251 debugfs_remove_recursive(lvts_td->dom_dentry); 252 } 253 254 #else 255 256 static inline int lvts_debugfs_init(struct device *dev, 257 struct lvts_domain *lvts_td) 258 { 259 return 0; 260 } 261 262 static void lvts_debugfs_exit(struct lvts_domain *lvts_td) { } 263 264 #endif 265 266 static int lvts_raw_to_temp(u32 raw_temp, int temp_factor) 267 { 268 int temperature; 269 270 temperature = ((s64)(raw_temp & 0xFFFF) * temp_factor) >> 14; 271 temperature += golden_temp_offset; 272 273 return temperature; 274 } 275 276 static u32 lvts_temp_to_raw(int temperature, int temp_factor) 277 { 278 u32 raw_temp = ((s64)(golden_temp_offset - temperature)) << 14; 279 280 raw_temp = div_s64(raw_temp, -temp_factor); 281 282 return raw_temp; 283 } 284 285 static int lvts_get_temp(struct thermal_zone_device *tz, int *temp) 286 { 287 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); 288 struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, 289 sensors[lvts_sensor->id]); 290 const struct lvts_data *lvts_data = lvts_ctrl->lvts_data; 291 void __iomem *msr = lvts_sensor->msr; 292 u32 value; 293 int rc; 294 295 /* 296 * Measurement registers: 297 * 298 * LVTS_MSR[0-3] / LVTS_IMMD[0-3] 299 * 300 * Bits: 301 * 302 * 32-17: Unused 303 * 16 : Valid temperature 304 * 15-0 : Raw temperature 305 */ 306 rc = readl_poll_timeout(msr, value, value & BIT(16), 307 LVTS_MSR_READ_WAIT_US, LVTS_MSR_READ_TIMEOUT_US); 308 309 /* 310 * As the thermal zone temperature will read before the 311 * hardware sensor is fully initialized, we have to check the 312 * validity of the temperature returned when reading the 313 * measurement register. The thermal controller will set the 314 * valid bit temperature only when it is totally initialized. 315 * 316 * Otherwise, we may end up with garbage values out of the 317 * functionning temperature and directly jump to a system 318 * shutdown. 319 */ 320 if (rc) 321 return -EAGAIN; 322 323 *temp = lvts_raw_to_temp(value & 0xFFFF, lvts_data->temp_factor); 324 325 return 0; 326 } 327 328 static void lvts_update_irq_mask(struct lvts_ctrl *lvts_ctrl) 329 { 330 u32 masks[] = { 331 LVTS_MONINT_OFFSET_SENSOR0, 332 LVTS_MONINT_OFFSET_SENSOR1, 333 LVTS_MONINT_OFFSET_SENSOR2, 334 LVTS_MONINT_OFFSET_SENSOR3, 335 }; 336 u32 value = 0; 337 int i; 338 339 value = readl(LVTS_MONINT(lvts_ctrl->base)); 340 341 for (i = 0; i < ARRAY_SIZE(masks); i++) { 342 if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh 343 && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh) 344 value |= masks[i]; 345 else 346 value &= ~masks[i]; 347 } 348 349 writel(value, LVTS_MONINT(lvts_ctrl->base)); 350 } 351 352 static bool lvts_should_update_thresh(struct lvts_ctrl *lvts_ctrl, int high) 353 { 354 int i; 355 356 if (high > lvts_ctrl->high_thresh) 357 return true; 358 359 lvts_for_each_valid_sensor(i, lvts_ctrl->lvts_data->lvts_ctrl) 360 if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh 361 && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh) 362 return false; 363 364 return true; 365 } 366 367 static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high) 368 { 369 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); 370 struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, 371 sensors[lvts_sensor->id]); 372 const struct lvts_data *lvts_data = lvts_ctrl->lvts_data; 373 void __iomem *base = lvts_sensor->base; 374 u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD, 375 lvts_data->temp_factor); 376 u32 raw_high = lvts_temp_to_raw(high, lvts_data->temp_factor); 377 bool should_update_thresh; 378 379 lvts_sensor->low_thresh = low; 380 lvts_sensor->high_thresh = high; 381 382 should_update_thresh = lvts_should_update_thresh(lvts_ctrl, high); 383 if (should_update_thresh) { 384 lvts_ctrl->high_thresh = high; 385 lvts_ctrl->low_thresh = low; 386 } 387 lvts_update_irq_mask(lvts_ctrl); 388 389 if (!should_update_thresh) 390 return 0; 391 392 /* 393 * Low offset temperature threshold 394 * 395 * LVTS_OFFSETL 396 * 397 * Bits: 398 * 399 * 14-0 : Raw temperature for threshold 400 */ 401 pr_debug("%s: Setting low limit temperature interrupt: %d\n", 402 thermal_zone_device_type(tz), low); 403 writel(raw_low, LVTS_OFFSETL(base)); 404 405 /* 406 * High offset temperature threshold 407 * 408 * LVTS_OFFSETH 409 * 410 * Bits: 411 * 412 * 14-0 : Raw temperature for threshold 413 */ 414 pr_debug("%s: Setting high limit temperature interrupt: %d\n", 415 thermal_zone_device_type(tz), high); 416 writel(raw_high, LVTS_OFFSETH(base)); 417 418 return 0; 419 } 420 421 static irqreturn_t lvts_ctrl_irq_handler(struct lvts_ctrl *lvts_ctrl) 422 { 423 irqreturn_t iret = IRQ_NONE; 424 u32 value; 425 u32 masks[] = { 426 LVTS_INT_SENSOR0, 427 LVTS_INT_SENSOR1, 428 LVTS_INT_SENSOR2, 429 LVTS_INT_SENSOR3 430 }; 431 int i; 432 433 /* 434 * Interrupt monitoring status 435 * 436 * LVTS_MONINTST 437 * 438 * Bits: 439 * 440 * 31 : Interrupt for stage 3 441 * 30 : Interrupt for stage 2 442 * 29 : Interrupt for state 1 443 * 28 : Interrupt using filter on sensor 3 444 * 445 * 27 : Interrupt using immediate on sensor 3 446 * 26 : Interrupt normal to hot on sensor 3 447 * 25 : Interrupt high offset on sensor 3 448 * 24 : Interrupt low offset on sensor 3 449 * 450 * 23 : Interrupt hot threshold on sensor 3 451 * 22 : Interrupt cold threshold on sensor 3 452 * 21 : Interrupt using filter on sensor 2 453 * 20 : Interrupt using filter on sensor 1 454 * 455 * 19 : Interrupt using filter on sensor 0 456 * 18 : Interrupt using immediate on sensor 2 457 * 17 : Interrupt using immediate on sensor 1 458 * 16 : Interrupt using immediate on sensor 0 459 * 460 * 15 : Interrupt device access timeout interrupt 461 * 14 : Interrupt normal to hot on sensor 2 462 * 13 : Interrupt high offset interrupt on sensor 2 463 * 12 : Interrupt low offset interrupt on sensor 2 464 * 465 * 11 : Interrupt hot threshold on sensor 2 466 * 10 : Interrupt cold threshold on sensor 2 467 * 9 : Interrupt normal to hot on sensor 1 468 * 8 : Interrupt high offset interrupt on sensor 1 469 * 470 * 7 : Interrupt low offset interrupt on sensor 1 471 * 6 : Interrupt hot threshold on sensor 1 472 * 5 : Interrupt cold threshold on sensor 1 473 * 4 : Interrupt normal to hot on sensor 0 474 * 475 * 3 : Interrupt high offset interrupt on sensor 0 476 * 2 : Interrupt low offset interrupt on sensor 0 477 * 1 : Interrupt hot threshold on sensor 0 478 * 0 : Interrupt cold threshold on sensor 0 479 * 480 * We are interested in the sensor(s) responsible of the 481 * interrupt event. We update the thermal framework with the 482 * thermal zone associated with the sensor. The framework will 483 * take care of the rest whatever the kind of interrupt, we 484 * are only interested in which sensor raised the interrupt. 485 * 486 * sensor 3 interrupt: 0001 1111 1100 0000 0000 0000 0000 0000 487 * => 0x1FC00000 488 * sensor 2 interrupt: 0000 0000 0010 0100 0111 1100 0000 0000 489 * => 0x00247C00 490 * sensor 1 interrupt: 0000 0000 0001 0010 0000 0011 1110 0000 491 * => 0X001203E0 492 * sensor 0 interrupt: 0000 0000 0000 1001 0000 0000 0001 1111 493 * => 0x0009001F 494 */ 495 value = readl(LVTS_MONINTSTS(lvts_ctrl->base)); 496 497 /* 498 * Let's figure out which sensors raised the interrupt 499 * 500 * NOTE: the masks array must be ordered with the index 501 * corresponding to the sensor id eg. index=0, mask for 502 * sensor0. 503 */ 504 for (i = 0; i < ARRAY_SIZE(masks); i++) { 505 506 if (!(value & masks[i])) 507 continue; 508 509 thermal_zone_device_update(lvts_ctrl->sensors[i].tz, 510 THERMAL_TRIP_VIOLATED); 511 iret = IRQ_HANDLED; 512 } 513 514 /* 515 * Write back to clear the interrupt status (W1C) 516 */ 517 writel(value, LVTS_MONINTSTS(lvts_ctrl->base)); 518 519 return iret; 520 } 521 522 /* 523 * Temperature interrupt handler. Even if the driver supports more 524 * interrupt modes, we use the interrupt when the temperature crosses 525 * the hot threshold the way up and the way down (modulo the 526 * hysteresis). 527 * 528 * Each thermal domain has a couple of interrupts, one for hardware 529 * reset and another one for all the thermal events happening on the 530 * different sensors. 531 * 532 * The interrupt is configured for thermal events when crossing the 533 * hot temperature limit. At each interrupt, we check in every 534 * controller if there is an interrupt pending. 535 */ 536 static irqreturn_t lvts_irq_handler(int irq, void *data) 537 { 538 struct lvts_domain *lvts_td = data; 539 irqreturn_t aux, iret = IRQ_NONE; 540 int i; 541 542 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 543 544 aux = lvts_ctrl_irq_handler(&lvts_td->lvts_ctrl[i]); 545 if (aux != IRQ_HANDLED) 546 continue; 547 548 iret = IRQ_HANDLED; 549 } 550 551 return iret; 552 } 553 554 static struct thermal_zone_device_ops lvts_ops = { 555 .get_temp = lvts_get_temp, 556 .set_trips = lvts_set_trips, 557 }; 558 559 static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, 560 const struct lvts_ctrl_data *lvts_ctrl_data) 561 { 562 struct lvts_sensor *lvts_sensor = lvts_ctrl->sensors; 563 564 void __iomem *msr_regs[] = { 565 LVTS_MSR0(lvts_ctrl->base), 566 LVTS_MSR1(lvts_ctrl->base), 567 LVTS_MSR2(lvts_ctrl->base), 568 LVTS_MSR3(lvts_ctrl->base) 569 }; 570 571 void __iomem *imm_regs[] = { 572 LVTS_IMMD0(lvts_ctrl->base), 573 LVTS_IMMD1(lvts_ctrl->base), 574 LVTS_IMMD2(lvts_ctrl->base), 575 LVTS_IMMD3(lvts_ctrl->base) 576 }; 577 578 int i; 579 580 lvts_for_each_valid_sensor(i, lvts_ctrl_data) { 581 582 int dt_id = lvts_ctrl_data->lvts_sensor[i].dt_id; 583 584 /* 585 * At this point, we don't know which id matches which 586 * sensor. Let's set arbitrally the id from the index. 587 */ 588 lvts_sensor[i].id = i; 589 590 /* 591 * The thermal zone registration will set the trip 592 * point interrupt in the thermal controller 593 * register. But this one will be reset in the 594 * initialization after. So we need to post pone the 595 * thermal zone creation after the controller is 596 * setup. For this reason, we store the device tree 597 * node id from the data in the sensor structure 598 */ 599 lvts_sensor[i].dt_id = dt_id; 600 601 /* 602 * We assign the base address of the thermal 603 * controller as a back pointer. So it will be 604 * accessible from the different thermal framework ops 605 * as we pass the lvts_sensor pointer as thermal zone 606 * private data. 607 */ 608 lvts_sensor[i].base = lvts_ctrl->base; 609 610 /* 611 * Each sensor has its own register address to read from. 612 */ 613 lvts_sensor[i].msr = lvts_ctrl_data->mode == LVTS_MSR_IMMEDIATE_MODE ? 614 imm_regs[i] : msr_regs[i]; 615 616 lvts_sensor[i].low_thresh = INT_MIN; 617 lvts_sensor[i].high_thresh = INT_MIN; 618 }; 619 620 return 0; 621 } 622 623 /* 624 * The efuse blob values follows the sensor enumeration per thermal 625 * controller. The decoding of the stream is as follow: 626 * 627 * MT8192 : 628 * Stream index map for MCU Domain mt8192 : 629 * 630 * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> 631 * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 | 0x0A | 0x0B 632 * 633 * <-----sensor#2-----> <-----sensor#3-----> 634 * 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 | 0x13 635 * 636 * <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7-----> 637 * 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 | 0x22 | 0x23 638 * 639 * Stream index map for AP Domain mt8192 : 640 * 641 * <-----sensor#0-----> <-----sensor#1-----> 642 * 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A | 0x2B 643 * 644 * <-----sensor#2-----> <-----sensor#3-----> 645 * 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33 646 * 647 * <-----sensor#4-----> <-----sensor#5-----> 648 * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B 649 * 650 * <-----sensor#6-----> <-----sensor#7-----> <-----sensor#8-----> 651 * 0x3C | 0x3D | 0x3E | 0x3F | 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 652 * 653 * MT8195 : 654 * Stream index map for MCU Domain mt8195 : 655 * 656 * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> 657 * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 658 * 659 * <-----mcu-tc#1-----> <-----sensor#2-----> <-----sensor#3-----> 660 * 0x0A | 0x0B | 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 661 * 662 * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7-----> 663 * 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 664 * 665 * Stream index map for AP Domain mt8195 : 666 * 667 * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1-----> 668 * 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A 669 * 670 * <-----ap--tc#1-----> <-----sensor#2-----> <-----sensor#3-----> 671 * 0x2B | 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33 672 * 673 * <-----ap--tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> 674 * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B | 0x3C | 0x3D | 0x3E | 0x3F 675 * 676 * <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8-----> 677 * 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48 678 * 679 * Note: In some cases, values don't strictly follow a little endian ordering. 680 * The data description gives byte offsets constituting each calibration value 681 * for each sensor. 682 */ 683 static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, 684 const struct lvts_ctrl_data *lvts_ctrl_data, 685 u8 *efuse_calibration, 686 size_t calib_len) 687 { 688 int i; 689 690 lvts_for_each_valid_sensor(i, lvts_ctrl_data) { 691 const struct lvts_sensor_data *sensor = 692 &lvts_ctrl_data->lvts_sensor[i]; 693 694 if (sensor->cal_offsets[0] >= calib_len || 695 sensor->cal_offsets[1] >= calib_len || 696 sensor->cal_offsets[2] >= calib_len) 697 return -EINVAL; 698 699 lvts_ctrl->calibration[i] = 700 (efuse_calibration[sensor->cal_offsets[0]] << 0) + 701 (efuse_calibration[sensor->cal_offsets[1]] << 8) + 702 (efuse_calibration[sensor->cal_offsets[2]] << 16); 703 } 704 705 return 0; 706 } 707 708 /* 709 * The efuse bytes stream can be split into different chunk of 710 * nvmems. This function reads and concatenate those into a single 711 * buffer so it can be read sequentially when initializing the 712 * calibration data. 713 */ 714 static int lvts_calibration_read(struct device *dev, struct lvts_domain *lvts_td, 715 const struct lvts_data *lvts_data) 716 { 717 struct device_node *np = dev_of_node(dev); 718 struct nvmem_cell *cell; 719 struct property *prop; 720 const char *cell_name; 721 722 of_property_for_each_string(np, "nvmem-cell-names", prop, cell_name) { 723 size_t len; 724 u8 *efuse; 725 726 cell = of_nvmem_cell_get(np, cell_name); 727 if (IS_ERR(cell)) { 728 dev_err(dev, "Failed to get cell '%s'\n", cell_name); 729 return PTR_ERR(cell); 730 } 731 732 efuse = nvmem_cell_read(cell, &len); 733 734 nvmem_cell_put(cell); 735 736 if (IS_ERR(efuse)) { 737 dev_err(dev, "Failed to read cell '%s'\n", cell_name); 738 return PTR_ERR(efuse); 739 } 740 741 lvts_td->calib = devm_krealloc(dev, lvts_td->calib, 742 lvts_td->calib_len + len, GFP_KERNEL); 743 if (!lvts_td->calib) { 744 kfree(efuse); 745 return -ENOMEM; 746 } 747 748 memcpy(lvts_td->calib + lvts_td->calib_len, efuse, len); 749 750 lvts_td->calib_len += len; 751 752 kfree(efuse); 753 } 754 755 return 0; 756 } 757 758 static int lvts_golden_temp_init(struct device *dev, u8 *calib, 759 const struct lvts_data *lvts_data) 760 { 761 u32 gt; 762 763 /* 764 * The golden temp information is contained in the first 32-bit 765 * word of efuse data at a specific bit offset. 766 */ 767 gt = (((u32 *)calib)[0] >> lvts_data->gt_calib_bit_offset) & 0xff; 768 769 if (gt && gt < LVTS_GOLDEN_TEMP_MAX) 770 golden_temp = gt; 771 772 golden_temp_offset = golden_temp * 500 + lvts_data->temp_offset; 773 774 return 0; 775 } 776 777 static int lvts_ctrl_init(struct device *dev, struct lvts_domain *lvts_td, 778 const struct lvts_data *lvts_data) 779 { 780 size_t size = sizeof(*lvts_td->lvts_ctrl) * lvts_data->num_lvts_ctrl; 781 struct lvts_ctrl *lvts_ctrl; 782 int i, ret; 783 784 /* 785 * Create the calibration bytes stream from efuse data 786 */ 787 ret = lvts_calibration_read(dev, lvts_td, lvts_data); 788 if (ret) 789 return ret; 790 791 ret = lvts_golden_temp_init(dev, lvts_td->calib, lvts_data); 792 if (ret) 793 return ret; 794 795 lvts_ctrl = devm_kzalloc(dev, size, GFP_KERNEL); 796 if (!lvts_ctrl) 797 return -ENOMEM; 798 799 for (i = 0; i < lvts_data->num_lvts_ctrl; i++) { 800 801 lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset; 802 lvts_ctrl[i].lvts_data = lvts_data; 803 804 ret = lvts_sensor_init(dev, &lvts_ctrl[i], 805 &lvts_data->lvts_ctrl[i]); 806 if (ret) 807 return ret; 808 809 ret = lvts_calibration_init(dev, &lvts_ctrl[i], 810 &lvts_data->lvts_ctrl[i], 811 lvts_td->calib, 812 lvts_td->calib_len); 813 if (ret) 814 return ret; 815 816 /* 817 * The mode the ctrl will use to read the temperature 818 * (filtered or immediate) 819 */ 820 lvts_ctrl[i].mode = lvts_data->lvts_ctrl[i].mode; 821 822 /* 823 * The temperature to raw temperature must be done 824 * after initializing the calibration. 825 */ 826 lvts_ctrl[i].hw_tshut_raw_temp = 827 lvts_temp_to_raw(LVTS_HW_TSHUT_TEMP, 828 lvts_data->temp_factor); 829 830 lvts_ctrl[i].low_thresh = INT_MIN; 831 lvts_ctrl[i].high_thresh = INT_MIN; 832 } 833 834 /* 835 * We no longer need the efuse bytes stream, let's free it 836 */ 837 devm_kfree(dev, lvts_td->calib); 838 839 lvts_td->lvts_ctrl = lvts_ctrl; 840 lvts_td->num_lvts_ctrl = lvts_data->num_lvts_ctrl; 841 842 return 0; 843 } 844 845 /* 846 * At this point the configuration register is the only place in the 847 * driver where we write multiple values. Per hardware constraint, 848 * each write in the configuration register must be separated by a 849 * delay of 2 us. 850 */ 851 static void lvts_write_config(struct lvts_ctrl *lvts_ctrl, u32 *cmds, int nr_cmds) 852 { 853 int i; 854 855 /* 856 * Configuration register 857 */ 858 for (i = 0; i < nr_cmds; i++) { 859 writel(cmds[i], LVTS_CONFIG(lvts_ctrl->base)); 860 usleep_range(2, 4); 861 } 862 } 863 864 static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl) 865 { 866 /* 867 * LVTS_PROTCTL : Thermal Protection Sensor Selection 868 * 869 * Bits: 870 * 871 * 19-18 : Sensor to base the protection on 872 * 17-16 : Strategy: 873 * 00 : Average of 4 sensors 874 * 01 : Max of 4 sensors 875 * 10 : Selected sensor with bits 19-18 876 * 11 : Reserved 877 */ 878 writel(BIT(16), LVTS_PROTCTL(lvts_ctrl->base)); 879 880 /* 881 * LVTS_PROTTA : Stage 1 temperature threshold 882 * LVTS_PROTTB : Stage 2 temperature threshold 883 * LVTS_PROTTC : Stage 3 temperature threshold 884 * 885 * Bits: 886 * 887 * 14-0: Raw temperature threshold 888 * 889 * writel(0x0, LVTS_PROTTA(lvts_ctrl->base)); 890 * writel(0x0, LVTS_PROTTB(lvts_ctrl->base)); 891 */ 892 writel(lvts_ctrl->hw_tshut_raw_temp, LVTS_PROTTC(lvts_ctrl->base)); 893 894 /* 895 * LVTS_MONINT : Interrupt configuration register 896 * 897 * The LVTS_MONINT register layout is the same as the LVTS_MONINTSTS 898 * register, except we set the bits to enable the interrupt. 899 */ 900 writel(LVTS_MONINT_CONF, LVTS_MONINT(lvts_ctrl->base)); 901 902 return 0; 903 } 904 905 static int lvts_domain_reset(struct device *dev, struct reset_control *reset) 906 { 907 int ret; 908 909 ret = reset_control_assert(reset); 910 if (ret) 911 return ret; 912 913 return reset_control_deassert(reset); 914 } 915 916 /* 917 * Enable or disable the clocks of a specified thermal controller 918 */ 919 static int lvts_ctrl_set_enable(struct lvts_ctrl *lvts_ctrl, int enable) 920 { 921 /* 922 * LVTS_CLKEN : Internal LVTS clock 923 * 924 * Bits: 925 * 926 * 0 : enable / disable clock 927 */ 928 writel(enable, LVTS_CLKEN(lvts_ctrl->base)); 929 930 return 0; 931 } 932 933 static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl) 934 { 935 u32 id, cmds[] = { 0xC103FFFF, 0xC502FF55 }; 936 937 lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); 938 939 /* 940 * LVTS_ID : Get ID and status of the thermal controller 941 * 942 * Bits: 943 * 944 * 0-5 : thermal controller id 945 * 7 : thermal controller connection is valid 946 */ 947 id = readl(LVTS_ID(lvts_ctrl->base)); 948 if (!(id & BIT(7))) 949 return -EIO; 950 951 return 0; 952 } 953 954 static int lvts_ctrl_initialize(struct device *dev, struct lvts_ctrl *lvts_ctrl) 955 { 956 /* 957 * Write device mask: 0xC1030000 958 */ 959 u32 cmds[] = { 960 0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1, 961 0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300, 962 0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC, 963 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1 964 }; 965 966 lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); 967 968 return 0; 969 } 970 971 static int lvts_ctrl_calibrate(struct device *dev, struct lvts_ctrl *lvts_ctrl) 972 { 973 int i; 974 void __iomem *lvts_edata[] = { 975 LVTS_EDATA00(lvts_ctrl->base), 976 LVTS_EDATA01(lvts_ctrl->base), 977 LVTS_EDATA02(lvts_ctrl->base), 978 LVTS_EDATA03(lvts_ctrl->base) 979 }; 980 981 /* 982 * LVTS_EDATA0X : Efuse calibration reference value for sensor X 983 * 984 * Bits: 985 * 986 * 20-0 : Efuse value for normalization data 987 */ 988 for (i = 0; i < LVTS_SENSOR_MAX; i++) 989 writel(lvts_ctrl->calibration[i], lvts_edata[i]); 990 991 return 0; 992 } 993 994 static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_ctrl) 995 { 996 u32 value; 997 998 /* 999 * LVTS_TSSEL : Sensing point index numbering 1000 * 1001 * Bits: 1002 * 1003 * 31-24: ADC Sense 3 1004 * 23-16: ADC Sense 2 1005 * 15-8 : ADC Sense 1 1006 * 7-0 : ADC Sense 0 1007 */ 1008 value = LVTS_TSSEL_CONF; 1009 writel(value, LVTS_TSSEL(lvts_ctrl->base)); 1010 1011 /* 1012 * LVTS_CALSCALE : ADC voltage round 1013 */ 1014 value = 0x300; 1015 value = LVTS_CALSCALE_CONF; 1016 1017 /* 1018 * LVTS_MSRCTL0 : Sensor filtering strategy 1019 * 1020 * Filters: 1021 * 1022 * 000 : One sample 1023 * 001 : Avg 2 samples 1024 * 010 : 4 samples, drop min and max, avg 2 samples 1025 * 011 : 6 samples, drop min and max, avg 4 samples 1026 * 100 : 10 samples, drop min and max, avg 8 samples 1027 * 101 : 18 samples, drop min and max, avg 16 samples 1028 * 1029 * Bits: 1030 * 1031 * 0-2 : Sensor0 filter 1032 * 3-5 : Sensor1 filter 1033 * 6-8 : Sensor2 filter 1034 * 9-11 : Sensor3 filter 1035 */ 1036 value = LVTS_HW_FILTER << 9 | LVTS_HW_FILTER << 6 | 1037 LVTS_HW_FILTER << 3 | LVTS_HW_FILTER; 1038 writel(value, LVTS_MSRCTL0(lvts_ctrl->base)); 1039 1040 /* 1041 * LVTS_MONCTL1 : Period unit and group interval configuration 1042 * 1043 * The clock source of LVTS thermal controller is 26MHz. 1044 * 1045 * The period unit is a time base for all the interval delays 1046 * specified in the registers. By default we use 12. The time 1047 * conversion is done by multiplying by 256 and 1/26.10^6 1048 * 1049 * An interval delay multiplied by the period unit gives the 1050 * duration in seconds. 1051 * 1052 * - Filter interval delay is a delay between two samples of 1053 * the same sensor. 1054 * 1055 * - Sensor interval delay is a delay between two samples of 1056 * different sensors. 1057 * 1058 * - Group interval delay is a delay between different rounds. 1059 * 1060 * For example: 1061 * If Period unit = C, filter delay = 1, sensor delay = 2, group delay = 1, 1062 * and two sensors, TS1 and TS2, are in a LVTS thermal controller 1063 * and then 1064 * Period unit time = C * 1/26M * 256 = 12 * 38.46ns * 256 = 118.149us 1065 * Filter interval delay = 1 * Period unit = 118.149us 1066 * Sensor interval delay = 2 * Period unit = 236.298us 1067 * Group interval delay = 1 * Period unit = 118.149us 1068 * 1069 * TS1 TS1 ... TS1 TS2 TS2 ... TS2 TS1... 1070 * <--> Filter interval delay 1071 * <--> Sensor interval delay 1072 * <--> Group interval delay 1073 * Bits: 1074 * 29 - 20 : Group interval 1075 * 16 - 13 : Send a single interrupt when crossing the hot threshold (1) 1076 * or an interrupt everytime the hot threshold is crossed (0) 1077 * 9 - 0 : Period unit 1078 * 1079 */ 1080 value = LVTS_GROUP_INTERVAL << 20 | LVTS_PERIOD_UNIT; 1081 writel(value, LVTS_MONCTL1(lvts_ctrl->base)); 1082 1083 /* 1084 * LVTS_MONCTL2 : Filtering and sensor interval 1085 * 1086 * Bits: 1087 * 1088 * 25-16 : Interval unit in PERIOD_UNIT between sample on 1089 * the same sensor, filter interval 1090 * 9-0 : Interval unit in PERIOD_UNIT between each sensor 1091 * 1092 */ 1093 value = LVTS_FILTER_INTERVAL << 16 | LVTS_SENSOR_INTERVAL; 1094 writel(value, LVTS_MONCTL2(lvts_ctrl->base)); 1095 1096 return lvts_irq_init(lvts_ctrl); 1097 } 1098 1099 static int lvts_ctrl_start(struct device *dev, struct lvts_ctrl *lvts_ctrl) 1100 { 1101 struct lvts_sensor *lvts_sensors = lvts_ctrl->sensors; 1102 struct thermal_zone_device *tz; 1103 u32 sensor_map = 0; 1104 int i; 1105 /* 1106 * Bitmaps to enable each sensor on immediate and filtered modes, as 1107 * described in MSRCTL1 and MONCTL0 registers below, respectively. 1108 */ 1109 u32 sensor_imm_bitmap[] = { BIT(4), BIT(5), BIT(6), BIT(9) }; 1110 u32 sensor_filt_bitmap[] = { BIT(0), BIT(1), BIT(2), BIT(3) }; 1111 1112 u32 *sensor_bitmap = lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE ? 1113 sensor_imm_bitmap : sensor_filt_bitmap; 1114 1115 lvts_for_each_valid_sensor(i, lvts_ctrl->lvts_data->lvts_ctrl) { 1116 1117 int dt_id = lvts_sensors[i].dt_id; 1118 1119 tz = devm_thermal_of_zone_register(dev, dt_id, &lvts_sensors[i], 1120 &lvts_ops); 1121 if (IS_ERR(tz)) { 1122 /* 1123 * This thermal zone is not described in the 1124 * device tree. It is not an error from the 1125 * thermal OF code POV, we just continue. 1126 */ 1127 if (PTR_ERR(tz) == -ENODEV) 1128 continue; 1129 1130 return PTR_ERR(tz); 1131 } 1132 1133 devm_thermal_add_hwmon_sysfs(dev, tz); 1134 1135 /* 1136 * The thermal zone pointer will be needed in the 1137 * interrupt handler, we store it in the sensor 1138 * structure. The thermal domain structure will be 1139 * passed to the interrupt handler private data as the 1140 * interrupt is shared for all the controller 1141 * belonging to the thermal domain. 1142 */ 1143 lvts_sensors[i].tz = tz; 1144 1145 /* 1146 * This sensor was correctly associated with a thermal 1147 * zone, let's set the corresponding bit in the sensor 1148 * map, so we can enable the temperature monitoring in 1149 * the hardware thermal controller. 1150 */ 1151 sensor_map |= sensor_bitmap[i]; 1152 } 1153 1154 /* 1155 * The initialization of the thermal zones give us 1156 * which sensor point to enable. If any thermal zone 1157 * was not described in the device tree, it won't be 1158 * enabled here in the sensor map. 1159 */ 1160 if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) { 1161 /* 1162 * LVTS_MSRCTL1 : Measurement control 1163 * 1164 * Bits: 1165 * 1166 * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3 1167 * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2 1168 * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1 1169 * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0 1170 * 1171 * That configuration will ignore the filtering and the delays 1172 * introduced in MONCTL1 and MONCTL2 1173 */ 1174 writel(sensor_map, LVTS_MSRCTL1(lvts_ctrl->base)); 1175 } else { 1176 /* 1177 * Bits: 1178 * 9: Single point access flow 1179 * 0-3: Enable sensing point 0-3 1180 */ 1181 writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base)); 1182 } 1183 1184 return 0; 1185 } 1186 1187 static int lvts_domain_init(struct device *dev, struct lvts_domain *lvts_td, 1188 const struct lvts_data *lvts_data) 1189 { 1190 struct lvts_ctrl *lvts_ctrl; 1191 int i, ret; 1192 1193 ret = lvts_ctrl_init(dev, lvts_td, lvts_data); 1194 if (ret) 1195 return ret; 1196 1197 ret = lvts_domain_reset(dev, lvts_td->reset); 1198 if (ret) { 1199 dev_dbg(dev, "Failed to reset domain"); 1200 return ret; 1201 } 1202 1203 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 1204 1205 lvts_ctrl = &lvts_td->lvts_ctrl[i]; 1206 1207 /* 1208 * Initialization steps: 1209 * 1210 * - Enable the clock 1211 * - Connect to the LVTS 1212 * - Initialize the LVTS 1213 * - Prepare the calibration data 1214 * - Select monitored sensors 1215 * [ Configure sampling ] 1216 * [ Configure the interrupt ] 1217 * - Start measurement 1218 */ 1219 ret = lvts_ctrl_set_enable(lvts_ctrl, true); 1220 if (ret) { 1221 dev_dbg(dev, "Failed to enable LVTS clock"); 1222 return ret; 1223 } 1224 1225 ret = lvts_ctrl_connect(dev, lvts_ctrl); 1226 if (ret) { 1227 dev_dbg(dev, "Failed to connect to LVTS controller"); 1228 return ret; 1229 } 1230 1231 ret = lvts_ctrl_initialize(dev, lvts_ctrl); 1232 if (ret) { 1233 dev_dbg(dev, "Failed to initialize controller"); 1234 return ret; 1235 } 1236 1237 ret = lvts_ctrl_calibrate(dev, lvts_ctrl); 1238 if (ret) { 1239 dev_dbg(dev, "Failed to calibrate controller"); 1240 return ret; 1241 } 1242 1243 ret = lvts_ctrl_configure(dev, lvts_ctrl); 1244 if (ret) { 1245 dev_dbg(dev, "Failed to configure controller"); 1246 return ret; 1247 } 1248 1249 ret = lvts_ctrl_start(dev, lvts_ctrl); 1250 if (ret) { 1251 dev_dbg(dev, "Failed to start controller"); 1252 return ret; 1253 } 1254 } 1255 1256 return lvts_debugfs_init(dev, lvts_td); 1257 } 1258 1259 static int lvts_probe(struct platform_device *pdev) 1260 { 1261 const struct lvts_data *lvts_data; 1262 struct lvts_domain *lvts_td; 1263 struct device *dev = &pdev->dev; 1264 struct resource *res; 1265 int irq, ret; 1266 1267 lvts_td = devm_kzalloc(dev, sizeof(*lvts_td), GFP_KERNEL); 1268 if (!lvts_td) 1269 return -ENOMEM; 1270 1271 lvts_data = of_device_get_match_data(dev); 1272 if (!lvts_data) 1273 return -ENODEV; 1274 1275 lvts_td->clk = devm_clk_get_enabled(dev, NULL); 1276 if (IS_ERR(lvts_td->clk)) 1277 return dev_err_probe(dev, PTR_ERR(lvts_td->clk), "Failed to retrieve clock\n"); 1278 1279 res = platform_get_mem_or_io(pdev, 0); 1280 if (!res) 1281 return dev_err_probe(dev, (-ENXIO), "No IO resource\n"); 1282 1283 lvts_td->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1284 if (IS_ERR(lvts_td->base)) 1285 return dev_err_probe(dev, PTR_ERR(lvts_td->base), "Failed to map io resource\n"); 1286 1287 lvts_td->reset = devm_reset_control_get_by_index(dev, 0); 1288 if (IS_ERR(lvts_td->reset)) 1289 return dev_err_probe(dev, PTR_ERR(lvts_td->reset), "Failed to get reset control\n"); 1290 1291 irq = platform_get_irq(pdev, 0); 1292 if (irq < 0) 1293 return irq; 1294 1295 golden_temp_offset = lvts_data->temp_offset; 1296 1297 ret = lvts_domain_init(dev, lvts_td, lvts_data); 1298 if (ret) 1299 return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n"); 1300 1301 /* 1302 * At this point the LVTS is initialized and enabled. We can 1303 * safely enable the interrupt. 1304 */ 1305 ret = devm_request_threaded_irq(dev, irq, NULL, lvts_irq_handler, 1306 IRQF_ONESHOT, dev_name(dev), lvts_td); 1307 if (ret) 1308 return dev_err_probe(dev, ret, "Failed to request interrupt\n"); 1309 1310 platform_set_drvdata(pdev, lvts_td); 1311 1312 return 0; 1313 } 1314 1315 static void lvts_remove(struct platform_device *pdev) 1316 { 1317 struct lvts_domain *lvts_td; 1318 int i; 1319 1320 lvts_td = platform_get_drvdata(pdev); 1321 1322 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) 1323 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); 1324 1325 lvts_debugfs_exit(lvts_td); 1326 } 1327 1328 static const struct lvts_ctrl_data mt7988_lvts_ap_data_ctrl[] = { 1329 { 1330 .lvts_sensor = { 1331 { .dt_id = MT7988_CPU_0, 1332 .cal_offsets = { 0x00, 0x01, 0x02 } }, 1333 { .dt_id = MT7988_CPU_1, 1334 .cal_offsets = { 0x04, 0x05, 0x06 } }, 1335 { .dt_id = MT7988_ETH2P5G_0, 1336 .cal_offsets = { 0x08, 0x09, 0x0a } }, 1337 { .dt_id = MT7988_ETH2P5G_1, 1338 .cal_offsets = { 0x0c, 0x0d, 0x0e } } 1339 }, 1340 VALID_SENSOR_MAP(1, 1, 1, 1), 1341 .offset = 0x0, 1342 }, 1343 { 1344 .lvts_sensor = { 1345 { .dt_id = MT7988_TOPS_0, 1346 .cal_offsets = { 0x14, 0x15, 0x16 } }, 1347 { .dt_id = MT7988_TOPS_1, 1348 .cal_offsets = { 0x18, 0x19, 0x1a } }, 1349 { .dt_id = MT7988_ETHWARP_0, 1350 .cal_offsets = { 0x1c, 0x1d, 0x1e } }, 1351 { .dt_id = MT7988_ETHWARP_1, 1352 .cal_offsets = { 0x20, 0x21, 0x22 } } 1353 }, 1354 VALID_SENSOR_MAP(1, 1, 1, 1), 1355 .offset = 0x100, 1356 } 1357 }; 1358 1359 static int lvts_suspend(struct device *dev) 1360 { 1361 struct lvts_domain *lvts_td; 1362 int i; 1363 1364 lvts_td = dev_get_drvdata(dev); 1365 1366 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) 1367 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); 1368 1369 clk_disable_unprepare(lvts_td->clk); 1370 1371 return 0; 1372 } 1373 1374 static int lvts_resume(struct device *dev) 1375 { 1376 struct lvts_domain *lvts_td; 1377 int i, ret; 1378 1379 lvts_td = dev_get_drvdata(dev); 1380 1381 ret = clk_prepare_enable(lvts_td->clk); 1382 if (ret) 1383 return ret; 1384 1385 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) 1386 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], true); 1387 1388 return 0; 1389 } 1390 1391 /* 1392 * The MT8186 calibration data is stored as packed 3-byte little-endian 1393 * values using a weird layout that makes sense only when viewed as a 32-bit 1394 * hexadecimal word dump. Let's suppose SxBy where x = sensor number and 1395 * y = byte number where the LSB is y=0. We then have: 1396 * 1397 * [S0B2-S0B1-S0B0-S1B2] [S1B1-S1B0-S2B2-S2B1] [S2B0-S3B2-S3B1-S3B0] 1398 * 1399 * However, when considering a byte stream, those appear as follows: 1400 * 1401 * [S1B2] [S0B0[ [S0B1] [S0B2] [S2B1] [S2B2] [S1B0] [S1B1] [S3B0] [S3B1] [S3B2] [S2B0] 1402 * 1403 * Hence the rather confusing offsets provided below. 1404 */ 1405 static const struct lvts_ctrl_data mt8186_lvts_data_ctrl[] = { 1406 { 1407 .lvts_sensor = { 1408 { .dt_id = MT8186_LITTLE_CPU0, 1409 .cal_offsets = { 5, 6, 7 } }, 1410 { .dt_id = MT8186_LITTLE_CPU1, 1411 .cal_offsets = { 10, 11, 4 } }, 1412 { .dt_id = MT8186_LITTLE_CPU2, 1413 .cal_offsets = { 15, 8, 9 } }, 1414 { .dt_id = MT8186_CAM, 1415 .cal_offsets = { 12, 13, 14 } } 1416 }, 1417 VALID_SENSOR_MAP(1, 1, 1, 1), 1418 .offset = 0x0, 1419 }, 1420 { 1421 .lvts_sensor = { 1422 { .dt_id = MT8186_BIG_CPU0, 1423 .cal_offsets = { 22, 23, 16 } }, 1424 { .dt_id = MT8186_BIG_CPU1, 1425 .cal_offsets = { 27, 20, 21 } } 1426 }, 1427 VALID_SENSOR_MAP(1, 1, 0, 0), 1428 .offset = 0x100, 1429 }, 1430 { 1431 .lvts_sensor = { 1432 { .dt_id = MT8186_NNA, 1433 .cal_offsets = { 29, 30, 31 } }, 1434 { .dt_id = MT8186_ADSP, 1435 .cal_offsets = { 34, 35, 28 } }, 1436 { .dt_id = MT8186_MFG, 1437 .cal_offsets = { 39, 32, 33 } } 1438 }, 1439 VALID_SENSOR_MAP(1, 1, 1, 0), 1440 .offset = 0x200, 1441 } 1442 }; 1443 1444 static const struct lvts_ctrl_data mt8188_lvts_mcu_data_ctrl[] = { 1445 { 1446 .lvts_sensor = { 1447 { .dt_id = MT8188_MCU_LITTLE_CPU0, 1448 .cal_offsets = { 22, 23, 24 } }, 1449 { .dt_id = MT8188_MCU_LITTLE_CPU1, 1450 .cal_offsets = { 25, 26, 27 } }, 1451 { .dt_id = MT8188_MCU_LITTLE_CPU2, 1452 .cal_offsets = { 28, 29, 30 } }, 1453 { .dt_id = MT8188_MCU_LITTLE_CPU3, 1454 .cal_offsets = { 31, 32, 33 } }, 1455 }, 1456 VALID_SENSOR_MAP(1, 1, 1, 1), 1457 .offset = 0x0, 1458 .mode = LVTS_MSR_FILTERED_MODE, 1459 }, 1460 { 1461 .lvts_sensor = { 1462 { .dt_id = MT8188_MCU_BIG_CPU0, 1463 .cal_offsets = { 34, 35, 36 } }, 1464 { .dt_id = MT8188_MCU_BIG_CPU1, 1465 .cal_offsets = { 37, 38, 39 } }, 1466 }, 1467 VALID_SENSOR_MAP(1, 1, 0, 0), 1468 .offset = 0x100, 1469 .mode = LVTS_MSR_FILTERED_MODE, 1470 } 1471 }; 1472 1473 static const struct lvts_ctrl_data mt8188_lvts_ap_data_ctrl[] = { 1474 { 1475 .lvts_sensor = { 1476 1477 { /* unused */ }, 1478 { .dt_id = MT8188_AP_APU, 1479 .cal_offsets = { 40, 41, 42 } }, 1480 }, 1481 VALID_SENSOR_MAP(0, 1, 0, 0), 1482 .offset = 0x0, 1483 .mode = LVTS_MSR_FILTERED_MODE, 1484 }, 1485 { 1486 .lvts_sensor = { 1487 { .dt_id = MT8188_AP_GPU1, 1488 .cal_offsets = { 43, 44, 45 } }, 1489 { .dt_id = MT8188_AP_GPU2, 1490 .cal_offsets = { 46, 47, 48 } }, 1491 { .dt_id = MT8188_AP_SOC1, 1492 .cal_offsets = { 49, 50, 51 } }, 1493 }, 1494 VALID_SENSOR_MAP(1, 1, 1, 0), 1495 .offset = 0x100, 1496 .mode = LVTS_MSR_FILTERED_MODE, 1497 }, 1498 { 1499 .lvts_sensor = { 1500 { .dt_id = MT8188_AP_SOC2, 1501 .cal_offsets = { 52, 53, 54 } }, 1502 { .dt_id = MT8188_AP_SOC3, 1503 .cal_offsets = { 55, 56, 57 } }, 1504 }, 1505 VALID_SENSOR_MAP(1, 1, 0, 0), 1506 .offset = 0x200, 1507 .mode = LVTS_MSR_FILTERED_MODE, 1508 }, 1509 { 1510 .lvts_sensor = { 1511 { .dt_id = MT8188_AP_CAM1, 1512 .cal_offsets = { 58, 59, 60 } }, 1513 { .dt_id = MT8188_AP_CAM2, 1514 .cal_offsets = { 61, 62, 63 } }, 1515 }, 1516 VALID_SENSOR_MAP(1, 1, 0, 0), 1517 .offset = 0x300, 1518 .mode = LVTS_MSR_FILTERED_MODE, 1519 } 1520 }; 1521 1522 static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = { 1523 { 1524 .lvts_sensor = { 1525 { .dt_id = MT8192_MCU_BIG_CPU0, 1526 .cal_offsets = { 0x04, 0x05, 0x06 } }, 1527 { .dt_id = MT8192_MCU_BIG_CPU1, 1528 .cal_offsets = { 0x08, 0x09, 0x0a } } 1529 }, 1530 VALID_SENSOR_MAP(1, 1, 0, 0), 1531 .offset = 0x0, 1532 .mode = LVTS_MSR_FILTERED_MODE, 1533 }, 1534 { 1535 .lvts_sensor = { 1536 { .dt_id = MT8192_MCU_BIG_CPU2, 1537 .cal_offsets = { 0x0c, 0x0d, 0x0e } }, 1538 { .dt_id = MT8192_MCU_BIG_CPU3, 1539 .cal_offsets = { 0x10, 0x11, 0x12 } } 1540 }, 1541 VALID_SENSOR_MAP(1, 1, 0, 0), 1542 .offset = 0x100, 1543 .mode = LVTS_MSR_FILTERED_MODE, 1544 }, 1545 { 1546 .lvts_sensor = { 1547 { .dt_id = MT8192_MCU_LITTLE_CPU0, 1548 .cal_offsets = { 0x14, 0x15, 0x16 } }, 1549 { .dt_id = MT8192_MCU_LITTLE_CPU1, 1550 .cal_offsets = { 0x18, 0x19, 0x1a } }, 1551 { .dt_id = MT8192_MCU_LITTLE_CPU2, 1552 .cal_offsets = { 0x1c, 0x1d, 0x1e } }, 1553 { .dt_id = MT8192_MCU_LITTLE_CPU3, 1554 .cal_offsets = { 0x20, 0x21, 0x22 } } 1555 }, 1556 VALID_SENSOR_MAP(1, 1, 1, 1), 1557 .offset = 0x200, 1558 .mode = LVTS_MSR_FILTERED_MODE, 1559 } 1560 }; 1561 1562 static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = { 1563 { 1564 .lvts_sensor = { 1565 { .dt_id = MT8192_AP_VPU0, 1566 .cal_offsets = { 0x24, 0x25, 0x26 } }, 1567 { .dt_id = MT8192_AP_VPU1, 1568 .cal_offsets = { 0x28, 0x29, 0x2a } } 1569 }, 1570 VALID_SENSOR_MAP(1, 1, 0, 0), 1571 .offset = 0x0, 1572 }, 1573 { 1574 .lvts_sensor = { 1575 { .dt_id = MT8192_AP_GPU0, 1576 .cal_offsets = { 0x2c, 0x2d, 0x2e } }, 1577 { .dt_id = MT8192_AP_GPU1, 1578 .cal_offsets = { 0x30, 0x31, 0x32 } } 1579 }, 1580 VALID_SENSOR_MAP(1, 1, 0, 0), 1581 .offset = 0x100, 1582 }, 1583 { 1584 .lvts_sensor = { 1585 { .dt_id = MT8192_AP_INFRA, 1586 .cal_offsets = { 0x34, 0x35, 0x36 } }, 1587 { .dt_id = MT8192_AP_CAM, 1588 .cal_offsets = { 0x38, 0x39, 0x3a } }, 1589 }, 1590 VALID_SENSOR_MAP(1, 1, 0, 0), 1591 .offset = 0x200, 1592 }, 1593 { 1594 .lvts_sensor = { 1595 { .dt_id = MT8192_AP_MD0, 1596 .cal_offsets = { 0x3c, 0x3d, 0x3e } }, 1597 { .dt_id = MT8192_AP_MD1, 1598 .cal_offsets = { 0x40, 0x41, 0x42 } }, 1599 { .dt_id = MT8192_AP_MD2, 1600 .cal_offsets = { 0x44, 0x45, 0x46 } } 1601 }, 1602 VALID_SENSOR_MAP(1, 1, 1, 0), 1603 .offset = 0x300, 1604 } 1605 }; 1606 1607 static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = { 1608 { 1609 .lvts_sensor = { 1610 { .dt_id = MT8195_MCU_BIG_CPU0, 1611 .cal_offsets = { 0x04, 0x05, 0x06 } }, 1612 { .dt_id = MT8195_MCU_BIG_CPU1, 1613 .cal_offsets = { 0x07, 0x08, 0x09 } } 1614 }, 1615 VALID_SENSOR_MAP(1, 1, 0, 0), 1616 .offset = 0x0, 1617 }, 1618 { 1619 .lvts_sensor = { 1620 { .dt_id = MT8195_MCU_BIG_CPU2, 1621 .cal_offsets = { 0x0d, 0x0e, 0x0f } }, 1622 { .dt_id = MT8195_MCU_BIG_CPU3, 1623 .cal_offsets = { 0x10, 0x11, 0x12 } } 1624 }, 1625 VALID_SENSOR_MAP(1, 1, 0, 0), 1626 .offset = 0x100, 1627 }, 1628 { 1629 .lvts_sensor = { 1630 { .dt_id = MT8195_MCU_LITTLE_CPU0, 1631 .cal_offsets = { 0x16, 0x17, 0x18 } }, 1632 { .dt_id = MT8195_MCU_LITTLE_CPU1, 1633 .cal_offsets = { 0x19, 0x1a, 0x1b } }, 1634 { .dt_id = MT8195_MCU_LITTLE_CPU2, 1635 .cal_offsets = { 0x1c, 0x1d, 0x1e } }, 1636 { .dt_id = MT8195_MCU_LITTLE_CPU3, 1637 .cal_offsets = { 0x1f, 0x20, 0x21 } } 1638 }, 1639 VALID_SENSOR_MAP(1, 1, 1, 1), 1640 .offset = 0x200, 1641 } 1642 }; 1643 1644 static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = { 1645 { 1646 .lvts_sensor = { 1647 { .dt_id = MT8195_AP_VPU0, 1648 .cal_offsets = { 0x25, 0x26, 0x27 } }, 1649 { .dt_id = MT8195_AP_VPU1, 1650 .cal_offsets = { 0x28, 0x29, 0x2a } } 1651 }, 1652 VALID_SENSOR_MAP(1, 1, 0, 0), 1653 .offset = 0x0, 1654 }, 1655 { 1656 .lvts_sensor = { 1657 { .dt_id = MT8195_AP_GPU0, 1658 .cal_offsets = { 0x2e, 0x2f, 0x30 } }, 1659 { .dt_id = MT8195_AP_GPU1, 1660 .cal_offsets = { 0x31, 0x32, 0x33 } } 1661 }, 1662 VALID_SENSOR_MAP(1, 1, 0, 0), 1663 .offset = 0x100, 1664 }, 1665 { 1666 .lvts_sensor = { 1667 { .dt_id = MT8195_AP_VDEC, 1668 .cal_offsets = { 0x37, 0x38, 0x39 } }, 1669 { .dt_id = MT8195_AP_IMG, 1670 .cal_offsets = { 0x3a, 0x3b, 0x3c } }, 1671 { .dt_id = MT8195_AP_INFRA, 1672 .cal_offsets = { 0x3d, 0x3e, 0x3f } } 1673 }, 1674 VALID_SENSOR_MAP(1, 1, 1, 0), 1675 .offset = 0x200, 1676 }, 1677 { 1678 .lvts_sensor = { 1679 { .dt_id = MT8195_AP_CAM0, 1680 .cal_offsets = { 0x43, 0x44, 0x45 } }, 1681 { .dt_id = MT8195_AP_CAM1, 1682 .cal_offsets = { 0x46, 0x47, 0x48 } } 1683 }, 1684 VALID_SENSOR_MAP(1, 1, 0, 0), 1685 .offset = 0x300, 1686 } 1687 }; 1688 1689 static const struct lvts_data mt7988_lvts_ap_data = { 1690 .lvts_ctrl = mt7988_lvts_ap_data_ctrl, 1691 .num_lvts_ctrl = ARRAY_SIZE(mt7988_lvts_ap_data_ctrl), 1692 .temp_factor = LVTS_COEFF_A_MT7988, 1693 .temp_offset = LVTS_COEFF_B_MT7988, 1694 .gt_calib_bit_offset = 24, 1695 }; 1696 1697 static const struct lvts_data mt8186_lvts_data = { 1698 .lvts_ctrl = mt8186_lvts_data_ctrl, 1699 .num_lvts_ctrl = ARRAY_SIZE(mt8186_lvts_data_ctrl), 1700 .temp_factor = LVTS_COEFF_A_MT7988, 1701 .temp_offset = LVTS_COEFF_B_MT7988, 1702 .gt_calib_bit_offset = 24, 1703 }; 1704 1705 static const struct lvts_data mt8188_lvts_mcu_data = { 1706 .lvts_ctrl = mt8188_lvts_mcu_data_ctrl, 1707 .num_lvts_ctrl = ARRAY_SIZE(mt8188_lvts_mcu_data_ctrl), 1708 .temp_factor = LVTS_COEFF_A_MT8195, 1709 .temp_offset = LVTS_COEFF_B_MT8195, 1710 .gt_calib_bit_offset = 20, 1711 }; 1712 1713 static const struct lvts_data mt8188_lvts_ap_data = { 1714 .lvts_ctrl = mt8188_lvts_ap_data_ctrl, 1715 .num_lvts_ctrl = ARRAY_SIZE(mt8188_lvts_ap_data_ctrl), 1716 .temp_factor = LVTS_COEFF_A_MT8195, 1717 .temp_offset = LVTS_COEFF_B_MT8195, 1718 .gt_calib_bit_offset = 20, 1719 }; 1720 1721 static const struct lvts_data mt8192_lvts_mcu_data = { 1722 .lvts_ctrl = mt8192_lvts_mcu_data_ctrl, 1723 .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl), 1724 .temp_factor = LVTS_COEFF_A_MT8195, 1725 .temp_offset = LVTS_COEFF_B_MT8195, 1726 .gt_calib_bit_offset = 24, 1727 }; 1728 1729 static const struct lvts_data mt8192_lvts_ap_data = { 1730 .lvts_ctrl = mt8192_lvts_ap_data_ctrl, 1731 .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_ap_data_ctrl), 1732 .temp_factor = LVTS_COEFF_A_MT8195, 1733 .temp_offset = LVTS_COEFF_B_MT8195, 1734 .gt_calib_bit_offset = 24, 1735 }; 1736 1737 static const struct lvts_data mt8195_lvts_mcu_data = { 1738 .lvts_ctrl = mt8195_lvts_mcu_data_ctrl, 1739 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl), 1740 .temp_factor = LVTS_COEFF_A_MT8195, 1741 .temp_offset = LVTS_COEFF_B_MT8195, 1742 .gt_calib_bit_offset = 24, 1743 }; 1744 1745 static const struct lvts_data mt8195_lvts_ap_data = { 1746 .lvts_ctrl = mt8195_lvts_ap_data_ctrl, 1747 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl), 1748 .temp_factor = LVTS_COEFF_A_MT8195, 1749 .temp_offset = LVTS_COEFF_B_MT8195, 1750 .gt_calib_bit_offset = 24, 1751 }; 1752 1753 static const struct of_device_id lvts_of_match[] = { 1754 { .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data }, 1755 { .compatible = "mediatek,mt8186-lvts", .data = &mt8186_lvts_data }, 1756 { .compatible = "mediatek,mt8188-lvts-mcu", .data = &mt8188_lvts_mcu_data }, 1757 { .compatible = "mediatek,mt8188-lvts-ap", .data = &mt8188_lvts_ap_data }, 1758 { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data }, 1759 { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data }, 1760 { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data }, 1761 { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data }, 1762 {}, 1763 }; 1764 MODULE_DEVICE_TABLE(of, lvts_of_match); 1765 1766 static const struct dev_pm_ops lvts_pm_ops = { 1767 NOIRQ_SYSTEM_SLEEP_PM_OPS(lvts_suspend, lvts_resume) 1768 }; 1769 1770 static struct platform_driver lvts_driver = { 1771 .probe = lvts_probe, 1772 .remove_new = lvts_remove, 1773 .driver = { 1774 .name = "mtk-lvts-thermal", 1775 .of_match_table = lvts_of_match, 1776 .pm = &lvts_pm_ops, 1777 }, 1778 }; 1779 module_platform_driver(lvts_driver); 1780 1781 MODULE_AUTHOR("Balsam CHIHI <bchihi@baylibre.com>"); 1782 MODULE_DESCRIPTION("MediaTek LVTS Thermal Driver"); 1783 MODULE_LICENSE("GPL"); 1784