1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2023 MediaTek Inc. 4 * Author: Balsam CHIHI <bchihi@baylibre.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/clk-provider.h> 9 #include <linux/delay.h> 10 #include <linux/debugfs.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/iopoll.h> 14 #include <linux/kernel.h> 15 #include <linux/nvmem-consumer.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/reset.h> 19 #include <linux/thermal.h> 20 #include <dt-bindings/thermal/mediatek,lvts-thermal.h> 21 22 #include "../thermal_hwmon.h" 23 24 #define LVTS_MONCTL0(__base) (__base + 0x0000) 25 #define LVTS_MONCTL1(__base) (__base + 0x0004) 26 #define LVTS_MONCTL2(__base) (__base + 0x0008) 27 #define LVTS_MONINT(__base) (__base + 0x000C) 28 #define LVTS_MONINTSTS(__base) (__base + 0x0010) 29 #define LVTS_MONIDET0(__base) (__base + 0x0014) 30 #define LVTS_MONIDET1(__base) (__base + 0x0018) 31 #define LVTS_MONIDET2(__base) (__base + 0x001C) 32 #define LVTS_MONIDET3(__base) (__base + 0x0020) 33 #define LVTS_H2NTHRE(__base) (__base + 0x0024) 34 #define LVTS_HTHRE(__base) (__base + 0x0028) 35 #define LVTS_OFFSETH(__base) (__base + 0x0030) 36 #define LVTS_OFFSETL(__base) (__base + 0x0034) 37 #define LVTS_MSRCTL0(__base) (__base + 0x0038) 38 #define LVTS_MSRCTL1(__base) (__base + 0x003C) 39 #define LVTS_TSSEL(__base) (__base + 0x0040) 40 #define LVTS_CALSCALE(__base) (__base + 0x0048) 41 #define LVTS_ID(__base) (__base + 0x004C) 42 #define LVTS_CONFIG(__base) (__base + 0x0050) 43 #define LVTS_EDATA00(__base) (__base + 0x0054) 44 #define LVTS_EDATA01(__base) (__base + 0x0058) 45 #define LVTS_EDATA02(__base) (__base + 0x005C) 46 #define LVTS_EDATA03(__base) (__base + 0x0060) 47 #define LVTS_MSR0(__base) (__base + 0x0090) 48 #define LVTS_MSR1(__base) (__base + 0x0094) 49 #define LVTS_MSR2(__base) (__base + 0x0098) 50 #define LVTS_MSR3(__base) (__base + 0x009C) 51 #define LVTS_IMMD0(__base) (__base + 0x00A0) 52 #define LVTS_IMMD1(__base) (__base + 0x00A4) 53 #define LVTS_IMMD2(__base) (__base + 0x00A8) 54 #define LVTS_IMMD3(__base) (__base + 0x00AC) 55 #define LVTS_PROTCTL(__base) (__base + 0x00C0) 56 #define LVTS_PROTTA(__base) (__base + 0x00C4) 57 #define LVTS_PROTTB(__base) (__base + 0x00C8) 58 #define LVTS_PROTTC(__base) (__base + 0x00CC) 59 #define LVTS_CLKEN(__base) (__base + 0x00E4) 60 61 #define LVTS_PERIOD_UNIT 0 62 #define LVTS_GROUP_INTERVAL 0 63 #define LVTS_FILTER_INTERVAL 0 64 #define LVTS_SENSOR_INTERVAL 0 65 #define LVTS_HW_FILTER 0x0 66 #define LVTS_TSSEL_CONF 0x13121110 67 #define LVTS_CALSCALE_CONF 0x300 68 #define LVTS_MONINT_CONF 0x8300318C 69 70 #define LVTS_MONINT_OFFSET_SENSOR0 0xC 71 #define LVTS_MONINT_OFFSET_SENSOR1 0x180 72 #define LVTS_MONINT_OFFSET_SENSOR2 0x3000 73 #define LVTS_MONINT_OFFSET_SENSOR3 0x3000000 74 75 #define LVTS_INT_SENSOR0 0x0009001F 76 #define LVTS_INT_SENSOR1 0x001203E0 77 #define LVTS_INT_SENSOR2 0x00247C00 78 #define LVTS_INT_SENSOR3 0x1FC00000 79 80 #define LVTS_SENSOR_MAX 4 81 #define LVTS_GOLDEN_TEMP_MAX 62 82 #define LVTS_GOLDEN_TEMP_DEFAULT 50 83 #define LVTS_COEFF_A_MT8195 -250460 84 #define LVTS_COEFF_B_MT8195 250460 85 #define LVTS_COEFF_A_MT7988 -204650 86 #define LVTS_COEFF_B_MT7988 204650 87 88 #define LVTS_MSR_IMMEDIATE_MODE 0 89 #define LVTS_MSR_FILTERED_MODE 1 90 91 #define LVTS_MSR_READ_TIMEOUT_US 400 92 #define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2) 93 94 #define LVTS_HW_TSHUT_TEMP 105000 95 96 #define LVTS_MINIMUM_THRESHOLD 20000 97 98 static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT; 99 static int golden_temp_offset; 100 101 struct lvts_sensor_data { 102 int dt_id; 103 u8 cal_offsets[3]; 104 }; 105 106 struct lvts_ctrl_data { 107 struct lvts_sensor_data lvts_sensor[LVTS_SENSOR_MAX]; 108 int cal_offset[LVTS_SENSOR_MAX]; 109 int num_lvts_sensor; 110 u8 valid_sensor_mask; 111 int offset; 112 int mode; 113 }; 114 115 #define VALID_SENSOR_MAP(s0, s1, s2, s3) \ 116 .valid_sensor_mask = (((s0) ? BIT(0) : 0) | \ 117 ((s1) ? BIT(1) : 0) | \ 118 ((s2) ? BIT(2) : 0) | \ 119 ((s3) ? BIT(3) : 0)) 120 121 #define lvts_for_each_valid_sensor(i, lvts_ctrl_data) \ 122 for ((i) = 0; (i) < LVTS_SENSOR_MAX; (i)++) \ 123 if (!((lvts_ctrl_data)->valid_sensor_mask & BIT(i))) \ 124 continue; \ 125 else 126 127 struct lvts_data { 128 const struct lvts_ctrl_data *lvts_ctrl; 129 int num_lvts_ctrl; 130 int temp_factor; 131 int temp_offset; 132 int gt_calib_bit_offset; 133 }; 134 135 struct lvts_sensor { 136 struct thermal_zone_device *tz; 137 void __iomem *msr; 138 void __iomem *base; 139 int id; 140 int dt_id; 141 int low_thresh; 142 int high_thresh; 143 }; 144 145 struct lvts_ctrl { 146 struct lvts_sensor sensors[LVTS_SENSOR_MAX]; 147 const struct lvts_data *lvts_data; 148 u32 calibration[LVTS_SENSOR_MAX]; 149 u32 hw_tshut_raw_temp; 150 int mode; 151 void __iomem *base; 152 int low_thresh; 153 int high_thresh; 154 }; 155 156 struct lvts_domain { 157 struct lvts_ctrl *lvts_ctrl; 158 struct reset_control *reset; 159 struct clk *clk; 160 int num_lvts_ctrl; 161 void __iomem *base; 162 size_t calib_len; 163 u8 *calib; 164 #ifdef CONFIG_DEBUG_FS 165 struct dentry *dom_dentry; 166 #endif 167 }; 168 169 #ifdef CONFIG_MTK_LVTS_THERMAL_DEBUGFS 170 171 #define LVTS_DEBUG_FS_REGS(__reg) \ 172 { \ 173 .name = __stringify(__reg), \ 174 .offset = __reg(0), \ 175 } 176 177 static const struct debugfs_reg32 lvts_regs[] = { 178 LVTS_DEBUG_FS_REGS(LVTS_MONCTL0), 179 LVTS_DEBUG_FS_REGS(LVTS_MONCTL1), 180 LVTS_DEBUG_FS_REGS(LVTS_MONCTL2), 181 LVTS_DEBUG_FS_REGS(LVTS_MONINT), 182 LVTS_DEBUG_FS_REGS(LVTS_MONINTSTS), 183 LVTS_DEBUG_FS_REGS(LVTS_MONIDET0), 184 LVTS_DEBUG_FS_REGS(LVTS_MONIDET1), 185 LVTS_DEBUG_FS_REGS(LVTS_MONIDET2), 186 LVTS_DEBUG_FS_REGS(LVTS_MONIDET3), 187 LVTS_DEBUG_FS_REGS(LVTS_H2NTHRE), 188 LVTS_DEBUG_FS_REGS(LVTS_HTHRE), 189 LVTS_DEBUG_FS_REGS(LVTS_OFFSETH), 190 LVTS_DEBUG_FS_REGS(LVTS_OFFSETL), 191 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL0), 192 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL1), 193 LVTS_DEBUG_FS_REGS(LVTS_TSSEL), 194 LVTS_DEBUG_FS_REGS(LVTS_CALSCALE), 195 LVTS_DEBUG_FS_REGS(LVTS_ID), 196 LVTS_DEBUG_FS_REGS(LVTS_CONFIG), 197 LVTS_DEBUG_FS_REGS(LVTS_EDATA00), 198 LVTS_DEBUG_FS_REGS(LVTS_EDATA01), 199 LVTS_DEBUG_FS_REGS(LVTS_EDATA02), 200 LVTS_DEBUG_FS_REGS(LVTS_EDATA03), 201 LVTS_DEBUG_FS_REGS(LVTS_MSR0), 202 LVTS_DEBUG_FS_REGS(LVTS_MSR1), 203 LVTS_DEBUG_FS_REGS(LVTS_MSR2), 204 LVTS_DEBUG_FS_REGS(LVTS_MSR3), 205 LVTS_DEBUG_FS_REGS(LVTS_IMMD0), 206 LVTS_DEBUG_FS_REGS(LVTS_IMMD1), 207 LVTS_DEBUG_FS_REGS(LVTS_IMMD2), 208 LVTS_DEBUG_FS_REGS(LVTS_IMMD3), 209 LVTS_DEBUG_FS_REGS(LVTS_PROTCTL), 210 LVTS_DEBUG_FS_REGS(LVTS_PROTTA), 211 LVTS_DEBUG_FS_REGS(LVTS_PROTTB), 212 LVTS_DEBUG_FS_REGS(LVTS_PROTTC), 213 LVTS_DEBUG_FS_REGS(LVTS_CLKEN), 214 }; 215 216 static int lvts_debugfs_init(struct device *dev, struct lvts_domain *lvts_td) 217 { 218 struct debugfs_regset32 *regset; 219 struct lvts_ctrl *lvts_ctrl; 220 struct dentry *dentry; 221 char name[64]; 222 int i; 223 224 lvts_td->dom_dentry = debugfs_create_dir(dev_name(dev), NULL); 225 if (IS_ERR(lvts_td->dom_dentry)) 226 return 0; 227 228 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 229 230 lvts_ctrl = &lvts_td->lvts_ctrl[i]; 231 232 sprintf(name, "controller%d", i); 233 dentry = debugfs_create_dir(name, lvts_td->dom_dentry); 234 if (IS_ERR(dentry)) 235 continue; 236 237 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 238 if (!regset) 239 continue; 240 241 regset->base = lvts_ctrl->base; 242 regset->regs = lvts_regs; 243 regset->nregs = ARRAY_SIZE(lvts_regs); 244 245 debugfs_create_regset32("registers", 0400, dentry, regset); 246 } 247 248 return 0; 249 } 250 251 static void lvts_debugfs_exit(struct lvts_domain *lvts_td) 252 { 253 debugfs_remove_recursive(lvts_td->dom_dentry); 254 } 255 256 #else 257 258 static inline int lvts_debugfs_init(struct device *dev, 259 struct lvts_domain *lvts_td) 260 { 261 return 0; 262 } 263 264 static void lvts_debugfs_exit(struct lvts_domain *lvts_td) { } 265 266 #endif 267 268 static int lvts_raw_to_temp(u32 raw_temp, int temp_factor) 269 { 270 int temperature; 271 272 temperature = ((s64)(raw_temp & 0xFFFF) * temp_factor) >> 14; 273 temperature += golden_temp_offset; 274 275 return temperature; 276 } 277 278 static u32 lvts_temp_to_raw(int temperature, int temp_factor) 279 { 280 u32 raw_temp = ((s64)(golden_temp_offset - temperature)) << 14; 281 282 raw_temp = div_s64(raw_temp, -temp_factor); 283 284 return raw_temp; 285 } 286 287 static int lvts_get_temp(struct thermal_zone_device *tz, int *temp) 288 { 289 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); 290 struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, 291 sensors[lvts_sensor->id]); 292 const struct lvts_data *lvts_data = lvts_ctrl->lvts_data; 293 void __iomem *msr = lvts_sensor->msr; 294 u32 value; 295 int rc; 296 297 /* 298 * Measurement registers: 299 * 300 * LVTS_MSR[0-3] / LVTS_IMMD[0-3] 301 * 302 * Bits: 303 * 304 * 32-17: Unused 305 * 16 : Valid temperature 306 * 15-0 : Raw temperature 307 */ 308 rc = readl_poll_timeout(msr, value, value & BIT(16), 309 LVTS_MSR_READ_WAIT_US, LVTS_MSR_READ_TIMEOUT_US); 310 311 /* 312 * As the thermal zone temperature will read before the 313 * hardware sensor is fully initialized, we have to check the 314 * validity of the temperature returned when reading the 315 * measurement register. The thermal controller will set the 316 * valid bit temperature only when it is totally initialized. 317 * 318 * Otherwise, we may end up with garbage values out of the 319 * functionning temperature and directly jump to a system 320 * shutdown. 321 */ 322 if (rc) 323 return -EAGAIN; 324 325 *temp = lvts_raw_to_temp(value & 0xFFFF, lvts_data->temp_factor); 326 327 return 0; 328 } 329 330 static void lvts_update_irq_mask(struct lvts_ctrl *lvts_ctrl) 331 { 332 u32 masks[] = { 333 LVTS_MONINT_OFFSET_SENSOR0, 334 LVTS_MONINT_OFFSET_SENSOR1, 335 LVTS_MONINT_OFFSET_SENSOR2, 336 LVTS_MONINT_OFFSET_SENSOR3, 337 }; 338 u32 value = 0; 339 int i; 340 341 value = readl(LVTS_MONINT(lvts_ctrl->base)); 342 343 for (i = 0; i < ARRAY_SIZE(masks); i++) { 344 if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh 345 && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh) 346 value |= masks[i]; 347 else 348 value &= ~masks[i]; 349 } 350 351 writel(value, LVTS_MONINT(lvts_ctrl->base)); 352 } 353 354 static bool lvts_should_update_thresh(struct lvts_ctrl *lvts_ctrl, int high) 355 { 356 int i; 357 358 if (high > lvts_ctrl->high_thresh) 359 return true; 360 361 lvts_for_each_valid_sensor(i, lvts_ctrl->lvts_data->lvts_ctrl) 362 if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh 363 && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh) 364 return false; 365 366 return true; 367 } 368 369 static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high) 370 { 371 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); 372 struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, 373 sensors[lvts_sensor->id]); 374 const struct lvts_data *lvts_data = lvts_ctrl->lvts_data; 375 void __iomem *base = lvts_sensor->base; 376 u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD, 377 lvts_data->temp_factor); 378 u32 raw_high = lvts_temp_to_raw(high, lvts_data->temp_factor); 379 bool should_update_thresh; 380 381 lvts_sensor->low_thresh = low; 382 lvts_sensor->high_thresh = high; 383 384 should_update_thresh = lvts_should_update_thresh(lvts_ctrl, high); 385 if (should_update_thresh) { 386 lvts_ctrl->high_thresh = high; 387 lvts_ctrl->low_thresh = low; 388 } 389 lvts_update_irq_mask(lvts_ctrl); 390 391 if (!should_update_thresh) 392 return 0; 393 394 /* 395 * Low offset temperature threshold 396 * 397 * LVTS_OFFSETL 398 * 399 * Bits: 400 * 401 * 14-0 : Raw temperature for threshold 402 */ 403 pr_debug("%s: Setting low limit temperature interrupt: %d\n", 404 thermal_zone_device_type(tz), low); 405 writel(raw_low, LVTS_OFFSETL(base)); 406 407 /* 408 * High offset temperature threshold 409 * 410 * LVTS_OFFSETH 411 * 412 * Bits: 413 * 414 * 14-0 : Raw temperature for threshold 415 */ 416 pr_debug("%s: Setting high limit temperature interrupt: %d\n", 417 thermal_zone_device_type(tz), high); 418 writel(raw_high, LVTS_OFFSETH(base)); 419 420 return 0; 421 } 422 423 static irqreturn_t lvts_ctrl_irq_handler(struct lvts_ctrl *lvts_ctrl) 424 { 425 irqreturn_t iret = IRQ_NONE; 426 u32 value; 427 u32 masks[] = { 428 LVTS_INT_SENSOR0, 429 LVTS_INT_SENSOR1, 430 LVTS_INT_SENSOR2, 431 LVTS_INT_SENSOR3 432 }; 433 int i; 434 435 /* 436 * Interrupt monitoring status 437 * 438 * LVTS_MONINTST 439 * 440 * Bits: 441 * 442 * 31 : Interrupt for stage 3 443 * 30 : Interrupt for stage 2 444 * 29 : Interrupt for state 1 445 * 28 : Interrupt using filter on sensor 3 446 * 447 * 27 : Interrupt using immediate on sensor 3 448 * 26 : Interrupt normal to hot on sensor 3 449 * 25 : Interrupt high offset on sensor 3 450 * 24 : Interrupt low offset on sensor 3 451 * 452 * 23 : Interrupt hot threshold on sensor 3 453 * 22 : Interrupt cold threshold on sensor 3 454 * 21 : Interrupt using filter on sensor 2 455 * 20 : Interrupt using filter on sensor 1 456 * 457 * 19 : Interrupt using filter on sensor 0 458 * 18 : Interrupt using immediate on sensor 2 459 * 17 : Interrupt using immediate on sensor 1 460 * 16 : Interrupt using immediate on sensor 0 461 * 462 * 15 : Interrupt device access timeout interrupt 463 * 14 : Interrupt normal to hot on sensor 2 464 * 13 : Interrupt high offset interrupt on sensor 2 465 * 12 : Interrupt low offset interrupt on sensor 2 466 * 467 * 11 : Interrupt hot threshold on sensor 2 468 * 10 : Interrupt cold threshold on sensor 2 469 * 9 : Interrupt normal to hot on sensor 1 470 * 8 : Interrupt high offset interrupt on sensor 1 471 * 472 * 7 : Interrupt low offset interrupt on sensor 1 473 * 6 : Interrupt hot threshold on sensor 1 474 * 5 : Interrupt cold threshold on sensor 1 475 * 4 : Interrupt normal to hot on sensor 0 476 * 477 * 3 : Interrupt high offset interrupt on sensor 0 478 * 2 : Interrupt low offset interrupt on sensor 0 479 * 1 : Interrupt hot threshold on sensor 0 480 * 0 : Interrupt cold threshold on sensor 0 481 * 482 * We are interested in the sensor(s) responsible of the 483 * interrupt event. We update the thermal framework with the 484 * thermal zone associated with the sensor. The framework will 485 * take care of the rest whatever the kind of interrupt, we 486 * are only interested in which sensor raised the interrupt. 487 * 488 * sensor 3 interrupt: 0001 1111 1100 0000 0000 0000 0000 0000 489 * => 0x1FC00000 490 * sensor 2 interrupt: 0000 0000 0010 0100 0111 1100 0000 0000 491 * => 0x00247C00 492 * sensor 1 interrupt: 0000 0000 0001 0010 0000 0011 1110 0000 493 * => 0X001203E0 494 * sensor 0 interrupt: 0000 0000 0000 1001 0000 0000 0001 1111 495 * => 0x0009001F 496 */ 497 value = readl(LVTS_MONINTSTS(lvts_ctrl->base)); 498 499 /* 500 * Let's figure out which sensors raised the interrupt 501 * 502 * NOTE: the masks array must be ordered with the index 503 * corresponding to the sensor id eg. index=0, mask for 504 * sensor0. 505 */ 506 for (i = 0; i < ARRAY_SIZE(masks); i++) { 507 508 if (!(value & masks[i])) 509 continue; 510 511 thermal_zone_device_update(lvts_ctrl->sensors[i].tz, 512 THERMAL_TRIP_VIOLATED); 513 iret = IRQ_HANDLED; 514 } 515 516 /* 517 * Write back to clear the interrupt status (W1C) 518 */ 519 writel(value, LVTS_MONINTSTS(lvts_ctrl->base)); 520 521 return iret; 522 } 523 524 /* 525 * Temperature interrupt handler. Even if the driver supports more 526 * interrupt modes, we use the interrupt when the temperature crosses 527 * the hot threshold the way up and the way down (modulo the 528 * hysteresis). 529 * 530 * Each thermal domain has a couple of interrupts, one for hardware 531 * reset and another one for all the thermal events happening on the 532 * different sensors. 533 * 534 * The interrupt is configured for thermal events when crossing the 535 * hot temperature limit. At each interrupt, we check in every 536 * controller if there is an interrupt pending. 537 */ 538 static irqreturn_t lvts_irq_handler(int irq, void *data) 539 { 540 struct lvts_domain *lvts_td = data; 541 irqreturn_t aux, iret = IRQ_NONE; 542 int i; 543 544 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 545 546 aux = lvts_ctrl_irq_handler(&lvts_td->lvts_ctrl[i]); 547 if (aux != IRQ_HANDLED) 548 continue; 549 550 iret = IRQ_HANDLED; 551 } 552 553 return iret; 554 } 555 556 static struct thermal_zone_device_ops lvts_ops = { 557 .get_temp = lvts_get_temp, 558 .set_trips = lvts_set_trips, 559 }; 560 561 static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, 562 const struct lvts_ctrl_data *lvts_ctrl_data) 563 { 564 struct lvts_sensor *lvts_sensor = lvts_ctrl->sensors; 565 566 void __iomem *msr_regs[] = { 567 LVTS_MSR0(lvts_ctrl->base), 568 LVTS_MSR1(lvts_ctrl->base), 569 LVTS_MSR2(lvts_ctrl->base), 570 LVTS_MSR3(lvts_ctrl->base) 571 }; 572 573 void __iomem *imm_regs[] = { 574 LVTS_IMMD0(lvts_ctrl->base), 575 LVTS_IMMD1(lvts_ctrl->base), 576 LVTS_IMMD2(lvts_ctrl->base), 577 LVTS_IMMD3(lvts_ctrl->base) 578 }; 579 580 int i; 581 582 lvts_for_each_valid_sensor(i, lvts_ctrl_data) { 583 584 int dt_id = lvts_ctrl_data->lvts_sensor[i].dt_id; 585 586 /* 587 * At this point, we don't know which id matches which 588 * sensor. Let's set arbitrally the id from the index. 589 */ 590 lvts_sensor[i].id = i; 591 592 /* 593 * The thermal zone registration will set the trip 594 * point interrupt in the thermal controller 595 * register. But this one will be reset in the 596 * initialization after. So we need to post pone the 597 * thermal zone creation after the controller is 598 * setup. For this reason, we store the device tree 599 * node id from the data in the sensor structure 600 */ 601 lvts_sensor[i].dt_id = dt_id; 602 603 /* 604 * We assign the base address of the thermal 605 * controller as a back pointer. So it will be 606 * accessible from the different thermal framework ops 607 * as we pass the lvts_sensor pointer as thermal zone 608 * private data. 609 */ 610 lvts_sensor[i].base = lvts_ctrl->base; 611 612 /* 613 * Each sensor has its own register address to read from. 614 */ 615 lvts_sensor[i].msr = lvts_ctrl_data->mode == LVTS_MSR_IMMEDIATE_MODE ? 616 imm_regs[i] : msr_regs[i]; 617 618 lvts_sensor[i].low_thresh = INT_MIN; 619 lvts_sensor[i].high_thresh = INT_MIN; 620 }; 621 622 return 0; 623 } 624 625 /* 626 * The efuse blob values follows the sensor enumeration per thermal 627 * controller. The decoding of the stream is as follow: 628 * 629 * MT8192 : 630 * Stream index map for MCU Domain mt8192 : 631 * 632 * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> 633 * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 | 0x0A | 0x0B 634 * 635 * <-----sensor#2-----> <-----sensor#3-----> 636 * 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 | 0x13 637 * 638 * <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7-----> 639 * 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 | 0x22 | 0x23 640 * 641 * Stream index map for AP Domain mt8192 : 642 * 643 * <-----sensor#0-----> <-----sensor#1-----> 644 * 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A | 0x2B 645 * 646 * <-----sensor#2-----> <-----sensor#3-----> 647 * 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33 648 * 649 * <-----sensor#4-----> <-----sensor#5-----> 650 * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B 651 * 652 * <-----sensor#6-----> <-----sensor#7-----> <-----sensor#8-----> 653 * 0x3C | 0x3D | 0x3E | 0x3F | 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 654 * 655 * MT8195 : 656 * Stream index map for MCU Domain mt8195 : 657 * 658 * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> 659 * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 660 * 661 * <-----mcu-tc#1-----> <-----sensor#2-----> <-----sensor#3-----> 662 * 0x0A | 0x0B | 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 663 * 664 * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7-----> 665 * 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 666 * 667 * Stream index map for AP Domain mt8195 : 668 * 669 * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1-----> 670 * 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A 671 * 672 * <-----ap--tc#1-----> <-----sensor#2-----> <-----sensor#3-----> 673 * 0x2B | 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33 674 * 675 * <-----ap--tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> 676 * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B | 0x3C | 0x3D | 0x3E | 0x3F 677 * 678 * <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8-----> 679 * 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48 680 * 681 * Note: In some cases, values don't strictly follow a little endian ordering. 682 * The data description gives byte offsets constituting each calibration value 683 * for each sensor. 684 */ 685 static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, 686 const struct lvts_ctrl_data *lvts_ctrl_data, 687 u8 *efuse_calibration, 688 size_t calib_len) 689 { 690 int i; 691 692 lvts_for_each_valid_sensor(i, lvts_ctrl_data) { 693 const struct lvts_sensor_data *sensor = 694 &lvts_ctrl_data->lvts_sensor[i]; 695 696 if (sensor->cal_offsets[0] >= calib_len || 697 sensor->cal_offsets[1] >= calib_len || 698 sensor->cal_offsets[2] >= calib_len) 699 return -EINVAL; 700 701 lvts_ctrl->calibration[i] = 702 (efuse_calibration[sensor->cal_offsets[0]] << 0) + 703 (efuse_calibration[sensor->cal_offsets[1]] << 8) + 704 (efuse_calibration[sensor->cal_offsets[2]] << 16); 705 } 706 707 return 0; 708 } 709 710 /* 711 * The efuse bytes stream can be split into different chunk of 712 * nvmems. This function reads and concatenate those into a single 713 * buffer so it can be read sequentially when initializing the 714 * calibration data. 715 */ 716 static int lvts_calibration_read(struct device *dev, struct lvts_domain *lvts_td, 717 const struct lvts_data *lvts_data) 718 { 719 struct device_node *np = dev_of_node(dev); 720 struct nvmem_cell *cell; 721 struct property *prop; 722 const char *cell_name; 723 724 of_property_for_each_string(np, "nvmem-cell-names", prop, cell_name) { 725 size_t len; 726 u8 *efuse; 727 728 cell = of_nvmem_cell_get(np, cell_name); 729 if (IS_ERR(cell)) { 730 dev_err(dev, "Failed to get cell '%s'\n", cell_name); 731 return PTR_ERR(cell); 732 } 733 734 efuse = nvmem_cell_read(cell, &len); 735 736 nvmem_cell_put(cell); 737 738 if (IS_ERR(efuse)) { 739 dev_err(dev, "Failed to read cell '%s'\n", cell_name); 740 return PTR_ERR(efuse); 741 } 742 743 lvts_td->calib = devm_krealloc(dev, lvts_td->calib, 744 lvts_td->calib_len + len, GFP_KERNEL); 745 if (!lvts_td->calib) { 746 kfree(efuse); 747 return -ENOMEM; 748 } 749 750 memcpy(lvts_td->calib + lvts_td->calib_len, efuse, len); 751 752 lvts_td->calib_len += len; 753 754 kfree(efuse); 755 } 756 757 return 0; 758 } 759 760 static int lvts_golden_temp_init(struct device *dev, u8 *calib, 761 const struct lvts_data *lvts_data) 762 { 763 u32 gt; 764 765 /* 766 * The golden temp information is contained in the first 32-bit 767 * word of efuse data at a specific bit offset. 768 */ 769 gt = (((u32 *)calib)[0] >> lvts_data->gt_calib_bit_offset) & 0xff; 770 771 if (gt && gt < LVTS_GOLDEN_TEMP_MAX) 772 golden_temp = gt; 773 774 golden_temp_offset = golden_temp * 500 + lvts_data->temp_offset; 775 776 return 0; 777 } 778 779 static int lvts_ctrl_init(struct device *dev, struct lvts_domain *lvts_td, 780 const struct lvts_data *lvts_data) 781 { 782 size_t size = sizeof(*lvts_td->lvts_ctrl) * lvts_data->num_lvts_ctrl; 783 struct lvts_ctrl *lvts_ctrl; 784 int i, ret; 785 786 /* 787 * Create the calibration bytes stream from efuse data 788 */ 789 ret = lvts_calibration_read(dev, lvts_td, lvts_data); 790 if (ret) 791 return ret; 792 793 ret = lvts_golden_temp_init(dev, lvts_td->calib, lvts_data); 794 if (ret) 795 return ret; 796 797 lvts_ctrl = devm_kzalloc(dev, size, GFP_KERNEL); 798 if (!lvts_ctrl) 799 return -ENOMEM; 800 801 for (i = 0; i < lvts_data->num_lvts_ctrl; i++) { 802 803 lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset; 804 lvts_ctrl[i].lvts_data = lvts_data; 805 806 ret = lvts_sensor_init(dev, &lvts_ctrl[i], 807 &lvts_data->lvts_ctrl[i]); 808 if (ret) 809 return ret; 810 811 ret = lvts_calibration_init(dev, &lvts_ctrl[i], 812 &lvts_data->lvts_ctrl[i], 813 lvts_td->calib, 814 lvts_td->calib_len); 815 if (ret) 816 return ret; 817 818 /* 819 * The mode the ctrl will use to read the temperature 820 * (filtered or immediate) 821 */ 822 lvts_ctrl[i].mode = lvts_data->lvts_ctrl[i].mode; 823 824 /* 825 * The temperature to raw temperature must be done 826 * after initializing the calibration. 827 */ 828 lvts_ctrl[i].hw_tshut_raw_temp = 829 lvts_temp_to_raw(LVTS_HW_TSHUT_TEMP, 830 lvts_data->temp_factor); 831 832 lvts_ctrl[i].low_thresh = INT_MIN; 833 lvts_ctrl[i].high_thresh = INT_MIN; 834 } 835 836 /* 837 * We no longer need the efuse bytes stream, let's free it 838 */ 839 devm_kfree(dev, lvts_td->calib); 840 841 lvts_td->lvts_ctrl = lvts_ctrl; 842 lvts_td->num_lvts_ctrl = lvts_data->num_lvts_ctrl; 843 844 return 0; 845 } 846 847 /* 848 * At this point the configuration register is the only place in the 849 * driver where we write multiple values. Per hardware constraint, 850 * each write in the configuration register must be separated by a 851 * delay of 2 us. 852 */ 853 static void lvts_write_config(struct lvts_ctrl *lvts_ctrl, u32 *cmds, int nr_cmds) 854 { 855 int i; 856 857 /* 858 * Configuration register 859 */ 860 for (i = 0; i < nr_cmds; i++) { 861 writel(cmds[i], LVTS_CONFIG(lvts_ctrl->base)); 862 usleep_range(2, 4); 863 } 864 } 865 866 static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl) 867 { 868 /* 869 * LVTS_PROTCTL : Thermal Protection Sensor Selection 870 * 871 * Bits: 872 * 873 * 19-18 : Sensor to base the protection on 874 * 17-16 : Strategy: 875 * 00 : Average of 4 sensors 876 * 01 : Max of 4 sensors 877 * 10 : Selected sensor with bits 19-18 878 * 11 : Reserved 879 */ 880 writel(BIT(16), LVTS_PROTCTL(lvts_ctrl->base)); 881 882 /* 883 * LVTS_PROTTA : Stage 1 temperature threshold 884 * LVTS_PROTTB : Stage 2 temperature threshold 885 * LVTS_PROTTC : Stage 3 temperature threshold 886 * 887 * Bits: 888 * 889 * 14-0: Raw temperature threshold 890 * 891 * writel(0x0, LVTS_PROTTA(lvts_ctrl->base)); 892 * writel(0x0, LVTS_PROTTB(lvts_ctrl->base)); 893 */ 894 writel(lvts_ctrl->hw_tshut_raw_temp, LVTS_PROTTC(lvts_ctrl->base)); 895 896 /* 897 * LVTS_MONINT : Interrupt configuration register 898 * 899 * The LVTS_MONINT register layout is the same as the LVTS_MONINTSTS 900 * register, except we set the bits to enable the interrupt. 901 */ 902 writel(LVTS_MONINT_CONF, LVTS_MONINT(lvts_ctrl->base)); 903 904 return 0; 905 } 906 907 static int lvts_domain_reset(struct device *dev, struct reset_control *reset) 908 { 909 int ret; 910 911 ret = reset_control_assert(reset); 912 if (ret) 913 return ret; 914 915 return reset_control_deassert(reset); 916 } 917 918 /* 919 * Enable or disable the clocks of a specified thermal controller 920 */ 921 static int lvts_ctrl_set_enable(struct lvts_ctrl *lvts_ctrl, int enable) 922 { 923 /* 924 * LVTS_CLKEN : Internal LVTS clock 925 * 926 * Bits: 927 * 928 * 0 : enable / disable clock 929 */ 930 writel(enable, LVTS_CLKEN(lvts_ctrl->base)); 931 932 return 0; 933 } 934 935 static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl) 936 { 937 u32 id, cmds[] = { 0xC103FFFF, 0xC502FF55 }; 938 939 lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); 940 941 /* 942 * LVTS_ID : Get ID and status of the thermal controller 943 * 944 * Bits: 945 * 946 * 0-5 : thermal controller id 947 * 7 : thermal controller connection is valid 948 */ 949 id = readl(LVTS_ID(lvts_ctrl->base)); 950 if (!(id & BIT(7))) 951 return -EIO; 952 953 return 0; 954 } 955 956 static int lvts_ctrl_initialize(struct device *dev, struct lvts_ctrl *lvts_ctrl) 957 { 958 /* 959 * Write device mask: 0xC1030000 960 */ 961 u32 cmds[] = { 962 0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1, 963 0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300, 964 0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC, 965 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1 966 }; 967 968 lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); 969 970 return 0; 971 } 972 973 static int lvts_ctrl_calibrate(struct device *dev, struct lvts_ctrl *lvts_ctrl) 974 { 975 int i; 976 void __iomem *lvts_edata[] = { 977 LVTS_EDATA00(lvts_ctrl->base), 978 LVTS_EDATA01(lvts_ctrl->base), 979 LVTS_EDATA02(lvts_ctrl->base), 980 LVTS_EDATA03(lvts_ctrl->base) 981 }; 982 983 /* 984 * LVTS_EDATA0X : Efuse calibration reference value for sensor X 985 * 986 * Bits: 987 * 988 * 20-0 : Efuse value for normalization data 989 */ 990 for (i = 0; i < LVTS_SENSOR_MAX; i++) 991 writel(lvts_ctrl->calibration[i], lvts_edata[i]); 992 993 return 0; 994 } 995 996 static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_ctrl) 997 { 998 u32 value; 999 1000 /* 1001 * LVTS_TSSEL : Sensing point index numbering 1002 * 1003 * Bits: 1004 * 1005 * 31-24: ADC Sense 3 1006 * 23-16: ADC Sense 2 1007 * 15-8 : ADC Sense 1 1008 * 7-0 : ADC Sense 0 1009 */ 1010 value = LVTS_TSSEL_CONF; 1011 writel(value, LVTS_TSSEL(lvts_ctrl->base)); 1012 1013 /* 1014 * LVTS_CALSCALE : ADC voltage round 1015 */ 1016 value = 0x300; 1017 value = LVTS_CALSCALE_CONF; 1018 1019 /* 1020 * LVTS_MSRCTL0 : Sensor filtering strategy 1021 * 1022 * Filters: 1023 * 1024 * 000 : One sample 1025 * 001 : Avg 2 samples 1026 * 010 : 4 samples, drop min and max, avg 2 samples 1027 * 011 : 6 samples, drop min and max, avg 4 samples 1028 * 100 : 10 samples, drop min and max, avg 8 samples 1029 * 101 : 18 samples, drop min and max, avg 16 samples 1030 * 1031 * Bits: 1032 * 1033 * 0-2 : Sensor0 filter 1034 * 3-5 : Sensor1 filter 1035 * 6-8 : Sensor2 filter 1036 * 9-11 : Sensor3 filter 1037 */ 1038 value = LVTS_HW_FILTER << 9 | LVTS_HW_FILTER << 6 | 1039 LVTS_HW_FILTER << 3 | LVTS_HW_FILTER; 1040 writel(value, LVTS_MSRCTL0(lvts_ctrl->base)); 1041 1042 /* 1043 * LVTS_MONCTL1 : Period unit and group interval configuration 1044 * 1045 * The clock source of LVTS thermal controller is 26MHz. 1046 * 1047 * The period unit is a time base for all the interval delays 1048 * specified in the registers. By default we use 12. The time 1049 * conversion is done by multiplying by 256 and 1/26.10^6 1050 * 1051 * An interval delay multiplied by the period unit gives the 1052 * duration in seconds. 1053 * 1054 * - Filter interval delay is a delay between two samples of 1055 * the same sensor. 1056 * 1057 * - Sensor interval delay is a delay between two samples of 1058 * different sensors. 1059 * 1060 * - Group interval delay is a delay between different rounds. 1061 * 1062 * For example: 1063 * If Period unit = C, filter delay = 1, sensor delay = 2, group delay = 1, 1064 * and two sensors, TS1 and TS2, are in a LVTS thermal controller 1065 * and then 1066 * Period unit time = C * 1/26M * 256 = 12 * 38.46ns * 256 = 118.149us 1067 * Filter interval delay = 1 * Period unit = 118.149us 1068 * Sensor interval delay = 2 * Period unit = 236.298us 1069 * Group interval delay = 1 * Period unit = 118.149us 1070 * 1071 * TS1 TS1 ... TS1 TS2 TS2 ... TS2 TS1... 1072 * <--> Filter interval delay 1073 * <--> Sensor interval delay 1074 * <--> Group interval delay 1075 * Bits: 1076 * 29 - 20 : Group interval 1077 * 16 - 13 : Send a single interrupt when crossing the hot threshold (1) 1078 * or an interrupt everytime the hot threshold is crossed (0) 1079 * 9 - 0 : Period unit 1080 * 1081 */ 1082 value = LVTS_GROUP_INTERVAL << 20 | LVTS_PERIOD_UNIT; 1083 writel(value, LVTS_MONCTL1(lvts_ctrl->base)); 1084 1085 /* 1086 * LVTS_MONCTL2 : Filtering and sensor interval 1087 * 1088 * Bits: 1089 * 1090 * 25-16 : Interval unit in PERIOD_UNIT between sample on 1091 * the same sensor, filter interval 1092 * 9-0 : Interval unit in PERIOD_UNIT between each sensor 1093 * 1094 */ 1095 value = LVTS_FILTER_INTERVAL << 16 | LVTS_SENSOR_INTERVAL; 1096 writel(value, LVTS_MONCTL2(lvts_ctrl->base)); 1097 1098 return lvts_irq_init(lvts_ctrl); 1099 } 1100 1101 static int lvts_ctrl_start(struct device *dev, struct lvts_ctrl *lvts_ctrl) 1102 { 1103 struct lvts_sensor *lvts_sensors = lvts_ctrl->sensors; 1104 struct thermal_zone_device *tz; 1105 u32 sensor_map = 0; 1106 int i; 1107 /* 1108 * Bitmaps to enable each sensor on immediate and filtered modes, as 1109 * described in MSRCTL1 and MONCTL0 registers below, respectively. 1110 */ 1111 u32 sensor_imm_bitmap[] = { BIT(4), BIT(5), BIT(6), BIT(9) }; 1112 u32 sensor_filt_bitmap[] = { BIT(0), BIT(1), BIT(2), BIT(3) }; 1113 1114 u32 *sensor_bitmap = lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE ? 1115 sensor_imm_bitmap : sensor_filt_bitmap; 1116 1117 lvts_for_each_valid_sensor(i, lvts_ctrl->lvts_data->lvts_ctrl) { 1118 1119 int dt_id = lvts_sensors[i].dt_id; 1120 1121 tz = devm_thermal_of_zone_register(dev, dt_id, &lvts_sensors[i], 1122 &lvts_ops); 1123 if (IS_ERR(tz)) { 1124 /* 1125 * This thermal zone is not described in the 1126 * device tree. It is not an error from the 1127 * thermal OF code POV, we just continue. 1128 */ 1129 if (PTR_ERR(tz) == -ENODEV) 1130 continue; 1131 1132 return PTR_ERR(tz); 1133 } 1134 1135 devm_thermal_add_hwmon_sysfs(dev, tz); 1136 1137 /* 1138 * The thermal zone pointer will be needed in the 1139 * interrupt handler, we store it in the sensor 1140 * structure. The thermal domain structure will be 1141 * passed to the interrupt handler private data as the 1142 * interrupt is shared for all the controller 1143 * belonging to the thermal domain. 1144 */ 1145 lvts_sensors[i].tz = tz; 1146 1147 /* 1148 * This sensor was correctly associated with a thermal 1149 * zone, let's set the corresponding bit in the sensor 1150 * map, so we can enable the temperature monitoring in 1151 * the hardware thermal controller. 1152 */ 1153 sensor_map |= sensor_bitmap[i]; 1154 } 1155 1156 /* 1157 * The initialization of the thermal zones give us 1158 * which sensor point to enable. If any thermal zone 1159 * was not described in the device tree, it won't be 1160 * enabled here in the sensor map. 1161 */ 1162 if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) { 1163 /* 1164 * LVTS_MSRCTL1 : Measurement control 1165 * 1166 * Bits: 1167 * 1168 * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3 1169 * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2 1170 * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1 1171 * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0 1172 * 1173 * That configuration will ignore the filtering and the delays 1174 * introduced in MONCTL1 and MONCTL2 1175 */ 1176 writel(sensor_map, LVTS_MSRCTL1(lvts_ctrl->base)); 1177 } else { 1178 /* 1179 * Bits: 1180 * 9: Single point access flow 1181 * 0-3: Enable sensing point 0-3 1182 */ 1183 writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base)); 1184 } 1185 1186 return 0; 1187 } 1188 1189 static int lvts_domain_init(struct device *dev, struct lvts_domain *lvts_td, 1190 const struct lvts_data *lvts_data) 1191 { 1192 struct lvts_ctrl *lvts_ctrl; 1193 int i, ret; 1194 1195 ret = lvts_ctrl_init(dev, lvts_td, lvts_data); 1196 if (ret) 1197 return ret; 1198 1199 ret = lvts_domain_reset(dev, lvts_td->reset); 1200 if (ret) { 1201 dev_dbg(dev, "Failed to reset domain"); 1202 return ret; 1203 } 1204 1205 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 1206 1207 lvts_ctrl = &lvts_td->lvts_ctrl[i]; 1208 1209 /* 1210 * Initialization steps: 1211 * 1212 * - Enable the clock 1213 * - Connect to the LVTS 1214 * - Initialize the LVTS 1215 * - Prepare the calibration data 1216 * - Select monitored sensors 1217 * [ Configure sampling ] 1218 * [ Configure the interrupt ] 1219 * - Start measurement 1220 */ 1221 ret = lvts_ctrl_set_enable(lvts_ctrl, true); 1222 if (ret) { 1223 dev_dbg(dev, "Failed to enable LVTS clock"); 1224 return ret; 1225 } 1226 1227 ret = lvts_ctrl_connect(dev, lvts_ctrl); 1228 if (ret) { 1229 dev_dbg(dev, "Failed to connect to LVTS controller"); 1230 return ret; 1231 } 1232 1233 ret = lvts_ctrl_initialize(dev, lvts_ctrl); 1234 if (ret) { 1235 dev_dbg(dev, "Failed to initialize controller"); 1236 return ret; 1237 } 1238 1239 ret = lvts_ctrl_calibrate(dev, lvts_ctrl); 1240 if (ret) { 1241 dev_dbg(dev, "Failed to calibrate controller"); 1242 return ret; 1243 } 1244 1245 ret = lvts_ctrl_configure(dev, lvts_ctrl); 1246 if (ret) { 1247 dev_dbg(dev, "Failed to configure controller"); 1248 return ret; 1249 } 1250 1251 ret = lvts_ctrl_start(dev, lvts_ctrl); 1252 if (ret) { 1253 dev_dbg(dev, "Failed to start controller"); 1254 return ret; 1255 } 1256 } 1257 1258 return lvts_debugfs_init(dev, lvts_td); 1259 } 1260 1261 static int lvts_probe(struct platform_device *pdev) 1262 { 1263 const struct lvts_data *lvts_data; 1264 struct lvts_domain *lvts_td; 1265 struct device *dev = &pdev->dev; 1266 struct resource *res; 1267 int irq, ret; 1268 1269 lvts_td = devm_kzalloc(dev, sizeof(*lvts_td), GFP_KERNEL); 1270 if (!lvts_td) 1271 return -ENOMEM; 1272 1273 lvts_data = of_device_get_match_data(dev); 1274 if (!lvts_data) 1275 return -ENODEV; 1276 1277 lvts_td->clk = devm_clk_get_enabled(dev, NULL); 1278 if (IS_ERR(lvts_td->clk)) 1279 return dev_err_probe(dev, PTR_ERR(lvts_td->clk), "Failed to retrieve clock\n"); 1280 1281 res = platform_get_mem_or_io(pdev, 0); 1282 if (!res) 1283 return dev_err_probe(dev, (-ENXIO), "No IO resource\n"); 1284 1285 lvts_td->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1286 if (IS_ERR(lvts_td->base)) 1287 return dev_err_probe(dev, PTR_ERR(lvts_td->base), "Failed to map io resource\n"); 1288 1289 lvts_td->reset = devm_reset_control_get_by_index(dev, 0); 1290 if (IS_ERR(lvts_td->reset)) 1291 return dev_err_probe(dev, PTR_ERR(lvts_td->reset), "Failed to get reset control\n"); 1292 1293 irq = platform_get_irq(pdev, 0); 1294 if (irq < 0) 1295 return irq; 1296 1297 golden_temp_offset = lvts_data->temp_offset; 1298 1299 ret = lvts_domain_init(dev, lvts_td, lvts_data); 1300 if (ret) 1301 return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n"); 1302 1303 /* 1304 * At this point the LVTS is initialized and enabled. We can 1305 * safely enable the interrupt. 1306 */ 1307 ret = devm_request_threaded_irq(dev, irq, NULL, lvts_irq_handler, 1308 IRQF_ONESHOT, dev_name(dev), lvts_td); 1309 if (ret) 1310 return dev_err_probe(dev, ret, "Failed to request interrupt\n"); 1311 1312 platform_set_drvdata(pdev, lvts_td); 1313 1314 return 0; 1315 } 1316 1317 static void lvts_remove(struct platform_device *pdev) 1318 { 1319 struct lvts_domain *lvts_td; 1320 int i; 1321 1322 lvts_td = platform_get_drvdata(pdev); 1323 1324 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) 1325 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); 1326 1327 lvts_debugfs_exit(lvts_td); 1328 } 1329 1330 static const struct lvts_ctrl_data mt7988_lvts_ap_data_ctrl[] = { 1331 { 1332 .lvts_sensor = { 1333 { .dt_id = MT7988_CPU_0, 1334 .cal_offsets = { 0x00, 0x01, 0x02 } }, 1335 { .dt_id = MT7988_CPU_1, 1336 .cal_offsets = { 0x04, 0x05, 0x06 } }, 1337 { .dt_id = MT7988_ETH2P5G_0, 1338 .cal_offsets = { 0x08, 0x09, 0x0a } }, 1339 { .dt_id = MT7988_ETH2P5G_1, 1340 .cal_offsets = { 0x0c, 0x0d, 0x0e } } 1341 }, 1342 VALID_SENSOR_MAP(1, 1, 1, 1), 1343 .offset = 0x0, 1344 }, 1345 { 1346 .lvts_sensor = { 1347 { .dt_id = MT7988_TOPS_0, 1348 .cal_offsets = { 0x14, 0x15, 0x16 } }, 1349 { .dt_id = MT7988_TOPS_1, 1350 .cal_offsets = { 0x18, 0x19, 0x1a } }, 1351 { .dt_id = MT7988_ETHWARP_0, 1352 .cal_offsets = { 0x1c, 0x1d, 0x1e } }, 1353 { .dt_id = MT7988_ETHWARP_1, 1354 .cal_offsets = { 0x20, 0x21, 0x22 } } 1355 }, 1356 VALID_SENSOR_MAP(1, 1, 1, 1), 1357 .offset = 0x100, 1358 } 1359 }; 1360 1361 static int lvts_suspend(struct device *dev) 1362 { 1363 struct lvts_domain *lvts_td; 1364 int i; 1365 1366 lvts_td = dev_get_drvdata(dev); 1367 1368 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) 1369 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); 1370 1371 clk_disable_unprepare(lvts_td->clk); 1372 1373 return 0; 1374 } 1375 1376 static int lvts_resume(struct device *dev) 1377 { 1378 struct lvts_domain *lvts_td; 1379 int i, ret; 1380 1381 lvts_td = dev_get_drvdata(dev); 1382 1383 ret = clk_prepare_enable(lvts_td->clk); 1384 if (ret) 1385 return ret; 1386 1387 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) 1388 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], true); 1389 1390 return 0; 1391 } 1392 1393 /* 1394 * The MT8186 calibration data is stored as packed 3-byte little-endian 1395 * values using a weird layout that makes sense only when viewed as a 32-bit 1396 * hexadecimal word dump. Let's suppose SxBy where x = sensor number and 1397 * y = byte number where the LSB is y=0. We then have: 1398 * 1399 * [S0B2-S0B1-S0B0-S1B2] [S1B1-S1B0-S2B2-S2B1] [S2B0-S3B2-S3B1-S3B0] 1400 * 1401 * However, when considering a byte stream, those appear as follows: 1402 * 1403 * [S1B2] [S0B0[ [S0B1] [S0B2] [S2B1] [S2B2] [S1B0] [S1B1] [S3B0] [S3B1] [S3B2] [S2B0] 1404 * 1405 * Hence the rather confusing offsets provided below. 1406 */ 1407 static const struct lvts_ctrl_data mt8186_lvts_data_ctrl[] = { 1408 { 1409 .lvts_sensor = { 1410 { .dt_id = MT8186_LITTLE_CPU0, 1411 .cal_offsets = { 5, 6, 7 } }, 1412 { .dt_id = MT8186_LITTLE_CPU1, 1413 .cal_offsets = { 10, 11, 4 } }, 1414 { .dt_id = MT8186_LITTLE_CPU2, 1415 .cal_offsets = { 15, 8, 9 } }, 1416 { .dt_id = MT8186_CAM, 1417 .cal_offsets = { 12, 13, 14 } } 1418 }, 1419 VALID_SENSOR_MAP(1, 1, 1, 1), 1420 .offset = 0x0, 1421 }, 1422 { 1423 .lvts_sensor = { 1424 { .dt_id = MT8186_BIG_CPU0, 1425 .cal_offsets = { 22, 23, 16 } }, 1426 { .dt_id = MT8186_BIG_CPU1, 1427 .cal_offsets = { 27, 20, 21 } } 1428 }, 1429 VALID_SENSOR_MAP(1, 1, 0, 0), 1430 .offset = 0x100, 1431 }, 1432 { 1433 .lvts_sensor = { 1434 { .dt_id = MT8186_NNA, 1435 .cal_offsets = { 29, 30, 31 } }, 1436 { .dt_id = MT8186_ADSP, 1437 .cal_offsets = { 34, 35, 28 } }, 1438 { .dt_id = MT8186_MFG, 1439 .cal_offsets = { 39, 32, 33 } } 1440 }, 1441 VALID_SENSOR_MAP(1, 1, 1, 0), 1442 .offset = 0x200, 1443 } 1444 }; 1445 1446 static const struct lvts_ctrl_data mt8188_lvts_mcu_data_ctrl[] = { 1447 { 1448 .lvts_sensor = { 1449 { .dt_id = MT8188_MCU_LITTLE_CPU0, 1450 .cal_offsets = { 22, 23, 24 } }, 1451 { .dt_id = MT8188_MCU_LITTLE_CPU1, 1452 .cal_offsets = { 25, 26, 27 } }, 1453 { .dt_id = MT8188_MCU_LITTLE_CPU2, 1454 .cal_offsets = { 28, 29, 30 } }, 1455 { .dt_id = MT8188_MCU_LITTLE_CPU3, 1456 .cal_offsets = { 31, 32, 33 } }, 1457 }, 1458 VALID_SENSOR_MAP(1, 1, 1, 1), 1459 .offset = 0x0, 1460 .mode = LVTS_MSR_FILTERED_MODE, 1461 }, 1462 { 1463 .lvts_sensor = { 1464 { .dt_id = MT8188_MCU_BIG_CPU0, 1465 .cal_offsets = { 34, 35, 36 } }, 1466 { .dt_id = MT8188_MCU_BIG_CPU1, 1467 .cal_offsets = { 37, 38, 39 } }, 1468 }, 1469 VALID_SENSOR_MAP(1, 1, 0, 0), 1470 .offset = 0x100, 1471 .mode = LVTS_MSR_FILTERED_MODE, 1472 } 1473 }; 1474 1475 static const struct lvts_ctrl_data mt8188_lvts_ap_data_ctrl[] = { 1476 { 1477 .lvts_sensor = { 1478 1479 { /* unused */ }, 1480 { .dt_id = MT8188_AP_APU, 1481 .cal_offsets = { 40, 41, 42 } }, 1482 }, 1483 VALID_SENSOR_MAP(0, 1, 0, 0), 1484 .offset = 0x0, 1485 .mode = LVTS_MSR_FILTERED_MODE, 1486 }, 1487 { 1488 .lvts_sensor = { 1489 { .dt_id = MT8188_AP_GPU1, 1490 .cal_offsets = { 43, 44, 45 } }, 1491 { .dt_id = MT8188_AP_GPU2, 1492 .cal_offsets = { 46, 47, 48 } }, 1493 { .dt_id = MT8188_AP_SOC1, 1494 .cal_offsets = { 49, 50, 51 } }, 1495 }, 1496 VALID_SENSOR_MAP(1, 1, 1, 0), 1497 .offset = 0x100, 1498 .mode = LVTS_MSR_FILTERED_MODE, 1499 }, 1500 { 1501 .lvts_sensor = { 1502 { .dt_id = MT8188_AP_SOC2, 1503 .cal_offsets = { 52, 53, 54 } }, 1504 { .dt_id = MT8188_AP_SOC3, 1505 .cal_offsets = { 55, 56, 57 } }, 1506 }, 1507 VALID_SENSOR_MAP(1, 1, 0, 0), 1508 .offset = 0x200, 1509 .mode = LVTS_MSR_FILTERED_MODE, 1510 }, 1511 { 1512 .lvts_sensor = { 1513 { .dt_id = MT8188_AP_CAM1, 1514 .cal_offsets = { 58, 59, 60 } }, 1515 { .dt_id = MT8188_AP_CAM2, 1516 .cal_offsets = { 61, 62, 63 } }, 1517 }, 1518 VALID_SENSOR_MAP(1, 1, 0, 0), 1519 .offset = 0x300, 1520 .mode = LVTS_MSR_FILTERED_MODE, 1521 } 1522 }; 1523 1524 static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = { 1525 { 1526 .lvts_sensor = { 1527 { .dt_id = MT8192_MCU_BIG_CPU0, 1528 .cal_offsets = { 0x04, 0x05, 0x06 } }, 1529 { .dt_id = MT8192_MCU_BIG_CPU1, 1530 .cal_offsets = { 0x08, 0x09, 0x0a } } 1531 }, 1532 VALID_SENSOR_MAP(1, 1, 0, 0), 1533 .offset = 0x0, 1534 .mode = LVTS_MSR_FILTERED_MODE, 1535 }, 1536 { 1537 .lvts_sensor = { 1538 { .dt_id = MT8192_MCU_BIG_CPU2, 1539 .cal_offsets = { 0x0c, 0x0d, 0x0e } }, 1540 { .dt_id = MT8192_MCU_BIG_CPU3, 1541 .cal_offsets = { 0x10, 0x11, 0x12 } } 1542 }, 1543 VALID_SENSOR_MAP(1, 1, 0, 0), 1544 .offset = 0x100, 1545 .mode = LVTS_MSR_FILTERED_MODE, 1546 }, 1547 { 1548 .lvts_sensor = { 1549 { .dt_id = MT8192_MCU_LITTLE_CPU0, 1550 .cal_offsets = { 0x14, 0x15, 0x16 } }, 1551 { .dt_id = MT8192_MCU_LITTLE_CPU1, 1552 .cal_offsets = { 0x18, 0x19, 0x1a } }, 1553 { .dt_id = MT8192_MCU_LITTLE_CPU2, 1554 .cal_offsets = { 0x1c, 0x1d, 0x1e } }, 1555 { .dt_id = MT8192_MCU_LITTLE_CPU3, 1556 .cal_offsets = { 0x20, 0x21, 0x22 } } 1557 }, 1558 VALID_SENSOR_MAP(1, 1, 1, 1), 1559 .offset = 0x200, 1560 .mode = LVTS_MSR_FILTERED_MODE, 1561 } 1562 }; 1563 1564 static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = { 1565 { 1566 .lvts_sensor = { 1567 { .dt_id = MT8192_AP_VPU0, 1568 .cal_offsets = { 0x24, 0x25, 0x26 } }, 1569 { .dt_id = MT8192_AP_VPU1, 1570 .cal_offsets = { 0x28, 0x29, 0x2a } } 1571 }, 1572 VALID_SENSOR_MAP(1, 1, 0, 0), 1573 .offset = 0x0, 1574 }, 1575 { 1576 .lvts_sensor = { 1577 { .dt_id = MT8192_AP_GPU0, 1578 .cal_offsets = { 0x2c, 0x2d, 0x2e } }, 1579 { .dt_id = MT8192_AP_GPU1, 1580 .cal_offsets = { 0x30, 0x31, 0x32 } } 1581 }, 1582 VALID_SENSOR_MAP(1, 1, 0, 0), 1583 .offset = 0x100, 1584 }, 1585 { 1586 .lvts_sensor = { 1587 { .dt_id = MT8192_AP_INFRA, 1588 .cal_offsets = { 0x34, 0x35, 0x36 } }, 1589 { .dt_id = MT8192_AP_CAM, 1590 .cal_offsets = { 0x38, 0x39, 0x3a } }, 1591 }, 1592 VALID_SENSOR_MAP(1, 1, 0, 0), 1593 .offset = 0x200, 1594 }, 1595 { 1596 .lvts_sensor = { 1597 { .dt_id = MT8192_AP_MD0, 1598 .cal_offsets = { 0x3c, 0x3d, 0x3e } }, 1599 { .dt_id = MT8192_AP_MD1, 1600 .cal_offsets = { 0x40, 0x41, 0x42 } }, 1601 { .dt_id = MT8192_AP_MD2, 1602 .cal_offsets = { 0x44, 0x45, 0x46 } } 1603 }, 1604 VALID_SENSOR_MAP(1, 1, 1, 0), 1605 .offset = 0x300, 1606 } 1607 }; 1608 1609 static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = { 1610 { 1611 .lvts_sensor = { 1612 { .dt_id = MT8195_MCU_BIG_CPU0, 1613 .cal_offsets = { 0x04, 0x05, 0x06 } }, 1614 { .dt_id = MT8195_MCU_BIG_CPU1, 1615 .cal_offsets = { 0x07, 0x08, 0x09 } } 1616 }, 1617 VALID_SENSOR_MAP(1, 1, 0, 0), 1618 .offset = 0x0, 1619 }, 1620 { 1621 .lvts_sensor = { 1622 { .dt_id = MT8195_MCU_BIG_CPU2, 1623 .cal_offsets = { 0x0d, 0x0e, 0x0f } }, 1624 { .dt_id = MT8195_MCU_BIG_CPU3, 1625 .cal_offsets = { 0x10, 0x11, 0x12 } } 1626 }, 1627 VALID_SENSOR_MAP(1, 1, 0, 0), 1628 .offset = 0x100, 1629 }, 1630 { 1631 .lvts_sensor = { 1632 { .dt_id = MT8195_MCU_LITTLE_CPU0, 1633 .cal_offsets = { 0x16, 0x17, 0x18 } }, 1634 { .dt_id = MT8195_MCU_LITTLE_CPU1, 1635 .cal_offsets = { 0x19, 0x1a, 0x1b } }, 1636 { .dt_id = MT8195_MCU_LITTLE_CPU2, 1637 .cal_offsets = { 0x1c, 0x1d, 0x1e } }, 1638 { .dt_id = MT8195_MCU_LITTLE_CPU3, 1639 .cal_offsets = { 0x1f, 0x20, 0x21 } } 1640 }, 1641 VALID_SENSOR_MAP(1, 1, 1, 1), 1642 .offset = 0x200, 1643 } 1644 }; 1645 1646 static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = { 1647 { 1648 .lvts_sensor = { 1649 { .dt_id = MT8195_AP_VPU0, 1650 .cal_offsets = { 0x25, 0x26, 0x27 } }, 1651 { .dt_id = MT8195_AP_VPU1, 1652 .cal_offsets = { 0x28, 0x29, 0x2a } } 1653 }, 1654 VALID_SENSOR_MAP(1, 1, 0, 0), 1655 .offset = 0x0, 1656 }, 1657 { 1658 .lvts_sensor = { 1659 { .dt_id = MT8195_AP_GPU0, 1660 .cal_offsets = { 0x2e, 0x2f, 0x30 } }, 1661 { .dt_id = MT8195_AP_GPU1, 1662 .cal_offsets = { 0x31, 0x32, 0x33 } } 1663 }, 1664 VALID_SENSOR_MAP(1, 1, 0, 0), 1665 .offset = 0x100, 1666 }, 1667 { 1668 .lvts_sensor = { 1669 { .dt_id = MT8195_AP_VDEC, 1670 .cal_offsets = { 0x37, 0x38, 0x39 } }, 1671 { .dt_id = MT8195_AP_IMG, 1672 .cal_offsets = { 0x3a, 0x3b, 0x3c } }, 1673 { .dt_id = MT8195_AP_INFRA, 1674 .cal_offsets = { 0x3d, 0x3e, 0x3f } } 1675 }, 1676 VALID_SENSOR_MAP(1, 1, 1, 0), 1677 .offset = 0x200, 1678 }, 1679 { 1680 .lvts_sensor = { 1681 { .dt_id = MT8195_AP_CAM0, 1682 .cal_offsets = { 0x43, 0x44, 0x45 } }, 1683 { .dt_id = MT8195_AP_CAM1, 1684 .cal_offsets = { 0x46, 0x47, 0x48 } } 1685 }, 1686 VALID_SENSOR_MAP(1, 1, 0, 0), 1687 .offset = 0x300, 1688 } 1689 }; 1690 1691 static const struct lvts_data mt7988_lvts_ap_data = { 1692 .lvts_ctrl = mt7988_lvts_ap_data_ctrl, 1693 .num_lvts_ctrl = ARRAY_SIZE(mt7988_lvts_ap_data_ctrl), 1694 .temp_factor = LVTS_COEFF_A_MT7988, 1695 .temp_offset = LVTS_COEFF_B_MT7988, 1696 .gt_calib_bit_offset = 24, 1697 }; 1698 1699 static const struct lvts_data mt8186_lvts_data = { 1700 .lvts_ctrl = mt8186_lvts_data_ctrl, 1701 .num_lvts_ctrl = ARRAY_SIZE(mt8186_lvts_data_ctrl), 1702 .temp_factor = LVTS_COEFF_A_MT7988, 1703 .temp_offset = LVTS_COEFF_B_MT7988, 1704 .gt_calib_bit_offset = 24, 1705 }; 1706 1707 static const struct lvts_data mt8188_lvts_mcu_data = { 1708 .lvts_ctrl = mt8188_lvts_mcu_data_ctrl, 1709 .num_lvts_ctrl = ARRAY_SIZE(mt8188_lvts_mcu_data_ctrl), 1710 .temp_factor = LVTS_COEFF_A_MT8195, 1711 .temp_offset = LVTS_COEFF_B_MT8195, 1712 .gt_calib_bit_offset = 20, 1713 }; 1714 1715 static const struct lvts_data mt8188_lvts_ap_data = { 1716 .lvts_ctrl = mt8188_lvts_ap_data_ctrl, 1717 .num_lvts_ctrl = ARRAY_SIZE(mt8188_lvts_ap_data_ctrl), 1718 .temp_factor = LVTS_COEFF_A_MT8195, 1719 .temp_offset = LVTS_COEFF_B_MT8195, 1720 .gt_calib_bit_offset = 20, 1721 }; 1722 1723 static const struct lvts_data mt8192_lvts_mcu_data = { 1724 .lvts_ctrl = mt8192_lvts_mcu_data_ctrl, 1725 .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl), 1726 .temp_factor = LVTS_COEFF_A_MT8195, 1727 .temp_offset = LVTS_COEFF_B_MT8195, 1728 .gt_calib_bit_offset = 24, 1729 }; 1730 1731 static const struct lvts_data mt8192_lvts_ap_data = { 1732 .lvts_ctrl = mt8192_lvts_ap_data_ctrl, 1733 .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_ap_data_ctrl), 1734 .temp_factor = LVTS_COEFF_A_MT8195, 1735 .temp_offset = LVTS_COEFF_B_MT8195, 1736 .gt_calib_bit_offset = 24, 1737 }; 1738 1739 static const struct lvts_data mt8195_lvts_mcu_data = { 1740 .lvts_ctrl = mt8195_lvts_mcu_data_ctrl, 1741 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl), 1742 .temp_factor = LVTS_COEFF_A_MT8195, 1743 .temp_offset = LVTS_COEFF_B_MT8195, 1744 .gt_calib_bit_offset = 24, 1745 }; 1746 1747 static const struct lvts_data mt8195_lvts_ap_data = { 1748 .lvts_ctrl = mt8195_lvts_ap_data_ctrl, 1749 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl), 1750 .temp_factor = LVTS_COEFF_A_MT8195, 1751 .temp_offset = LVTS_COEFF_B_MT8195, 1752 .gt_calib_bit_offset = 24, 1753 }; 1754 1755 static const struct of_device_id lvts_of_match[] = { 1756 { .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data }, 1757 { .compatible = "mediatek,mt8186-lvts", .data = &mt8186_lvts_data }, 1758 { .compatible = "mediatek,mt8188-lvts-mcu", .data = &mt8188_lvts_mcu_data }, 1759 { .compatible = "mediatek,mt8188-lvts-ap", .data = &mt8188_lvts_ap_data }, 1760 { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data }, 1761 { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data }, 1762 { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data }, 1763 { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data }, 1764 {}, 1765 }; 1766 MODULE_DEVICE_TABLE(of, lvts_of_match); 1767 1768 static const struct dev_pm_ops lvts_pm_ops = { 1769 NOIRQ_SYSTEM_SLEEP_PM_OPS(lvts_suspend, lvts_resume) 1770 }; 1771 1772 static struct platform_driver lvts_driver = { 1773 .probe = lvts_probe, 1774 .remove_new = lvts_remove, 1775 .driver = { 1776 .name = "mtk-lvts-thermal", 1777 .of_match_table = lvts_of_match, 1778 .pm = &lvts_pm_ops, 1779 }, 1780 }; 1781 module_platform_driver(lvts_driver); 1782 1783 MODULE_AUTHOR("Balsam CHIHI <bchihi@baylibre.com>"); 1784 MODULE_DESCRIPTION("MediaTek LVTS Thermal Driver"); 1785 MODULE_LICENSE("GPL"); 1786