1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2023 MediaTek Inc. 4 * Author: Balsam CHIHI <bchihi@baylibre.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/clk-provider.h> 9 #include <linux/delay.h> 10 #include <linux/debugfs.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/iopoll.h> 14 #include <linux/kernel.h> 15 #include <linux/nvmem-consumer.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/reset.h> 19 #include <linux/thermal.h> 20 #include <dt-bindings/thermal/mediatek,lvts-thermal.h> 21 22 #include "../thermal_hwmon.h" 23 24 #define LVTS_MONCTL0(__base) (__base + 0x0000) 25 #define LVTS_MONCTL1(__base) (__base + 0x0004) 26 #define LVTS_MONCTL2(__base) (__base + 0x0008) 27 #define LVTS_MONINT(__base) (__base + 0x000C) 28 #define LVTS_MONINTSTS(__base) (__base + 0x0010) 29 #define LVTS_MONIDET0(__base) (__base + 0x0014) 30 #define LVTS_MONIDET1(__base) (__base + 0x0018) 31 #define LVTS_MONIDET2(__base) (__base + 0x001C) 32 #define LVTS_MONIDET3(__base) (__base + 0x0020) 33 #define LVTS_H2NTHRE(__base) (__base + 0x0024) 34 #define LVTS_HTHRE(__base) (__base + 0x0028) 35 #define LVTS_OFFSETH(__base) (__base + 0x0030) 36 #define LVTS_OFFSETL(__base) (__base + 0x0034) 37 #define LVTS_MSRCTL0(__base) (__base + 0x0038) 38 #define LVTS_MSRCTL1(__base) (__base + 0x003C) 39 #define LVTS_TSSEL(__base) (__base + 0x0040) 40 #define LVTS_CALSCALE(__base) (__base + 0x0048) 41 #define LVTS_ID(__base) (__base + 0x004C) 42 #define LVTS_CONFIG(__base) (__base + 0x0050) 43 #define LVTS_EDATA00(__base) (__base + 0x0054) 44 #define LVTS_EDATA01(__base) (__base + 0x0058) 45 #define LVTS_EDATA02(__base) (__base + 0x005C) 46 #define LVTS_EDATA03(__base) (__base + 0x0060) 47 #define LVTS_MSR0(__base) (__base + 0x0090) 48 #define LVTS_MSR1(__base) (__base + 0x0094) 49 #define LVTS_MSR2(__base) (__base + 0x0098) 50 #define LVTS_MSR3(__base) (__base + 0x009C) 51 #define LVTS_IMMD0(__base) (__base + 0x00A0) 52 #define LVTS_IMMD1(__base) (__base + 0x00A4) 53 #define LVTS_IMMD2(__base) (__base + 0x00A8) 54 #define LVTS_IMMD3(__base) (__base + 0x00AC) 55 #define LVTS_PROTCTL(__base) (__base + 0x00C0) 56 #define LVTS_PROTTA(__base) (__base + 0x00C4) 57 #define LVTS_PROTTB(__base) (__base + 0x00C8) 58 #define LVTS_PROTTC(__base) (__base + 0x00CC) 59 #define LVTS_CLKEN(__base) (__base + 0x00E4) 60 61 #define LVTS_PERIOD_UNIT 0 62 #define LVTS_GROUP_INTERVAL 0 63 #define LVTS_FILTER_INTERVAL 0 64 #define LVTS_SENSOR_INTERVAL 0 65 #define LVTS_HW_FILTER 0x0 66 #define LVTS_TSSEL_CONF 0x13121110 67 #define LVTS_CALSCALE_CONF 0x300 68 #define LVTS_MONINT_CONF 0x8300318C 69 70 #define LVTS_MONINT_OFFSET_SENSOR0 0xC 71 #define LVTS_MONINT_OFFSET_SENSOR1 0x180 72 #define LVTS_MONINT_OFFSET_SENSOR2 0x3000 73 #define LVTS_MONINT_OFFSET_SENSOR3 0x3000000 74 75 #define LVTS_INT_SENSOR0 0x0009001F 76 #define LVTS_INT_SENSOR1 0x001203E0 77 #define LVTS_INT_SENSOR2 0x00247C00 78 #define LVTS_INT_SENSOR3 0x1FC00000 79 80 #define LVTS_SENSOR_MAX 4 81 #define LVTS_GOLDEN_TEMP_MAX 62 82 #define LVTS_GOLDEN_TEMP_DEFAULT 50 83 #define LVTS_COEFF_A_MT8195 -250460 84 #define LVTS_COEFF_B_MT8195 250460 85 #define LVTS_COEFF_A_MT7988 -204650 86 #define LVTS_COEFF_B_MT7988 204650 87 88 #define LVTS_MSR_IMMEDIATE_MODE 0 89 #define LVTS_MSR_FILTERED_MODE 1 90 91 #define LVTS_MSR_READ_TIMEOUT_US 400 92 #define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2) 93 94 #define LVTS_HW_TSHUT_TEMP 105000 95 96 #define LVTS_MINIMUM_THRESHOLD 20000 97 98 static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT; 99 static int golden_temp_offset; 100 101 struct lvts_sensor_data { 102 int dt_id; 103 u8 cal_offsets[3]; 104 }; 105 106 struct lvts_ctrl_data { 107 struct lvts_sensor_data lvts_sensor[LVTS_SENSOR_MAX]; 108 u8 valid_sensor_mask; 109 int offset; 110 int mode; 111 }; 112 113 #define VALID_SENSOR_MAP(s0, s1, s2, s3) \ 114 .valid_sensor_mask = (((s0) ? BIT(0) : 0) | \ 115 ((s1) ? BIT(1) : 0) | \ 116 ((s2) ? BIT(2) : 0) | \ 117 ((s3) ? BIT(3) : 0)) 118 119 #define lvts_for_each_valid_sensor(i, lvts_ctrl) \ 120 for ((i) = 0; (i) < LVTS_SENSOR_MAX; (i)++) \ 121 if (!((lvts_ctrl)->valid_sensor_mask & BIT(i))) \ 122 continue; \ 123 else 124 125 struct lvts_data { 126 const struct lvts_ctrl_data *lvts_ctrl; 127 int num_lvts_ctrl; 128 int temp_factor; 129 int temp_offset; 130 int gt_calib_bit_offset; 131 }; 132 133 struct lvts_sensor { 134 struct thermal_zone_device *tz; 135 void __iomem *msr; 136 void __iomem *base; 137 int id; 138 int dt_id; 139 int low_thresh; 140 int high_thresh; 141 }; 142 143 struct lvts_ctrl { 144 struct lvts_sensor sensors[LVTS_SENSOR_MAX]; 145 const struct lvts_data *lvts_data; 146 u32 calibration[LVTS_SENSOR_MAX]; 147 u32 hw_tshut_raw_temp; 148 u8 valid_sensor_mask; 149 int mode; 150 void __iomem *base; 151 int low_thresh; 152 int high_thresh; 153 }; 154 155 struct lvts_domain { 156 struct lvts_ctrl *lvts_ctrl; 157 struct reset_control *reset; 158 struct clk *clk; 159 int num_lvts_ctrl; 160 void __iomem *base; 161 size_t calib_len; 162 u8 *calib; 163 #ifdef CONFIG_DEBUG_FS 164 struct dentry *dom_dentry; 165 #endif 166 }; 167 168 #ifdef CONFIG_MTK_LVTS_THERMAL_DEBUGFS 169 170 #define LVTS_DEBUG_FS_REGS(__reg) \ 171 { \ 172 .name = __stringify(__reg), \ 173 .offset = __reg(0), \ 174 } 175 176 static const struct debugfs_reg32 lvts_regs[] = { 177 LVTS_DEBUG_FS_REGS(LVTS_MONCTL0), 178 LVTS_DEBUG_FS_REGS(LVTS_MONCTL1), 179 LVTS_DEBUG_FS_REGS(LVTS_MONCTL2), 180 LVTS_DEBUG_FS_REGS(LVTS_MONINT), 181 LVTS_DEBUG_FS_REGS(LVTS_MONINTSTS), 182 LVTS_DEBUG_FS_REGS(LVTS_MONIDET0), 183 LVTS_DEBUG_FS_REGS(LVTS_MONIDET1), 184 LVTS_DEBUG_FS_REGS(LVTS_MONIDET2), 185 LVTS_DEBUG_FS_REGS(LVTS_MONIDET3), 186 LVTS_DEBUG_FS_REGS(LVTS_H2NTHRE), 187 LVTS_DEBUG_FS_REGS(LVTS_HTHRE), 188 LVTS_DEBUG_FS_REGS(LVTS_OFFSETH), 189 LVTS_DEBUG_FS_REGS(LVTS_OFFSETL), 190 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL0), 191 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL1), 192 LVTS_DEBUG_FS_REGS(LVTS_TSSEL), 193 LVTS_DEBUG_FS_REGS(LVTS_CALSCALE), 194 LVTS_DEBUG_FS_REGS(LVTS_ID), 195 LVTS_DEBUG_FS_REGS(LVTS_CONFIG), 196 LVTS_DEBUG_FS_REGS(LVTS_EDATA00), 197 LVTS_DEBUG_FS_REGS(LVTS_EDATA01), 198 LVTS_DEBUG_FS_REGS(LVTS_EDATA02), 199 LVTS_DEBUG_FS_REGS(LVTS_EDATA03), 200 LVTS_DEBUG_FS_REGS(LVTS_MSR0), 201 LVTS_DEBUG_FS_REGS(LVTS_MSR1), 202 LVTS_DEBUG_FS_REGS(LVTS_MSR2), 203 LVTS_DEBUG_FS_REGS(LVTS_MSR3), 204 LVTS_DEBUG_FS_REGS(LVTS_IMMD0), 205 LVTS_DEBUG_FS_REGS(LVTS_IMMD1), 206 LVTS_DEBUG_FS_REGS(LVTS_IMMD2), 207 LVTS_DEBUG_FS_REGS(LVTS_IMMD3), 208 LVTS_DEBUG_FS_REGS(LVTS_PROTCTL), 209 LVTS_DEBUG_FS_REGS(LVTS_PROTTA), 210 LVTS_DEBUG_FS_REGS(LVTS_PROTTB), 211 LVTS_DEBUG_FS_REGS(LVTS_PROTTC), 212 LVTS_DEBUG_FS_REGS(LVTS_CLKEN), 213 }; 214 215 static int lvts_debugfs_init(struct device *dev, struct lvts_domain *lvts_td) 216 { 217 struct debugfs_regset32 *regset; 218 struct lvts_ctrl *lvts_ctrl; 219 struct dentry *dentry; 220 char name[64]; 221 int i; 222 223 lvts_td->dom_dentry = debugfs_create_dir(dev_name(dev), NULL); 224 if (IS_ERR(lvts_td->dom_dentry)) 225 return 0; 226 227 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 228 229 lvts_ctrl = &lvts_td->lvts_ctrl[i]; 230 231 sprintf(name, "controller%d", i); 232 dentry = debugfs_create_dir(name, lvts_td->dom_dentry); 233 if (IS_ERR(dentry)) 234 continue; 235 236 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 237 if (!regset) 238 continue; 239 240 regset->base = lvts_ctrl->base; 241 regset->regs = lvts_regs; 242 regset->nregs = ARRAY_SIZE(lvts_regs); 243 244 debugfs_create_regset32("registers", 0400, dentry, regset); 245 } 246 247 return 0; 248 } 249 250 static void lvts_debugfs_exit(struct lvts_domain *lvts_td) 251 { 252 debugfs_remove_recursive(lvts_td->dom_dentry); 253 } 254 255 #else 256 257 static inline int lvts_debugfs_init(struct device *dev, 258 struct lvts_domain *lvts_td) 259 { 260 return 0; 261 } 262 263 static void lvts_debugfs_exit(struct lvts_domain *lvts_td) { } 264 265 #endif 266 267 static int lvts_raw_to_temp(u32 raw_temp, int temp_factor) 268 { 269 int temperature; 270 271 temperature = ((s64)(raw_temp & 0xFFFF) * temp_factor) >> 14; 272 temperature += golden_temp_offset; 273 274 return temperature; 275 } 276 277 static u32 lvts_temp_to_raw(int temperature, int temp_factor) 278 { 279 u32 raw_temp = ((s64)(golden_temp_offset - temperature)) << 14; 280 281 raw_temp = div_s64(raw_temp, -temp_factor); 282 283 return raw_temp; 284 } 285 286 static int lvts_get_temp(struct thermal_zone_device *tz, int *temp) 287 { 288 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); 289 struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, 290 sensors[lvts_sensor->id]); 291 const struct lvts_data *lvts_data = lvts_ctrl->lvts_data; 292 void __iomem *msr = lvts_sensor->msr; 293 u32 value; 294 int rc; 295 296 /* 297 * Measurement registers: 298 * 299 * LVTS_MSR[0-3] / LVTS_IMMD[0-3] 300 * 301 * Bits: 302 * 303 * 32-17: Unused 304 * 16 : Valid temperature 305 * 15-0 : Raw temperature 306 */ 307 rc = readl_poll_timeout(msr, value, value & BIT(16), 308 LVTS_MSR_READ_WAIT_US, LVTS_MSR_READ_TIMEOUT_US); 309 310 /* 311 * As the thermal zone temperature will read before the 312 * hardware sensor is fully initialized, we have to check the 313 * validity of the temperature returned when reading the 314 * measurement register. The thermal controller will set the 315 * valid bit temperature only when it is totally initialized. 316 * 317 * Otherwise, we may end up with garbage values out of the 318 * functionning temperature and directly jump to a system 319 * shutdown. 320 */ 321 if (rc) 322 return -EAGAIN; 323 324 *temp = lvts_raw_to_temp(value & 0xFFFF, lvts_data->temp_factor); 325 326 return 0; 327 } 328 329 static void lvts_update_irq_mask(struct lvts_ctrl *lvts_ctrl) 330 { 331 u32 masks[] = { 332 LVTS_MONINT_OFFSET_SENSOR0, 333 LVTS_MONINT_OFFSET_SENSOR1, 334 LVTS_MONINT_OFFSET_SENSOR2, 335 LVTS_MONINT_OFFSET_SENSOR3, 336 }; 337 u32 value = 0; 338 int i; 339 340 value = readl(LVTS_MONINT(lvts_ctrl->base)); 341 342 for (i = 0; i < ARRAY_SIZE(masks); i++) { 343 if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh 344 && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh) 345 value |= masks[i]; 346 else 347 value &= ~masks[i]; 348 } 349 350 writel(value, LVTS_MONINT(lvts_ctrl->base)); 351 } 352 353 static bool lvts_should_update_thresh(struct lvts_ctrl *lvts_ctrl, int high) 354 { 355 int i; 356 357 if (high > lvts_ctrl->high_thresh) 358 return true; 359 360 lvts_for_each_valid_sensor(i, lvts_ctrl) 361 if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh 362 && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh) 363 return false; 364 365 return true; 366 } 367 368 static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high) 369 { 370 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); 371 struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, 372 sensors[lvts_sensor->id]); 373 const struct lvts_data *lvts_data = lvts_ctrl->lvts_data; 374 void __iomem *base = lvts_sensor->base; 375 u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD, 376 lvts_data->temp_factor); 377 u32 raw_high = lvts_temp_to_raw(high, lvts_data->temp_factor); 378 bool should_update_thresh; 379 380 lvts_sensor->low_thresh = low; 381 lvts_sensor->high_thresh = high; 382 383 should_update_thresh = lvts_should_update_thresh(lvts_ctrl, high); 384 if (should_update_thresh) { 385 lvts_ctrl->high_thresh = high; 386 lvts_ctrl->low_thresh = low; 387 } 388 lvts_update_irq_mask(lvts_ctrl); 389 390 if (!should_update_thresh) 391 return 0; 392 393 /* 394 * Low offset temperature threshold 395 * 396 * LVTS_OFFSETL 397 * 398 * Bits: 399 * 400 * 14-0 : Raw temperature for threshold 401 */ 402 pr_debug("%s: Setting low limit temperature interrupt: %d\n", 403 thermal_zone_device_type(tz), low); 404 writel(raw_low, LVTS_OFFSETL(base)); 405 406 /* 407 * High offset temperature threshold 408 * 409 * LVTS_OFFSETH 410 * 411 * Bits: 412 * 413 * 14-0 : Raw temperature for threshold 414 */ 415 pr_debug("%s: Setting high limit temperature interrupt: %d\n", 416 thermal_zone_device_type(tz), high); 417 writel(raw_high, LVTS_OFFSETH(base)); 418 419 return 0; 420 } 421 422 static irqreturn_t lvts_ctrl_irq_handler(struct lvts_ctrl *lvts_ctrl) 423 { 424 irqreturn_t iret = IRQ_NONE; 425 u32 value; 426 u32 masks[] = { 427 LVTS_INT_SENSOR0, 428 LVTS_INT_SENSOR1, 429 LVTS_INT_SENSOR2, 430 LVTS_INT_SENSOR3 431 }; 432 int i; 433 434 /* 435 * Interrupt monitoring status 436 * 437 * LVTS_MONINTST 438 * 439 * Bits: 440 * 441 * 31 : Interrupt for stage 3 442 * 30 : Interrupt for stage 2 443 * 29 : Interrupt for state 1 444 * 28 : Interrupt using filter on sensor 3 445 * 446 * 27 : Interrupt using immediate on sensor 3 447 * 26 : Interrupt normal to hot on sensor 3 448 * 25 : Interrupt high offset on sensor 3 449 * 24 : Interrupt low offset on sensor 3 450 * 451 * 23 : Interrupt hot threshold on sensor 3 452 * 22 : Interrupt cold threshold on sensor 3 453 * 21 : Interrupt using filter on sensor 2 454 * 20 : Interrupt using filter on sensor 1 455 * 456 * 19 : Interrupt using filter on sensor 0 457 * 18 : Interrupt using immediate on sensor 2 458 * 17 : Interrupt using immediate on sensor 1 459 * 16 : Interrupt using immediate on sensor 0 460 * 461 * 15 : Interrupt device access timeout interrupt 462 * 14 : Interrupt normal to hot on sensor 2 463 * 13 : Interrupt high offset interrupt on sensor 2 464 * 12 : Interrupt low offset interrupt on sensor 2 465 * 466 * 11 : Interrupt hot threshold on sensor 2 467 * 10 : Interrupt cold threshold on sensor 2 468 * 9 : Interrupt normal to hot on sensor 1 469 * 8 : Interrupt high offset interrupt on sensor 1 470 * 471 * 7 : Interrupt low offset interrupt on sensor 1 472 * 6 : Interrupt hot threshold on sensor 1 473 * 5 : Interrupt cold threshold on sensor 1 474 * 4 : Interrupt normal to hot on sensor 0 475 * 476 * 3 : Interrupt high offset interrupt on sensor 0 477 * 2 : Interrupt low offset interrupt on sensor 0 478 * 1 : Interrupt hot threshold on sensor 0 479 * 0 : Interrupt cold threshold on sensor 0 480 * 481 * We are interested in the sensor(s) responsible of the 482 * interrupt event. We update the thermal framework with the 483 * thermal zone associated with the sensor. The framework will 484 * take care of the rest whatever the kind of interrupt, we 485 * are only interested in which sensor raised the interrupt. 486 * 487 * sensor 3 interrupt: 0001 1111 1100 0000 0000 0000 0000 0000 488 * => 0x1FC00000 489 * sensor 2 interrupt: 0000 0000 0010 0100 0111 1100 0000 0000 490 * => 0x00247C00 491 * sensor 1 interrupt: 0000 0000 0001 0010 0000 0011 1110 0000 492 * => 0X001203E0 493 * sensor 0 interrupt: 0000 0000 0000 1001 0000 0000 0001 1111 494 * => 0x0009001F 495 */ 496 value = readl(LVTS_MONINTSTS(lvts_ctrl->base)); 497 498 /* 499 * Let's figure out which sensors raised the interrupt 500 * 501 * NOTE: the masks array must be ordered with the index 502 * corresponding to the sensor id eg. index=0, mask for 503 * sensor0. 504 */ 505 for (i = 0; i < ARRAY_SIZE(masks); i++) { 506 507 if (!(value & masks[i])) 508 continue; 509 510 thermal_zone_device_update(lvts_ctrl->sensors[i].tz, 511 THERMAL_TRIP_VIOLATED); 512 iret = IRQ_HANDLED; 513 } 514 515 /* 516 * Write back to clear the interrupt status (W1C) 517 */ 518 writel(value, LVTS_MONINTSTS(lvts_ctrl->base)); 519 520 return iret; 521 } 522 523 /* 524 * Temperature interrupt handler. Even if the driver supports more 525 * interrupt modes, we use the interrupt when the temperature crosses 526 * the hot threshold the way up and the way down (modulo the 527 * hysteresis). 528 * 529 * Each thermal domain has a couple of interrupts, one for hardware 530 * reset and another one for all the thermal events happening on the 531 * different sensors. 532 * 533 * The interrupt is configured for thermal events when crossing the 534 * hot temperature limit. At each interrupt, we check in every 535 * controller if there is an interrupt pending. 536 */ 537 static irqreturn_t lvts_irq_handler(int irq, void *data) 538 { 539 struct lvts_domain *lvts_td = data; 540 irqreturn_t aux, iret = IRQ_NONE; 541 int i; 542 543 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 544 545 aux = lvts_ctrl_irq_handler(&lvts_td->lvts_ctrl[i]); 546 if (aux != IRQ_HANDLED) 547 continue; 548 549 iret = IRQ_HANDLED; 550 } 551 552 return iret; 553 } 554 555 static struct thermal_zone_device_ops lvts_ops = { 556 .get_temp = lvts_get_temp, 557 .set_trips = lvts_set_trips, 558 }; 559 560 static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, 561 const struct lvts_ctrl_data *lvts_ctrl_data) 562 { 563 struct lvts_sensor *lvts_sensor = lvts_ctrl->sensors; 564 565 void __iomem *msr_regs[] = { 566 LVTS_MSR0(lvts_ctrl->base), 567 LVTS_MSR1(lvts_ctrl->base), 568 LVTS_MSR2(lvts_ctrl->base), 569 LVTS_MSR3(lvts_ctrl->base) 570 }; 571 572 void __iomem *imm_regs[] = { 573 LVTS_IMMD0(lvts_ctrl->base), 574 LVTS_IMMD1(lvts_ctrl->base), 575 LVTS_IMMD2(lvts_ctrl->base), 576 LVTS_IMMD3(lvts_ctrl->base) 577 }; 578 579 int i; 580 581 lvts_for_each_valid_sensor(i, lvts_ctrl_data) { 582 583 int dt_id = lvts_ctrl_data->lvts_sensor[i].dt_id; 584 585 /* 586 * At this point, we don't know which id matches which 587 * sensor. Let's set arbitrally the id from the index. 588 */ 589 lvts_sensor[i].id = i; 590 591 /* 592 * The thermal zone registration will set the trip 593 * point interrupt in the thermal controller 594 * register. But this one will be reset in the 595 * initialization after. So we need to post pone the 596 * thermal zone creation after the controller is 597 * setup. For this reason, we store the device tree 598 * node id from the data in the sensor structure 599 */ 600 lvts_sensor[i].dt_id = dt_id; 601 602 /* 603 * We assign the base address of the thermal 604 * controller as a back pointer. So it will be 605 * accessible from the different thermal framework ops 606 * as we pass the lvts_sensor pointer as thermal zone 607 * private data. 608 */ 609 lvts_sensor[i].base = lvts_ctrl->base; 610 611 /* 612 * Each sensor has its own register address to read from. 613 */ 614 lvts_sensor[i].msr = lvts_ctrl_data->mode == LVTS_MSR_IMMEDIATE_MODE ? 615 imm_regs[i] : msr_regs[i]; 616 617 lvts_sensor[i].low_thresh = INT_MIN; 618 lvts_sensor[i].high_thresh = INT_MIN; 619 }; 620 621 lvts_ctrl->valid_sensor_mask = lvts_ctrl_data->valid_sensor_mask; 622 623 return 0; 624 } 625 626 /* 627 * The efuse blob values follows the sensor enumeration per thermal 628 * controller. The decoding of the stream is as follow: 629 * 630 * MT8192 : 631 * Stream index map for MCU Domain mt8192 : 632 * 633 * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> 634 * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 | 0x0A | 0x0B 635 * 636 * <-----sensor#2-----> <-----sensor#3-----> 637 * 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 | 0x13 638 * 639 * <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7-----> 640 * 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 | 0x22 | 0x23 641 * 642 * Stream index map for AP Domain mt8192 : 643 * 644 * <-----sensor#0-----> <-----sensor#1-----> 645 * 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A | 0x2B 646 * 647 * <-----sensor#2-----> <-----sensor#3-----> 648 * 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33 649 * 650 * <-----sensor#4-----> <-----sensor#5-----> 651 * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B 652 * 653 * <-----sensor#6-----> <-----sensor#7-----> <-----sensor#8-----> 654 * 0x3C | 0x3D | 0x3E | 0x3F | 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 655 * 656 * MT8195 : 657 * Stream index map for MCU Domain mt8195 : 658 * 659 * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> 660 * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 661 * 662 * <-----mcu-tc#1-----> <-----sensor#2-----> <-----sensor#3-----> 663 * 0x0A | 0x0B | 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 664 * 665 * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7-----> 666 * 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 667 * 668 * Stream index map for AP Domain mt8195 : 669 * 670 * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1-----> 671 * 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A 672 * 673 * <-----ap--tc#1-----> <-----sensor#2-----> <-----sensor#3-----> 674 * 0x2B | 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33 675 * 676 * <-----ap--tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> 677 * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B | 0x3C | 0x3D | 0x3E | 0x3F 678 * 679 * <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8-----> 680 * 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48 681 * 682 * Note: In some cases, values don't strictly follow a little endian ordering. 683 * The data description gives byte offsets constituting each calibration value 684 * for each sensor. 685 */ 686 static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, 687 const struct lvts_ctrl_data *lvts_ctrl_data, 688 u8 *efuse_calibration, 689 size_t calib_len) 690 { 691 int i; 692 693 lvts_for_each_valid_sensor(i, lvts_ctrl_data) { 694 const struct lvts_sensor_data *sensor = 695 &lvts_ctrl_data->lvts_sensor[i]; 696 697 if (sensor->cal_offsets[0] >= calib_len || 698 sensor->cal_offsets[1] >= calib_len || 699 sensor->cal_offsets[2] >= calib_len) 700 return -EINVAL; 701 702 lvts_ctrl->calibration[i] = 703 (efuse_calibration[sensor->cal_offsets[0]] << 0) + 704 (efuse_calibration[sensor->cal_offsets[1]] << 8) + 705 (efuse_calibration[sensor->cal_offsets[2]] << 16); 706 } 707 708 return 0; 709 } 710 711 /* 712 * The efuse bytes stream can be split into different chunk of 713 * nvmems. This function reads and concatenate those into a single 714 * buffer so it can be read sequentially when initializing the 715 * calibration data. 716 */ 717 static int lvts_calibration_read(struct device *dev, struct lvts_domain *lvts_td, 718 const struct lvts_data *lvts_data) 719 { 720 struct device_node *np = dev_of_node(dev); 721 struct nvmem_cell *cell; 722 struct property *prop; 723 const char *cell_name; 724 725 of_property_for_each_string(np, "nvmem-cell-names", prop, cell_name) { 726 size_t len; 727 u8 *efuse; 728 729 cell = of_nvmem_cell_get(np, cell_name); 730 if (IS_ERR(cell)) { 731 dev_err(dev, "Failed to get cell '%s'\n", cell_name); 732 return PTR_ERR(cell); 733 } 734 735 efuse = nvmem_cell_read(cell, &len); 736 737 nvmem_cell_put(cell); 738 739 if (IS_ERR(efuse)) { 740 dev_err(dev, "Failed to read cell '%s'\n", cell_name); 741 return PTR_ERR(efuse); 742 } 743 744 lvts_td->calib = devm_krealloc(dev, lvts_td->calib, 745 lvts_td->calib_len + len, GFP_KERNEL); 746 if (!lvts_td->calib) { 747 kfree(efuse); 748 return -ENOMEM; 749 } 750 751 memcpy(lvts_td->calib + lvts_td->calib_len, efuse, len); 752 753 lvts_td->calib_len += len; 754 755 kfree(efuse); 756 } 757 758 return 0; 759 } 760 761 static int lvts_golden_temp_init(struct device *dev, u8 *calib, 762 const struct lvts_data *lvts_data) 763 { 764 u32 gt; 765 766 /* 767 * The golden temp information is contained in the first 32-bit 768 * word of efuse data at a specific bit offset. 769 */ 770 gt = (((u32 *)calib)[0] >> lvts_data->gt_calib_bit_offset) & 0xff; 771 772 /* A zero value for gt means that device has invalid efuse data */ 773 if (!gt) 774 return -ENODATA; 775 776 if (gt < LVTS_GOLDEN_TEMP_MAX) 777 golden_temp = gt; 778 779 golden_temp_offset = golden_temp * 500 + lvts_data->temp_offset; 780 781 return 0; 782 } 783 784 static int lvts_ctrl_init(struct device *dev, struct lvts_domain *lvts_td, 785 const struct lvts_data *lvts_data) 786 { 787 size_t size = sizeof(*lvts_td->lvts_ctrl) * lvts_data->num_lvts_ctrl; 788 struct lvts_ctrl *lvts_ctrl; 789 int i, ret; 790 791 /* 792 * Create the calibration bytes stream from efuse data 793 */ 794 ret = lvts_calibration_read(dev, lvts_td, lvts_data); 795 if (ret) 796 return ret; 797 798 ret = lvts_golden_temp_init(dev, lvts_td->calib, lvts_data); 799 if (ret) 800 return ret; 801 802 lvts_ctrl = devm_kzalloc(dev, size, GFP_KERNEL); 803 if (!lvts_ctrl) 804 return -ENOMEM; 805 806 for (i = 0; i < lvts_data->num_lvts_ctrl; i++) { 807 808 lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset; 809 lvts_ctrl[i].lvts_data = lvts_data; 810 811 ret = lvts_sensor_init(dev, &lvts_ctrl[i], 812 &lvts_data->lvts_ctrl[i]); 813 if (ret) 814 return ret; 815 816 ret = lvts_calibration_init(dev, &lvts_ctrl[i], 817 &lvts_data->lvts_ctrl[i], 818 lvts_td->calib, 819 lvts_td->calib_len); 820 if (ret) 821 return ret; 822 823 /* 824 * The mode the ctrl will use to read the temperature 825 * (filtered or immediate) 826 */ 827 lvts_ctrl[i].mode = lvts_data->lvts_ctrl[i].mode; 828 829 /* 830 * The temperature to raw temperature must be done 831 * after initializing the calibration. 832 */ 833 lvts_ctrl[i].hw_tshut_raw_temp = 834 lvts_temp_to_raw(LVTS_HW_TSHUT_TEMP, 835 lvts_data->temp_factor); 836 837 lvts_ctrl[i].low_thresh = INT_MIN; 838 lvts_ctrl[i].high_thresh = INT_MIN; 839 } 840 841 /* 842 * We no longer need the efuse bytes stream, let's free it 843 */ 844 devm_kfree(dev, lvts_td->calib); 845 846 lvts_td->lvts_ctrl = lvts_ctrl; 847 lvts_td->num_lvts_ctrl = lvts_data->num_lvts_ctrl; 848 849 return 0; 850 } 851 852 /* 853 * At this point the configuration register is the only place in the 854 * driver where we write multiple values. Per hardware constraint, 855 * each write in the configuration register must be separated by a 856 * delay of 2 us. 857 */ 858 static void lvts_write_config(struct lvts_ctrl *lvts_ctrl, u32 *cmds, int nr_cmds) 859 { 860 int i; 861 862 /* 863 * Configuration register 864 */ 865 for (i = 0; i < nr_cmds; i++) { 866 writel(cmds[i], LVTS_CONFIG(lvts_ctrl->base)); 867 usleep_range(2, 4); 868 } 869 } 870 871 static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl) 872 { 873 /* 874 * LVTS_PROTCTL : Thermal Protection Sensor Selection 875 * 876 * Bits: 877 * 878 * 19-18 : Sensor to base the protection on 879 * 17-16 : Strategy: 880 * 00 : Average of 4 sensors 881 * 01 : Max of 4 sensors 882 * 10 : Selected sensor with bits 19-18 883 * 11 : Reserved 884 */ 885 writel(BIT(16), LVTS_PROTCTL(lvts_ctrl->base)); 886 887 /* 888 * LVTS_PROTTA : Stage 1 temperature threshold 889 * LVTS_PROTTB : Stage 2 temperature threshold 890 * LVTS_PROTTC : Stage 3 temperature threshold 891 * 892 * Bits: 893 * 894 * 14-0: Raw temperature threshold 895 * 896 * writel(0x0, LVTS_PROTTA(lvts_ctrl->base)); 897 * writel(0x0, LVTS_PROTTB(lvts_ctrl->base)); 898 */ 899 writel(lvts_ctrl->hw_tshut_raw_temp, LVTS_PROTTC(lvts_ctrl->base)); 900 901 /* 902 * LVTS_MONINT : Interrupt configuration register 903 * 904 * The LVTS_MONINT register layout is the same as the LVTS_MONINTSTS 905 * register, except we set the bits to enable the interrupt. 906 */ 907 writel(LVTS_MONINT_CONF, LVTS_MONINT(lvts_ctrl->base)); 908 909 return 0; 910 } 911 912 static int lvts_domain_reset(struct device *dev, struct reset_control *reset) 913 { 914 int ret; 915 916 ret = reset_control_assert(reset); 917 if (ret) 918 return ret; 919 920 return reset_control_deassert(reset); 921 } 922 923 /* 924 * Enable or disable the clocks of a specified thermal controller 925 */ 926 static int lvts_ctrl_set_enable(struct lvts_ctrl *lvts_ctrl, int enable) 927 { 928 /* 929 * LVTS_CLKEN : Internal LVTS clock 930 * 931 * Bits: 932 * 933 * 0 : enable / disable clock 934 */ 935 writel(enable, LVTS_CLKEN(lvts_ctrl->base)); 936 937 return 0; 938 } 939 940 static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl) 941 { 942 u32 id, cmds[] = { 0xC103FFFF, 0xC502FF55 }; 943 944 lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); 945 946 /* 947 * LVTS_ID : Get ID and status of the thermal controller 948 * 949 * Bits: 950 * 951 * 0-5 : thermal controller id 952 * 7 : thermal controller connection is valid 953 */ 954 id = readl(LVTS_ID(lvts_ctrl->base)); 955 if (!(id & BIT(7))) 956 return -EIO; 957 958 return 0; 959 } 960 961 static int lvts_ctrl_initialize(struct device *dev, struct lvts_ctrl *lvts_ctrl) 962 { 963 /* 964 * Write device mask: 0xC1030000 965 */ 966 u32 cmds[] = { 967 0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1, 968 0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300, 969 0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC, 970 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1 971 }; 972 973 lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); 974 975 return 0; 976 } 977 978 static int lvts_ctrl_calibrate(struct device *dev, struct lvts_ctrl *lvts_ctrl) 979 { 980 int i; 981 void __iomem *lvts_edata[] = { 982 LVTS_EDATA00(lvts_ctrl->base), 983 LVTS_EDATA01(lvts_ctrl->base), 984 LVTS_EDATA02(lvts_ctrl->base), 985 LVTS_EDATA03(lvts_ctrl->base) 986 }; 987 988 /* 989 * LVTS_EDATA0X : Efuse calibration reference value for sensor X 990 * 991 * Bits: 992 * 993 * 20-0 : Efuse value for normalization data 994 */ 995 for (i = 0; i < LVTS_SENSOR_MAX; i++) 996 writel(lvts_ctrl->calibration[i], lvts_edata[i]); 997 998 return 0; 999 } 1000 1001 static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_ctrl) 1002 { 1003 u32 value; 1004 1005 /* 1006 * LVTS_TSSEL : Sensing point index numbering 1007 * 1008 * Bits: 1009 * 1010 * 31-24: ADC Sense 3 1011 * 23-16: ADC Sense 2 1012 * 15-8 : ADC Sense 1 1013 * 7-0 : ADC Sense 0 1014 */ 1015 value = LVTS_TSSEL_CONF; 1016 writel(value, LVTS_TSSEL(lvts_ctrl->base)); 1017 1018 /* 1019 * LVTS_CALSCALE : ADC voltage round 1020 */ 1021 value = 0x300; 1022 value = LVTS_CALSCALE_CONF; 1023 1024 /* 1025 * LVTS_MSRCTL0 : Sensor filtering strategy 1026 * 1027 * Filters: 1028 * 1029 * 000 : One sample 1030 * 001 : Avg 2 samples 1031 * 010 : 4 samples, drop min and max, avg 2 samples 1032 * 011 : 6 samples, drop min and max, avg 4 samples 1033 * 100 : 10 samples, drop min and max, avg 8 samples 1034 * 101 : 18 samples, drop min and max, avg 16 samples 1035 * 1036 * Bits: 1037 * 1038 * 0-2 : Sensor0 filter 1039 * 3-5 : Sensor1 filter 1040 * 6-8 : Sensor2 filter 1041 * 9-11 : Sensor3 filter 1042 */ 1043 value = LVTS_HW_FILTER << 9 | LVTS_HW_FILTER << 6 | 1044 LVTS_HW_FILTER << 3 | LVTS_HW_FILTER; 1045 writel(value, LVTS_MSRCTL0(lvts_ctrl->base)); 1046 1047 /* 1048 * LVTS_MONCTL1 : Period unit and group interval configuration 1049 * 1050 * The clock source of LVTS thermal controller is 26MHz. 1051 * 1052 * The period unit is a time base for all the interval delays 1053 * specified in the registers. By default we use 12. The time 1054 * conversion is done by multiplying by 256 and 1/26.10^6 1055 * 1056 * An interval delay multiplied by the period unit gives the 1057 * duration in seconds. 1058 * 1059 * - Filter interval delay is a delay between two samples of 1060 * the same sensor. 1061 * 1062 * - Sensor interval delay is a delay between two samples of 1063 * different sensors. 1064 * 1065 * - Group interval delay is a delay between different rounds. 1066 * 1067 * For example: 1068 * If Period unit = C, filter delay = 1, sensor delay = 2, group delay = 1, 1069 * and two sensors, TS1 and TS2, are in a LVTS thermal controller 1070 * and then 1071 * Period unit time = C * 1/26M * 256 = 12 * 38.46ns * 256 = 118.149us 1072 * Filter interval delay = 1 * Period unit = 118.149us 1073 * Sensor interval delay = 2 * Period unit = 236.298us 1074 * Group interval delay = 1 * Period unit = 118.149us 1075 * 1076 * TS1 TS1 ... TS1 TS2 TS2 ... TS2 TS1... 1077 * <--> Filter interval delay 1078 * <--> Sensor interval delay 1079 * <--> Group interval delay 1080 * Bits: 1081 * 29 - 20 : Group interval 1082 * 16 - 13 : Send a single interrupt when crossing the hot threshold (1) 1083 * or an interrupt everytime the hot threshold is crossed (0) 1084 * 9 - 0 : Period unit 1085 * 1086 */ 1087 value = LVTS_GROUP_INTERVAL << 20 | LVTS_PERIOD_UNIT; 1088 writel(value, LVTS_MONCTL1(lvts_ctrl->base)); 1089 1090 /* 1091 * LVTS_MONCTL2 : Filtering and sensor interval 1092 * 1093 * Bits: 1094 * 1095 * 25-16 : Interval unit in PERIOD_UNIT between sample on 1096 * the same sensor, filter interval 1097 * 9-0 : Interval unit in PERIOD_UNIT between each sensor 1098 * 1099 */ 1100 value = LVTS_FILTER_INTERVAL << 16 | LVTS_SENSOR_INTERVAL; 1101 writel(value, LVTS_MONCTL2(lvts_ctrl->base)); 1102 1103 return lvts_irq_init(lvts_ctrl); 1104 } 1105 1106 static int lvts_ctrl_start(struct device *dev, struct lvts_ctrl *lvts_ctrl) 1107 { 1108 struct lvts_sensor *lvts_sensors = lvts_ctrl->sensors; 1109 struct thermal_zone_device *tz; 1110 u32 sensor_map = 0; 1111 int i; 1112 /* 1113 * Bitmaps to enable each sensor on immediate and filtered modes, as 1114 * described in MSRCTL1 and MONCTL0 registers below, respectively. 1115 */ 1116 u32 sensor_imm_bitmap[] = { BIT(4), BIT(5), BIT(6), BIT(9) }; 1117 u32 sensor_filt_bitmap[] = { BIT(0), BIT(1), BIT(2), BIT(3) }; 1118 1119 u32 *sensor_bitmap = lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE ? 1120 sensor_imm_bitmap : sensor_filt_bitmap; 1121 1122 lvts_for_each_valid_sensor(i, lvts_ctrl) { 1123 1124 int dt_id = lvts_sensors[i].dt_id; 1125 1126 tz = devm_thermal_of_zone_register(dev, dt_id, &lvts_sensors[i], 1127 &lvts_ops); 1128 if (IS_ERR(tz)) { 1129 /* 1130 * This thermal zone is not described in the 1131 * device tree. It is not an error from the 1132 * thermal OF code POV, we just continue. 1133 */ 1134 if (PTR_ERR(tz) == -ENODEV) 1135 continue; 1136 1137 return PTR_ERR(tz); 1138 } 1139 1140 devm_thermal_add_hwmon_sysfs(dev, tz); 1141 1142 /* 1143 * The thermal zone pointer will be needed in the 1144 * interrupt handler, we store it in the sensor 1145 * structure. The thermal domain structure will be 1146 * passed to the interrupt handler private data as the 1147 * interrupt is shared for all the controller 1148 * belonging to the thermal domain. 1149 */ 1150 lvts_sensors[i].tz = tz; 1151 1152 /* 1153 * This sensor was correctly associated with a thermal 1154 * zone, let's set the corresponding bit in the sensor 1155 * map, so we can enable the temperature monitoring in 1156 * the hardware thermal controller. 1157 */ 1158 sensor_map |= sensor_bitmap[i]; 1159 } 1160 1161 /* 1162 * The initialization of the thermal zones give us 1163 * which sensor point to enable. If any thermal zone 1164 * was not described in the device tree, it won't be 1165 * enabled here in the sensor map. 1166 */ 1167 if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) { 1168 /* 1169 * LVTS_MSRCTL1 : Measurement control 1170 * 1171 * Bits: 1172 * 1173 * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3 1174 * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2 1175 * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1 1176 * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0 1177 * 1178 * That configuration will ignore the filtering and the delays 1179 * introduced in MONCTL1 and MONCTL2 1180 */ 1181 writel(sensor_map, LVTS_MSRCTL1(lvts_ctrl->base)); 1182 } else { 1183 /* 1184 * Bits: 1185 * 9: Single point access flow 1186 * 0-3: Enable sensing point 0-3 1187 */ 1188 writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base)); 1189 } 1190 1191 return 0; 1192 } 1193 1194 static int lvts_domain_init(struct device *dev, struct lvts_domain *lvts_td, 1195 const struct lvts_data *lvts_data) 1196 { 1197 struct lvts_ctrl *lvts_ctrl; 1198 int i, ret; 1199 1200 ret = lvts_ctrl_init(dev, lvts_td, lvts_data); 1201 if (ret) 1202 return ret; 1203 1204 ret = lvts_domain_reset(dev, lvts_td->reset); 1205 if (ret) { 1206 dev_dbg(dev, "Failed to reset domain"); 1207 return ret; 1208 } 1209 1210 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 1211 1212 lvts_ctrl = &lvts_td->lvts_ctrl[i]; 1213 1214 /* 1215 * Initialization steps: 1216 * 1217 * - Enable the clock 1218 * - Connect to the LVTS 1219 * - Initialize the LVTS 1220 * - Prepare the calibration data 1221 * - Select monitored sensors 1222 * [ Configure sampling ] 1223 * [ Configure the interrupt ] 1224 * - Start measurement 1225 */ 1226 ret = lvts_ctrl_set_enable(lvts_ctrl, true); 1227 if (ret) { 1228 dev_dbg(dev, "Failed to enable LVTS clock"); 1229 return ret; 1230 } 1231 1232 ret = lvts_ctrl_connect(dev, lvts_ctrl); 1233 if (ret) { 1234 dev_dbg(dev, "Failed to connect to LVTS controller"); 1235 return ret; 1236 } 1237 1238 ret = lvts_ctrl_initialize(dev, lvts_ctrl); 1239 if (ret) { 1240 dev_dbg(dev, "Failed to initialize controller"); 1241 return ret; 1242 } 1243 1244 ret = lvts_ctrl_calibrate(dev, lvts_ctrl); 1245 if (ret) { 1246 dev_dbg(dev, "Failed to calibrate controller"); 1247 return ret; 1248 } 1249 1250 ret = lvts_ctrl_configure(dev, lvts_ctrl); 1251 if (ret) { 1252 dev_dbg(dev, "Failed to configure controller"); 1253 return ret; 1254 } 1255 1256 ret = lvts_ctrl_start(dev, lvts_ctrl); 1257 if (ret) { 1258 dev_dbg(dev, "Failed to start controller"); 1259 return ret; 1260 } 1261 } 1262 1263 return lvts_debugfs_init(dev, lvts_td); 1264 } 1265 1266 static int lvts_probe(struct platform_device *pdev) 1267 { 1268 const struct lvts_data *lvts_data; 1269 struct lvts_domain *lvts_td; 1270 struct device *dev = &pdev->dev; 1271 struct resource *res; 1272 int irq, ret; 1273 1274 lvts_td = devm_kzalloc(dev, sizeof(*lvts_td), GFP_KERNEL); 1275 if (!lvts_td) 1276 return -ENOMEM; 1277 1278 lvts_data = of_device_get_match_data(dev); 1279 if (!lvts_data) 1280 return -ENODEV; 1281 1282 lvts_td->clk = devm_clk_get_enabled(dev, NULL); 1283 if (IS_ERR(lvts_td->clk)) 1284 return dev_err_probe(dev, PTR_ERR(lvts_td->clk), "Failed to retrieve clock\n"); 1285 1286 res = platform_get_mem_or_io(pdev, 0); 1287 if (!res) 1288 return dev_err_probe(dev, (-ENXIO), "No IO resource\n"); 1289 1290 lvts_td->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1291 if (IS_ERR(lvts_td->base)) 1292 return dev_err_probe(dev, PTR_ERR(lvts_td->base), "Failed to map io resource\n"); 1293 1294 lvts_td->reset = devm_reset_control_get_by_index(dev, 0); 1295 if (IS_ERR(lvts_td->reset)) 1296 return dev_err_probe(dev, PTR_ERR(lvts_td->reset), "Failed to get reset control\n"); 1297 1298 irq = platform_get_irq(pdev, 0); 1299 if (irq < 0) 1300 return irq; 1301 1302 golden_temp_offset = lvts_data->temp_offset; 1303 1304 ret = lvts_domain_init(dev, lvts_td, lvts_data); 1305 if (ret) 1306 return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n"); 1307 1308 /* 1309 * At this point the LVTS is initialized and enabled. We can 1310 * safely enable the interrupt. 1311 */ 1312 ret = devm_request_threaded_irq(dev, irq, NULL, lvts_irq_handler, 1313 IRQF_ONESHOT, dev_name(dev), lvts_td); 1314 if (ret) 1315 return dev_err_probe(dev, ret, "Failed to request interrupt\n"); 1316 1317 platform_set_drvdata(pdev, lvts_td); 1318 1319 return 0; 1320 } 1321 1322 static void lvts_remove(struct platform_device *pdev) 1323 { 1324 struct lvts_domain *lvts_td; 1325 int i; 1326 1327 lvts_td = platform_get_drvdata(pdev); 1328 1329 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) 1330 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); 1331 1332 lvts_debugfs_exit(lvts_td); 1333 } 1334 1335 static const struct lvts_ctrl_data mt7988_lvts_ap_data_ctrl[] = { 1336 { 1337 .lvts_sensor = { 1338 { .dt_id = MT7988_CPU_0, 1339 .cal_offsets = { 0x00, 0x01, 0x02 } }, 1340 { .dt_id = MT7988_CPU_1, 1341 .cal_offsets = { 0x04, 0x05, 0x06 } }, 1342 { .dt_id = MT7988_ETH2P5G_0, 1343 .cal_offsets = { 0x08, 0x09, 0x0a } }, 1344 { .dt_id = MT7988_ETH2P5G_1, 1345 .cal_offsets = { 0x0c, 0x0d, 0x0e } } 1346 }, 1347 VALID_SENSOR_MAP(1, 1, 1, 1), 1348 .offset = 0x0, 1349 }, 1350 { 1351 .lvts_sensor = { 1352 { .dt_id = MT7988_TOPS_0, 1353 .cal_offsets = { 0x14, 0x15, 0x16 } }, 1354 { .dt_id = MT7988_TOPS_1, 1355 .cal_offsets = { 0x18, 0x19, 0x1a } }, 1356 { .dt_id = MT7988_ETHWARP_0, 1357 .cal_offsets = { 0x1c, 0x1d, 0x1e } }, 1358 { .dt_id = MT7988_ETHWARP_1, 1359 .cal_offsets = { 0x20, 0x21, 0x22 } } 1360 }, 1361 VALID_SENSOR_MAP(1, 1, 1, 1), 1362 .offset = 0x100, 1363 } 1364 }; 1365 1366 static int lvts_suspend(struct device *dev) 1367 { 1368 struct lvts_domain *lvts_td; 1369 int i; 1370 1371 lvts_td = dev_get_drvdata(dev); 1372 1373 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) 1374 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); 1375 1376 clk_disable_unprepare(lvts_td->clk); 1377 1378 return 0; 1379 } 1380 1381 static int lvts_resume(struct device *dev) 1382 { 1383 struct lvts_domain *lvts_td; 1384 int i, ret; 1385 1386 lvts_td = dev_get_drvdata(dev); 1387 1388 ret = clk_prepare_enable(lvts_td->clk); 1389 if (ret) 1390 return ret; 1391 1392 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) 1393 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], true); 1394 1395 return 0; 1396 } 1397 1398 /* 1399 * The MT8186 calibration data is stored as packed 3-byte little-endian 1400 * values using a weird layout that makes sense only when viewed as a 32-bit 1401 * hexadecimal word dump. Let's suppose SxBy where x = sensor number and 1402 * y = byte number where the LSB is y=0. We then have: 1403 * 1404 * [S0B2-S0B1-S0B0-S1B2] [S1B1-S1B0-S2B2-S2B1] [S2B0-S3B2-S3B1-S3B0] 1405 * 1406 * However, when considering a byte stream, those appear as follows: 1407 * 1408 * [S1B2] [S0B0[ [S0B1] [S0B2] [S2B1] [S2B2] [S1B0] [S1B1] [S3B0] [S3B1] [S3B2] [S2B0] 1409 * 1410 * Hence the rather confusing offsets provided below. 1411 */ 1412 static const struct lvts_ctrl_data mt8186_lvts_data_ctrl[] = { 1413 { 1414 .lvts_sensor = { 1415 { .dt_id = MT8186_LITTLE_CPU0, 1416 .cal_offsets = { 5, 6, 7 } }, 1417 { .dt_id = MT8186_LITTLE_CPU1, 1418 .cal_offsets = { 10, 11, 4 } }, 1419 { .dt_id = MT8186_LITTLE_CPU2, 1420 .cal_offsets = { 15, 8, 9 } }, 1421 { .dt_id = MT8186_CAM, 1422 .cal_offsets = { 12, 13, 14 } } 1423 }, 1424 VALID_SENSOR_MAP(1, 1, 1, 1), 1425 .offset = 0x0, 1426 }, 1427 { 1428 .lvts_sensor = { 1429 { .dt_id = MT8186_BIG_CPU0, 1430 .cal_offsets = { 22, 23, 16 } }, 1431 { .dt_id = MT8186_BIG_CPU1, 1432 .cal_offsets = { 27, 20, 21 } } 1433 }, 1434 VALID_SENSOR_MAP(1, 1, 0, 0), 1435 .offset = 0x100, 1436 }, 1437 { 1438 .lvts_sensor = { 1439 { .dt_id = MT8186_NNA, 1440 .cal_offsets = { 29, 30, 31 } }, 1441 { .dt_id = MT8186_ADSP, 1442 .cal_offsets = { 34, 35, 28 } }, 1443 { .dt_id = MT8186_MFG, 1444 .cal_offsets = { 39, 32, 33 } } 1445 }, 1446 VALID_SENSOR_MAP(1, 1, 1, 0), 1447 .offset = 0x200, 1448 } 1449 }; 1450 1451 static const struct lvts_ctrl_data mt8188_lvts_mcu_data_ctrl[] = { 1452 { 1453 .lvts_sensor = { 1454 { .dt_id = MT8188_MCU_LITTLE_CPU0, 1455 .cal_offsets = { 22, 23, 24 } }, 1456 { .dt_id = MT8188_MCU_LITTLE_CPU1, 1457 .cal_offsets = { 25, 26, 27 } }, 1458 { .dt_id = MT8188_MCU_LITTLE_CPU2, 1459 .cal_offsets = { 28, 29, 30 } }, 1460 { .dt_id = MT8188_MCU_LITTLE_CPU3, 1461 .cal_offsets = { 31, 32, 33 } }, 1462 }, 1463 VALID_SENSOR_MAP(1, 1, 1, 1), 1464 .offset = 0x0, 1465 }, 1466 { 1467 .lvts_sensor = { 1468 { .dt_id = MT8188_MCU_BIG_CPU0, 1469 .cal_offsets = { 34, 35, 36 } }, 1470 { .dt_id = MT8188_MCU_BIG_CPU1, 1471 .cal_offsets = { 37, 38, 39 } }, 1472 }, 1473 VALID_SENSOR_MAP(1, 1, 0, 0), 1474 .offset = 0x100, 1475 } 1476 }; 1477 1478 static const struct lvts_ctrl_data mt8188_lvts_ap_data_ctrl[] = { 1479 { 1480 .lvts_sensor = { 1481 1482 { /* unused */ }, 1483 { .dt_id = MT8188_AP_APU, 1484 .cal_offsets = { 40, 41, 42 } }, 1485 }, 1486 VALID_SENSOR_MAP(0, 1, 0, 0), 1487 .offset = 0x0, 1488 }, 1489 { 1490 .lvts_sensor = { 1491 { .dt_id = MT8188_AP_GPU1, 1492 .cal_offsets = { 43, 44, 45 } }, 1493 { .dt_id = MT8188_AP_GPU2, 1494 .cal_offsets = { 46, 47, 48 } }, 1495 { .dt_id = MT8188_AP_SOC1, 1496 .cal_offsets = { 49, 50, 51 } }, 1497 }, 1498 VALID_SENSOR_MAP(1, 1, 1, 0), 1499 .offset = 0x100, 1500 }, 1501 { 1502 .lvts_sensor = { 1503 { .dt_id = MT8188_AP_SOC2, 1504 .cal_offsets = { 52, 53, 54 } }, 1505 { .dt_id = MT8188_AP_SOC3, 1506 .cal_offsets = { 55, 56, 57 } }, 1507 }, 1508 VALID_SENSOR_MAP(1, 1, 0, 0), 1509 .offset = 0x200, 1510 }, 1511 { 1512 .lvts_sensor = { 1513 { .dt_id = MT8188_AP_CAM1, 1514 .cal_offsets = { 58, 59, 60 } }, 1515 { .dt_id = MT8188_AP_CAM2, 1516 .cal_offsets = { 61, 62, 63 } }, 1517 }, 1518 VALID_SENSOR_MAP(1, 1, 0, 0), 1519 .offset = 0x300, 1520 } 1521 }; 1522 1523 static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = { 1524 { 1525 .lvts_sensor = { 1526 { .dt_id = MT8192_MCU_BIG_CPU0, 1527 .cal_offsets = { 0x04, 0x05, 0x06 } }, 1528 { .dt_id = MT8192_MCU_BIG_CPU1, 1529 .cal_offsets = { 0x08, 0x09, 0x0a } } 1530 }, 1531 VALID_SENSOR_MAP(1, 1, 0, 0), 1532 .offset = 0x0, 1533 .mode = LVTS_MSR_FILTERED_MODE, 1534 }, 1535 { 1536 .lvts_sensor = { 1537 { .dt_id = MT8192_MCU_BIG_CPU2, 1538 .cal_offsets = { 0x0c, 0x0d, 0x0e } }, 1539 { .dt_id = MT8192_MCU_BIG_CPU3, 1540 .cal_offsets = { 0x10, 0x11, 0x12 } } 1541 }, 1542 VALID_SENSOR_MAP(1, 1, 0, 0), 1543 .offset = 0x100, 1544 .mode = LVTS_MSR_FILTERED_MODE, 1545 }, 1546 { 1547 .lvts_sensor = { 1548 { .dt_id = MT8192_MCU_LITTLE_CPU0, 1549 .cal_offsets = { 0x14, 0x15, 0x16 } }, 1550 { .dt_id = MT8192_MCU_LITTLE_CPU1, 1551 .cal_offsets = { 0x18, 0x19, 0x1a } }, 1552 { .dt_id = MT8192_MCU_LITTLE_CPU2, 1553 .cal_offsets = { 0x1c, 0x1d, 0x1e } }, 1554 { .dt_id = MT8192_MCU_LITTLE_CPU3, 1555 .cal_offsets = { 0x20, 0x21, 0x22 } } 1556 }, 1557 VALID_SENSOR_MAP(1, 1, 1, 1), 1558 .offset = 0x200, 1559 .mode = LVTS_MSR_FILTERED_MODE, 1560 } 1561 }; 1562 1563 static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = { 1564 { 1565 .lvts_sensor = { 1566 { .dt_id = MT8192_AP_VPU0, 1567 .cal_offsets = { 0x24, 0x25, 0x26 } }, 1568 { .dt_id = MT8192_AP_VPU1, 1569 .cal_offsets = { 0x28, 0x29, 0x2a } } 1570 }, 1571 VALID_SENSOR_MAP(1, 1, 0, 0), 1572 .offset = 0x0, 1573 }, 1574 { 1575 .lvts_sensor = { 1576 { .dt_id = MT8192_AP_GPU0, 1577 .cal_offsets = { 0x2c, 0x2d, 0x2e } }, 1578 { .dt_id = MT8192_AP_GPU1, 1579 .cal_offsets = { 0x30, 0x31, 0x32 } } 1580 }, 1581 VALID_SENSOR_MAP(1, 1, 0, 0), 1582 .offset = 0x100, 1583 }, 1584 { 1585 .lvts_sensor = { 1586 { .dt_id = MT8192_AP_INFRA, 1587 .cal_offsets = { 0x34, 0x35, 0x36 } }, 1588 { .dt_id = MT8192_AP_CAM, 1589 .cal_offsets = { 0x38, 0x39, 0x3a } }, 1590 }, 1591 VALID_SENSOR_MAP(1, 1, 0, 0), 1592 .offset = 0x200, 1593 }, 1594 { 1595 .lvts_sensor = { 1596 { .dt_id = MT8192_AP_MD0, 1597 .cal_offsets = { 0x3c, 0x3d, 0x3e } }, 1598 { .dt_id = MT8192_AP_MD1, 1599 .cal_offsets = { 0x40, 0x41, 0x42 } }, 1600 { .dt_id = MT8192_AP_MD2, 1601 .cal_offsets = { 0x44, 0x45, 0x46 } } 1602 }, 1603 VALID_SENSOR_MAP(1, 1, 1, 0), 1604 .offset = 0x300, 1605 } 1606 }; 1607 1608 static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = { 1609 { 1610 .lvts_sensor = { 1611 { .dt_id = MT8195_MCU_BIG_CPU0, 1612 .cal_offsets = { 0x04, 0x05, 0x06 } }, 1613 { .dt_id = MT8195_MCU_BIG_CPU1, 1614 .cal_offsets = { 0x07, 0x08, 0x09 } } 1615 }, 1616 VALID_SENSOR_MAP(1, 1, 0, 0), 1617 .offset = 0x0, 1618 }, 1619 { 1620 .lvts_sensor = { 1621 { .dt_id = MT8195_MCU_BIG_CPU2, 1622 .cal_offsets = { 0x0d, 0x0e, 0x0f } }, 1623 { .dt_id = MT8195_MCU_BIG_CPU3, 1624 .cal_offsets = { 0x10, 0x11, 0x12 } } 1625 }, 1626 VALID_SENSOR_MAP(1, 1, 0, 0), 1627 .offset = 0x100, 1628 }, 1629 { 1630 .lvts_sensor = { 1631 { .dt_id = MT8195_MCU_LITTLE_CPU0, 1632 .cal_offsets = { 0x16, 0x17, 0x18 } }, 1633 { .dt_id = MT8195_MCU_LITTLE_CPU1, 1634 .cal_offsets = { 0x19, 0x1a, 0x1b } }, 1635 { .dt_id = MT8195_MCU_LITTLE_CPU2, 1636 .cal_offsets = { 0x1c, 0x1d, 0x1e } }, 1637 { .dt_id = MT8195_MCU_LITTLE_CPU3, 1638 .cal_offsets = { 0x1f, 0x20, 0x21 } } 1639 }, 1640 VALID_SENSOR_MAP(1, 1, 1, 1), 1641 .offset = 0x200, 1642 } 1643 }; 1644 1645 static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = { 1646 { 1647 .lvts_sensor = { 1648 { .dt_id = MT8195_AP_VPU0, 1649 .cal_offsets = { 0x25, 0x26, 0x27 } }, 1650 { .dt_id = MT8195_AP_VPU1, 1651 .cal_offsets = { 0x28, 0x29, 0x2a } } 1652 }, 1653 VALID_SENSOR_MAP(1, 1, 0, 0), 1654 .offset = 0x0, 1655 }, 1656 { 1657 .lvts_sensor = { 1658 { .dt_id = MT8195_AP_GPU0, 1659 .cal_offsets = { 0x2e, 0x2f, 0x30 } }, 1660 { .dt_id = MT8195_AP_GPU1, 1661 .cal_offsets = { 0x31, 0x32, 0x33 } } 1662 }, 1663 VALID_SENSOR_MAP(1, 1, 0, 0), 1664 .offset = 0x100, 1665 }, 1666 { 1667 .lvts_sensor = { 1668 { .dt_id = MT8195_AP_VDEC, 1669 .cal_offsets = { 0x37, 0x38, 0x39 } }, 1670 { .dt_id = MT8195_AP_IMG, 1671 .cal_offsets = { 0x3a, 0x3b, 0x3c } }, 1672 { .dt_id = MT8195_AP_INFRA, 1673 .cal_offsets = { 0x3d, 0x3e, 0x3f } } 1674 }, 1675 VALID_SENSOR_MAP(1, 1, 1, 0), 1676 .offset = 0x200, 1677 }, 1678 { 1679 .lvts_sensor = { 1680 { .dt_id = MT8195_AP_CAM0, 1681 .cal_offsets = { 0x43, 0x44, 0x45 } }, 1682 { .dt_id = MT8195_AP_CAM1, 1683 .cal_offsets = { 0x46, 0x47, 0x48 } } 1684 }, 1685 VALID_SENSOR_MAP(1, 1, 0, 0), 1686 .offset = 0x300, 1687 } 1688 }; 1689 1690 static const struct lvts_data mt7988_lvts_ap_data = { 1691 .lvts_ctrl = mt7988_lvts_ap_data_ctrl, 1692 .num_lvts_ctrl = ARRAY_SIZE(mt7988_lvts_ap_data_ctrl), 1693 .temp_factor = LVTS_COEFF_A_MT7988, 1694 .temp_offset = LVTS_COEFF_B_MT7988, 1695 .gt_calib_bit_offset = 24, 1696 }; 1697 1698 static const struct lvts_data mt8186_lvts_data = { 1699 .lvts_ctrl = mt8186_lvts_data_ctrl, 1700 .num_lvts_ctrl = ARRAY_SIZE(mt8186_lvts_data_ctrl), 1701 .temp_factor = LVTS_COEFF_A_MT7988, 1702 .temp_offset = LVTS_COEFF_B_MT7988, 1703 .gt_calib_bit_offset = 24, 1704 }; 1705 1706 static const struct lvts_data mt8188_lvts_mcu_data = { 1707 .lvts_ctrl = mt8188_lvts_mcu_data_ctrl, 1708 .num_lvts_ctrl = ARRAY_SIZE(mt8188_lvts_mcu_data_ctrl), 1709 .temp_factor = LVTS_COEFF_A_MT8195, 1710 .temp_offset = LVTS_COEFF_B_MT8195, 1711 .gt_calib_bit_offset = 20, 1712 }; 1713 1714 static const struct lvts_data mt8188_lvts_ap_data = { 1715 .lvts_ctrl = mt8188_lvts_ap_data_ctrl, 1716 .num_lvts_ctrl = ARRAY_SIZE(mt8188_lvts_ap_data_ctrl), 1717 .temp_factor = LVTS_COEFF_A_MT8195, 1718 .temp_offset = LVTS_COEFF_B_MT8195, 1719 .gt_calib_bit_offset = 20, 1720 }; 1721 1722 static const struct lvts_data mt8192_lvts_mcu_data = { 1723 .lvts_ctrl = mt8192_lvts_mcu_data_ctrl, 1724 .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl), 1725 .temp_factor = LVTS_COEFF_A_MT8195, 1726 .temp_offset = LVTS_COEFF_B_MT8195, 1727 .gt_calib_bit_offset = 24, 1728 }; 1729 1730 static const struct lvts_data mt8192_lvts_ap_data = { 1731 .lvts_ctrl = mt8192_lvts_ap_data_ctrl, 1732 .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_ap_data_ctrl), 1733 .temp_factor = LVTS_COEFF_A_MT8195, 1734 .temp_offset = LVTS_COEFF_B_MT8195, 1735 .gt_calib_bit_offset = 24, 1736 }; 1737 1738 static const struct lvts_data mt8195_lvts_mcu_data = { 1739 .lvts_ctrl = mt8195_lvts_mcu_data_ctrl, 1740 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl), 1741 .temp_factor = LVTS_COEFF_A_MT8195, 1742 .temp_offset = LVTS_COEFF_B_MT8195, 1743 .gt_calib_bit_offset = 24, 1744 }; 1745 1746 static const struct lvts_data mt8195_lvts_ap_data = { 1747 .lvts_ctrl = mt8195_lvts_ap_data_ctrl, 1748 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl), 1749 .temp_factor = LVTS_COEFF_A_MT8195, 1750 .temp_offset = LVTS_COEFF_B_MT8195, 1751 .gt_calib_bit_offset = 24, 1752 }; 1753 1754 static const struct of_device_id lvts_of_match[] = { 1755 { .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data }, 1756 { .compatible = "mediatek,mt8186-lvts", .data = &mt8186_lvts_data }, 1757 { .compatible = "mediatek,mt8188-lvts-mcu", .data = &mt8188_lvts_mcu_data }, 1758 { .compatible = "mediatek,mt8188-lvts-ap", .data = &mt8188_lvts_ap_data }, 1759 { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data }, 1760 { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data }, 1761 { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data }, 1762 { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data }, 1763 {}, 1764 }; 1765 MODULE_DEVICE_TABLE(of, lvts_of_match); 1766 1767 static const struct dev_pm_ops lvts_pm_ops = { 1768 NOIRQ_SYSTEM_SLEEP_PM_OPS(lvts_suspend, lvts_resume) 1769 }; 1770 1771 static struct platform_driver lvts_driver = { 1772 .probe = lvts_probe, 1773 .remove_new = lvts_remove, 1774 .driver = { 1775 .name = "mtk-lvts-thermal", 1776 .of_match_table = lvts_of_match, 1777 .pm = &lvts_pm_ops, 1778 }, 1779 }; 1780 module_platform_driver(lvts_driver); 1781 1782 MODULE_AUTHOR("Balsam CHIHI <bchihi@baylibre.com>"); 1783 MODULE_DESCRIPTION("MediaTek LVTS Thermal Driver"); 1784 MODULE_LICENSE("GPL"); 1785