1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2023 MediaTek Inc. 4 * Author: Balsam CHIHI <bchihi@baylibre.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/clk-provider.h> 9 #include <linux/delay.h> 10 #include <linux/debugfs.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/iopoll.h> 14 #include <linux/kernel.h> 15 #include <linux/nvmem-consumer.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/reset.h> 19 #include <linux/thermal.h> 20 #include <dt-bindings/thermal/mediatek,lvts-thermal.h> 21 22 #include "../thermal_hwmon.h" 23 24 #define LVTS_MONCTL0(__base) (__base + 0x0000) 25 #define LVTS_MONCTL1(__base) (__base + 0x0004) 26 #define LVTS_MONCTL2(__base) (__base + 0x0008) 27 #define LVTS_MONINT(__base) (__base + 0x000C) 28 #define LVTS_MONINTSTS(__base) (__base + 0x0010) 29 #define LVTS_MONIDET0(__base) (__base + 0x0014) 30 #define LVTS_MONIDET1(__base) (__base + 0x0018) 31 #define LVTS_MONIDET2(__base) (__base + 0x001C) 32 #define LVTS_MONIDET3(__base) (__base + 0x0020) 33 #define LVTS_H2NTHRE(__base) (__base + 0x0024) 34 #define LVTS_HTHRE(__base) (__base + 0x0028) 35 #define LVTS_OFFSETH(__base) (__base + 0x0030) 36 #define LVTS_OFFSETL(__base) (__base + 0x0034) 37 #define LVTS_MSRCTL0(__base) (__base + 0x0038) 38 #define LVTS_MSRCTL1(__base) (__base + 0x003C) 39 #define LVTS_TSSEL(__base) (__base + 0x0040) 40 #define LVTS_CALSCALE(__base) (__base + 0x0048) 41 #define LVTS_ID(__base) (__base + 0x004C) 42 #define LVTS_CONFIG(__base) (__base + 0x0050) 43 #define LVTS_EDATA00(__base) (__base + 0x0054) 44 #define LVTS_EDATA01(__base) (__base + 0x0058) 45 #define LVTS_EDATA02(__base) (__base + 0x005C) 46 #define LVTS_EDATA03(__base) (__base + 0x0060) 47 #define LVTS_MSR0(__base) (__base + 0x0090) 48 #define LVTS_MSR1(__base) (__base + 0x0094) 49 #define LVTS_MSR2(__base) (__base + 0x0098) 50 #define LVTS_MSR3(__base) (__base + 0x009C) 51 #define LVTS_IMMD0(__base) (__base + 0x00A0) 52 #define LVTS_IMMD1(__base) (__base + 0x00A4) 53 #define LVTS_IMMD2(__base) (__base + 0x00A8) 54 #define LVTS_IMMD3(__base) (__base + 0x00AC) 55 #define LVTS_PROTCTL(__base) (__base + 0x00C0) 56 #define LVTS_PROTTA(__base) (__base + 0x00C4) 57 #define LVTS_PROTTB(__base) (__base + 0x00C8) 58 #define LVTS_PROTTC(__base) (__base + 0x00CC) 59 #define LVTS_CLKEN(__base) (__base + 0x00E4) 60 61 #define LVTS_PERIOD_UNIT 0 62 #define LVTS_GROUP_INTERVAL 0 63 #define LVTS_FILTER_INTERVAL 0 64 #define LVTS_SENSOR_INTERVAL 0 65 #define LVTS_HW_FILTER 0x0 66 #define LVTS_TSSEL_CONF 0x13121110 67 #define LVTS_CALSCALE_CONF 0x300 68 #define LVTS_MONINT_CONF 0x8300318C 69 70 #define LVTS_MONINT_OFFSET_SENSOR0 0xC 71 #define LVTS_MONINT_OFFSET_SENSOR1 0x180 72 #define LVTS_MONINT_OFFSET_SENSOR2 0x3000 73 #define LVTS_MONINT_OFFSET_SENSOR3 0x3000000 74 75 #define LVTS_INT_SENSOR0 0x0009001F 76 #define LVTS_INT_SENSOR1 0x001203E0 77 #define LVTS_INT_SENSOR2 0x00247C00 78 #define LVTS_INT_SENSOR3 0x1FC00000 79 80 #define LVTS_SENSOR_MAX 4 81 #define LVTS_GOLDEN_TEMP_MAX 62 82 #define LVTS_GOLDEN_TEMP_DEFAULT 50 83 #define LVTS_COEFF_A_MT8195 -250460 84 #define LVTS_COEFF_B_MT8195 250460 85 #define LVTS_COEFF_A_MT7988 -204650 86 #define LVTS_COEFF_B_MT7988 204650 87 88 #define LVTS_MSR_IMMEDIATE_MODE 0 89 #define LVTS_MSR_FILTERED_MODE 1 90 91 #define LVTS_MSR_READ_TIMEOUT_US 400 92 #define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2) 93 94 #define LVTS_HW_SHUTDOWN_MT7988 105000 95 #define LVTS_HW_SHUTDOWN_MT8195 105000 96 97 #define LVTS_MINIMUM_THRESHOLD 20000 98 99 static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT; 100 static int golden_temp_offset; 101 102 struct lvts_sensor_data { 103 int dt_id; 104 }; 105 106 struct lvts_ctrl_data { 107 struct lvts_sensor_data lvts_sensor[LVTS_SENSOR_MAX]; 108 int cal_offset[LVTS_SENSOR_MAX]; 109 int hw_tshut_temp; 110 int num_lvts_sensor; 111 int offset; 112 int mode; 113 }; 114 115 struct lvts_data { 116 const struct lvts_ctrl_data *lvts_ctrl; 117 int num_lvts_ctrl; 118 int temp_factor; 119 int temp_offset; 120 }; 121 122 struct lvts_sensor { 123 struct thermal_zone_device *tz; 124 void __iomem *msr; 125 void __iomem *base; 126 int id; 127 int dt_id; 128 int low_thresh; 129 int high_thresh; 130 }; 131 132 struct lvts_ctrl { 133 struct lvts_sensor sensors[LVTS_SENSOR_MAX]; 134 const struct lvts_data *lvts_data; 135 u32 calibration[LVTS_SENSOR_MAX]; 136 u32 hw_tshut_raw_temp; 137 int num_lvts_sensor; 138 int mode; 139 void __iomem *base; 140 int low_thresh; 141 int high_thresh; 142 }; 143 144 struct lvts_domain { 145 struct lvts_ctrl *lvts_ctrl; 146 struct reset_control *reset; 147 struct clk *clk; 148 int num_lvts_ctrl; 149 void __iomem *base; 150 size_t calib_len; 151 u8 *calib; 152 #ifdef CONFIG_DEBUG_FS 153 struct dentry *dom_dentry; 154 #endif 155 }; 156 157 #ifdef CONFIG_MTK_LVTS_THERMAL_DEBUGFS 158 159 #define LVTS_DEBUG_FS_REGS(__reg) \ 160 { \ 161 .name = __stringify(__reg), \ 162 .offset = __reg(0), \ 163 } 164 165 static const struct debugfs_reg32 lvts_regs[] = { 166 LVTS_DEBUG_FS_REGS(LVTS_MONCTL0), 167 LVTS_DEBUG_FS_REGS(LVTS_MONCTL1), 168 LVTS_DEBUG_FS_REGS(LVTS_MONCTL2), 169 LVTS_DEBUG_FS_REGS(LVTS_MONINT), 170 LVTS_DEBUG_FS_REGS(LVTS_MONINTSTS), 171 LVTS_DEBUG_FS_REGS(LVTS_MONIDET0), 172 LVTS_DEBUG_FS_REGS(LVTS_MONIDET1), 173 LVTS_DEBUG_FS_REGS(LVTS_MONIDET2), 174 LVTS_DEBUG_FS_REGS(LVTS_MONIDET3), 175 LVTS_DEBUG_FS_REGS(LVTS_H2NTHRE), 176 LVTS_DEBUG_FS_REGS(LVTS_HTHRE), 177 LVTS_DEBUG_FS_REGS(LVTS_OFFSETH), 178 LVTS_DEBUG_FS_REGS(LVTS_OFFSETL), 179 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL0), 180 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL1), 181 LVTS_DEBUG_FS_REGS(LVTS_TSSEL), 182 LVTS_DEBUG_FS_REGS(LVTS_CALSCALE), 183 LVTS_DEBUG_FS_REGS(LVTS_ID), 184 LVTS_DEBUG_FS_REGS(LVTS_CONFIG), 185 LVTS_DEBUG_FS_REGS(LVTS_EDATA00), 186 LVTS_DEBUG_FS_REGS(LVTS_EDATA01), 187 LVTS_DEBUG_FS_REGS(LVTS_EDATA02), 188 LVTS_DEBUG_FS_REGS(LVTS_EDATA03), 189 LVTS_DEBUG_FS_REGS(LVTS_MSR0), 190 LVTS_DEBUG_FS_REGS(LVTS_MSR1), 191 LVTS_DEBUG_FS_REGS(LVTS_MSR2), 192 LVTS_DEBUG_FS_REGS(LVTS_MSR3), 193 LVTS_DEBUG_FS_REGS(LVTS_IMMD0), 194 LVTS_DEBUG_FS_REGS(LVTS_IMMD1), 195 LVTS_DEBUG_FS_REGS(LVTS_IMMD2), 196 LVTS_DEBUG_FS_REGS(LVTS_IMMD3), 197 LVTS_DEBUG_FS_REGS(LVTS_PROTCTL), 198 LVTS_DEBUG_FS_REGS(LVTS_PROTTA), 199 LVTS_DEBUG_FS_REGS(LVTS_PROTTB), 200 LVTS_DEBUG_FS_REGS(LVTS_PROTTC), 201 LVTS_DEBUG_FS_REGS(LVTS_CLKEN), 202 }; 203 204 static int lvts_debugfs_init(struct device *dev, struct lvts_domain *lvts_td) 205 { 206 struct debugfs_regset32 *regset; 207 struct lvts_ctrl *lvts_ctrl; 208 struct dentry *dentry; 209 char name[64]; 210 int i; 211 212 lvts_td->dom_dentry = debugfs_create_dir(dev_name(dev), NULL); 213 if (IS_ERR(lvts_td->dom_dentry)) 214 return 0; 215 216 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 217 218 lvts_ctrl = &lvts_td->lvts_ctrl[i]; 219 220 sprintf(name, "controller%d", i); 221 dentry = debugfs_create_dir(name, lvts_td->dom_dentry); 222 if (IS_ERR(dentry)) 223 continue; 224 225 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 226 if (!regset) 227 continue; 228 229 regset->base = lvts_ctrl->base; 230 regset->regs = lvts_regs; 231 regset->nregs = ARRAY_SIZE(lvts_regs); 232 233 debugfs_create_regset32("registers", 0400, dentry, regset); 234 } 235 236 return 0; 237 } 238 239 static void lvts_debugfs_exit(struct lvts_domain *lvts_td) 240 { 241 debugfs_remove_recursive(lvts_td->dom_dentry); 242 } 243 244 #else 245 246 static inline int lvts_debugfs_init(struct device *dev, 247 struct lvts_domain *lvts_td) 248 { 249 return 0; 250 } 251 252 static void lvts_debugfs_exit(struct lvts_domain *lvts_td) { } 253 254 #endif 255 256 static int lvts_raw_to_temp(u32 raw_temp, int temp_factor) 257 { 258 int temperature; 259 260 temperature = ((s64)(raw_temp & 0xFFFF) * temp_factor) >> 14; 261 temperature += golden_temp_offset; 262 263 return temperature; 264 } 265 266 static u32 lvts_temp_to_raw(int temperature, int temp_factor) 267 { 268 u32 raw_temp = ((s64)(golden_temp_offset - temperature)) << 14; 269 270 raw_temp = div_s64(raw_temp, -temp_factor); 271 272 return raw_temp; 273 } 274 275 static int lvts_get_temp(struct thermal_zone_device *tz, int *temp) 276 { 277 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); 278 struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, 279 sensors[lvts_sensor->id]); 280 const struct lvts_data *lvts_data = lvts_ctrl->lvts_data; 281 void __iomem *msr = lvts_sensor->msr; 282 u32 value; 283 int rc; 284 285 /* 286 * Measurement registers: 287 * 288 * LVTS_MSR[0-3] / LVTS_IMMD[0-3] 289 * 290 * Bits: 291 * 292 * 32-17: Unused 293 * 16 : Valid temperature 294 * 15-0 : Raw temperature 295 */ 296 rc = readl_poll_timeout(msr, value, value & BIT(16), 297 LVTS_MSR_READ_WAIT_US, LVTS_MSR_READ_TIMEOUT_US); 298 299 /* 300 * As the thermal zone temperature will read before the 301 * hardware sensor is fully initialized, we have to check the 302 * validity of the temperature returned when reading the 303 * measurement register. The thermal controller will set the 304 * valid bit temperature only when it is totally initialized. 305 * 306 * Otherwise, we may end up with garbage values out of the 307 * functionning temperature and directly jump to a system 308 * shutdown. 309 */ 310 if (rc) 311 return -EAGAIN; 312 313 *temp = lvts_raw_to_temp(value & 0xFFFF, lvts_data->temp_factor); 314 315 return 0; 316 } 317 318 static void lvts_update_irq_mask(struct lvts_ctrl *lvts_ctrl) 319 { 320 u32 masks[] = { 321 LVTS_MONINT_OFFSET_SENSOR0, 322 LVTS_MONINT_OFFSET_SENSOR1, 323 LVTS_MONINT_OFFSET_SENSOR2, 324 LVTS_MONINT_OFFSET_SENSOR3, 325 }; 326 u32 value = 0; 327 int i; 328 329 value = readl(LVTS_MONINT(lvts_ctrl->base)); 330 331 for (i = 0; i < ARRAY_SIZE(masks); i++) { 332 if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh 333 && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh) 334 value |= masks[i]; 335 else 336 value &= ~masks[i]; 337 } 338 339 writel(value, LVTS_MONINT(lvts_ctrl->base)); 340 } 341 342 static bool lvts_should_update_thresh(struct lvts_ctrl *lvts_ctrl, int high) 343 { 344 int i; 345 346 if (high > lvts_ctrl->high_thresh) 347 return true; 348 349 for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) 350 if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh 351 && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh) 352 return false; 353 354 return true; 355 } 356 357 static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high) 358 { 359 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); 360 struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, 361 sensors[lvts_sensor->id]); 362 const struct lvts_data *lvts_data = lvts_ctrl->lvts_data; 363 void __iomem *base = lvts_sensor->base; 364 u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD, 365 lvts_data->temp_factor); 366 u32 raw_high = lvts_temp_to_raw(high, lvts_data->temp_factor); 367 bool should_update_thresh; 368 369 lvts_sensor->low_thresh = low; 370 lvts_sensor->high_thresh = high; 371 372 should_update_thresh = lvts_should_update_thresh(lvts_ctrl, high); 373 if (should_update_thresh) { 374 lvts_ctrl->high_thresh = high; 375 lvts_ctrl->low_thresh = low; 376 } 377 lvts_update_irq_mask(lvts_ctrl); 378 379 if (!should_update_thresh) 380 return 0; 381 382 /* 383 * Low offset temperature threshold 384 * 385 * LVTS_OFFSETL 386 * 387 * Bits: 388 * 389 * 14-0 : Raw temperature for threshold 390 */ 391 pr_debug("%s: Setting low limit temperature interrupt: %d\n", 392 thermal_zone_device_type(tz), low); 393 writel(raw_low, LVTS_OFFSETL(base)); 394 395 /* 396 * High offset temperature threshold 397 * 398 * LVTS_OFFSETH 399 * 400 * Bits: 401 * 402 * 14-0 : Raw temperature for threshold 403 */ 404 pr_debug("%s: Setting high limit temperature interrupt: %d\n", 405 thermal_zone_device_type(tz), high); 406 writel(raw_high, LVTS_OFFSETH(base)); 407 408 return 0; 409 } 410 411 static irqreturn_t lvts_ctrl_irq_handler(struct lvts_ctrl *lvts_ctrl) 412 { 413 irqreturn_t iret = IRQ_NONE; 414 u32 value; 415 u32 masks[] = { 416 LVTS_INT_SENSOR0, 417 LVTS_INT_SENSOR1, 418 LVTS_INT_SENSOR2, 419 LVTS_INT_SENSOR3 420 }; 421 int i; 422 423 /* 424 * Interrupt monitoring status 425 * 426 * LVTS_MONINTST 427 * 428 * Bits: 429 * 430 * 31 : Interrupt for stage 3 431 * 30 : Interrupt for stage 2 432 * 29 : Interrupt for state 1 433 * 28 : Interrupt using filter on sensor 3 434 * 435 * 27 : Interrupt using immediate on sensor 3 436 * 26 : Interrupt normal to hot on sensor 3 437 * 25 : Interrupt high offset on sensor 3 438 * 24 : Interrupt low offset on sensor 3 439 * 440 * 23 : Interrupt hot threshold on sensor 3 441 * 22 : Interrupt cold threshold on sensor 3 442 * 21 : Interrupt using filter on sensor 2 443 * 20 : Interrupt using filter on sensor 1 444 * 445 * 19 : Interrupt using filter on sensor 0 446 * 18 : Interrupt using immediate on sensor 2 447 * 17 : Interrupt using immediate on sensor 1 448 * 16 : Interrupt using immediate on sensor 0 449 * 450 * 15 : Interrupt device access timeout interrupt 451 * 14 : Interrupt normal to hot on sensor 2 452 * 13 : Interrupt high offset interrupt on sensor 2 453 * 12 : Interrupt low offset interrupt on sensor 2 454 * 455 * 11 : Interrupt hot threshold on sensor 2 456 * 10 : Interrupt cold threshold on sensor 2 457 * 9 : Interrupt normal to hot on sensor 1 458 * 8 : Interrupt high offset interrupt on sensor 1 459 * 460 * 7 : Interrupt low offset interrupt on sensor 1 461 * 6 : Interrupt hot threshold on sensor 1 462 * 5 : Interrupt cold threshold on sensor 1 463 * 4 : Interrupt normal to hot on sensor 0 464 * 465 * 3 : Interrupt high offset interrupt on sensor 0 466 * 2 : Interrupt low offset interrupt on sensor 0 467 * 1 : Interrupt hot threshold on sensor 0 468 * 0 : Interrupt cold threshold on sensor 0 469 * 470 * We are interested in the sensor(s) responsible of the 471 * interrupt event. We update the thermal framework with the 472 * thermal zone associated with the sensor. The framework will 473 * take care of the rest whatever the kind of interrupt, we 474 * are only interested in which sensor raised the interrupt. 475 * 476 * sensor 3 interrupt: 0001 1111 1100 0000 0000 0000 0000 0000 477 * => 0x1FC00000 478 * sensor 2 interrupt: 0000 0000 0010 0100 0111 1100 0000 0000 479 * => 0x00247C00 480 * sensor 1 interrupt: 0000 0000 0001 0010 0000 0011 1110 0000 481 * => 0X001203E0 482 * sensor 0 interrupt: 0000 0000 0000 1001 0000 0000 0001 1111 483 * => 0x0009001F 484 */ 485 value = readl(LVTS_MONINTSTS(lvts_ctrl->base)); 486 487 /* 488 * Let's figure out which sensors raised the interrupt 489 * 490 * NOTE: the masks array must be ordered with the index 491 * corresponding to the sensor id eg. index=0, mask for 492 * sensor0. 493 */ 494 for (i = 0; i < ARRAY_SIZE(masks); i++) { 495 496 if (!(value & masks[i])) 497 continue; 498 499 thermal_zone_device_update(lvts_ctrl->sensors[i].tz, 500 THERMAL_TRIP_VIOLATED); 501 iret = IRQ_HANDLED; 502 } 503 504 /* 505 * Write back to clear the interrupt status (W1C) 506 */ 507 writel(value, LVTS_MONINTSTS(lvts_ctrl->base)); 508 509 return iret; 510 } 511 512 /* 513 * Temperature interrupt handler. Even if the driver supports more 514 * interrupt modes, we use the interrupt when the temperature crosses 515 * the hot threshold the way up and the way down (modulo the 516 * hysteresis). 517 * 518 * Each thermal domain has a couple of interrupts, one for hardware 519 * reset and another one for all the thermal events happening on the 520 * different sensors. 521 * 522 * The interrupt is configured for thermal events when crossing the 523 * hot temperature limit. At each interrupt, we check in every 524 * controller if there is an interrupt pending. 525 */ 526 static irqreturn_t lvts_irq_handler(int irq, void *data) 527 { 528 struct lvts_domain *lvts_td = data; 529 irqreturn_t aux, iret = IRQ_NONE; 530 int i; 531 532 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 533 534 aux = lvts_ctrl_irq_handler(&lvts_td->lvts_ctrl[i]); 535 if (aux != IRQ_HANDLED) 536 continue; 537 538 iret = IRQ_HANDLED; 539 } 540 541 return iret; 542 } 543 544 static struct thermal_zone_device_ops lvts_ops = { 545 .get_temp = lvts_get_temp, 546 .set_trips = lvts_set_trips, 547 }; 548 549 static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, 550 const struct lvts_ctrl_data *lvts_ctrl_data) 551 { 552 struct lvts_sensor *lvts_sensor = lvts_ctrl->sensors; 553 void __iomem *msr_regs[] = { 554 LVTS_MSR0(lvts_ctrl->base), 555 LVTS_MSR1(lvts_ctrl->base), 556 LVTS_MSR2(lvts_ctrl->base), 557 LVTS_MSR3(lvts_ctrl->base) 558 }; 559 560 void __iomem *imm_regs[] = { 561 LVTS_IMMD0(lvts_ctrl->base), 562 LVTS_IMMD1(lvts_ctrl->base), 563 LVTS_IMMD2(lvts_ctrl->base), 564 LVTS_IMMD3(lvts_ctrl->base) 565 }; 566 567 int i; 568 569 for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++) { 570 571 int dt_id = lvts_ctrl_data->lvts_sensor[i].dt_id; 572 573 /* 574 * At this point, we don't know which id matches which 575 * sensor. Let's set arbitrally the id from the index. 576 */ 577 lvts_sensor[i].id = i; 578 579 /* 580 * The thermal zone registration will set the trip 581 * point interrupt in the thermal controller 582 * register. But this one will be reset in the 583 * initialization after. So we need to post pone the 584 * thermal zone creation after the controller is 585 * setup. For this reason, we store the device tree 586 * node id from the data in the sensor structure 587 */ 588 lvts_sensor[i].dt_id = dt_id; 589 590 /* 591 * We assign the base address of the thermal 592 * controller as a back pointer. So it will be 593 * accessible from the different thermal framework ops 594 * as we pass the lvts_sensor pointer as thermal zone 595 * private data. 596 */ 597 lvts_sensor[i].base = lvts_ctrl->base; 598 599 /* 600 * Each sensor has its own register address to read from. 601 */ 602 lvts_sensor[i].msr = lvts_ctrl_data->mode == LVTS_MSR_IMMEDIATE_MODE ? 603 imm_regs[i] : msr_regs[i]; 604 605 lvts_sensor[i].low_thresh = INT_MIN; 606 lvts_sensor[i].high_thresh = INT_MIN; 607 }; 608 609 lvts_ctrl->num_lvts_sensor = lvts_ctrl_data->num_lvts_sensor; 610 611 return 0; 612 } 613 614 /* 615 * The efuse blob values follows the sensor enumeration per thermal 616 * controller. The decoding of the stream is as follow: 617 * 618 * stream index map for MCU Domain : 619 * 620 * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> 621 * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 622 * 623 * <-----mcu-tc#1-----> <-----sensor#2-----> <-----sensor#3-----> 624 * 0x0A | 0x0B | 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 625 * 626 * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7-----> 627 * 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 628 * 629 * stream index map for AP Domain : 630 * 631 * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1-----> 632 * 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A 633 * 634 * <-----ap--tc#1-----> <-----sensor#2-----> <-----sensor#3-----> 635 * 0x2B | 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33 636 * 637 * <-----ap--tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> 638 * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B | 0x3C | 0x3D | 0x3E | 0x3F 639 * 640 * <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8-----> 641 * 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48 642 * 643 * The data description gives the offset of the calibration data in 644 * this bytes stream for each sensor. 645 */ 646 static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, 647 const struct lvts_ctrl_data *lvts_ctrl_data, 648 u8 *efuse_calibration) 649 { 650 int i; 651 652 for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++) 653 memcpy(&lvts_ctrl->calibration[i], 654 efuse_calibration + lvts_ctrl_data->cal_offset[i], 2); 655 656 return 0; 657 } 658 659 /* 660 * The efuse bytes stream can be split into different chunk of 661 * nvmems. This function reads and concatenate those into a single 662 * buffer so it can be read sequentially when initializing the 663 * calibration data. 664 */ 665 static int lvts_calibration_read(struct device *dev, struct lvts_domain *lvts_td, 666 const struct lvts_data *lvts_data) 667 { 668 struct device_node *np = dev_of_node(dev); 669 struct nvmem_cell *cell; 670 struct property *prop; 671 const char *cell_name; 672 673 of_property_for_each_string(np, "nvmem-cell-names", prop, cell_name) { 674 size_t len; 675 u8 *efuse; 676 677 cell = of_nvmem_cell_get(np, cell_name); 678 if (IS_ERR(cell)) { 679 dev_err(dev, "Failed to get cell '%s'\n", cell_name); 680 return PTR_ERR(cell); 681 } 682 683 efuse = nvmem_cell_read(cell, &len); 684 685 nvmem_cell_put(cell); 686 687 if (IS_ERR(efuse)) { 688 dev_err(dev, "Failed to read cell '%s'\n", cell_name); 689 return PTR_ERR(efuse); 690 } 691 692 lvts_td->calib = devm_krealloc(dev, lvts_td->calib, 693 lvts_td->calib_len + len, GFP_KERNEL); 694 if (!lvts_td->calib) 695 return -ENOMEM; 696 697 memcpy(lvts_td->calib + lvts_td->calib_len, efuse, len); 698 699 lvts_td->calib_len += len; 700 701 kfree(efuse); 702 } 703 704 return 0; 705 } 706 707 static int lvts_golden_temp_init(struct device *dev, u32 *value, int temp_offset) 708 { 709 u32 gt; 710 711 gt = (*value) >> 24; 712 713 if (gt && gt < LVTS_GOLDEN_TEMP_MAX) 714 golden_temp = gt; 715 716 golden_temp_offset = golden_temp * 500 + temp_offset; 717 718 return 0; 719 } 720 721 static int lvts_ctrl_init(struct device *dev, struct lvts_domain *lvts_td, 722 const struct lvts_data *lvts_data) 723 { 724 size_t size = sizeof(*lvts_td->lvts_ctrl) * lvts_data->num_lvts_ctrl; 725 struct lvts_ctrl *lvts_ctrl; 726 int i, ret; 727 728 /* 729 * Create the calibration bytes stream from efuse data 730 */ 731 ret = lvts_calibration_read(dev, lvts_td, lvts_data); 732 if (ret) 733 return ret; 734 735 /* 736 * The golden temp information is contained in the first chunk 737 * of efuse data. 738 */ 739 ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib, lvts_data->temp_offset); 740 if (ret) 741 return ret; 742 743 lvts_ctrl = devm_kzalloc(dev, size, GFP_KERNEL); 744 if (!lvts_ctrl) 745 return -ENOMEM; 746 747 for (i = 0; i < lvts_data->num_lvts_ctrl; i++) { 748 749 lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset; 750 lvts_ctrl[i].lvts_data = lvts_data; 751 752 ret = lvts_sensor_init(dev, &lvts_ctrl[i], 753 &lvts_data->lvts_ctrl[i]); 754 if (ret) 755 return ret; 756 757 ret = lvts_calibration_init(dev, &lvts_ctrl[i], 758 &lvts_data->lvts_ctrl[i], 759 lvts_td->calib); 760 if (ret) 761 return ret; 762 763 /* 764 * The mode the ctrl will use to read the temperature 765 * (filtered or immediate) 766 */ 767 lvts_ctrl[i].mode = lvts_data->lvts_ctrl[i].mode; 768 769 /* 770 * The temperature to raw temperature must be done 771 * after initializing the calibration. 772 */ 773 lvts_ctrl[i].hw_tshut_raw_temp = 774 lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp, 775 lvts_data->temp_factor); 776 777 lvts_ctrl[i].low_thresh = INT_MIN; 778 lvts_ctrl[i].high_thresh = INT_MIN; 779 } 780 781 /* 782 * We no longer need the efuse bytes stream, let's free it 783 */ 784 devm_kfree(dev, lvts_td->calib); 785 786 lvts_td->lvts_ctrl = lvts_ctrl; 787 lvts_td->num_lvts_ctrl = lvts_data->num_lvts_ctrl; 788 789 return 0; 790 } 791 792 /* 793 * At this point the configuration register is the only place in the 794 * driver where we write multiple values. Per hardware constraint, 795 * each write in the configuration register must be separated by a 796 * delay of 2 us. 797 */ 798 static void lvts_write_config(struct lvts_ctrl *lvts_ctrl, u32 *cmds, int nr_cmds) 799 { 800 int i; 801 802 /* 803 * Configuration register 804 */ 805 for (i = 0; i < nr_cmds; i++) { 806 writel(cmds[i], LVTS_CONFIG(lvts_ctrl->base)); 807 usleep_range(2, 4); 808 } 809 } 810 811 static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl) 812 { 813 /* 814 * LVTS_PROTCTL : Thermal Protection Sensor Selection 815 * 816 * Bits: 817 * 818 * 19-18 : Sensor to base the protection on 819 * 17-16 : Strategy: 820 * 00 : Average of 4 sensors 821 * 01 : Max of 4 sensors 822 * 10 : Selected sensor with bits 19-18 823 * 11 : Reserved 824 */ 825 writel(BIT(16), LVTS_PROTCTL(lvts_ctrl->base)); 826 827 /* 828 * LVTS_PROTTA : Stage 1 temperature threshold 829 * LVTS_PROTTB : Stage 2 temperature threshold 830 * LVTS_PROTTC : Stage 3 temperature threshold 831 * 832 * Bits: 833 * 834 * 14-0: Raw temperature threshold 835 * 836 * writel(0x0, LVTS_PROTTA(lvts_ctrl->base)); 837 * writel(0x0, LVTS_PROTTB(lvts_ctrl->base)); 838 */ 839 writel(lvts_ctrl->hw_tshut_raw_temp, LVTS_PROTTC(lvts_ctrl->base)); 840 841 /* 842 * LVTS_MONINT : Interrupt configuration register 843 * 844 * The LVTS_MONINT register layout is the same as the LVTS_MONINTSTS 845 * register, except we set the bits to enable the interrupt. 846 */ 847 writel(LVTS_MONINT_CONF, LVTS_MONINT(lvts_ctrl->base)); 848 849 return 0; 850 } 851 852 static int lvts_domain_reset(struct device *dev, struct reset_control *reset) 853 { 854 int ret; 855 856 ret = reset_control_assert(reset); 857 if (ret) 858 return ret; 859 860 return reset_control_deassert(reset); 861 } 862 863 /* 864 * Enable or disable the clocks of a specified thermal controller 865 */ 866 static int lvts_ctrl_set_enable(struct lvts_ctrl *lvts_ctrl, int enable) 867 { 868 /* 869 * LVTS_CLKEN : Internal LVTS clock 870 * 871 * Bits: 872 * 873 * 0 : enable / disable clock 874 */ 875 writel(enable, LVTS_CLKEN(lvts_ctrl->base)); 876 877 return 0; 878 } 879 880 static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl) 881 { 882 u32 id, cmds[] = { 0xC103FFFF, 0xC502FF55 }; 883 884 lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); 885 886 /* 887 * LVTS_ID : Get ID and status of the thermal controller 888 * 889 * Bits: 890 * 891 * 0-5 : thermal controller id 892 * 7 : thermal controller connection is valid 893 */ 894 id = readl(LVTS_ID(lvts_ctrl->base)); 895 if (!(id & BIT(7))) 896 return -EIO; 897 898 return 0; 899 } 900 901 static int lvts_ctrl_initialize(struct device *dev, struct lvts_ctrl *lvts_ctrl) 902 { 903 /* 904 * Write device mask: 0xC1030000 905 */ 906 u32 cmds[] = { 907 0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1, 908 0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300, 909 0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC, 910 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1 911 }; 912 913 lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); 914 915 return 0; 916 } 917 918 static int lvts_ctrl_calibrate(struct device *dev, struct lvts_ctrl *lvts_ctrl) 919 { 920 int i; 921 void __iomem *lvts_edata[] = { 922 LVTS_EDATA00(lvts_ctrl->base), 923 LVTS_EDATA01(lvts_ctrl->base), 924 LVTS_EDATA02(lvts_ctrl->base), 925 LVTS_EDATA03(lvts_ctrl->base) 926 }; 927 928 /* 929 * LVTS_EDATA0X : Efuse calibration reference value for sensor X 930 * 931 * Bits: 932 * 933 * 20-0 : Efuse value for normalization data 934 */ 935 for (i = 0; i < LVTS_SENSOR_MAX; i++) 936 writel(lvts_ctrl->calibration[i], lvts_edata[i]); 937 938 return 0; 939 } 940 941 static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_ctrl) 942 { 943 u32 value; 944 945 /* 946 * LVTS_TSSEL : Sensing point index numbering 947 * 948 * Bits: 949 * 950 * 31-24: ADC Sense 3 951 * 23-16: ADC Sense 2 952 * 15-8 : ADC Sense 1 953 * 7-0 : ADC Sense 0 954 */ 955 value = LVTS_TSSEL_CONF; 956 writel(value, LVTS_TSSEL(lvts_ctrl->base)); 957 958 /* 959 * LVTS_CALSCALE : ADC voltage round 960 */ 961 value = 0x300; 962 value = LVTS_CALSCALE_CONF; 963 964 /* 965 * LVTS_MSRCTL0 : Sensor filtering strategy 966 * 967 * Filters: 968 * 969 * 000 : One sample 970 * 001 : Avg 2 samples 971 * 010 : 4 samples, drop min and max, avg 2 samples 972 * 011 : 6 samples, drop min and max, avg 4 samples 973 * 100 : 10 samples, drop min and max, avg 8 samples 974 * 101 : 18 samples, drop min and max, avg 16 samples 975 * 976 * Bits: 977 * 978 * 0-2 : Sensor0 filter 979 * 3-5 : Sensor1 filter 980 * 6-8 : Sensor2 filter 981 * 9-11 : Sensor3 filter 982 */ 983 value = LVTS_HW_FILTER << 9 | LVTS_HW_FILTER << 6 | 984 LVTS_HW_FILTER << 3 | LVTS_HW_FILTER; 985 writel(value, LVTS_MSRCTL0(lvts_ctrl->base)); 986 987 /* 988 * LVTS_MONCTL1 : Period unit and group interval configuration 989 * 990 * The clock source of LVTS thermal controller is 26MHz. 991 * 992 * The period unit is a time base for all the interval delays 993 * specified in the registers. By default we use 12. The time 994 * conversion is done by multiplying by 256 and 1/26.10^6 995 * 996 * An interval delay multiplied by the period unit gives the 997 * duration in seconds. 998 * 999 * - Filter interval delay is a delay between two samples of 1000 * the same sensor. 1001 * 1002 * - Sensor interval delay is a delay between two samples of 1003 * different sensors. 1004 * 1005 * - Group interval delay is a delay between different rounds. 1006 * 1007 * For example: 1008 * If Period unit = C, filter delay = 1, sensor delay = 2, group delay = 1, 1009 * and two sensors, TS1 and TS2, are in a LVTS thermal controller 1010 * and then 1011 * Period unit time = C * 1/26M * 256 = 12 * 38.46ns * 256 = 118.149us 1012 * Filter interval delay = 1 * Period unit = 118.149us 1013 * Sensor interval delay = 2 * Period unit = 236.298us 1014 * Group interval delay = 1 * Period unit = 118.149us 1015 * 1016 * TS1 TS1 ... TS1 TS2 TS2 ... TS2 TS1... 1017 * <--> Filter interval delay 1018 * <--> Sensor interval delay 1019 * <--> Group interval delay 1020 * Bits: 1021 * 29 - 20 : Group interval 1022 * 16 - 13 : Send a single interrupt when crossing the hot threshold (1) 1023 * or an interrupt everytime the hot threshold is crossed (0) 1024 * 9 - 0 : Period unit 1025 * 1026 */ 1027 value = LVTS_GROUP_INTERVAL << 20 | LVTS_PERIOD_UNIT; 1028 writel(value, LVTS_MONCTL1(lvts_ctrl->base)); 1029 1030 /* 1031 * LVTS_MONCTL2 : Filtering and sensor interval 1032 * 1033 * Bits: 1034 * 1035 * 25-16 : Interval unit in PERIOD_UNIT between sample on 1036 * the same sensor, filter interval 1037 * 9-0 : Interval unit in PERIOD_UNIT between each sensor 1038 * 1039 */ 1040 value = LVTS_FILTER_INTERVAL << 16 | LVTS_SENSOR_INTERVAL; 1041 writel(value, LVTS_MONCTL2(lvts_ctrl->base)); 1042 1043 return lvts_irq_init(lvts_ctrl); 1044 } 1045 1046 static int lvts_ctrl_start(struct device *dev, struct lvts_ctrl *lvts_ctrl) 1047 { 1048 struct lvts_sensor *lvts_sensors = lvts_ctrl->sensors; 1049 struct thermal_zone_device *tz; 1050 u32 sensor_map = 0; 1051 int i; 1052 /* 1053 * Bitmaps to enable each sensor on immediate and filtered modes, as 1054 * described in MSRCTL1 and MONCTL0 registers below, respectively. 1055 */ 1056 u32 sensor_imm_bitmap[] = { BIT(4), BIT(5), BIT(6), BIT(9) }; 1057 u32 sensor_filt_bitmap[] = { BIT(0), BIT(1), BIT(2), BIT(3) }; 1058 1059 u32 *sensor_bitmap = lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE ? 1060 sensor_imm_bitmap : sensor_filt_bitmap; 1061 1062 for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) { 1063 1064 int dt_id = lvts_sensors[i].dt_id; 1065 1066 tz = devm_thermal_of_zone_register(dev, dt_id, &lvts_sensors[i], 1067 &lvts_ops); 1068 if (IS_ERR(tz)) { 1069 /* 1070 * This thermal zone is not described in the 1071 * device tree. It is not an error from the 1072 * thermal OF code POV, we just continue. 1073 */ 1074 if (PTR_ERR(tz) == -ENODEV) 1075 continue; 1076 1077 return PTR_ERR(tz); 1078 } 1079 1080 devm_thermal_add_hwmon_sysfs(dev, tz); 1081 1082 /* 1083 * The thermal zone pointer will be needed in the 1084 * interrupt handler, we store it in the sensor 1085 * structure. The thermal domain structure will be 1086 * passed to the interrupt handler private data as the 1087 * interrupt is shared for all the controller 1088 * belonging to the thermal domain. 1089 */ 1090 lvts_sensors[i].tz = tz; 1091 1092 /* 1093 * This sensor was correctly associated with a thermal 1094 * zone, let's set the corresponding bit in the sensor 1095 * map, so we can enable the temperature monitoring in 1096 * the hardware thermal controller. 1097 */ 1098 sensor_map |= sensor_bitmap[i]; 1099 } 1100 1101 /* 1102 * The initialization of the thermal zones give us 1103 * which sensor point to enable. If any thermal zone 1104 * was not described in the device tree, it won't be 1105 * enabled here in the sensor map. 1106 */ 1107 if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) { 1108 /* 1109 * LVTS_MSRCTL1 : Measurement control 1110 * 1111 * Bits: 1112 * 1113 * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3 1114 * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2 1115 * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1 1116 * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0 1117 * 1118 * That configuration will ignore the filtering and the delays 1119 * introduced in MONCTL1 and MONCTL2 1120 */ 1121 writel(sensor_map, LVTS_MSRCTL1(lvts_ctrl->base)); 1122 } else { 1123 /* 1124 * Bits: 1125 * 9: Single point access flow 1126 * 0-3: Enable sensing point 0-3 1127 */ 1128 writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base)); 1129 } 1130 1131 return 0; 1132 } 1133 1134 static int lvts_domain_init(struct device *dev, struct lvts_domain *lvts_td, 1135 const struct lvts_data *lvts_data) 1136 { 1137 struct lvts_ctrl *lvts_ctrl; 1138 int i, ret; 1139 1140 ret = lvts_ctrl_init(dev, lvts_td, lvts_data); 1141 if (ret) 1142 return ret; 1143 1144 ret = lvts_domain_reset(dev, lvts_td->reset); 1145 if (ret) { 1146 dev_dbg(dev, "Failed to reset domain"); 1147 return ret; 1148 } 1149 1150 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 1151 1152 lvts_ctrl = &lvts_td->lvts_ctrl[i]; 1153 1154 /* 1155 * Initialization steps: 1156 * 1157 * - Enable the clock 1158 * - Connect to the LVTS 1159 * - Initialize the LVTS 1160 * - Prepare the calibration data 1161 * - Select monitored sensors 1162 * [ Configure sampling ] 1163 * [ Configure the interrupt ] 1164 * - Start measurement 1165 */ 1166 ret = lvts_ctrl_set_enable(lvts_ctrl, true); 1167 if (ret) { 1168 dev_dbg(dev, "Failed to enable LVTS clock"); 1169 return ret; 1170 } 1171 1172 ret = lvts_ctrl_connect(dev, lvts_ctrl); 1173 if (ret) { 1174 dev_dbg(dev, "Failed to connect to LVTS controller"); 1175 return ret; 1176 } 1177 1178 ret = lvts_ctrl_initialize(dev, lvts_ctrl); 1179 if (ret) { 1180 dev_dbg(dev, "Failed to initialize controller"); 1181 return ret; 1182 } 1183 1184 ret = lvts_ctrl_calibrate(dev, lvts_ctrl); 1185 if (ret) { 1186 dev_dbg(dev, "Failed to calibrate controller"); 1187 return ret; 1188 } 1189 1190 ret = lvts_ctrl_configure(dev, lvts_ctrl); 1191 if (ret) { 1192 dev_dbg(dev, "Failed to configure controller"); 1193 return ret; 1194 } 1195 1196 ret = lvts_ctrl_start(dev, lvts_ctrl); 1197 if (ret) { 1198 dev_dbg(dev, "Failed to start controller"); 1199 return ret; 1200 } 1201 } 1202 1203 return lvts_debugfs_init(dev, lvts_td); 1204 } 1205 1206 static int lvts_probe(struct platform_device *pdev) 1207 { 1208 const struct lvts_data *lvts_data; 1209 struct lvts_domain *lvts_td; 1210 struct device *dev = &pdev->dev; 1211 struct resource *res; 1212 int irq, ret; 1213 1214 lvts_td = devm_kzalloc(dev, sizeof(*lvts_td), GFP_KERNEL); 1215 if (!lvts_td) 1216 return -ENOMEM; 1217 1218 lvts_data = of_device_get_match_data(dev); 1219 1220 lvts_td->clk = devm_clk_get_enabled(dev, NULL); 1221 if (IS_ERR(lvts_td->clk)) 1222 return dev_err_probe(dev, PTR_ERR(lvts_td->clk), "Failed to retrieve clock\n"); 1223 1224 res = platform_get_mem_or_io(pdev, 0); 1225 if (!res) 1226 return dev_err_probe(dev, (-ENXIO), "No IO resource\n"); 1227 1228 lvts_td->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1229 if (IS_ERR(lvts_td->base)) 1230 return dev_err_probe(dev, PTR_ERR(lvts_td->base), "Failed to map io resource\n"); 1231 1232 lvts_td->reset = devm_reset_control_get_by_index(dev, 0); 1233 if (IS_ERR(lvts_td->reset)) 1234 return dev_err_probe(dev, PTR_ERR(lvts_td->reset), "Failed to get reset control\n"); 1235 1236 irq = platform_get_irq(pdev, 0); 1237 if (irq < 0) 1238 return irq; 1239 1240 golden_temp_offset = lvts_data->temp_offset; 1241 1242 ret = lvts_domain_init(dev, lvts_td, lvts_data); 1243 if (ret) 1244 return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n"); 1245 1246 /* 1247 * At this point the LVTS is initialized and enabled. We can 1248 * safely enable the interrupt. 1249 */ 1250 ret = devm_request_threaded_irq(dev, irq, NULL, lvts_irq_handler, 1251 IRQF_ONESHOT, dev_name(dev), lvts_td); 1252 if (ret) 1253 return dev_err_probe(dev, ret, "Failed to request interrupt\n"); 1254 1255 platform_set_drvdata(pdev, lvts_td); 1256 1257 return 0; 1258 } 1259 1260 static void lvts_remove(struct platform_device *pdev) 1261 { 1262 struct lvts_domain *lvts_td; 1263 int i; 1264 1265 lvts_td = platform_get_drvdata(pdev); 1266 1267 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) 1268 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); 1269 1270 lvts_debugfs_exit(lvts_td); 1271 } 1272 1273 static const struct lvts_ctrl_data mt7988_lvts_ap_data_ctrl[] = { 1274 { 1275 .cal_offset = { 0x00, 0x04, 0x08, 0x0c }, 1276 .lvts_sensor = { 1277 { .dt_id = MT7988_CPU_0 }, 1278 { .dt_id = MT7988_CPU_1 }, 1279 { .dt_id = MT7988_ETH2P5G_0 }, 1280 { .dt_id = MT7988_ETH2P5G_1 } 1281 }, 1282 .num_lvts_sensor = 4, 1283 .offset = 0x0, 1284 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT7988, 1285 }, 1286 { 1287 .cal_offset = { 0x14, 0x18, 0x1c, 0x20 }, 1288 .lvts_sensor = { 1289 { .dt_id = MT7988_TOPS_0}, 1290 { .dt_id = MT7988_TOPS_1}, 1291 { .dt_id = MT7988_ETHWARP_0}, 1292 { .dt_id = MT7988_ETHWARP_1} 1293 }, 1294 .num_lvts_sensor = 4, 1295 .offset = 0x100, 1296 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT7988, 1297 } 1298 }; 1299 1300 static int lvts_suspend(struct device *dev) 1301 { 1302 struct lvts_domain *lvts_td; 1303 int i; 1304 1305 lvts_td = dev_get_drvdata(dev); 1306 1307 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) 1308 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); 1309 1310 clk_disable_unprepare(lvts_td->clk); 1311 1312 return 0; 1313 } 1314 1315 static int lvts_resume(struct device *dev) 1316 { 1317 struct lvts_domain *lvts_td; 1318 int i, ret; 1319 1320 lvts_td = dev_get_drvdata(dev); 1321 1322 ret = clk_prepare_enable(lvts_td->clk); 1323 if (ret) 1324 return ret; 1325 1326 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) 1327 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], true); 1328 1329 return 0; 1330 } 1331 1332 static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = { 1333 { 1334 .cal_offset = { 0x04, 0x07 }, 1335 .lvts_sensor = { 1336 { .dt_id = MT8195_MCU_BIG_CPU0 }, 1337 { .dt_id = MT8195_MCU_BIG_CPU1 } 1338 }, 1339 .num_lvts_sensor = 2, 1340 .offset = 0x0, 1341 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1342 }, 1343 { 1344 .cal_offset = { 0x0d, 0x10 }, 1345 .lvts_sensor = { 1346 { .dt_id = MT8195_MCU_BIG_CPU2 }, 1347 { .dt_id = MT8195_MCU_BIG_CPU3 } 1348 }, 1349 .num_lvts_sensor = 2, 1350 .offset = 0x100, 1351 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1352 }, 1353 { 1354 .cal_offset = { 0x16, 0x19, 0x1c, 0x1f }, 1355 .lvts_sensor = { 1356 { .dt_id = MT8195_MCU_LITTLE_CPU0 }, 1357 { .dt_id = MT8195_MCU_LITTLE_CPU1 }, 1358 { .dt_id = MT8195_MCU_LITTLE_CPU2 }, 1359 { .dt_id = MT8195_MCU_LITTLE_CPU3 } 1360 }, 1361 .num_lvts_sensor = 4, 1362 .offset = 0x200, 1363 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1364 } 1365 }; 1366 1367 static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = { 1368 { 1369 .cal_offset = { 0x25, 0x28 }, 1370 .lvts_sensor = { 1371 { .dt_id = MT8195_AP_VPU0 }, 1372 { .dt_id = MT8195_AP_VPU1 } 1373 }, 1374 .num_lvts_sensor = 2, 1375 .offset = 0x0, 1376 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1377 }, 1378 { 1379 .cal_offset = { 0x2e, 0x31 }, 1380 .lvts_sensor = { 1381 { .dt_id = MT8195_AP_GPU0 }, 1382 { .dt_id = MT8195_AP_GPU1 } 1383 }, 1384 .num_lvts_sensor = 2, 1385 .offset = 0x100, 1386 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1387 }, 1388 { 1389 .cal_offset = { 0x37, 0x3a, 0x3d }, 1390 .lvts_sensor = { 1391 { .dt_id = MT8195_AP_VDEC }, 1392 { .dt_id = MT8195_AP_IMG }, 1393 { .dt_id = MT8195_AP_INFRA }, 1394 }, 1395 .num_lvts_sensor = 3, 1396 .offset = 0x200, 1397 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1398 }, 1399 { 1400 .cal_offset = { 0x43, 0x46 }, 1401 .lvts_sensor = { 1402 { .dt_id = MT8195_AP_CAM0 }, 1403 { .dt_id = MT8195_AP_CAM1 } 1404 }, 1405 .num_lvts_sensor = 2, 1406 .offset = 0x300, 1407 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1408 } 1409 }; 1410 1411 static const struct lvts_data mt7988_lvts_ap_data = { 1412 .lvts_ctrl = mt7988_lvts_ap_data_ctrl, 1413 .num_lvts_ctrl = ARRAY_SIZE(mt7988_lvts_ap_data_ctrl), 1414 .temp_factor = LVTS_COEFF_A_MT7988, 1415 .temp_offset = LVTS_COEFF_B_MT7988, 1416 }; 1417 1418 static const struct lvts_data mt8195_lvts_mcu_data = { 1419 .lvts_ctrl = mt8195_lvts_mcu_data_ctrl, 1420 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl), 1421 .temp_factor = LVTS_COEFF_A_MT8195, 1422 .temp_offset = LVTS_COEFF_B_MT8195, 1423 }; 1424 1425 static const struct lvts_data mt8195_lvts_ap_data = { 1426 .lvts_ctrl = mt8195_lvts_ap_data_ctrl, 1427 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl), 1428 .temp_factor = LVTS_COEFF_A_MT8195, 1429 .temp_offset = LVTS_COEFF_B_MT8195, 1430 }; 1431 1432 static const struct of_device_id lvts_of_match[] = { 1433 { .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data }, 1434 { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data }, 1435 { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data }, 1436 {}, 1437 }; 1438 MODULE_DEVICE_TABLE(of, lvts_of_match); 1439 1440 static const struct dev_pm_ops lvts_pm_ops = { 1441 NOIRQ_SYSTEM_SLEEP_PM_OPS(lvts_suspend, lvts_resume) 1442 }; 1443 1444 static struct platform_driver lvts_driver = { 1445 .probe = lvts_probe, 1446 .remove_new = lvts_remove, 1447 .driver = { 1448 .name = "mtk-lvts-thermal", 1449 .of_match_table = lvts_of_match, 1450 .pm = &lvts_pm_ops, 1451 }, 1452 }; 1453 module_platform_driver(lvts_driver); 1454 1455 MODULE_AUTHOR("Balsam CHIHI <bchihi@baylibre.com>"); 1456 MODULE_DESCRIPTION("MediaTek LVTS Thermal Driver"); 1457 MODULE_LICENSE("GPL"); 1458