1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2023 MediaTek Inc. 4 * Author: Balsam CHIHI <bchihi@baylibre.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/clk-provider.h> 9 #include <linux/delay.h> 10 #include <linux/debugfs.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/iopoll.h> 14 #include <linux/kernel.h> 15 #include <linux/nvmem-consumer.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/reset.h> 19 #include <linux/thermal.h> 20 #include <dt-bindings/thermal/mediatek,lvts-thermal.h> 21 22 #include "../thermal_hwmon.h" 23 24 #define LVTS_MONCTL0(__base) (__base + 0x0000) 25 #define LVTS_MONCTL1(__base) (__base + 0x0004) 26 #define LVTS_MONCTL2(__base) (__base + 0x0008) 27 #define LVTS_MONINT(__base) (__base + 0x000C) 28 #define LVTS_MONINTSTS(__base) (__base + 0x0010) 29 #define LVTS_MONIDET0(__base) (__base + 0x0014) 30 #define LVTS_MONIDET1(__base) (__base + 0x0018) 31 #define LVTS_MONIDET2(__base) (__base + 0x001C) 32 #define LVTS_MONIDET3(__base) (__base + 0x0020) 33 #define LVTS_H2NTHRE(__base) (__base + 0x0024) 34 #define LVTS_HTHRE(__base) (__base + 0x0028) 35 #define LVTS_OFFSETH(__base) (__base + 0x0030) 36 #define LVTS_OFFSETL(__base) (__base + 0x0034) 37 #define LVTS_MSRCTL0(__base) (__base + 0x0038) 38 #define LVTS_MSRCTL1(__base) (__base + 0x003C) 39 #define LVTS_TSSEL(__base) (__base + 0x0040) 40 #define LVTS_CALSCALE(__base) (__base + 0x0048) 41 #define LVTS_ID(__base) (__base + 0x004C) 42 #define LVTS_CONFIG(__base) (__base + 0x0050) 43 #define LVTS_EDATA00(__base) (__base + 0x0054) 44 #define LVTS_EDATA01(__base) (__base + 0x0058) 45 #define LVTS_EDATA02(__base) (__base + 0x005C) 46 #define LVTS_EDATA03(__base) (__base + 0x0060) 47 #define LVTS_MSR0(__base) (__base + 0x0090) 48 #define LVTS_MSR1(__base) (__base + 0x0094) 49 #define LVTS_MSR2(__base) (__base + 0x0098) 50 #define LVTS_MSR3(__base) (__base + 0x009C) 51 #define LVTS_IMMD0(__base) (__base + 0x00A0) 52 #define LVTS_IMMD1(__base) (__base + 0x00A4) 53 #define LVTS_IMMD2(__base) (__base + 0x00A8) 54 #define LVTS_IMMD3(__base) (__base + 0x00AC) 55 #define LVTS_PROTCTL(__base) (__base + 0x00C0) 56 #define LVTS_PROTTA(__base) (__base + 0x00C4) 57 #define LVTS_PROTTB(__base) (__base + 0x00C8) 58 #define LVTS_PROTTC(__base) (__base + 0x00CC) 59 #define LVTS_CLKEN(__base) (__base + 0x00E4) 60 61 #define LVTS_PERIOD_UNIT 0 62 #define LVTS_GROUP_INTERVAL 0 63 #define LVTS_FILTER_INTERVAL 0 64 #define LVTS_SENSOR_INTERVAL 0 65 #define LVTS_HW_FILTER 0x0 66 #define LVTS_TSSEL_CONF 0x13121110 67 #define LVTS_CALSCALE_CONF 0x300 68 #define LVTS_MONINT_CONF 0x8300318C 69 70 #define LVTS_MONINT_OFFSET_SENSOR0 0xC 71 #define LVTS_MONINT_OFFSET_SENSOR1 0x180 72 #define LVTS_MONINT_OFFSET_SENSOR2 0x3000 73 #define LVTS_MONINT_OFFSET_SENSOR3 0x3000000 74 75 #define LVTS_INT_SENSOR0 0x0009001F 76 #define LVTS_INT_SENSOR1 0x001203E0 77 #define LVTS_INT_SENSOR2 0x00247C00 78 #define LVTS_INT_SENSOR3 0x1FC00000 79 80 #define LVTS_SENSOR_MAX 4 81 #define LVTS_GOLDEN_TEMP_MAX 62 82 #define LVTS_GOLDEN_TEMP_DEFAULT 50 83 #define LVTS_COEFF_A_MT8195 -250460 84 #define LVTS_COEFF_B_MT8195 250460 85 #define LVTS_COEFF_A_MT7988 -204650 86 #define LVTS_COEFF_B_MT7988 204650 87 88 #define LVTS_MSR_IMMEDIATE_MODE 0 89 #define LVTS_MSR_FILTERED_MODE 1 90 91 #define LVTS_MSR_READ_TIMEOUT_US 400 92 #define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2) 93 94 #define LVTS_HW_TSHUT_TEMP 105000 95 96 #define LVTS_MINIMUM_THRESHOLD 20000 97 98 static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT; 99 static int golden_temp_offset; 100 101 struct lvts_sensor_data { 102 int dt_id; 103 u8 cal_offsets[3]; 104 }; 105 106 struct lvts_ctrl_data { 107 struct lvts_sensor_data lvts_sensor[LVTS_SENSOR_MAX]; 108 int cal_offset[LVTS_SENSOR_MAX]; 109 int num_lvts_sensor; 110 int offset; 111 int mode; 112 }; 113 114 struct lvts_data { 115 const struct lvts_ctrl_data *lvts_ctrl; 116 int num_lvts_ctrl; 117 int temp_factor; 118 int temp_offset; 119 int gt_calib_bit_offset; 120 }; 121 122 struct lvts_sensor { 123 struct thermal_zone_device *tz; 124 void __iomem *msr; 125 void __iomem *base; 126 int id; 127 int dt_id; 128 int low_thresh; 129 int high_thresh; 130 }; 131 132 struct lvts_ctrl { 133 struct lvts_sensor sensors[LVTS_SENSOR_MAX]; 134 const struct lvts_data *lvts_data; 135 u32 calibration[LVTS_SENSOR_MAX]; 136 u32 hw_tshut_raw_temp; 137 int num_lvts_sensor; 138 int mode; 139 void __iomem *base; 140 int low_thresh; 141 int high_thresh; 142 }; 143 144 struct lvts_domain { 145 struct lvts_ctrl *lvts_ctrl; 146 struct reset_control *reset; 147 struct clk *clk; 148 int num_lvts_ctrl; 149 void __iomem *base; 150 size_t calib_len; 151 u8 *calib; 152 #ifdef CONFIG_DEBUG_FS 153 struct dentry *dom_dentry; 154 #endif 155 }; 156 157 #ifdef CONFIG_MTK_LVTS_THERMAL_DEBUGFS 158 159 #define LVTS_DEBUG_FS_REGS(__reg) \ 160 { \ 161 .name = __stringify(__reg), \ 162 .offset = __reg(0), \ 163 } 164 165 static const struct debugfs_reg32 lvts_regs[] = { 166 LVTS_DEBUG_FS_REGS(LVTS_MONCTL0), 167 LVTS_DEBUG_FS_REGS(LVTS_MONCTL1), 168 LVTS_DEBUG_FS_REGS(LVTS_MONCTL2), 169 LVTS_DEBUG_FS_REGS(LVTS_MONINT), 170 LVTS_DEBUG_FS_REGS(LVTS_MONINTSTS), 171 LVTS_DEBUG_FS_REGS(LVTS_MONIDET0), 172 LVTS_DEBUG_FS_REGS(LVTS_MONIDET1), 173 LVTS_DEBUG_FS_REGS(LVTS_MONIDET2), 174 LVTS_DEBUG_FS_REGS(LVTS_MONIDET3), 175 LVTS_DEBUG_FS_REGS(LVTS_H2NTHRE), 176 LVTS_DEBUG_FS_REGS(LVTS_HTHRE), 177 LVTS_DEBUG_FS_REGS(LVTS_OFFSETH), 178 LVTS_DEBUG_FS_REGS(LVTS_OFFSETL), 179 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL0), 180 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL1), 181 LVTS_DEBUG_FS_REGS(LVTS_TSSEL), 182 LVTS_DEBUG_FS_REGS(LVTS_CALSCALE), 183 LVTS_DEBUG_FS_REGS(LVTS_ID), 184 LVTS_DEBUG_FS_REGS(LVTS_CONFIG), 185 LVTS_DEBUG_FS_REGS(LVTS_EDATA00), 186 LVTS_DEBUG_FS_REGS(LVTS_EDATA01), 187 LVTS_DEBUG_FS_REGS(LVTS_EDATA02), 188 LVTS_DEBUG_FS_REGS(LVTS_EDATA03), 189 LVTS_DEBUG_FS_REGS(LVTS_MSR0), 190 LVTS_DEBUG_FS_REGS(LVTS_MSR1), 191 LVTS_DEBUG_FS_REGS(LVTS_MSR2), 192 LVTS_DEBUG_FS_REGS(LVTS_MSR3), 193 LVTS_DEBUG_FS_REGS(LVTS_IMMD0), 194 LVTS_DEBUG_FS_REGS(LVTS_IMMD1), 195 LVTS_DEBUG_FS_REGS(LVTS_IMMD2), 196 LVTS_DEBUG_FS_REGS(LVTS_IMMD3), 197 LVTS_DEBUG_FS_REGS(LVTS_PROTCTL), 198 LVTS_DEBUG_FS_REGS(LVTS_PROTTA), 199 LVTS_DEBUG_FS_REGS(LVTS_PROTTB), 200 LVTS_DEBUG_FS_REGS(LVTS_PROTTC), 201 LVTS_DEBUG_FS_REGS(LVTS_CLKEN), 202 }; 203 204 static int lvts_debugfs_init(struct device *dev, struct lvts_domain *lvts_td) 205 { 206 struct debugfs_regset32 *regset; 207 struct lvts_ctrl *lvts_ctrl; 208 struct dentry *dentry; 209 char name[64]; 210 int i; 211 212 lvts_td->dom_dentry = debugfs_create_dir(dev_name(dev), NULL); 213 if (IS_ERR(lvts_td->dom_dentry)) 214 return 0; 215 216 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 217 218 lvts_ctrl = &lvts_td->lvts_ctrl[i]; 219 220 sprintf(name, "controller%d", i); 221 dentry = debugfs_create_dir(name, lvts_td->dom_dentry); 222 if (IS_ERR(dentry)) 223 continue; 224 225 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 226 if (!regset) 227 continue; 228 229 regset->base = lvts_ctrl->base; 230 regset->regs = lvts_regs; 231 regset->nregs = ARRAY_SIZE(lvts_regs); 232 233 debugfs_create_regset32("registers", 0400, dentry, regset); 234 } 235 236 return 0; 237 } 238 239 static void lvts_debugfs_exit(struct lvts_domain *lvts_td) 240 { 241 debugfs_remove_recursive(lvts_td->dom_dentry); 242 } 243 244 #else 245 246 static inline int lvts_debugfs_init(struct device *dev, 247 struct lvts_domain *lvts_td) 248 { 249 return 0; 250 } 251 252 static void lvts_debugfs_exit(struct lvts_domain *lvts_td) { } 253 254 #endif 255 256 static int lvts_raw_to_temp(u32 raw_temp, int temp_factor) 257 { 258 int temperature; 259 260 temperature = ((s64)(raw_temp & 0xFFFF) * temp_factor) >> 14; 261 temperature += golden_temp_offset; 262 263 return temperature; 264 } 265 266 static u32 lvts_temp_to_raw(int temperature, int temp_factor) 267 { 268 u32 raw_temp = ((s64)(golden_temp_offset - temperature)) << 14; 269 270 raw_temp = div_s64(raw_temp, -temp_factor); 271 272 return raw_temp; 273 } 274 275 static int lvts_get_temp(struct thermal_zone_device *tz, int *temp) 276 { 277 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); 278 struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, 279 sensors[lvts_sensor->id]); 280 const struct lvts_data *lvts_data = lvts_ctrl->lvts_data; 281 void __iomem *msr = lvts_sensor->msr; 282 u32 value; 283 int rc; 284 285 /* 286 * Measurement registers: 287 * 288 * LVTS_MSR[0-3] / LVTS_IMMD[0-3] 289 * 290 * Bits: 291 * 292 * 32-17: Unused 293 * 16 : Valid temperature 294 * 15-0 : Raw temperature 295 */ 296 rc = readl_poll_timeout(msr, value, value & BIT(16), 297 LVTS_MSR_READ_WAIT_US, LVTS_MSR_READ_TIMEOUT_US); 298 299 /* 300 * As the thermal zone temperature will read before the 301 * hardware sensor is fully initialized, we have to check the 302 * validity of the temperature returned when reading the 303 * measurement register. The thermal controller will set the 304 * valid bit temperature only when it is totally initialized. 305 * 306 * Otherwise, we may end up with garbage values out of the 307 * functionning temperature and directly jump to a system 308 * shutdown. 309 */ 310 if (rc) 311 return -EAGAIN; 312 313 *temp = lvts_raw_to_temp(value & 0xFFFF, lvts_data->temp_factor); 314 315 return 0; 316 } 317 318 static void lvts_update_irq_mask(struct lvts_ctrl *lvts_ctrl) 319 { 320 u32 masks[] = { 321 LVTS_MONINT_OFFSET_SENSOR0, 322 LVTS_MONINT_OFFSET_SENSOR1, 323 LVTS_MONINT_OFFSET_SENSOR2, 324 LVTS_MONINT_OFFSET_SENSOR3, 325 }; 326 u32 value = 0; 327 int i; 328 329 value = readl(LVTS_MONINT(lvts_ctrl->base)); 330 331 for (i = 0; i < ARRAY_SIZE(masks); i++) { 332 if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh 333 && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh) 334 value |= masks[i]; 335 else 336 value &= ~masks[i]; 337 } 338 339 writel(value, LVTS_MONINT(lvts_ctrl->base)); 340 } 341 342 static bool lvts_should_update_thresh(struct lvts_ctrl *lvts_ctrl, int high) 343 { 344 int i; 345 346 if (high > lvts_ctrl->high_thresh) 347 return true; 348 349 for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) 350 if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh 351 && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh) 352 return false; 353 354 return true; 355 } 356 357 static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high) 358 { 359 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); 360 struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, 361 sensors[lvts_sensor->id]); 362 const struct lvts_data *lvts_data = lvts_ctrl->lvts_data; 363 void __iomem *base = lvts_sensor->base; 364 u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD, 365 lvts_data->temp_factor); 366 u32 raw_high = lvts_temp_to_raw(high, lvts_data->temp_factor); 367 bool should_update_thresh; 368 369 lvts_sensor->low_thresh = low; 370 lvts_sensor->high_thresh = high; 371 372 should_update_thresh = lvts_should_update_thresh(lvts_ctrl, high); 373 if (should_update_thresh) { 374 lvts_ctrl->high_thresh = high; 375 lvts_ctrl->low_thresh = low; 376 } 377 lvts_update_irq_mask(lvts_ctrl); 378 379 if (!should_update_thresh) 380 return 0; 381 382 /* 383 * Low offset temperature threshold 384 * 385 * LVTS_OFFSETL 386 * 387 * Bits: 388 * 389 * 14-0 : Raw temperature for threshold 390 */ 391 pr_debug("%s: Setting low limit temperature interrupt: %d\n", 392 thermal_zone_device_type(tz), low); 393 writel(raw_low, LVTS_OFFSETL(base)); 394 395 /* 396 * High offset temperature threshold 397 * 398 * LVTS_OFFSETH 399 * 400 * Bits: 401 * 402 * 14-0 : Raw temperature for threshold 403 */ 404 pr_debug("%s: Setting high limit temperature interrupt: %d\n", 405 thermal_zone_device_type(tz), high); 406 writel(raw_high, LVTS_OFFSETH(base)); 407 408 return 0; 409 } 410 411 static irqreturn_t lvts_ctrl_irq_handler(struct lvts_ctrl *lvts_ctrl) 412 { 413 irqreturn_t iret = IRQ_NONE; 414 u32 value; 415 u32 masks[] = { 416 LVTS_INT_SENSOR0, 417 LVTS_INT_SENSOR1, 418 LVTS_INT_SENSOR2, 419 LVTS_INT_SENSOR3 420 }; 421 int i; 422 423 /* 424 * Interrupt monitoring status 425 * 426 * LVTS_MONINTST 427 * 428 * Bits: 429 * 430 * 31 : Interrupt for stage 3 431 * 30 : Interrupt for stage 2 432 * 29 : Interrupt for state 1 433 * 28 : Interrupt using filter on sensor 3 434 * 435 * 27 : Interrupt using immediate on sensor 3 436 * 26 : Interrupt normal to hot on sensor 3 437 * 25 : Interrupt high offset on sensor 3 438 * 24 : Interrupt low offset on sensor 3 439 * 440 * 23 : Interrupt hot threshold on sensor 3 441 * 22 : Interrupt cold threshold on sensor 3 442 * 21 : Interrupt using filter on sensor 2 443 * 20 : Interrupt using filter on sensor 1 444 * 445 * 19 : Interrupt using filter on sensor 0 446 * 18 : Interrupt using immediate on sensor 2 447 * 17 : Interrupt using immediate on sensor 1 448 * 16 : Interrupt using immediate on sensor 0 449 * 450 * 15 : Interrupt device access timeout interrupt 451 * 14 : Interrupt normal to hot on sensor 2 452 * 13 : Interrupt high offset interrupt on sensor 2 453 * 12 : Interrupt low offset interrupt on sensor 2 454 * 455 * 11 : Interrupt hot threshold on sensor 2 456 * 10 : Interrupt cold threshold on sensor 2 457 * 9 : Interrupt normal to hot on sensor 1 458 * 8 : Interrupt high offset interrupt on sensor 1 459 * 460 * 7 : Interrupt low offset interrupt on sensor 1 461 * 6 : Interrupt hot threshold on sensor 1 462 * 5 : Interrupt cold threshold on sensor 1 463 * 4 : Interrupt normal to hot on sensor 0 464 * 465 * 3 : Interrupt high offset interrupt on sensor 0 466 * 2 : Interrupt low offset interrupt on sensor 0 467 * 1 : Interrupt hot threshold on sensor 0 468 * 0 : Interrupt cold threshold on sensor 0 469 * 470 * We are interested in the sensor(s) responsible of the 471 * interrupt event. We update the thermal framework with the 472 * thermal zone associated with the sensor. The framework will 473 * take care of the rest whatever the kind of interrupt, we 474 * are only interested in which sensor raised the interrupt. 475 * 476 * sensor 3 interrupt: 0001 1111 1100 0000 0000 0000 0000 0000 477 * => 0x1FC00000 478 * sensor 2 interrupt: 0000 0000 0010 0100 0111 1100 0000 0000 479 * => 0x00247C00 480 * sensor 1 interrupt: 0000 0000 0001 0010 0000 0011 1110 0000 481 * => 0X001203E0 482 * sensor 0 interrupt: 0000 0000 0000 1001 0000 0000 0001 1111 483 * => 0x0009001F 484 */ 485 value = readl(LVTS_MONINTSTS(lvts_ctrl->base)); 486 487 /* 488 * Let's figure out which sensors raised the interrupt 489 * 490 * NOTE: the masks array must be ordered with the index 491 * corresponding to the sensor id eg. index=0, mask for 492 * sensor0. 493 */ 494 for (i = 0; i < ARRAY_SIZE(masks); i++) { 495 496 if (!(value & masks[i])) 497 continue; 498 499 thermal_zone_device_update(lvts_ctrl->sensors[i].tz, 500 THERMAL_TRIP_VIOLATED); 501 iret = IRQ_HANDLED; 502 } 503 504 /* 505 * Write back to clear the interrupt status (W1C) 506 */ 507 writel(value, LVTS_MONINTSTS(lvts_ctrl->base)); 508 509 return iret; 510 } 511 512 /* 513 * Temperature interrupt handler. Even if the driver supports more 514 * interrupt modes, we use the interrupt when the temperature crosses 515 * the hot threshold the way up and the way down (modulo the 516 * hysteresis). 517 * 518 * Each thermal domain has a couple of interrupts, one for hardware 519 * reset and another one for all the thermal events happening on the 520 * different sensors. 521 * 522 * The interrupt is configured for thermal events when crossing the 523 * hot temperature limit. At each interrupt, we check in every 524 * controller if there is an interrupt pending. 525 */ 526 static irqreturn_t lvts_irq_handler(int irq, void *data) 527 { 528 struct lvts_domain *lvts_td = data; 529 irqreturn_t aux, iret = IRQ_NONE; 530 int i; 531 532 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 533 534 aux = lvts_ctrl_irq_handler(&lvts_td->lvts_ctrl[i]); 535 if (aux != IRQ_HANDLED) 536 continue; 537 538 iret = IRQ_HANDLED; 539 } 540 541 return iret; 542 } 543 544 static struct thermal_zone_device_ops lvts_ops = { 545 .get_temp = lvts_get_temp, 546 .set_trips = lvts_set_trips, 547 }; 548 549 static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, 550 const struct lvts_ctrl_data *lvts_ctrl_data) 551 { 552 struct lvts_sensor *lvts_sensor = lvts_ctrl->sensors; 553 void __iomem *msr_regs[] = { 554 LVTS_MSR0(lvts_ctrl->base), 555 LVTS_MSR1(lvts_ctrl->base), 556 LVTS_MSR2(lvts_ctrl->base), 557 LVTS_MSR3(lvts_ctrl->base) 558 }; 559 560 void __iomem *imm_regs[] = { 561 LVTS_IMMD0(lvts_ctrl->base), 562 LVTS_IMMD1(lvts_ctrl->base), 563 LVTS_IMMD2(lvts_ctrl->base), 564 LVTS_IMMD3(lvts_ctrl->base) 565 }; 566 567 int i; 568 569 for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++) { 570 571 int dt_id = lvts_ctrl_data->lvts_sensor[i].dt_id; 572 573 /* 574 * At this point, we don't know which id matches which 575 * sensor. Let's set arbitrally the id from the index. 576 */ 577 lvts_sensor[i].id = i; 578 579 /* 580 * The thermal zone registration will set the trip 581 * point interrupt in the thermal controller 582 * register. But this one will be reset in the 583 * initialization after. So we need to post pone the 584 * thermal zone creation after the controller is 585 * setup. For this reason, we store the device tree 586 * node id from the data in the sensor structure 587 */ 588 lvts_sensor[i].dt_id = dt_id; 589 590 /* 591 * We assign the base address of the thermal 592 * controller as a back pointer. So it will be 593 * accessible from the different thermal framework ops 594 * as we pass the lvts_sensor pointer as thermal zone 595 * private data. 596 */ 597 lvts_sensor[i].base = lvts_ctrl->base; 598 599 /* 600 * Each sensor has its own register address to read from. 601 */ 602 lvts_sensor[i].msr = lvts_ctrl_data->mode == LVTS_MSR_IMMEDIATE_MODE ? 603 imm_regs[i] : msr_regs[i]; 604 605 lvts_sensor[i].low_thresh = INT_MIN; 606 lvts_sensor[i].high_thresh = INT_MIN; 607 }; 608 609 lvts_ctrl->num_lvts_sensor = lvts_ctrl_data->num_lvts_sensor; 610 611 return 0; 612 } 613 614 /* 615 * The efuse blob values follows the sensor enumeration per thermal 616 * controller. The decoding of the stream is as follow: 617 * 618 * MT8192 : 619 * Stream index map for MCU Domain mt8192 : 620 * 621 * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> 622 * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 | 0x0A | 0x0B 623 * 624 * <-----sensor#2-----> <-----sensor#3-----> 625 * 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 | 0x13 626 * 627 * <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7-----> 628 * 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 | 0x22 | 0x23 629 * 630 * Stream index map for AP Domain mt8192 : 631 * 632 * <-----sensor#0-----> <-----sensor#1-----> 633 * 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A | 0x2B 634 * 635 * <-----sensor#2-----> <-----sensor#3-----> 636 * 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33 637 * 638 * <-----sensor#4-----> <-----sensor#5-----> 639 * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B 640 * 641 * <-----sensor#6-----> <-----sensor#7-----> <-----sensor#8-----> 642 * 0x3C | 0x3D | 0x3E | 0x3F | 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 643 * 644 * MT8195 : 645 * Stream index map for MCU Domain mt8195 : 646 * 647 * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> 648 * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 649 * 650 * <-----mcu-tc#1-----> <-----sensor#2-----> <-----sensor#3-----> 651 * 0x0A | 0x0B | 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 652 * 653 * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7-----> 654 * 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 655 * 656 * Stream index map for AP Domain mt8195 : 657 * 658 * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1-----> 659 * 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A 660 * 661 * <-----ap--tc#1-----> <-----sensor#2-----> <-----sensor#3-----> 662 * 0x2B | 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33 663 * 664 * <-----ap--tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> 665 * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B | 0x3C | 0x3D | 0x3E | 0x3F 666 * 667 * <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8-----> 668 * 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48 669 * 670 * Note: In some cases, values don't strictly follow a little endian ordering. 671 * The data description gives byte offsets constituting each calibration value 672 * for each sensor. 673 */ 674 static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, 675 const struct lvts_ctrl_data *lvts_ctrl_data, 676 u8 *efuse_calibration, 677 size_t calib_len) 678 { 679 int i; 680 681 for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++) { 682 const struct lvts_sensor_data *sensor = 683 &lvts_ctrl_data->lvts_sensor[i]; 684 685 if (sensor->cal_offsets[0] >= calib_len || 686 sensor->cal_offsets[1] >= calib_len || 687 sensor->cal_offsets[2] >= calib_len) 688 return -EINVAL; 689 690 lvts_ctrl->calibration[i] = 691 (efuse_calibration[sensor->cal_offsets[0]] << 0) + 692 (efuse_calibration[sensor->cal_offsets[1]] << 8) + 693 (efuse_calibration[sensor->cal_offsets[2]] << 16); 694 } 695 696 return 0; 697 } 698 699 /* 700 * The efuse bytes stream can be split into different chunk of 701 * nvmems. This function reads and concatenate those into a single 702 * buffer so it can be read sequentially when initializing the 703 * calibration data. 704 */ 705 static int lvts_calibration_read(struct device *dev, struct lvts_domain *lvts_td, 706 const struct lvts_data *lvts_data) 707 { 708 struct device_node *np = dev_of_node(dev); 709 struct nvmem_cell *cell; 710 struct property *prop; 711 const char *cell_name; 712 713 of_property_for_each_string(np, "nvmem-cell-names", prop, cell_name) { 714 size_t len; 715 u8 *efuse; 716 717 cell = of_nvmem_cell_get(np, cell_name); 718 if (IS_ERR(cell)) { 719 dev_err(dev, "Failed to get cell '%s'\n", cell_name); 720 return PTR_ERR(cell); 721 } 722 723 efuse = nvmem_cell_read(cell, &len); 724 725 nvmem_cell_put(cell); 726 727 if (IS_ERR(efuse)) { 728 dev_err(dev, "Failed to read cell '%s'\n", cell_name); 729 return PTR_ERR(efuse); 730 } 731 732 lvts_td->calib = devm_krealloc(dev, lvts_td->calib, 733 lvts_td->calib_len + len, GFP_KERNEL); 734 if (!lvts_td->calib) { 735 kfree(efuse); 736 return -ENOMEM; 737 } 738 739 memcpy(lvts_td->calib + lvts_td->calib_len, efuse, len); 740 741 lvts_td->calib_len += len; 742 743 kfree(efuse); 744 } 745 746 return 0; 747 } 748 749 static int lvts_golden_temp_init(struct device *dev, u8 *calib, 750 const struct lvts_data *lvts_data) 751 { 752 u32 gt; 753 754 /* 755 * The golden temp information is contained in the first 32-bit 756 * word of efuse data at a specific bit offset. 757 */ 758 gt = (((u32 *)calib)[0] >> lvts_data->gt_calib_bit_offset) & 0xff; 759 760 if (gt && gt < LVTS_GOLDEN_TEMP_MAX) 761 golden_temp = gt; 762 763 golden_temp_offset = golden_temp * 500 + lvts_data->temp_offset; 764 765 return 0; 766 } 767 768 static int lvts_ctrl_init(struct device *dev, struct lvts_domain *lvts_td, 769 const struct lvts_data *lvts_data) 770 { 771 size_t size = sizeof(*lvts_td->lvts_ctrl) * lvts_data->num_lvts_ctrl; 772 struct lvts_ctrl *lvts_ctrl; 773 int i, ret; 774 775 /* 776 * Create the calibration bytes stream from efuse data 777 */ 778 ret = lvts_calibration_read(dev, lvts_td, lvts_data); 779 if (ret) 780 return ret; 781 782 ret = lvts_golden_temp_init(dev, lvts_td->calib, lvts_data); 783 if (ret) 784 return ret; 785 786 lvts_ctrl = devm_kzalloc(dev, size, GFP_KERNEL); 787 if (!lvts_ctrl) 788 return -ENOMEM; 789 790 for (i = 0; i < lvts_data->num_lvts_ctrl; i++) { 791 792 lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset; 793 lvts_ctrl[i].lvts_data = lvts_data; 794 795 ret = lvts_sensor_init(dev, &lvts_ctrl[i], 796 &lvts_data->lvts_ctrl[i]); 797 if (ret) 798 return ret; 799 800 ret = lvts_calibration_init(dev, &lvts_ctrl[i], 801 &lvts_data->lvts_ctrl[i], 802 lvts_td->calib, 803 lvts_td->calib_len); 804 if (ret) 805 return ret; 806 807 /* 808 * The mode the ctrl will use to read the temperature 809 * (filtered or immediate) 810 */ 811 lvts_ctrl[i].mode = lvts_data->lvts_ctrl[i].mode; 812 813 /* 814 * The temperature to raw temperature must be done 815 * after initializing the calibration. 816 */ 817 lvts_ctrl[i].hw_tshut_raw_temp = 818 lvts_temp_to_raw(LVTS_HW_TSHUT_TEMP, 819 lvts_data->temp_factor); 820 821 lvts_ctrl[i].low_thresh = INT_MIN; 822 lvts_ctrl[i].high_thresh = INT_MIN; 823 } 824 825 /* 826 * We no longer need the efuse bytes stream, let's free it 827 */ 828 devm_kfree(dev, lvts_td->calib); 829 830 lvts_td->lvts_ctrl = lvts_ctrl; 831 lvts_td->num_lvts_ctrl = lvts_data->num_lvts_ctrl; 832 833 return 0; 834 } 835 836 /* 837 * At this point the configuration register is the only place in the 838 * driver where we write multiple values. Per hardware constraint, 839 * each write in the configuration register must be separated by a 840 * delay of 2 us. 841 */ 842 static void lvts_write_config(struct lvts_ctrl *lvts_ctrl, u32 *cmds, int nr_cmds) 843 { 844 int i; 845 846 /* 847 * Configuration register 848 */ 849 for (i = 0; i < nr_cmds; i++) { 850 writel(cmds[i], LVTS_CONFIG(lvts_ctrl->base)); 851 usleep_range(2, 4); 852 } 853 } 854 855 static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl) 856 { 857 /* 858 * LVTS_PROTCTL : Thermal Protection Sensor Selection 859 * 860 * Bits: 861 * 862 * 19-18 : Sensor to base the protection on 863 * 17-16 : Strategy: 864 * 00 : Average of 4 sensors 865 * 01 : Max of 4 sensors 866 * 10 : Selected sensor with bits 19-18 867 * 11 : Reserved 868 */ 869 writel(BIT(16), LVTS_PROTCTL(lvts_ctrl->base)); 870 871 /* 872 * LVTS_PROTTA : Stage 1 temperature threshold 873 * LVTS_PROTTB : Stage 2 temperature threshold 874 * LVTS_PROTTC : Stage 3 temperature threshold 875 * 876 * Bits: 877 * 878 * 14-0: Raw temperature threshold 879 * 880 * writel(0x0, LVTS_PROTTA(lvts_ctrl->base)); 881 * writel(0x0, LVTS_PROTTB(lvts_ctrl->base)); 882 */ 883 writel(lvts_ctrl->hw_tshut_raw_temp, LVTS_PROTTC(lvts_ctrl->base)); 884 885 /* 886 * LVTS_MONINT : Interrupt configuration register 887 * 888 * The LVTS_MONINT register layout is the same as the LVTS_MONINTSTS 889 * register, except we set the bits to enable the interrupt. 890 */ 891 writel(LVTS_MONINT_CONF, LVTS_MONINT(lvts_ctrl->base)); 892 893 return 0; 894 } 895 896 static int lvts_domain_reset(struct device *dev, struct reset_control *reset) 897 { 898 int ret; 899 900 ret = reset_control_assert(reset); 901 if (ret) 902 return ret; 903 904 return reset_control_deassert(reset); 905 } 906 907 /* 908 * Enable or disable the clocks of a specified thermal controller 909 */ 910 static int lvts_ctrl_set_enable(struct lvts_ctrl *lvts_ctrl, int enable) 911 { 912 /* 913 * LVTS_CLKEN : Internal LVTS clock 914 * 915 * Bits: 916 * 917 * 0 : enable / disable clock 918 */ 919 writel(enable, LVTS_CLKEN(lvts_ctrl->base)); 920 921 return 0; 922 } 923 924 static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl) 925 { 926 u32 id, cmds[] = { 0xC103FFFF, 0xC502FF55 }; 927 928 lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); 929 930 /* 931 * LVTS_ID : Get ID and status of the thermal controller 932 * 933 * Bits: 934 * 935 * 0-5 : thermal controller id 936 * 7 : thermal controller connection is valid 937 */ 938 id = readl(LVTS_ID(lvts_ctrl->base)); 939 if (!(id & BIT(7))) 940 return -EIO; 941 942 return 0; 943 } 944 945 static int lvts_ctrl_initialize(struct device *dev, struct lvts_ctrl *lvts_ctrl) 946 { 947 /* 948 * Write device mask: 0xC1030000 949 */ 950 u32 cmds[] = { 951 0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1, 952 0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300, 953 0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC, 954 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1 955 }; 956 957 lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); 958 959 return 0; 960 } 961 962 static int lvts_ctrl_calibrate(struct device *dev, struct lvts_ctrl *lvts_ctrl) 963 { 964 int i; 965 void __iomem *lvts_edata[] = { 966 LVTS_EDATA00(lvts_ctrl->base), 967 LVTS_EDATA01(lvts_ctrl->base), 968 LVTS_EDATA02(lvts_ctrl->base), 969 LVTS_EDATA03(lvts_ctrl->base) 970 }; 971 972 /* 973 * LVTS_EDATA0X : Efuse calibration reference value for sensor X 974 * 975 * Bits: 976 * 977 * 20-0 : Efuse value for normalization data 978 */ 979 for (i = 0; i < LVTS_SENSOR_MAX; i++) 980 writel(lvts_ctrl->calibration[i], lvts_edata[i]); 981 982 return 0; 983 } 984 985 static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_ctrl) 986 { 987 u32 value; 988 989 /* 990 * LVTS_TSSEL : Sensing point index numbering 991 * 992 * Bits: 993 * 994 * 31-24: ADC Sense 3 995 * 23-16: ADC Sense 2 996 * 15-8 : ADC Sense 1 997 * 7-0 : ADC Sense 0 998 */ 999 value = LVTS_TSSEL_CONF; 1000 writel(value, LVTS_TSSEL(lvts_ctrl->base)); 1001 1002 /* 1003 * LVTS_CALSCALE : ADC voltage round 1004 */ 1005 value = 0x300; 1006 value = LVTS_CALSCALE_CONF; 1007 1008 /* 1009 * LVTS_MSRCTL0 : Sensor filtering strategy 1010 * 1011 * Filters: 1012 * 1013 * 000 : One sample 1014 * 001 : Avg 2 samples 1015 * 010 : 4 samples, drop min and max, avg 2 samples 1016 * 011 : 6 samples, drop min and max, avg 4 samples 1017 * 100 : 10 samples, drop min and max, avg 8 samples 1018 * 101 : 18 samples, drop min and max, avg 16 samples 1019 * 1020 * Bits: 1021 * 1022 * 0-2 : Sensor0 filter 1023 * 3-5 : Sensor1 filter 1024 * 6-8 : Sensor2 filter 1025 * 9-11 : Sensor3 filter 1026 */ 1027 value = LVTS_HW_FILTER << 9 | LVTS_HW_FILTER << 6 | 1028 LVTS_HW_FILTER << 3 | LVTS_HW_FILTER; 1029 writel(value, LVTS_MSRCTL0(lvts_ctrl->base)); 1030 1031 /* 1032 * LVTS_MONCTL1 : Period unit and group interval configuration 1033 * 1034 * The clock source of LVTS thermal controller is 26MHz. 1035 * 1036 * The period unit is a time base for all the interval delays 1037 * specified in the registers. By default we use 12. The time 1038 * conversion is done by multiplying by 256 and 1/26.10^6 1039 * 1040 * An interval delay multiplied by the period unit gives the 1041 * duration in seconds. 1042 * 1043 * - Filter interval delay is a delay between two samples of 1044 * the same sensor. 1045 * 1046 * - Sensor interval delay is a delay between two samples of 1047 * different sensors. 1048 * 1049 * - Group interval delay is a delay between different rounds. 1050 * 1051 * For example: 1052 * If Period unit = C, filter delay = 1, sensor delay = 2, group delay = 1, 1053 * and two sensors, TS1 and TS2, are in a LVTS thermal controller 1054 * and then 1055 * Period unit time = C * 1/26M * 256 = 12 * 38.46ns * 256 = 118.149us 1056 * Filter interval delay = 1 * Period unit = 118.149us 1057 * Sensor interval delay = 2 * Period unit = 236.298us 1058 * Group interval delay = 1 * Period unit = 118.149us 1059 * 1060 * TS1 TS1 ... TS1 TS2 TS2 ... TS2 TS1... 1061 * <--> Filter interval delay 1062 * <--> Sensor interval delay 1063 * <--> Group interval delay 1064 * Bits: 1065 * 29 - 20 : Group interval 1066 * 16 - 13 : Send a single interrupt when crossing the hot threshold (1) 1067 * or an interrupt everytime the hot threshold is crossed (0) 1068 * 9 - 0 : Period unit 1069 * 1070 */ 1071 value = LVTS_GROUP_INTERVAL << 20 | LVTS_PERIOD_UNIT; 1072 writel(value, LVTS_MONCTL1(lvts_ctrl->base)); 1073 1074 /* 1075 * LVTS_MONCTL2 : Filtering and sensor interval 1076 * 1077 * Bits: 1078 * 1079 * 25-16 : Interval unit in PERIOD_UNIT between sample on 1080 * the same sensor, filter interval 1081 * 9-0 : Interval unit in PERIOD_UNIT between each sensor 1082 * 1083 */ 1084 value = LVTS_FILTER_INTERVAL << 16 | LVTS_SENSOR_INTERVAL; 1085 writel(value, LVTS_MONCTL2(lvts_ctrl->base)); 1086 1087 return lvts_irq_init(lvts_ctrl); 1088 } 1089 1090 static int lvts_ctrl_start(struct device *dev, struct lvts_ctrl *lvts_ctrl) 1091 { 1092 struct lvts_sensor *lvts_sensors = lvts_ctrl->sensors; 1093 struct thermal_zone_device *tz; 1094 u32 sensor_map = 0; 1095 int i; 1096 /* 1097 * Bitmaps to enable each sensor on immediate and filtered modes, as 1098 * described in MSRCTL1 and MONCTL0 registers below, respectively. 1099 */ 1100 u32 sensor_imm_bitmap[] = { BIT(4), BIT(5), BIT(6), BIT(9) }; 1101 u32 sensor_filt_bitmap[] = { BIT(0), BIT(1), BIT(2), BIT(3) }; 1102 1103 u32 *sensor_bitmap = lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE ? 1104 sensor_imm_bitmap : sensor_filt_bitmap; 1105 1106 for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) { 1107 1108 int dt_id = lvts_sensors[i].dt_id; 1109 1110 tz = devm_thermal_of_zone_register(dev, dt_id, &lvts_sensors[i], 1111 &lvts_ops); 1112 if (IS_ERR(tz)) { 1113 /* 1114 * This thermal zone is not described in the 1115 * device tree. It is not an error from the 1116 * thermal OF code POV, we just continue. 1117 */ 1118 if (PTR_ERR(tz) == -ENODEV) 1119 continue; 1120 1121 return PTR_ERR(tz); 1122 } 1123 1124 devm_thermal_add_hwmon_sysfs(dev, tz); 1125 1126 /* 1127 * The thermal zone pointer will be needed in the 1128 * interrupt handler, we store it in the sensor 1129 * structure. The thermal domain structure will be 1130 * passed to the interrupt handler private data as the 1131 * interrupt is shared for all the controller 1132 * belonging to the thermal domain. 1133 */ 1134 lvts_sensors[i].tz = tz; 1135 1136 /* 1137 * This sensor was correctly associated with a thermal 1138 * zone, let's set the corresponding bit in the sensor 1139 * map, so we can enable the temperature monitoring in 1140 * the hardware thermal controller. 1141 */ 1142 sensor_map |= sensor_bitmap[i]; 1143 } 1144 1145 /* 1146 * The initialization of the thermal zones give us 1147 * which sensor point to enable. If any thermal zone 1148 * was not described in the device tree, it won't be 1149 * enabled here in the sensor map. 1150 */ 1151 if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) { 1152 /* 1153 * LVTS_MSRCTL1 : Measurement control 1154 * 1155 * Bits: 1156 * 1157 * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3 1158 * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2 1159 * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1 1160 * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0 1161 * 1162 * That configuration will ignore the filtering and the delays 1163 * introduced in MONCTL1 and MONCTL2 1164 */ 1165 writel(sensor_map, LVTS_MSRCTL1(lvts_ctrl->base)); 1166 } else { 1167 /* 1168 * Bits: 1169 * 9: Single point access flow 1170 * 0-3: Enable sensing point 0-3 1171 */ 1172 writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base)); 1173 } 1174 1175 return 0; 1176 } 1177 1178 static int lvts_domain_init(struct device *dev, struct lvts_domain *lvts_td, 1179 const struct lvts_data *lvts_data) 1180 { 1181 struct lvts_ctrl *lvts_ctrl; 1182 int i, ret; 1183 1184 ret = lvts_ctrl_init(dev, lvts_td, lvts_data); 1185 if (ret) 1186 return ret; 1187 1188 ret = lvts_domain_reset(dev, lvts_td->reset); 1189 if (ret) { 1190 dev_dbg(dev, "Failed to reset domain"); 1191 return ret; 1192 } 1193 1194 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 1195 1196 lvts_ctrl = &lvts_td->lvts_ctrl[i]; 1197 1198 /* 1199 * Initialization steps: 1200 * 1201 * - Enable the clock 1202 * - Connect to the LVTS 1203 * - Initialize the LVTS 1204 * - Prepare the calibration data 1205 * - Select monitored sensors 1206 * [ Configure sampling ] 1207 * [ Configure the interrupt ] 1208 * - Start measurement 1209 */ 1210 ret = lvts_ctrl_set_enable(lvts_ctrl, true); 1211 if (ret) { 1212 dev_dbg(dev, "Failed to enable LVTS clock"); 1213 return ret; 1214 } 1215 1216 ret = lvts_ctrl_connect(dev, lvts_ctrl); 1217 if (ret) { 1218 dev_dbg(dev, "Failed to connect to LVTS controller"); 1219 return ret; 1220 } 1221 1222 ret = lvts_ctrl_initialize(dev, lvts_ctrl); 1223 if (ret) { 1224 dev_dbg(dev, "Failed to initialize controller"); 1225 return ret; 1226 } 1227 1228 ret = lvts_ctrl_calibrate(dev, lvts_ctrl); 1229 if (ret) { 1230 dev_dbg(dev, "Failed to calibrate controller"); 1231 return ret; 1232 } 1233 1234 ret = lvts_ctrl_configure(dev, lvts_ctrl); 1235 if (ret) { 1236 dev_dbg(dev, "Failed to configure controller"); 1237 return ret; 1238 } 1239 1240 ret = lvts_ctrl_start(dev, lvts_ctrl); 1241 if (ret) { 1242 dev_dbg(dev, "Failed to start controller"); 1243 return ret; 1244 } 1245 } 1246 1247 return lvts_debugfs_init(dev, lvts_td); 1248 } 1249 1250 static int lvts_probe(struct platform_device *pdev) 1251 { 1252 const struct lvts_data *lvts_data; 1253 struct lvts_domain *lvts_td; 1254 struct device *dev = &pdev->dev; 1255 struct resource *res; 1256 int irq, ret; 1257 1258 lvts_td = devm_kzalloc(dev, sizeof(*lvts_td), GFP_KERNEL); 1259 if (!lvts_td) 1260 return -ENOMEM; 1261 1262 lvts_data = of_device_get_match_data(dev); 1263 1264 lvts_td->clk = devm_clk_get_enabled(dev, NULL); 1265 if (IS_ERR(lvts_td->clk)) 1266 return dev_err_probe(dev, PTR_ERR(lvts_td->clk), "Failed to retrieve clock\n"); 1267 1268 res = platform_get_mem_or_io(pdev, 0); 1269 if (!res) 1270 return dev_err_probe(dev, (-ENXIO), "No IO resource\n"); 1271 1272 lvts_td->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1273 if (IS_ERR(lvts_td->base)) 1274 return dev_err_probe(dev, PTR_ERR(lvts_td->base), "Failed to map io resource\n"); 1275 1276 lvts_td->reset = devm_reset_control_get_by_index(dev, 0); 1277 if (IS_ERR(lvts_td->reset)) 1278 return dev_err_probe(dev, PTR_ERR(lvts_td->reset), "Failed to get reset control\n"); 1279 1280 irq = platform_get_irq(pdev, 0); 1281 if (irq < 0) 1282 return irq; 1283 1284 golden_temp_offset = lvts_data->temp_offset; 1285 1286 ret = lvts_domain_init(dev, lvts_td, lvts_data); 1287 if (ret) 1288 return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n"); 1289 1290 /* 1291 * At this point the LVTS is initialized and enabled. We can 1292 * safely enable the interrupt. 1293 */ 1294 ret = devm_request_threaded_irq(dev, irq, NULL, lvts_irq_handler, 1295 IRQF_ONESHOT, dev_name(dev), lvts_td); 1296 if (ret) 1297 return dev_err_probe(dev, ret, "Failed to request interrupt\n"); 1298 1299 platform_set_drvdata(pdev, lvts_td); 1300 1301 return 0; 1302 } 1303 1304 static void lvts_remove(struct platform_device *pdev) 1305 { 1306 struct lvts_domain *lvts_td; 1307 int i; 1308 1309 lvts_td = platform_get_drvdata(pdev); 1310 1311 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) 1312 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); 1313 1314 lvts_debugfs_exit(lvts_td); 1315 } 1316 1317 static const struct lvts_ctrl_data mt7988_lvts_ap_data_ctrl[] = { 1318 { 1319 .lvts_sensor = { 1320 { .dt_id = MT7988_CPU_0, 1321 .cal_offsets = { 0x00, 0x01, 0x02 } }, 1322 { .dt_id = MT7988_CPU_1, 1323 .cal_offsets = { 0x04, 0x05, 0x06 } }, 1324 { .dt_id = MT7988_ETH2P5G_0, 1325 .cal_offsets = { 0x08, 0x09, 0x0a } }, 1326 { .dt_id = MT7988_ETH2P5G_1, 1327 .cal_offsets = { 0x0c, 0x0d, 0x0e } } 1328 }, 1329 .num_lvts_sensor = 4, 1330 .offset = 0x0, 1331 }, 1332 { 1333 .lvts_sensor = { 1334 { .dt_id = MT7988_TOPS_0, 1335 .cal_offsets = { 0x14, 0x15, 0x16 } }, 1336 { .dt_id = MT7988_TOPS_1, 1337 .cal_offsets = { 0x18, 0x19, 0x1a } }, 1338 { .dt_id = MT7988_ETHWARP_0, 1339 .cal_offsets = { 0x1c, 0x1d, 0x1e } }, 1340 { .dt_id = MT7988_ETHWARP_1, 1341 .cal_offsets = { 0x20, 0x21, 0x22 } } 1342 }, 1343 .num_lvts_sensor = 4, 1344 .offset = 0x100, 1345 } 1346 }; 1347 1348 static int lvts_suspend(struct device *dev) 1349 { 1350 struct lvts_domain *lvts_td; 1351 int i; 1352 1353 lvts_td = dev_get_drvdata(dev); 1354 1355 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) 1356 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); 1357 1358 clk_disable_unprepare(lvts_td->clk); 1359 1360 return 0; 1361 } 1362 1363 static int lvts_resume(struct device *dev) 1364 { 1365 struct lvts_domain *lvts_td; 1366 int i, ret; 1367 1368 lvts_td = dev_get_drvdata(dev); 1369 1370 ret = clk_prepare_enable(lvts_td->clk); 1371 if (ret) 1372 return ret; 1373 1374 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) 1375 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], true); 1376 1377 return 0; 1378 } 1379 1380 /* 1381 * The MT8186 calibration data is stored as packed 3-byte little-endian 1382 * values using a weird layout that makes sense only when viewed as a 32-bit 1383 * hexadecimal word dump. Let's suppose SxBy where x = sensor number and 1384 * y = byte number where the LSB is y=0. We then have: 1385 * 1386 * [S0B2-S0B1-S0B0-S1B2] [S1B1-S1B0-S2B2-S2B1] [S2B0-S3B2-S3B1-S3B0] 1387 * 1388 * However, when considering a byte stream, those appear as follows: 1389 * 1390 * [S1B2] [S0B0[ [S0B1] [S0B2] [S2B1] [S2B2] [S1B0] [S1B1] [S3B0] [S3B1] [S3B2] [S2B0] 1391 * 1392 * Hence the rather confusing offsets provided below. 1393 */ 1394 static const struct lvts_ctrl_data mt8186_lvts_data_ctrl[] = { 1395 { 1396 .lvts_sensor = { 1397 { .dt_id = MT8186_LITTLE_CPU0, 1398 .cal_offsets = { 5, 6, 7 } }, 1399 { .dt_id = MT8186_LITTLE_CPU1, 1400 .cal_offsets = { 10, 11, 4 } }, 1401 { .dt_id = MT8186_LITTLE_CPU2, 1402 .cal_offsets = { 15, 8, 9 } }, 1403 { .dt_id = MT8186_CAM, 1404 .cal_offsets = { 12, 13, 14 } } 1405 }, 1406 .num_lvts_sensor = 4, 1407 .offset = 0x0, 1408 }, 1409 { 1410 .lvts_sensor = { 1411 { .dt_id = MT8186_BIG_CPU0, 1412 .cal_offsets = { 22, 23, 16 } }, 1413 { .dt_id = MT8186_BIG_CPU1, 1414 .cal_offsets = { 27, 20, 21 } } 1415 }, 1416 .num_lvts_sensor = 2, 1417 .offset = 0x100, 1418 }, 1419 { 1420 .lvts_sensor = { 1421 { .dt_id = MT8186_NNA, 1422 .cal_offsets = { 29, 30, 31 } }, 1423 { .dt_id = MT8186_ADSP, 1424 .cal_offsets = { 34, 35, 28 } }, 1425 { .dt_id = MT8186_MFG, 1426 .cal_offsets = { 39, 32, 33 } } 1427 }, 1428 .num_lvts_sensor = 3, 1429 .offset = 0x200, 1430 } 1431 }; 1432 1433 static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = { 1434 { 1435 .lvts_sensor = { 1436 { .dt_id = MT8192_MCU_BIG_CPU0, 1437 .cal_offsets = { 0x04, 0x05, 0x06 } }, 1438 { .dt_id = MT8192_MCU_BIG_CPU1, 1439 .cal_offsets = { 0x08, 0x09, 0x0a } } 1440 }, 1441 .num_lvts_sensor = 2, 1442 .offset = 0x0, 1443 .mode = LVTS_MSR_FILTERED_MODE, 1444 }, 1445 { 1446 .lvts_sensor = { 1447 { .dt_id = MT8192_MCU_BIG_CPU2, 1448 .cal_offsets = { 0x0c, 0x0d, 0x0e } }, 1449 { .dt_id = MT8192_MCU_BIG_CPU3, 1450 .cal_offsets = { 0x10, 0x11, 0x12 } } 1451 }, 1452 .num_lvts_sensor = 2, 1453 .offset = 0x100, 1454 .mode = LVTS_MSR_FILTERED_MODE, 1455 }, 1456 { 1457 .lvts_sensor = { 1458 { .dt_id = MT8192_MCU_LITTLE_CPU0, 1459 .cal_offsets = { 0x14, 0x15, 0x16 } }, 1460 { .dt_id = MT8192_MCU_LITTLE_CPU1, 1461 .cal_offsets = { 0x18, 0x19, 0x1a } }, 1462 { .dt_id = MT8192_MCU_LITTLE_CPU2, 1463 .cal_offsets = { 0x1c, 0x1d, 0x1e } }, 1464 { .dt_id = MT8192_MCU_LITTLE_CPU3, 1465 .cal_offsets = { 0x20, 0x21, 0x22 } } 1466 }, 1467 .num_lvts_sensor = 4, 1468 .offset = 0x200, 1469 .mode = LVTS_MSR_FILTERED_MODE, 1470 } 1471 }; 1472 1473 static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = { 1474 { 1475 .lvts_sensor = { 1476 { .dt_id = MT8192_AP_VPU0, 1477 .cal_offsets = { 0x24, 0x25, 0x26 } }, 1478 { .dt_id = MT8192_AP_VPU1, 1479 .cal_offsets = { 0x28, 0x29, 0x2a } } 1480 }, 1481 .num_lvts_sensor = 2, 1482 .offset = 0x0, 1483 }, 1484 { 1485 .lvts_sensor = { 1486 { .dt_id = MT8192_AP_GPU0, 1487 .cal_offsets = { 0x2c, 0x2d, 0x2e } }, 1488 { .dt_id = MT8192_AP_GPU1, 1489 .cal_offsets = { 0x30, 0x31, 0x32 } } 1490 }, 1491 .num_lvts_sensor = 2, 1492 .offset = 0x100, 1493 }, 1494 { 1495 .lvts_sensor = { 1496 { .dt_id = MT8192_AP_INFRA, 1497 .cal_offsets = { 0x34, 0x35, 0x36 } }, 1498 { .dt_id = MT8192_AP_CAM, 1499 .cal_offsets = { 0x38, 0x39, 0x3a } }, 1500 }, 1501 .num_lvts_sensor = 2, 1502 .offset = 0x200, 1503 }, 1504 { 1505 .lvts_sensor = { 1506 { .dt_id = MT8192_AP_MD0, 1507 .cal_offsets = { 0x3c, 0x3d, 0x3e } }, 1508 { .dt_id = MT8192_AP_MD1, 1509 .cal_offsets = { 0x40, 0x41, 0x42 } }, 1510 { .dt_id = MT8192_AP_MD2, 1511 .cal_offsets = { 0x44, 0x45, 0x46 } } 1512 }, 1513 .num_lvts_sensor = 3, 1514 .offset = 0x300, 1515 } 1516 }; 1517 1518 static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = { 1519 { 1520 .lvts_sensor = { 1521 { .dt_id = MT8195_MCU_BIG_CPU0, 1522 .cal_offsets = { 0x04, 0x05, 0x06 } }, 1523 { .dt_id = MT8195_MCU_BIG_CPU1, 1524 .cal_offsets = { 0x07, 0x08, 0x09 } } 1525 }, 1526 .num_lvts_sensor = 2, 1527 .offset = 0x0, 1528 }, 1529 { 1530 .lvts_sensor = { 1531 { .dt_id = MT8195_MCU_BIG_CPU2, 1532 .cal_offsets = { 0x0d, 0x0e, 0x0f } }, 1533 { .dt_id = MT8195_MCU_BIG_CPU3, 1534 .cal_offsets = { 0x10, 0x11, 0x12 } } 1535 }, 1536 .num_lvts_sensor = 2, 1537 .offset = 0x100, 1538 }, 1539 { 1540 .lvts_sensor = { 1541 { .dt_id = MT8195_MCU_LITTLE_CPU0, 1542 .cal_offsets = { 0x16, 0x17, 0x18 } }, 1543 { .dt_id = MT8195_MCU_LITTLE_CPU1, 1544 .cal_offsets = { 0x19, 0x1a, 0x1b } }, 1545 { .dt_id = MT8195_MCU_LITTLE_CPU2, 1546 .cal_offsets = { 0x1c, 0x1d, 0x1e } }, 1547 { .dt_id = MT8195_MCU_LITTLE_CPU3, 1548 .cal_offsets = { 0x1f, 0x20, 0x21 } } 1549 }, 1550 .num_lvts_sensor = 4, 1551 .offset = 0x200, 1552 } 1553 }; 1554 1555 static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = { 1556 { 1557 .lvts_sensor = { 1558 { .dt_id = MT8195_AP_VPU0, 1559 .cal_offsets = { 0x25, 0x26, 0x27 } }, 1560 { .dt_id = MT8195_AP_VPU1, 1561 .cal_offsets = { 0x28, 0x29, 0x2a } } 1562 }, 1563 .num_lvts_sensor = 2, 1564 .offset = 0x0, 1565 }, 1566 { 1567 .lvts_sensor = { 1568 { .dt_id = MT8195_AP_GPU0, 1569 .cal_offsets = { 0x2e, 0x2f, 0x30 } }, 1570 { .dt_id = MT8195_AP_GPU1, 1571 .cal_offsets = { 0x31, 0x32, 0x33 } } 1572 }, 1573 .num_lvts_sensor = 2, 1574 .offset = 0x100, 1575 }, 1576 { 1577 .lvts_sensor = { 1578 { .dt_id = MT8195_AP_VDEC, 1579 .cal_offsets = { 0x37, 0x38, 0x39 } }, 1580 { .dt_id = MT8195_AP_IMG, 1581 .cal_offsets = { 0x3a, 0x3b, 0x3c } }, 1582 { .dt_id = MT8195_AP_INFRA, 1583 .cal_offsets = { 0x3d, 0x3e, 0x3f } } 1584 }, 1585 .num_lvts_sensor = 3, 1586 .offset = 0x200, 1587 }, 1588 { 1589 .lvts_sensor = { 1590 { .dt_id = MT8195_AP_CAM0, 1591 .cal_offsets = { 0x43, 0x44, 0x45 } }, 1592 { .dt_id = MT8195_AP_CAM1, 1593 .cal_offsets = { 0x46, 0x47, 0x48 } } 1594 }, 1595 .num_lvts_sensor = 2, 1596 .offset = 0x300, 1597 } 1598 }; 1599 1600 static const struct lvts_data mt7988_lvts_ap_data = { 1601 .lvts_ctrl = mt7988_lvts_ap_data_ctrl, 1602 .num_lvts_ctrl = ARRAY_SIZE(mt7988_lvts_ap_data_ctrl), 1603 .temp_factor = LVTS_COEFF_A_MT7988, 1604 .temp_offset = LVTS_COEFF_B_MT7988, 1605 .gt_calib_bit_offset = 24, 1606 }; 1607 1608 static const struct lvts_data mt8186_lvts_data = { 1609 .lvts_ctrl = mt8186_lvts_data_ctrl, 1610 .num_lvts_ctrl = ARRAY_SIZE(mt8186_lvts_data_ctrl), 1611 .temp_factor = LVTS_COEFF_A_MT7988, 1612 .temp_offset = LVTS_COEFF_B_MT7988, 1613 .gt_calib_bit_offset = 24, 1614 }; 1615 1616 static const struct lvts_data mt8192_lvts_mcu_data = { 1617 .lvts_ctrl = mt8192_lvts_mcu_data_ctrl, 1618 .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl), 1619 .temp_factor = LVTS_COEFF_A_MT8195, 1620 .temp_offset = LVTS_COEFF_B_MT8195, 1621 .gt_calib_bit_offset = 24, 1622 }; 1623 1624 static const struct lvts_data mt8192_lvts_ap_data = { 1625 .lvts_ctrl = mt8192_lvts_ap_data_ctrl, 1626 .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_ap_data_ctrl), 1627 .temp_factor = LVTS_COEFF_A_MT8195, 1628 .temp_offset = LVTS_COEFF_B_MT8195, 1629 .gt_calib_bit_offset = 24, 1630 }; 1631 1632 static const struct lvts_data mt8195_lvts_mcu_data = { 1633 .lvts_ctrl = mt8195_lvts_mcu_data_ctrl, 1634 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl), 1635 .temp_factor = LVTS_COEFF_A_MT8195, 1636 .temp_offset = LVTS_COEFF_B_MT8195, 1637 .gt_calib_bit_offset = 24, 1638 }; 1639 1640 static const struct lvts_data mt8195_lvts_ap_data = { 1641 .lvts_ctrl = mt8195_lvts_ap_data_ctrl, 1642 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl), 1643 .temp_factor = LVTS_COEFF_A_MT8195, 1644 .temp_offset = LVTS_COEFF_B_MT8195, 1645 .gt_calib_bit_offset = 24, 1646 }; 1647 1648 static const struct of_device_id lvts_of_match[] = { 1649 { .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data }, 1650 { .compatible = "mediatek,mt8186-lvts", .data = &mt8186_lvts_data }, 1651 { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data }, 1652 { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data }, 1653 { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data }, 1654 { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data }, 1655 {}, 1656 }; 1657 MODULE_DEVICE_TABLE(of, lvts_of_match); 1658 1659 static const struct dev_pm_ops lvts_pm_ops = { 1660 NOIRQ_SYSTEM_SLEEP_PM_OPS(lvts_suspend, lvts_resume) 1661 }; 1662 1663 static struct platform_driver lvts_driver = { 1664 .probe = lvts_probe, 1665 .remove_new = lvts_remove, 1666 .driver = { 1667 .name = "mtk-lvts-thermal", 1668 .of_match_table = lvts_of_match, 1669 .pm = &lvts_pm_ops, 1670 }, 1671 }; 1672 module_platform_driver(lvts_driver); 1673 1674 MODULE_AUTHOR("Balsam CHIHI <bchihi@baylibre.com>"); 1675 MODULE_DESCRIPTION("MediaTek LVTS Thermal Driver"); 1676 MODULE_LICENSE("GPL"); 1677