1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2023 MediaTek Inc. 4 * Author: Balsam CHIHI <bchihi@baylibre.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/clk-provider.h> 9 #include <linux/delay.h> 10 #include <linux/debugfs.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/iopoll.h> 14 #include <linux/kernel.h> 15 #include <linux/nvmem-consumer.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/reset.h> 19 #include <linux/thermal.h> 20 #include <dt-bindings/thermal/mediatek,lvts-thermal.h> 21 22 #include "../thermal_hwmon.h" 23 24 #define LVTS_MONCTL0(__base) (__base + 0x0000) 25 #define LVTS_MONCTL1(__base) (__base + 0x0004) 26 #define LVTS_MONCTL2(__base) (__base + 0x0008) 27 #define LVTS_MONINT(__base) (__base + 0x000C) 28 #define LVTS_MONINTSTS(__base) (__base + 0x0010) 29 #define LVTS_MONIDET0(__base) (__base + 0x0014) 30 #define LVTS_MONIDET1(__base) (__base + 0x0018) 31 #define LVTS_MONIDET2(__base) (__base + 0x001C) 32 #define LVTS_MONIDET3(__base) (__base + 0x0020) 33 #define LVTS_H2NTHRE(__base) (__base + 0x0024) 34 #define LVTS_HTHRE(__base) (__base + 0x0028) 35 #define LVTS_OFFSETH(__base) (__base + 0x0030) 36 #define LVTS_OFFSETL(__base) (__base + 0x0034) 37 #define LVTS_MSRCTL0(__base) (__base + 0x0038) 38 #define LVTS_MSRCTL1(__base) (__base + 0x003C) 39 #define LVTS_TSSEL(__base) (__base + 0x0040) 40 #define LVTS_CALSCALE(__base) (__base + 0x0048) 41 #define LVTS_ID(__base) (__base + 0x004C) 42 #define LVTS_CONFIG(__base) (__base + 0x0050) 43 #define LVTS_EDATA00(__base) (__base + 0x0054) 44 #define LVTS_EDATA01(__base) (__base + 0x0058) 45 #define LVTS_EDATA02(__base) (__base + 0x005C) 46 #define LVTS_EDATA03(__base) (__base + 0x0060) 47 #define LVTS_MSR0(__base) (__base + 0x0090) 48 #define LVTS_MSR1(__base) (__base + 0x0094) 49 #define LVTS_MSR2(__base) (__base + 0x0098) 50 #define LVTS_MSR3(__base) (__base + 0x009C) 51 #define LVTS_IMMD0(__base) (__base + 0x00A0) 52 #define LVTS_IMMD1(__base) (__base + 0x00A4) 53 #define LVTS_IMMD2(__base) (__base + 0x00A8) 54 #define LVTS_IMMD3(__base) (__base + 0x00AC) 55 #define LVTS_PROTCTL(__base) (__base + 0x00C0) 56 #define LVTS_PROTTA(__base) (__base + 0x00C4) 57 #define LVTS_PROTTB(__base) (__base + 0x00C8) 58 #define LVTS_PROTTC(__base) (__base + 0x00CC) 59 #define LVTS_CLKEN(__base) (__base + 0x00E4) 60 61 #define LVTS_PERIOD_UNIT 0 62 #define LVTS_GROUP_INTERVAL 0 63 #define LVTS_FILTER_INTERVAL 0 64 #define LVTS_SENSOR_INTERVAL 0 65 #define LVTS_HW_FILTER 0x0 66 #define LVTS_TSSEL_CONF 0x13121110 67 #define LVTS_CALSCALE_CONF 0x300 68 #define LVTS_MONINT_CONF 0x8300318C 69 70 #define LVTS_MONINT_OFFSET_SENSOR0 0xC 71 #define LVTS_MONINT_OFFSET_SENSOR1 0x180 72 #define LVTS_MONINT_OFFSET_SENSOR2 0x3000 73 #define LVTS_MONINT_OFFSET_SENSOR3 0x3000000 74 75 #define LVTS_INT_SENSOR0 0x0009001F 76 #define LVTS_INT_SENSOR1 0x001203E0 77 #define LVTS_INT_SENSOR2 0x00247C00 78 #define LVTS_INT_SENSOR3 0x1FC00000 79 80 #define LVTS_SENSOR_MAX 4 81 #define LVTS_GOLDEN_TEMP_MAX 62 82 #define LVTS_GOLDEN_TEMP_DEFAULT 50 83 #define LVTS_COEFF_A_MT8195 -250460 84 #define LVTS_COEFF_B_MT8195 250460 85 #define LVTS_COEFF_A_MT7988 -204650 86 #define LVTS_COEFF_B_MT7988 204650 87 88 #define LVTS_MSR_IMMEDIATE_MODE 0 89 #define LVTS_MSR_FILTERED_MODE 1 90 91 #define LVTS_MSR_READ_TIMEOUT_US 400 92 #define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2) 93 94 #define LVTS_HW_TSHUT_TEMP 105000 95 96 #define LVTS_MINIMUM_THRESHOLD 20000 97 98 static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT; 99 static int golden_temp_offset; 100 101 struct lvts_sensor_data { 102 int dt_id; 103 u8 cal_offsets[3]; 104 }; 105 106 struct lvts_ctrl_data { 107 struct lvts_sensor_data lvts_sensor[LVTS_SENSOR_MAX]; 108 int cal_offset[LVTS_SENSOR_MAX]; 109 int num_lvts_sensor; 110 int offset; 111 int mode; 112 }; 113 114 struct lvts_data { 115 const struct lvts_ctrl_data *lvts_ctrl; 116 int num_lvts_ctrl; 117 int temp_factor; 118 int temp_offset; 119 }; 120 121 struct lvts_sensor { 122 struct thermal_zone_device *tz; 123 void __iomem *msr; 124 void __iomem *base; 125 int id; 126 int dt_id; 127 int low_thresh; 128 int high_thresh; 129 }; 130 131 struct lvts_ctrl { 132 struct lvts_sensor sensors[LVTS_SENSOR_MAX]; 133 const struct lvts_data *lvts_data; 134 u32 calibration[LVTS_SENSOR_MAX]; 135 u32 hw_tshut_raw_temp; 136 int num_lvts_sensor; 137 int mode; 138 void __iomem *base; 139 int low_thresh; 140 int high_thresh; 141 }; 142 143 struct lvts_domain { 144 struct lvts_ctrl *lvts_ctrl; 145 struct reset_control *reset; 146 struct clk *clk; 147 int num_lvts_ctrl; 148 void __iomem *base; 149 size_t calib_len; 150 u8 *calib; 151 #ifdef CONFIG_DEBUG_FS 152 struct dentry *dom_dentry; 153 #endif 154 }; 155 156 #ifdef CONFIG_MTK_LVTS_THERMAL_DEBUGFS 157 158 #define LVTS_DEBUG_FS_REGS(__reg) \ 159 { \ 160 .name = __stringify(__reg), \ 161 .offset = __reg(0), \ 162 } 163 164 static const struct debugfs_reg32 lvts_regs[] = { 165 LVTS_DEBUG_FS_REGS(LVTS_MONCTL0), 166 LVTS_DEBUG_FS_REGS(LVTS_MONCTL1), 167 LVTS_DEBUG_FS_REGS(LVTS_MONCTL2), 168 LVTS_DEBUG_FS_REGS(LVTS_MONINT), 169 LVTS_DEBUG_FS_REGS(LVTS_MONINTSTS), 170 LVTS_DEBUG_FS_REGS(LVTS_MONIDET0), 171 LVTS_DEBUG_FS_REGS(LVTS_MONIDET1), 172 LVTS_DEBUG_FS_REGS(LVTS_MONIDET2), 173 LVTS_DEBUG_FS_REGS(LVTS_MONIDET3), 174 LVTS_DEBUG_FS_REGS(LVTS_H2NTHRE), 175 LVTS_DEBUG_FS_REGS(LVTS_HTHRE), 176 LVTS_DEBUG_FS_REGS(LVTS_OFFSETH), 177 LVTS_DEBUG_FS_REGS(LVTS_OFFSETL), 178 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL0), 179 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL1), 180 LVTS_DEBUG_FS_REGS(LVTS_TSSEL), 181 LVTS_DEBUG_FS_REGS(LVTS_CALSCALE), 182 LVTS_DEBUG_FS_REGS(LVTS_ID), 183 LVTS_DEBUG_FS_REGS(LVTS_CONFIG), 184 LVTS_DEBUG_FS_REGS(LVTS_EDATA00), 185 LVTS_DEBUG_FS_REGS(LVTS_EDATA01), 186 LVTS_DEBUG_FS_REGS(LVTS_EDATA02), 187 LVTS_DEBUG_FS_REGS(LVTS_EDATA03), 188 LVTS_DEBUG_FS_REGS(LVTS_MSR0), 189 LVTS_DEBUG_FS_REGS(LVTS_MSR1), 190 LVTS_DEBUG_FS_REGS(LVTS_MSR2), 191 LVTS_DEBUG_FS_REGS(LVTS_MSR3), 192 LVTS_DEBUG_FS_REGS(LVTS_IMMD0), 193 LVTS_DEBUG_FS_REGS(LVTS_IMMD1), 194 LVTS_DEBUG_FS_REGS(LVTS_IMMD2), 195 LVTS_DEBUG_FS_REGS(LVTS_IMMD3), 196 LVTS_DEBUG_FS_REGS(LVTS_PROTCTL), 197 LVTS_DEBUG_FS_REGS(LVTS_PROTTA), 198 LVTS_DEBUG_FS_REGS(LVTS_PROTTB), 199 LVTS_DEBUG_FS_REGS(LVTS_PROTTC), 200 LVTS_DEBUG_FS_REGS(LVTS_CLKEN), 201 }; 202 203 static int lvts_debugfs_init(struct device *dev, struct lvts_domain *lvts_td) 204 { 205 struct debugfs_regset32 *regset; 206 struct lvts_ctrl *lvts_ctrl; 207 struct dentry *dentry; 208 char name[64]; 209 int i; 210 211 lvts_td->dom_dentry = debugfs_create_dir(dev_name(dev), NULL); 212 if (IS_ERR(lvts_td->dom_dentry)) 213 return 0; 214 215 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 216 217 lvts_ctrl = &lvts_td->lvts_ctrl[i]; 218 219 sprintf(name, "controller%d", i); 220 dentry = debugfs_create_dir(name, lvts_td->dom_dentry); 221 if (IS_ERR(dentry)) 222 continue; 223 224 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 225 if (!regset) 226 continue; 227 228 regset->base = lvts_ctrl->base; 229 regset->regs = lvts_regs; 230 regset->nregs = ARRAY_SIZE(lvts_regs); 231 232 debugfs_create_regset32("registers", 0400, dentry, regset); 233 } 234 235 return 0; 236 } 237 238 static void lvts_debugfs_exit(struct lvts_domain *lvts_td) 239 { 240 debugfs_remove_recursive(lvts_td->dom_dentry); 241 } 242 243 #else 244 245 static inline int lvts_debugfs_init(struct device *dev, 246 struct lvts_domain *lvts_td) 247 { 248 return 0; 249 } 250 251 static void lvts_debugfs_exit(struct lvts_domain *lvts_td) { } 252 253 #endif 254 255 static int lvts_raw_to_temp(u32 raw_temp, int temp_factor) 256 { 257 int temperature; 258 259 temperature = ((s64)(raw_temp & 0xFFFF) * temp_factor) >> 14; 260 temperature += golden_temp_offset; 261 262 return temperature; 263 } 264 265 static u32 lvts_temp_to_raw(int temperature, int temp_factor) 266 { 267 u32 raw_temp = ((s64)(golden_temp_offset - temperature)) << 14; 268 269 raw_temp = div_s64(raw_temp, -temp_factor); 270 271 return raw_temp; 272 } 273 274 static int lvts_get_temp(struct thermal_zone_device *tz, int *temp) 275 { 276 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); 277 struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, 278 sensors[lvts_sensor->id]); 279 const struct lvts_data *lvts_data = lvts_ctrl->lvts_data; 280 void __iomem *msr = lvts_sensor->msr; 281 u32 value; 282 int rc; 283 284 /* 285 * Measurement registers: 286 * 287 * LVTS_MSR[0-3] / LVTS_IMMD[0-3] 288 * 289 * Bits: 290 * 291 * 32-17: Unused 292 * 16 : Valid temperature 293 * 15-0 : Raw temperature 294 */ 295 rc = readl_poll_timeout(msr, value, value & BIT(16), 296 LVTS_MSR_READ_WAIT_US, LVTS_MSR_READ_TIMEOUT_US); 297 298 /* 299 * As the thermal zone temperature will read before the 300 * hardware sensor is fully initialized, we have to check the 301 * validity of the temperature returned when reading the 302 * measurement register. The thermal controller will set the 303 * valid bit temperature only when it is totally initialized. 304 * 305 * Otherwise, we may end up with garbage values out of the 306 * functionning temperature and directly jump to a system 307 * shutdown. 308 */ 309 if (rc) 310 return -EAGAIN; 311 312 *temp = lvts_raw_to_temp(value & 0xFFFF, lvts_data->temp_factor); 313 314 return 0; 315 } 316 317 static void lvts_update_irq_mask(struct lvts_ctrl *lvts_ctrl) 318 { 319 u32 masks[] = { 320 LVTS_MONINT_OFFSET_SENSOR0, 321 LVTS_MONINT_OFFSET_SENSOR1, 322 LVTS_MONINT_OFFSET_SENSOR2, 323 LVTS_MONINT_OFFSET_SENSOR3, 324 }; 325 u32 value = 0; 326 int i; 327 328 value = readl(LVTS_MONINT(lvts_ctrl->base)); 329 330 for (i = 0; i < ARRAY_SIZE(masks); i++) { 331 if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh 332 && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh) 333 value |= masks[i]; 334 else 335 value &= ~masks[i]; 336 } 337 338 writel(value, LVTS_MONINT(lvts_ctrl->base)); 339 } 340 341 static bool lvts_should_update_thresh(struct lvts_ctrl *lvts_ctrl, int high) 342 { 343 int i; 344 345 if (high > lvts_ctrl->high_thresh) 346 return true; 347 348 for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) 349 if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh 350 && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh) 351 return false; 352 353 return true; 354 } 355 356 static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high) 357 { 358 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); 359 struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, 360 sensors[lvts_sensor->id]); 361 const struct lvts_data *lvts_data = lvts_ctrl->lvts_data; 362 void __iomem *base = lvts_sensor->base; 363 u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD, 364 lvts_data->temp_factor); 365 u32 raw_high = lvts_temp_to_raw(high, lvts_data->temp_factor); 366 bool should_update_thresh; 367 368 lvts_sensor->low_thresh = low; 369 lvts_sensor->high_thresh = high; 370 371 should_update_thresh = lvts_should_update_thresh(lvts_ctrl, high); 372 if (should_update_thresh) { 373 lvts_ctrl->high_thresh = high; 374 lvts_ctrl->low_thresh = low; 375 } 376 lvts_update_irq_mask(lvts_ctrl); 377 378 if (!should_update_thresh) 379 return 0; 380 381 /* 382 * Low offset temperature threshold 383 * 384 * LVTS_OFFSETL 385 * 386 * Bits: 387 * 388 * 14-0 : Raw temperature for threshold 389 */ 390 pr_debug("%s: Setting low limit temperature interrupt: %d\n", 391 thermal_zone_device_type(tz), low); 392 writel(raw_low, LVTS_OFFSETL(base)); 393 394 /* 395 * High offset temperature threshold 396 * 397 * LVTS_OFFSETH 398 * 399 * Bits: 400 * 401 * 14-0 : Raw temperature for threshold 402 */ 403 pr_debug("%s: Setting high limit temperature interrupt: %d\n", 404 thermal_zone_device_type(tz), high); 405 writel(raw_high, LVTS_OFFSETH(base)); 406 407 return 0; 408 } 409 410 static irqreturn_t lvts_ctrl_irq_handler(struct lvts_ctrl *lvts_ctrl) 411 { 412 irqreturn_t iret = IRQ_NONE; 413 u32 value; 414 u32 masks[] = { 415 LVTS_INT_SENSOR0, 416 LVTS_INT_SENSOR1, 417 LVTS_INT_SENSOR2, 418 LVTS_INT_SENSOR3 419 }; 420 int i; 421 422 /* 423 * Interrupt monitoring status 424 * 425 * LVTS_MONINTST 426 * 427 * Bits: 428 * 429 * 31 : Interrupt for stage 3 430 * 30 : Interrupt for stage 2 431 * 29 : Interrupt for state 1 432 * 28 : Interrupt using filter on sensor 3 433 * 434 * 27 : Interrupt using immediate on sensor 3 435 * 26 : Interrupt normal to hot on sensor 3 436 * 25 : Interrupt high offset on sensor 3 437 * 24 : Interrupt low offset on sensor 3 438 * 439 * 23 : Interrupt hot threshold on sensor 3 440 * 22 : Interrupt cold threshold on sensor 3 441 * 21 : Interrupt using filter on sensor 2 442 * 20 : Interrupt using filter on sensor 1 443 * 444 * 19 : Interrupt using filter on sensor 0 445 * 18 : Interrupt using immediate on sensor 2 446 * 17 : Interrupt using immediate on sensor 1 447 * 16 : Interrupt using immediate on sensor 0 448 * 449 * 15 : Interrupt device access timeout interrupt 450 * 14 : Interrupt normal to hot on sensor 2 451 * 13 : Interrupt high offset interrupt on sensor 2 452 * 12 : Interrupt low offset interrupt on sensor 2 453 * 454 * 11 : Interrupt hot threshold on sensor 2 455 * 10 : Interrupt cold threshold on sensor 2 456 * 9 : Interrupt normal to hot on sensor 1 457 * 8 : Interrupt high offset interrupt on sensor 1 458 * 459 * 7 : Interrupt low offset interrupt on sensor 1 460 * 6 : Interrupt hot threshold on sensor 1 461 * 5 : Interrupt cold threshold on sensor 1 462 * 4 : Interrupt normal to hot on sensor 0 463 * 464 * 3 : Interrupt high offset interrupt on sensor 0 465 * 2 : Interrupt low offset interrupt on sensor 0 466 * 1 : Interrupt hot threshold on sensor 0 467 * 0 : Interrupt cold threshold on sensor 0 468 * 469 * We are interested in the sensor(s) responsible of the 470 * interrupt event. We update the thermal framework with the 471 * thermal zone associated with the sensor. The framework will 472 * take care of the rest whatever the kind of interrupt, we 473 * are only interested in which sensor raised the interrupt. 474 * 475 * sensor 3 interrupt: 0001 1111 1100 0000 0000 0000 0000 0000 476 * => 0x1FC00000 477 * sensor 2 interrupt: 0000 0000 0010 0100 0111 1100 0000 0000 478 * => 0x00247C00 479 * sensor 1 interrupt: 0000 0000 0001 0010 0000 0011 1110 0000 480 * => 0X001203E0 481 * sensor 0 interrupt: 0000 0000 0000 1001 0000 0000 0001 1111 482 * => 0x0009001F 483 */ 484 value = readl(LVTS_MONINTSTS(lvts_ctrl->base)); 485 486 /* 487 * Let's figure out which sensors raised the interrupt 488 * 489 * NOTE: the masks array must be ordered with the index 490 * corresponding to the sensor id eg. index=0, mask for 491 * sensor0. 492 */ 493 for (i = 0; i < ARRAY_SIZE(masks); i++) { 494 495 if (!(value & masks[i])) 496 continue; 497 498 thermal_zone_device_update(lvts_ctrl->sensors[i].tz, 499 THERMAL_TRIP_VIOLATED); 500 iret = IRQ_HANDLED; 501 } 502 503 /* 504 * Write back to clear the interrupt status (W1C) 505 */ 506 writel(value, LVTS_MONINTSTS(lvts_ctrl->base)); 507 508 return iret; 509 } 510 511 /* 512 * Temperature interrupt handler. Even if the driver supports more 513 * interrupt modes, we use the interrupt when the temperature crosses 514 * the hot threshold the way up and the way down (modulo the 515 * hysteresis). 516 * 517 * Each thermal domain has a couple of interrupts, one for hardware 518 * reset and another one for all the thermal events happening on the 519 * different sensors. 520 * 521 * The interrupt is configured for thermal events when crossing the 522 * hot temperature limit. At each interrupt, we check in every 523 * controller if there is an interrupt pending. 524 */ 525 static irqreturn_t lvts_irq_handler(int irq, void *data) 526 { 527 struct lvts_domain *lvts_td = data; 528 irqreturn_t aux, iret = IRQ_NONE; 529 int i; 530 531 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 532 533 aux = lvts_ctrl_irq_handler(&lvts_td->lvts_ctrl[i]); 534 if (aux != IRQ_HANDLED) 535 continue; 536 537 iret = IRQ_HANDLED; 538 } 539 540 return iret; 541 } 542 543 static struct thermal_zone_device_ops lvts_ops = { 544 .get_temp = lvts_get_temp, 545 .set_trips = lvts_set_trips, 546 }; 547 548 static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, 549 const struct lvts_ctrl_data *lvts_ctrl_data) 550 { 551 struct lvts_sensor *lvts_sensor = lvts_ctrl->sensors; 552 void __iomem *msr_regs[] = { 553 LVTS_MSR0(lvts_ctrl->base), 554 LVTS_MSR1(lvts_ctrl->base), 555 LVTS_MSR2(lvts_ctrl->base), 556 LVTS_MSR3(lvts_ctrl->base) 557 }; 558 559 void __iomem *imm_regs[] = { 560 LVTS_IMMD0(lvts_ctrl->base), 561 LVTS_IMMD1(lvts_ctrl->base), 562 LVTS_IMMD2(lvts_ctrl->base), 563 LVTS_IMMD3(lvts_ctrl->base) 564 }; 565 566 int i; 567 568 for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++) { 569 570 int dt_id = lvts_ctrl_data->lvts_sensor[i].dt_id; 571 572 /* 573 * At this point, we don't know which id matches which 574 * sensor. Let's set arbitrally the id from the index. 575 */ 576 lvts_sensor[i].id = i; 577 578 /* 579 * The thermal zone registration will set the trip 580 * point interrupt in the thermal controller 581 * register. But this one will be reset in the 582 * initialization after. So we need to post pone the 583 * thermal zone creation after the controller is 584 * setup. For this reason, we store the device tree 585 * node id from the data in the sensor structure 586 */ 587 lvts_sensor[i].dt_id = dt_id; 588 589 /* 590 * We assign the base address of the thermal 591 * controller as a back pointer. So it will be 592 * accessible from the different thermal framework ops 593 * as we pass the lvts_sensor pointer as thermal zone 594 * private data. 595 */ 596 lvts_sensor[i].base = lvts_ctrl->base; 597 598 /* 599 * Each sensor has its own register address to read from. 600 */ 601 lvts_sensor[i].msr = lvts_ctrl_data->mode == LVTS_MSR_IMMEDIATE_MODE ? 602 imm_regs[i] : msr_regs[i]; 603 604 lvts_sensor[i].low_thresh = INT_MIN; 605 lvts_sensor[i].high_thresh = INT_MIN; 606 }; 607 608 lvts_ctrl->num_lvts_sensor = lvts_ctrl_data->num_lvts_sensor; 609 610 return 0; 611 } 612 613 /* 614 * The efuse blob values follows the sensor enumeration per thermal 615 * controller. The decoding of the stream is as follow: 616 * 617 * MT8192 : 618 * Stream index map for MCU Domain mt8192 : 619 * 620 * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> 621 * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 | 0x0A | 0x0B 622 * 623 * <-----sensor#2-----> <-----sensor#3-----> 624 * 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 | 0x13 625 * 626 * <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7-----> 627 * 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 | 0x22 | 0x23 628 * 629 * Stream index map for AP Domain mt8192 : 630 * 631 * <-----sensor#0-----> <-----sensor#1-----> 632 * 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A | 0x2B 633 * 634 * <-----sensor#2-----> <-----sensor#3-----> 635 * 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33 636 * 637 * <-----sensor#4-----> <-----sensor#5-----> 638 * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B 639 * 640 * <-----sensor#6-----> <-----sensor#7-----> <-----sensor#8-----> 641 * 0x3C | 0x3D | 0x3E | 0x3F | 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 642 * 643 * MT8195 : 644 * Stream index map for MCU Domain mt8195 : 645 * 646 * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> 647 * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 648 * 649 * <-----mcu-tc#1-----> <-----sensor#2-----> <-----sensor#3-----> 650 * 0x0A | 0x0B | 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 651 * 652 * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7-----> 653 * 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 654 * 655 * Stream index map for AP Domain mt8195 : 656 * 657 * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1-----> 658 * 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A 659 * 660 * <-----ap--tc#1-----> <-----sensor#2-----> <-----sensor#3-----> 661 * 0x2B | 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33 662 * 663 * <-----ap--tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> 664 * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B | 0x3C | 0x3D | 0x3E | 0x3F 665 * 666 * <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8-----> 667 * 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48 668 * 669 * Note: In some cases, values don't strictly follow a little endian ordering. 670 * The data description gives byte offsets constituting each calibration value 671 * for each sensor. 672 */ 673 static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, 674 const struct lvts_ctrl_data *lvts_ctrl_data, 675 u8 *efuse_calibration) 676 { 677 int i; 678 679 for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++) { 680 const struct lvts_sensor_data *sensor = 681 &lvts_ctrl_data->lvts_sensor[i]; 682 683 lvts_ctrl->calibration[i] = 684 (efuse_calibration[sensor->cal_offsets[0]] << 0) + 685 (efuse_calibration[sensor->cal_offsets[1]] << 8) + 686 (efuse_calibration[sensor->cal_offsets[2]] << 16); 687 } 688 689 return 0; 690 } 691 692 /* 693 * The efuse bytes stream can be split into different chunk of 694 * nvmems. This function reads and concatenate those into a single 695 * buffer so it can be read sequentially when initializing the 696 * calibration data. 697 */ 698 static int lvts_calibration_read(struct device *dev, struct lvts_domain *lvts_td, 699 const struct lvts_data *lvts_data) 700 { 701 struct device_node *np = dev_of_node(dev); 702 struct nvmem_cell *cell; 703 struct property *prop; 704 const char *cell_name; 705 706 of_property_for_each_string(np, "nvmem-cell-names", prop, cell_name) { 707 size_t len; 708 u8 *efuse; 709 710 cell = of_nvmem_cell_get(np, cell_name); 711 if (IS_ERR(cell)) { 712 dev_err(dev, "Failed to get cell '%s'\n", cell_name); 713 return PTR_ERR(cell); 714 } 715 716 efuse = nvmem_cell_read(cell, &len); 717 718 nvmem_cell_put(cell); 719 720 if (IS_ERR(efuse)) { 721 dev_err(dev, "Failed to read cell '%s'\n", cell_name); 722 return PTR_ERR(efuse); 723 } 724 725 lvts_td->calib = devm_krealloc(dev, lvts_td->calib, 726 lvts_td->calib_len + len, GFP_KERNEL); 727 if (!lvts_td->calib) { 728 kfree(efuse); 729 return -ENOMEM; 730 } 731 732 memcpy(lvts_td->calib + lvts_td->calib_len, efuse, len); 733 734 lvts_td->calib_len += len; 735 736 kfree(efuse); 737 } 738 739 return 0; 740 } 741 742 static int lvts_golden_temp_init(struct device *dev, u8 *calib, int temp_offset) 743 { 744 u32 gt; 745 746 /* 747 * The golden temp information is contained in the 4th byte (index = 3) 748 * of efuse data. 749 */ 750 gt = calib[3]; 751 752 if (gt && gt < LVTS_GOLDEN_TEMP_MAX) 753 golden_temp = gt; 754 755 golden_temp_offset = golden_temp * 500 + temp_offset; 756 757 return 0; 758 } 759 760 static int lvts_ctrl_init(struct device *dev, struct lvts_domain *lvts_td, 761 const struct lvts_data *lvts_data) 762 { 763 size_t size = sizeof(*lvts_td->lvts_ctrl) * lvts_data->num_lvts_ctrl; 764 struct lvts_ctrl *lvts_ctrl; 765 int i, ret; 766 767 /* 768 * Create the calibration bytes stream from efuse data 769 */ 770 ret = lvts_calibration_read(dev, lvts_td, lvts_data); 771 if (ret) 772 return ret; 773 774 ret = lvts_golden_temp_init(dev, lvts_td->calib, lvts_data->temp_offset); 775 if (ret) 776 return ret; 777 778 lvts_ctrl = devm_kzalloc(dev, size, GFP_KERNEL); 779 if (!lvts_ctrl) 780 return -ENOMEM; 781 782 for (i = 0; i < lvts_data->num_lvts_ctrl; i++) { 783 784 lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset; 785 lvts_ctrl[i].lvts_data = lvts_data; 786 787 ret = lvts_sensor_init(dev, &lvts_ctrl[i], 788 &lvts_data->lvts_ctrl[i]); 789 if (ret) 790 return ret; 791 792 ret = lvts_calibration_init(dev, &lvts_ctrl[i], 793 &lvts_data->lvts_ctrl[i], 794 lvts_td->calib); 795 if (ret) 796 return ret; 797 798 /* 799 * The mode the ctrl will use to read the temperature 800 * (filtered or immediate) 801 */ 802 lvts_ctrl[i].mode = lvts_data->lvts_ctrl[i].mode; 803 804 /* 805 * The temperature to raw temperature must be done 806 * after initializing the calibration. 807 */ 808 lvts_ctrl[i].hw_tshut_raw_temp = 809 lvts_temp_to_raw(LVTS_HW_TSHUT_TEMP, 810 lvts_data->temp_factor); 811 812 lvts_ctrl[i].low_thresh = INT_MIN; 813 lvts_ctrl[i].high_thresh = INT_MIN; 814 } 815 816 /* 817 * We no longer need the efuse bytes stream, let's free it 818 */ 819 devm_kfree(dev, lvts_td->calib); 820 821 lvts_td->lvts_ctrl = lvts_ctrl; 822 lvts_td->num_lvts_ctrl = lvts_data->num_lvts_ctrl; 823 824 return 0; 825 } 826 827 /* 828 * At this point the configuration register is the only place in the 829 * driver where we write multiple values. Per hardware constraint, 830 * each write in the configuration register must be separated by a 831 * delay of 2 us. 832 */ 833 static void lvts_write_config(struct lvts_ctrl *lvts_ctrl, u32 *cmds, int nr_cmds) 834 { 835 int i; 836 837 /* 838 * Configuration register 839 */ 840 for (i = 0; i < nr_cmds; i++) { 841 writel(cmds[i], LVTS_CONFIG(lvts_ctrl->base)); 842 usleep_range(2, 4); 843 } 844 } 845 846 static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl) 847 { 848 /* 849 * LVTS_PROTCTL : Thermal Protection Sensor Selection 850 * 851 * Bits: 852 * 853 * 19-18 : Sensor to base the protection on 854 * 17-16 : Strategy: 855 * 00 : Average of 4 sensors 856 * 01 : Max of 4 sensors 857 * 10 : Selected sensor with bits 19-18 858 * 11 : Reserved 859 */ 860 writel(BIT(16), LVTS_PROTCTL(lvts_ctrl->base)); 861 862 /* 863 * LVTS_PROTTA : Stage 1 temperature threshold 864 * LVTS_PROTTB : Stage 2 temperature threshold 865 * LVTS_PROTTC : Stage 3 temperature threshold 866 * 867 * Bits: 868 * 869 * 14-0: Raw temperature threshold 870 * 871 * writel(0x0, LVTS_PROTTA(lvts_ctrl->base)); 872 * writel(0x0, LVTS_PROTTB(lvts_ctrl->base)); 873 */ 874 writel(lvts_ctrl->hw_tshut_raw_temp, LVTS_PROTTC(lvts_ctrl->base)); 875 876 /* 877 * LVTS_MONINT : Interrupt configuration register 878 * 879 * The LVTS_MONINT register layout is the same as the LVTS_MONINTSTS 880 * register, except we set the bits to enable the interrupt. 881 */ 882 writel(LVTS_MONINT_CONF, LVTS_MONINT(lvts_ctrl->base)); 883 884 return 0; 885 } 886 887 static int lvts_domain_reset(struct device *dev, struct reset_control *reset) 888 { 889 int ret; 890 891 ret = reset_control_assert(reset); 892 if (ret) 893 return ret; 894 895 return reset_control_deassert(reset); 896 } 897 898 /* 899 * Enable or disable the clocks of a specified thermal controller 900 */ 901 static int lvts_ctrl_set_enable(struct lvts_ctrl *lvts_ctrl, int enable) 902 { 903 /* 904 * LVTS_CLKEN : Internal LVTS clock 905 * 906 * Bits: 907 * 908 * 0 : enable / disable clock 909 */ 910 writel(enable, LVTS_CLKEN(lvts_ctrl->base)); 911 912 return 0; 913 } 914 915 static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl) 916 { 917 u32 id, cmds[] = { 0xC103FFFF, 0xC502FF55 }; 918 919 lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); 920 921 /* 922 * LVTS_ID : Get ID and status of the thermal controller 923 * 924 * Bits: 925 * 926 * 0-5 : thermal controller id 927 * 7 : thermal controller connection is valid 928 */ 929 id = readl(LVTS_ID(lvts_ctrl->base)); 930 if (!(id & BIT(7))) 931 return -EIO; 932 933 return 0; 934 } 935 936 static int lvts_ctrl_initialize(struct device *dev, struct lvts_ctrl *lvts_ctrl) 937 { 938 /* 939 * Write device mask: 0xC1030000 940 */ 941 u32 cmds[] = { 942 0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1, 943 0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300, 944 0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC, 945 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1 946 }; 947 948 lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); 949 950 return 0; 951 } 952 953 static int lvts_ctrl_calibrate(struct device *dev, struct lvts_ctrl *lvts_ctrl) 954 { 955 int i; 956 void __iomem *lvts_edata[] = { 957 LVTS_EDATA00(lvts_ctrl->base), 958 LVTS_EDATA01(lvts_ctrl->base), 959 LVTS_EDATA02(lvts_ctrl->base), 960 LVTS_EDATA03(lvts_ctrl->base) 961 }; 962 963 /* 964 * LVTS_EDATA0X : Efuse calibration reference value for sensor X 965 * 966 * Bits: 967 * 968 * 20-0 : Efuse value for normalization data 969 */ 970 for (i = 0; i < LVTS_SENSOR_MAX; i++) 971 writel(lvts_ctrl->calibration[i], lvts_edata[i]); 972 973 return 0; 974 } 975 976 static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_ctrl) 977 { 978 u32 value; 979 980 /* 981 * LVTS_TSSEL : Sensing point index numbering 982 * 983 * Bits: 984 * 985 * 31-24: ADC Sense 3 986 * 23-16: ADC Sense 2 987 * 15-8 : ADC Sense 1 988 * 7-0 : ADC Sense 0 989 */ 990 value = LVTS_TSSEL_CONF; 991 writel(value, LVTS_TSSEL(lvts_ctrl->base)); 992 993 /* 994 * LVTS_CALSCALE : ADC voltage round 995 */ 996 value = 0x300; 997 value = LVTS_CALSCALE_CONF; 998 999 /* 1000 * LVTS_MSRCTL0 : Sensor filtering strategy 1001 * 1002 * Filters: 1003 * 1004 * 000 : One sample 1005 * 001 : Avg 2 samples 1006 * 010 : 4 samples, drop min and max, avg 2 samples 1007 * 011 : 6 samples, drop min and max, avg 4 samples 1008 * 100 : 10 samples, drop min and max, avg 8 samples 1009 * 101 : 18 samples, drop min and max, avg 16 samples 1010 * 1011 * Bits: 1012 * 1013 * 0-2 : Sensor0 filter 1014 * 3-5 : Sensor1 filter 1015 * 6-8 : Sensor2 filter 1016 * 9-11 : Sensor3 filter 1017 */ 1018 value = LVTS_HW_FILTER << 9 | LVTS_HW_FILTER << 6 | 1019 LVTS_HW_FILTER << 3 | LVTS_HW_FILTER; 1020 writel(value, LVTS_MSRCTL0(lvts_ctrl->base)); 1021 1022 /* 1023 * LVTS_MONCTL1 : Period unit and group interval configuration 1024 * 1025 * The clock source of LVTS thermal controller is 26MHz. 1026 * 1027 * The period unit is a time base for all the interval delays 1028 * specified in the registers. By default we use 12. The time 1029 * conversion is done by multiplying by 256 and 1/26.10^6 1030 * 1031 * An interval delay multiplied by the period unit gives the 1032 * duration in seconds. 1033 * 1034 * - Filter interval delay is a delay between two samples of 1035 * the same sensor. 1036 * 1037 * - Sensor interval delay is a delay between two samples of 1038 * different sensors. 1039 * 1040 * - Group interval delay is a delay between different rounds. 1041 * 1042 * For example: 1043 * If Period unit = C, filter delay = 1, sensor delay = 2, group delay = 1, 1044 * and two sensors, TS1 and TS2, are in a LVTS thermal controller 1045 * and then 1046 * Period unit time = C * 1/26M * 256 = 12 * 38.46ns * 256 = 118.149us 1047 * Filter interval delay = 1 * Period unit = 118.149us 1048 * Sensor interval delay = 2 * Period unit = 236.298us 1049 * Group interval delay = 1 * Period unit = 118.149us 1050 * 1051 * TS1 TS1 ... TS1 TS2 TS2 ... TS2 TS1... 1052 * <--> Filter interval delay 1053 * <--> Sensor interval delay 1054 * <--> Group interval delay 1055 * Bits: 1056 * 29 - 20 : Group interval 1057 * 16 - 13 : Send a single interrupt when crossing the hot threshold (1) 1058 * or an interrupt everytime the hot threshold is crossed (0) 1059 * 9 - 0 : Period unit 1060 * 1061 */ 1062 value = LVTS_GROUP_INTERVAL << 20 | LVTS_PERIOD_UNIT; 1063 writel(value, LVTS_MONCTL1(lvts_ctrl->base)); 1064 1065 /* 1066 * LVTS_MONCTL2 : Filtering and sensor interval 1067 * 1068 * Bits: 1069 * 1070 * 25-16 : Interval unit in PERIOD_UNIT between sample on 1071 * the same sensor, filter interval 1072 * 9-0 : Interval unit in PERIOD_UNIT between each sensor 1073 * 1074 */ 1075 value = LVTS_FILTER_INTERVAL << 16 | LVTS_SENSOR_INTERVAL; 1076 writel(value, LVTS_MONCTL2(lvts_ctrl->base)); 1077 1078 return lvts_irq_init(lvts_ctrl); 1079 } 1080 1081 static int lvts_ctrl_start(struct device *dev, struct lvts_ctrl *lvts_ctrl) 1082 { 1083 struct lvts_sensor *lvts_sensors = lvts_ctrl->sensors; 1084 struct thermal_zone_device *tz; 1085 u32 sensor_map = 0; 1086 int i; 1087 /* 1088 * Bitmaps to enable each sensor on immediate and filtered modes, as 1089 * described in MSRCTL1 and MONCTL0 registers below, respectively. 1090 */ 1091 u32 sensor_imm_bitmap[] = { BIT(4), BIT(5), BIT(6), BIT(9) }; 1092 u32 sensor_filt_bitmap[] = { BIT(0), BIT(1), BIT(2), BIT(3) }; 1093 1094 u32 *sensor_bitmap = lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE ? 1095 sensor_imm_bitmap : sensor_filt_bitmap; 1096 1097 for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) { 1098 1099 int dt_id = lvts_sensors[i].dt_id; 1100 1101 tz = devm_thermal_of_zone_register(dev, dt_id, &lvts_sensors[i], 1102 &lvts_ops); 1103 if (IS_ERR(tz)) { 1104 /* 1105 * This thermal zone is not described in the 1106 * device tree. It is not an error from the 1107 * thermal OF code POV, we just continue. 1108 */ 1109 if (PTR_ERR(tz) == -ENODEV) 1110 continue; 1111 1112 return PTR_ERR(tz); 1113 } 1114 1115 devm_thermal_add_hwmon_sysfs(dev, tz); 1116 1117 /* 1118 * The thermal zone pointer will be needed in the 1119 * interrupt handler, we store it in the sensor 1120 * structure. The thermal domain structure will be 1121 * passed to the interrupt handler private data as the 1122 * interrupt is shared for all the controller 1123 * belonging to the thermal domain. 1124 */ 1125 lvts_sensors[i].tz = tz; 1126 1127 /* 1128 * This sensor was correctly associated with a thermal 1129 * zone, let's set the corresponding bit in the sensor 1130 * map, so we can enable the temperature monitoring in 1131 * the hardware thermal controller. 1132 */ 1133 sensor_map |= sensor_bitmap[i]; 1134 } 1135 1136 /* 1137 * The initialization of the thermal zones give us 1138 * which sensor point to enable. If any thermal zone 1139 * was not described in the device tree, it won't be 1140 * enabled here in the sensor map. 1141 */ 1142 if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) { 1143 /* 1144 * LVTS_MSRCTL1 : Measurement control 1145 * 1146 * Bits: 1147 * 1148 * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3 1149 * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2 1150 * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1 1151 * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0 1152 * 1153 * That configuration will ignore the filtering and the delays 1154 * introduced in MONCTL1 and MONCTL2 1155 */ 1156 writel(sensor_map, LVTS_MSRCTL1(lvts_ctrl->base)); 1157 } else { 1158 /* 1159 * Bits: 1160 * 9: Single point access flow 1161 * 0-3: Enable sensing point 0-3 1162 */ 1163 writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base)); 1164 } 1165 1166 return 0; 1167 } 1168 1169 static int lvts_domain_init(struct device *dev, struct lvts_domain *lvts_td, 1170 const struct lvts_data *lvts_data) 1171 { 1172 struct lvts_ctrl *lvts_ctrl; 1173 int i, ret; 1174 1175 ret = lvts_ctrl_init(dev, lvts_td, lvts_data); 1176 if (ret) 1177 return ret; 1178 1179 ret = lvts_domain_reset(dev, lvts_td->reset); 1180 if (ret) { 1181 dev_dbg(dev, "Failed to reset domain"); 1182 return ret; 1183 } 1184 1185 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 1186 1187 lvts_ctrl = &lvts_td->lvts_ctrl[i]; 1188 1189 /* 1190 * Initialization steps: 1191 * 1192 * - Enable the clock 1193 * - Connect to the LVTS 1194 * - Initialize the LVTS 1195 * - Prepare the calibration data 1196 * - Select monitored sensors 1197 * [ Configure sampling ] 1198 * [ Configure the interrupt ] 1199 * - Start measurement 1200 */ 1201 ret = lvts_ctrl_set_enable(lvts_ctrl, true); 1202 if (ret) { 1203 dev_dbg(dev, "Failed to enable LVTS clock"); 1204 return ret; 1205 } 1206 1207 ret = lvts_ctrl_connect(dev, lvts_ctrl); 1208 if (ret) { 1209 dev_dbg(dev, "Failed to connect to LVTS controller"); 1210 return ret; 1211 } 1212 1213 ret = lvts_ctrl_initialize(dev, lvts_ctrl); 1214 if (ret) { 1215 dev_dbg(dev, "Failed to initialize controller"); 1216 return ret; 1217 } 1218 1219 ret = lvts_ctrl_calibrate(dev, lvts_ctrl); 1220 if (ret) { 1221 dev_dbg(dev, "Failed to calibrate controller"); 1222 return ret; 1223 } 1224 1225 ret = lvts_ctrl_configure(dev, lvts_ctrl); 1226 if (ret) { 1227 dev_dbg(dev, "Failed to configure controller"); 1228 return ret; 1229 } 1230 1231 ret = lvts_ctrl_start(dev, lvts_ctrl); 1232 if (ret) { 1233 dev_dbg(dev, "Failed to start controller"); 1234 return ret; 1235 } 1236 } 1237 1238 return lvts_debugfs_init(dev, lvts_td); 1239 } 1240 1241 static int lvts_probe(struct platform_device *pdev) 1242 { 1243 const struct lvts_data *lvts_data; 1244 struct lvts_domain *lvts_td; 1245 struct device *dev = &pdev->dev; 1246 struct resource *res; 1247 int irq, ret; 1248 1249 lvts_td = devm_kzalloc(dev, sizeof(*lvts_td), GFP_KERNEL); 1250 if (!lvts_td) 1251 return -ENOMEM; 1252 1253 lvts_data = of_device_get_match_data(dev); 1254 1255 lvts_td->clk = devm_clk_get_enabled(dev, NULL); 1256 if (IS_ERR(lvts_td->clk)) 1257 return dev_err_probe(dev, PTR_ERR(lvts_td->clk), "Failed to retrieve clock\n"); 1258 1259 res = platform_get_mem_or_io(pdev, 0); 1260 if (!res) 1261 return dev_err_probe(dev, (-ENXIO), "No IO resource\n"); 1262 1263 lvts_td->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1264 if (IS_ERR(lvts_td->base)) 1265 return dev_err_probe(dev, PTR_ERR(lvts_td->base), "Failed to map io resource\n"); 1266 1267 lvts_td->reset = devm_reset_control_get_by_index(dev, 0); 1268 if (IS_ERR(lvts_td->reset)) 1269 return dev_err_probe(dev, PTR_ERR(lvts_td->reset), "Failed to get reset control\n"); 1270 1271 irq = platform_get_irq(pdev, 0); 1272 if (irq < 0) 1273 return irq; 1274 1275 golden_temp_offset = lvts_data->temp_offset; 1276 1277 ret = lvts_domain_init(dev, lvts_td, lvts_data); 1278 if (ret) 1279 return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n"); 1280 1281 /* 1282 * At this point the LVTS is initialized and enabled. We can 1283 * safely enable the interrupt. 1284 */ 1285 ret = devm_request_threaded_irq(dev, irq, NULL, lvts_irq_handler, 1286 IRQF_ONESHOT, dev_name(dev), lvts_td); 1287 if (ret) 1288 return dev_err_probe(dev, ret, "Failed to request interrupt\n"); 1289 1290 platform_set_drvdata(pdev, lvts_td); 1291 1292 return 0; 1293 } 1294 1295 static void lvts_remove(struct platform_device *pdev) 1296 { 1297 struct lvts_domain *lvts_td; 1298 int i; 1299 1300 lvts_td = platform_get_drvdata(pdev); 1301 1302 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) 1303 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); 1304 1305 lvts_debugfs_exit(lvts_td); 1306 } 1307 1308 static const struct lvts_ctrl_data mt7988_lvts_ap_data_ctrl[] = { 1309 { 1310 .lvts_sensor = { 1311 { .dt_id = MT7988_CPU_0, 1312 .cal_offsets = { 0x00, 0x01, 0x02 } }, 1313 { .dt_id = MT7988_CPU_1, 1314 .cal_offsets = { 0x04, 0x05, 0x06 } }, 1315 { .dt_id = MT7988_ETH2P5G_0, 1316 .cal_offsets = { 0x08, 0x09, 0x0a } }, 1317 { .dt_id = MT7988_ETH2P5G_1, 1318 .cal_offsets = { 0x0c, 0x0d, 0x0e } } 1319 }, 1320 .num_lvts_sensor = 4, 1321 .offset = 0x0, 1322 }, 1323 { 1324 .lvts_sensor = { 1325 { .dt_id = MT7988_TOPS_0, 1326 .cal_offsets = { 0x14, 0x15, 0x16 } }, 1327 { .dt_id = MT7988_TOPS_1, 1328 .cal_offsets = { 0x18, 0x19, 0x1a } }, 1329 { .dt_id = MT7988_ETHWARP_0, 1330 .cal_offsets = { 0x1c, 0x1d, 0x1e } }, 1331 { .dt_id = MT7988_ETHWARP_1, 1332 .cal_offsets = { 0x20, 0x21, 0x22 } } 1333 }, 1334 .num_lvts_sensor = 4, 1335 .offset = 0x100, 1336 } 1337 }; 1338 1339 static int lvts_suspend(struct device *dev) 1340 { 1341 struct lvts_domain *lvts_td; 1342 int i; 1343 1344 lvts_td = dev_get_drvdata(dev); 1345 1346 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) 1347 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); 1348 1349 clk_disable_unprepare(lvts_td->clk); 1350 1351 return 0; 1352 } 1353 1354 static int lvts_resume(struct device *dev) 1355 { 1356 struct lvts_domain *lvts_td; 1357 int i, ret; 1358 1359 lvts_td = dev_get_drvdata(dev); 1360 1361 ret = clk_prepare_enable(lvts_td->clk); 1362 if (ret) 1363 return ret; 1364 1365 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) 1366 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], true); 1367 1368 return 0; 1369 } 1370 1371 static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = { 1372 { 1373 .lvts_sensor = { 1374 { .dt_id = MT8192_MCU_BIG_CPU0, 1375 .cal_offsets = { 0x04, 0x05, 0x06 } }, 1376 { .dt_id = MT8192_MCU_BIG_CPU1, 1377 .cal_offsets = { 0x08, 0x09, 0x0a } } 1378 }, 1379 .num_lvts_sensor = 2, 1380 .offset = 0x0, 1381 .mode = LVTS_MSR_FILTERED_MODE, 1382 }, 1383 { 1384 .lvts_sensor = { 1385 { .dt_id = MT8192_MCU_BIG_CPU2, 1386 .cal_offsets = { 0x0c, 0x0d, 0x0e } }, 1387 { .dt_id = MT8192_MCU_BIG_CPU3, 1388 .cal_offsets = { 0x10, 0x11, 0x12 } } 1389 }, 1390 .num_lvts_sensor = 2, 1391 .offset = 0x100, 1392 .mode = LVTS_MSR_FILTERED_MODE, 1393 }, 1394 { 1395 .lvts_sensor = { 1396 { .dt_id = MT8192_MCU_LITTLE_CPU0, 1397 .cal_offsets = { 0x14, 0x15, 0x16 } }, 1398 { .dt_id = MT8192_MCU_LITTLE_CPU1, 1399 .cal_offsets = { 0x18, 0x19, 0x1a } }, 1400 { .dt_id = MT8192_MCU_LITTLE_CPU2, 1401 .cal_offsets = { 0x1c, 0x1d, 0x1e } }, 1402 { .dt_id = MT8192_MCU_LITTLE_CPU3, 1403 .cal_offsets = { 0x20, 0x21, 0x22 } } 1404 }, 1405 .num_lvts_sensor = 4, 1406 .offset = 0x200, 1407 .mode = LVTS_MSR_FILTERED_MODE, 1408 } 1409 }; 1410 1411 static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = { 1412 { 1413 .lvts_sensor = { 1414 { .dt_id = MT8192_AP_VPU0, 1415 .cal_offsets = { 0x24, 0x25, 0x26 } }, 1416 { .dt_id = MT8192_AP_VPU1, 1417 .cal_offsets = { 0x28, 0x29, 0x2a } } 1418 }, 1419 .num_lvts_sensor = 2, 1420 .offset = 0x0, 1421 }, 1422 { 1423 .lvts_sensor = { 1424 { .dt_id = MT8192_AP_GPU0, 1425 .cal_offsets = { 0x2c, 0x2d, 0x2e } }, 1426 { .dt_id = MT8192_AP_GPU1, 1427 .cal_offsets = { 0x30, 0x31, 0x32 } } 1428 }, 1429 .num_lvts_sensor = 2, 1430 .offset = 0x100, 1431 }, 1432 { 1433 .lvts_sensor = { 1434 { .dt_id = MT8192_AP_INFRA, 1435 .cal_offsets = { 0x34, 0x35, 0x36 } }, 1436 { .dt_id = MT8192_AP_CAM, 1437 .cal_offsets = { 0x38, 0x39, 0x3a } }, 1438 }, 1439 .num_lvts_sensor = 2, 1440 .offset = 0x200, 1441 }, 1442 { 1443 .lvts_sensor = { 1444 { .dt_id = MT8192_AP_MD0, 1445 .cal_offsets = { 0x3c, 0x3d, 0x3e } }, 1446 { .dt_id = MT8192_AP_MD1, 1447 .cal_offsets = { 0x40, 0x41, 0x42 } }, 1448 { .dt_id = MT8192_AP_MD2, 1449 .cal_offsets = { 0x44, 0x45, 0x46 } } 1450 }, 1451 .num_lvts_sensor = 3, 1452 .offset = 0x300, 1453 } 1454 }; 1455 1456 static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = { 1457 { 1458 .lvts_sensor = { 1459 { .dt_id = MT8195_MCU_BIG_CPU0, 1460 .cal_offsets = { 0x04, 0x05, 0x06 } }, 1461 { .dt_id = MT8195_MCU_BIG_CPU1, 1462 .cal_offsets = { 0x07, 0x08, 0x09 } } 1463 }, 1464 .num_lvts_sensor = 2, 1465 .offset = 0x0, 1466 }, 1467 { 1468 .lvts_sensor = { 1469 { .dt_id = MT8195_MCU_BIG_CPU2, 1470 .cal_offsets = { 0x0d, 0x0e, 0x0f } }, 1471 { .dt_id = MT8195_MCU_BIG_CPU3, 1472 .cal_offsets = { 0x10, 0x11, 0x12 } } 1473 }, 1474 .num_lvts_sensor = 2, 1475 .offset = 0x100, 1476 }, 1477 { 1478 .lvts_sensor = { 1479 { .dt_id = MT8195_MCU_LITTLE_CPU0, 1480 .cal_offsets = { 0x16, 0x17, 0x18 } }, 1481 { .dt_id = MT8195_MCU_LITTLE_CPU1, 1482 .cal_offsets = { 0x19, 0x1a, 0x1b } }, 1483 { .dt_id = MT8195_MCU_LITTLE_CPU2, 1484 .cal_offsets = { 0x1c, 0x1d, 0x1e } }, 1485 { .dt_id = MT8195_MCU_LITTLE_CPU3, 1486 .cal_offsets = { 0x1f, 0x20, 0x21 } } 1487 }, 1488 .num_lvts_sensor = 4, 1489 .offset = 0x200, 1490 } 1491 }; 1492 1493 static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = { 1494 { 1495 .lvts_sensor = { 1496 { .dt_id = MT8195_AP_VPU0, 1497 .cal_offsets = { 0x25, 0x26, 0x27 } }, 1498 { .dt_id = MT8195_AP_VPU1, 1499 .cal_offsets = { 0x28, 0x29, 0x2a } } 1500 }, 1501 .num_lvts_sensor = 2, 1502 .offset = 0x0, 1503 }, 1504 { 1505 .lvts_sensor = { 1506 { .dt_id = MT8195_AP_GPU0, 1507 .cal_offsets = { 0x2e, 0x2f, 0x30 } }, 1508 { .dt_id = MT8195_AP_GPU1, 1509 .cal_offsets = { 0x31, 0x32, 0x33 } } 1510 }, 1511 .num_lvts_sensor = 2, 1512 .offset = 0x100, 1513 }, 1514 { 1515 .lvts_sensor = { 1516 { .dt_id = MT8195_AP_VDEC, 1517 .cal_offsets = { 0x37, 0x38, 0x39 } }, 1518 { .dt_id = MT8195_AP_IMG, 1519 .cal_offsets = { 0x3a, 0x3b, 0x3c } }, 1520 { .dt_id = MT8195_AP_INFRA, 1521 .cal_offsets = { 0x3d, 0x3e, 0x3f } } 1522 }, 1523 .num_lvts_sensor = 3, 1524 .offset = 0x200, 1525 }, 1526 { 1527 .lvts_sensor = { 1528 { .dt_id = MT8195_AP_CAM0, 1529 .cal_offsets = { 0x43, 0x44, 0x45 } }, 1530 { .dt_id = MT8195_AP_CAM1, 1531 .cal_offsets = { 0x46, 0x47, 0x48 } } 1532 }, 1533 .num_lvts_sensor = 2, 1534 .offset = 0x300, 1535 } 1536 }; 1537 1538 static const struct lvts_data mt7988_lvts_ap_data = { 1539 .lvts_ctrl = mt7988_lvts_ap_data_ctrl, 1540 .num_lvts_ctrl = ARRAY_SIZE(mt7988_lvts_ap_data_ctrl), 1541 .temp_factor = LVTS_COEFF_A_MT7988, 1542 .temp_offset = LVTS_COEFF_B_MT7988, 1543 }; 1544 1545 static const struct lvts_data mt8192_lvts_mcu_data = { 1546 .lvts_ctrl = mt8192_lvts_mcu_data_ctrl, 1547 .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl), 1548 .temp_factor = LVTS_COEFF_A_MT8195, 1549 .temp_offset = LVTS_COEFF_B_MT8195, 1550 }; 1551 1552 static const struct lvts_data mt8192_lvts_ap_data = { 1553 .lvts_ctrl = mt8192_lvts_ap_data_ctrl, 1554 .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_ap_data_ctrl), 1555 .temp_factor = LVTS_COEFF_A_MT8195, 1556 .temp_offset = LVTS_COEFF_B_MT8195, 1557 }; 1558 1559 static const struct lvts_data mt8195_lvts_mcu_data = { 1560 .lvts_ctrl = mt8195_lvts_mcu_data_ctrl, 1561 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl), 1562 .temp_factor = LVTS_COEFF_A_MT8195, 1563 .temp_offset = LVTS_COEFF_B_MT8195, 1564 }; 1565 1566 static const struct lvts_data mt8195_lvts_ap_data = { 1567 .lvts_ctrl = mt8195_lvts_ap_data_ctrl, 1568 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl), 1569 .temp_factor = LVTS_COEFF_A_MT8195, 1570 .temp_offset = LVTS_COEFF_B_MT8195, 1571 }; 1572 1573 static const struct of_device_id lvts_of_match[] = { 1574 { .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data }, 1575 { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data }, 1576 { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data }, 1577 { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data }, 1578 { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data }, 1579 {}, 1580 }; 1581 MODULE_DEVICE_TABLE(of, lvts_of_match); 1582 1583 static const struct dev_pm_ops lvts_pm_ops = { 1584 NOIRQ_SYSTEM_SLEEP_PM_OPS(lvts_suspend, lvts_resume) 1585 }; 1586 1587 static struct platform_driver lvts_driver = { 1588 .probe = lvts_probe, 1589 .remove_new = lvts_remove, 1590 .driver = { 1591 .name = "mtk-lvts-thermal", 1592 .of_match_table = lvts_of_match, 1593 .pm = &lvts_pm_ops, 1594 }, 1595 }; 1596 module_platform_driver(lvts_driver); 1597 1598 MODULE_AUTHOR("Balsam CHIHI <bchihi@baylibre.com>"); 1599 MODULE_DESCRIPTION("MediaTek LVTS Thermal Driver"); 1600 MODULE_LICENSE("GPL"); 1601