1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2023 MediaTek Inc. 4 * Author: Balsam CHIHI <bchihi@baylibre.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/clk-provider.h> 9 #include <linux/delay.h> 10 #include <linux/debugfs.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/iopoll.h> 14 #include <linux/kernel.h> 15 #include <linux/nvmem-consumer.h> 16 #include <linux/of.h> 17 #include <linux/platform_device.h> 18 #include <linux/reset.h> 19 #include <linux/thermal.h> 20 #include <dt-bindings/thermal/mediatek,lvts-thermal.h> 21 22 #include "../thermal_hwmon.h" 23 24 #define LVTS_MONCTL0(__base) (__base + 0x0000) 25 #define LVTS_MONCTL1(__base) (__base + 0x0004) 26 #define LVTS_MONCTL2(__base) (__base + 0x0008) 27 #define LVTS_MONINT(__base) (__base + 0x000C) 28 #define LVTS_MONINTSTS(__base) (__base + 0x0010) 29 #define LVTS_MONIDET0(__base) (__base + 0x0014) 30 #define LVTS_MONIDET1(__base) (__base + 0x0018) 31 #define LVTS_MONIDET2(__base) (__base + 0x001C) 32 #define LVTS_MONIDET3(__base) (__base + 0x0020) 33 #define LVTS_H2NTHRE(__base) (__base + 0x0024) 34 #define LVTS_HTHRE(__base) (__base + 0x0028) 35 #define LVTS_OFFSETH(__base) (__base + 0x0030) 36 #define LVTS_OFFSETL(__base) (__base + 0x0034) 37 #define LVTS_MSRCTL0(__base) (__base + 0x0038) 38 #define LVTS_MSRCTL1(__base) (__base + 0x003C) 39 #define LVTS_TSSEL(__base) (__base + 0x0040) 40 #define LVTS_CALSCALE(__base) (__base + 0x0048) 41 #define LVTS_ID(__base) (__base + 0x004C) 42 #define LVTS_CONFIG(__base) (__base + 0x0050) 43 #define LVTS_EDATA00(__base) (__base + 0x0054) 44 #define LVTS_EDATA01(__base) (__base + 0x0058) 45 #define LVTS_EDATA02(__base) (__base + 0x005C) 46 #define LVTS_EDATA03(__base) (__base + 0x0060) 47 #define LVTS_MSR0(__base) (__base + 0x0090) 48 #define LVTS_MSR1(__base) (__base + 0x0094) 49 #define LVTS_MSR2(__base) (__base + 0x0098) 50 #define LVTS_MSR3(__base) (__base + 0x009C) 51 #define LVTS_IMMD0(__base) (__base + 0x00A0) 52 #define LVTS_IMMD1(__base) (__base + 0x00A4) 53 #define LVTS_IMMD2(__base) (__base + 0x00A8) 54 #define LVTS_IMMD3(__base) (__base + 0x00AC) 55 #define LVTS_PROTCTL(__base) (__base + 0x00C0) 56 #define LVTS_PROTTA(__base) (__base + 0x00C4) 57 #define LVTS_PROTTB(__base) (__base + 0x00C8) 58 #define LVTS_PROTTC(__base) (__base + 0x00CC) 59 #define LVTS_CLKEN(__base) (__base + 0x00E4) 60 61 #define LVTS_PERIOD_UNIT 0 62 #define LVTS_GROUP_INTERVAL 0 63 #define LVTS_FILTER_INTERVAL 0 64 #define LVTS_SENSOR_INTERVAL 0 65 #define LVTS_HW_FILTER 0x0 66 #define LVTS_TSSEL_CONF 0x13121110 67 #define LVTS_CALSCALE_CONF 0x300 68 #define LVTS_MONINT_CONF 0x8300318C 69 70 #define LVTS_MONINT_OFFSET_SENSOR0 0xC 71 #define LVTS_MONINT_OFFSET_SENSOR1 0x180 72 #define LVTS_MONINT_OFFSET_SENSOR2 0x3000 73 #define LVTS_MONINT_OFFSET_SENSOR3 0x3000000 74 75 #define LVTS_INT_SENSOR0 0x0009001F 76 #define LVTS_INT_SENSOR1 0x001203E0 77 #define LVTS_INT_SENSOR2 0x00247C00 78 #define LVTS_INT_SENSOR3 0x1FC00000 79 80 #define LVTS_SENSOR_MAX 4 81 #define LVTS_GOLDEN_TEMP_MAX 62 82 #define LVTS_GOLDEN_TEMP_DEFAULT 50 83 #define LVTS_COEFF_A_MT8195 -250460 84 #define LVTS_COEFF_B_MT8195 250460 85 #define LVTS_COEFF_A_MT7988 -204650 86 #define LVTS_COEFF_B_MT7988 204650 87 88 #define LVTS_MSR_IMMEDIATE_MODE 0 89 #define LVTS_MSR_FILTERED_MODE 1 90 91 #define LVTS_MSR_READ_TIMEOUT_US 400 92 #define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2) 93 94 #define LVTS_HW_TSHUT_TEMP 105000 95 96 #define LVTS_MINIMUM_THRESHOLD 20000 97 98 static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT; 99 static int golden_temp_offset; 100 101 struct lvts_sensor_data { 102 int dt_id; 103 u8 cal_offsets[3]; 104 }; 105 106 struct lvts_ctrl_data { 107 struct lvts_sensor_data lvts_sensor[LVTS_SENSOR_MAX]; 108 int cal_offset[LVTS_SENSOR_MAX]; 109 int num_lvts_sensor; 110 int offset; 111 int mode; 112 }; 113 114 struct lvts_data { 115 const struct lvts_ctrl_data *lvts_ctrl; 116 int num_lvts_ctrl; 117 int temp_factor; 118 int temp_offset; 119 }; 120 121 struct lvts_sensor { 122 struct thermal_zone_device *tz; 123 void __iomem *msr; 124 void __iomem *base; 125 int id; 126 int dt_id; 127 int low_thresh; 128 int high_thresh; 129 }; 130 131 struct lvts_ctrl { 132 struct lvts_sensor sensors[LVTS_SENSOR_MAX]; 133 const struct lvts_data *lvts_data; 134 u32 calibration[LVTS_SENSOR_MAX]; 135 u32 hw_tshut_raw_temp; 136 int num_lvts_sensor; 137 int mode; 138 void __iomem *base; 139 int low_thresh; 140 int high_thresh; 141 }; 142 143 struct lvts_domain { 144 struct lvts_ctrl *lvts_ctrl; 145 struct reset_control *reset; 146 struct clk *clk; 147 int num_lvts_ctrl; 148 void __iomem *base; 149 size_t calib_len; 150 u8 *calib; 151 #ifdef CONFIG_DEBUG_FS 152 struct dentry *dom_dentry; 153 #endif 154 }; 155 156 #ifdef CONFIG_MTK_LVTS_THERMAL_DEBUGFS 157 158 #define LVTS_DEBUG_FS_REGS(__reg) \ 159 { \ 160 .name = __stringify(__reg), \ 161 .offset = __reg(0), \ 162 } 163 164 static const struct debugfs_reg32 lvts_regs[] = { 165 LVTS_DEBUG_FS_REGS(LVTS_MONCTL0), 166 LVTS_DEBUG_FS_REGS(LVTS_MONCTL1), 167 LVTS_DEBUG_FS_REGS(LVTS_MONCTL2), 168 LVTS_DEBUG_FS_REGS(LVTS_MONINT), 169 LVTS_DEBUG_FS_REGS(LVTS_MONINTSTS), 170 LVTS_DEBUG_FS_REGS(LVTS_MONIDET0), 171 LVTS_DEBUG_FS_REGS(LVTS_MONIDET1), 172 LVTS_DEBUG_FS_REGS(LVTS_MONIDET2), 173 LVTS_DEBUG_FS_REGS(LVTS_MONIDET3), 174 LVTS_DEBUG_FS_REGS(LVTS_H2NTHRE), 175 LVTS_DEBUG_FS_REGS(LVTS_HTHRE), 176 LVTS_DEBUG_FS_REGS(LVTS_OFFSETH), 177 LVTS_DEBUG_FS_REGS(LVTS_OFFSETL), 178 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL0), 179 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL1), 180 LVTS_DEBUG_FS_REGS(LVTS_TSSEL), 181 LVTS_DEBUG_FS_REGS(LVTS_CALSCALE), 182 LVTS_DEBUG_FS_REGS(LVTS_ID), 183 LVTS_DEBUG_FS_REGS(LVTS_CONFIG), 184 LVTS_DEBUG_FS_REGS(LVTS_EDATA00), 185 LVTS_DEBUG_FS_REGS(LVTS_EDATA01), 186 LVTS_DEBUG_FS_REGS(LVTS_EDATA02), 187 LVTS_DEBUG_FS_REGS(LVTS_EDATA03), 188 LVTS_DEBUG_FS_REGS(LVTS_MSR0), 189 LVTS_DEBUG_FS_REGS(LVTS_MSR1), 190 LVTS_DEBUG_FS_REGS(LVTS_MSR2), 191 LVTS_DEBUG_FS_REGS(LVTS_MSR3), 192 LVTS_DEBUG_FS_REGS(LVTS_IMMD0), 193 LVTS_DEBUG_FS_REGS(LVTS_IMMD1), 194 LVTS_DEBUG_FS_REGS(LVTS_IMMD2), 195 LVTS_DEBUG_FS_REGS(LVTS_IMMD3), 196 LVTS_DEBUG_FS_REGS(LVTS_PROTCTL), 197 LVTS_DEBUG_FS_REGS(LVTS_PROTTA), 198 LVTS_DEBUG_FS_REGS(LVTS_PROTTB), 199 LVTS_DEBUG_FS_REGS(LVTS_PROTTC), 200 LVTS_DEBUG_FS_REGS(LVTS_CLKEN), 201 }; 202 203 static int lvts_debugfs_init(struct device *dev, struct lvts_domain *lvts_td) 204 { 205 struct debugfs_regset32 *regset; 206 struct lvts_ctrl *lvts_ctrl; 207 struct dentry *dentry; 208 char name[64]; 209 int i; 210 211 lvts_td->dom_dentry = debugfs_create_dir(dev_name(dev), NULL); 212 if (IS_ERR(lvts_td->dom_dentry)) 213 return 0; 214 215 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 216 217 lvts_ctrl = &lvts_td->lvts_ctrl[i]; 218 219 sprintf(name, "controller%d", i); 220 dentry = debugfs_create_dir(name, lvts_td->dom_dentry); 221 if (IS_ERR(dentry)) 222 continue; 223 224 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 225 if (!regset) 226 continue; 227 228 regset->base = lvts_ctrl->base; 229 regset->regs = lvts_regs; 230 regset->nregs = ARRAY_SIZE(lvts_regs); 231 232 debugfs_create_regset32("registers", 0400, dentry, regset); 233 } 234 235 return 0; 236 } 237 238 static void lvts_debugfs_exit(struct lvts_domain *lvts_td) 239 { 240 debugfs_remove_recursive(lvts_td->dom_dentry); 241 } 242 243 #else 244 245 static inline int lvts_debugfs_init(struct device *dev, 246 struct lvts_domain *lvts_td) 247 { 248 return 0; 249 } 250 251 static void lvts_debugfs_exit(struct lvts_domain *lvts_td) { } 252 253 #endif 254 255 static int lvts_raw_to_temp(u32 raw_temp, int temp_factor) 256 { 257 int temperature; 258 259 temperature = ((s64)(raw_temp & 0xFFFF) * temp_factor) >> 14; 260 temperature += golden_temp_offset; 261 262 return temperature; 263 } 264 265 static u32 lvts_temp_to_raw(int temperature, int temp_factor) 266 { 267 u32 raw_temp = ((s64)(golden_temp_offset - temperature)) << 14; 268 269 raw_temp = div_s64(raw_temp, -temp_factor); 270 271 return raw_temp; 272 } 273 274 static int lvts_get_temp(struct thermal_zone_device *tz, int *temp) 275 { 276 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); 277 struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, 278 sensors[lvts_sensor->id]); 279 const struct lvts_data *lvts_data = lvts_ctrl->lvts_data; 280 void __iomem *msr = lvts_sensor->msr; 281 u32 value; 282 int rc; 283 284 /* 285 * Measurement registers: 286 * 287 * LVTS_MSR[0-3] / LVTS_IMMD[0-3] 288 * 289 * Bits: 290 * 291 * 32-17: Unused 292 * 16 : Valid temperature 293 * 15-0 : Raw temperature 294 */ 295 rc = readl_poll_timeout(msr, value, value & BIT(16), 296 LVTS_MSR_READ_WAIT_US, LVTS_MSR_READ_TIMEOUT_US); 297 298 /* 299 * As the thermal zone temperature will read before the 300 * hardware sensor is fully initialized, we have to check the 301 * validity of the temperature returned when reading the 302 * measurement register. The thermal controller will set the 303 * valid bit temperature only when it is totally initialized. 304 * 305 * Otherwise, we may end up with garbage values out of the 306 * functionning temperature and directly jump to a system 307 * shutdown. 308 */ 309 if (rc) 310 return -EAGAIN; 311 312 *temp = lvts_raw_to_temp(value & 0xFFFF, lvts_data->temp_factor); 313 314 return 0; 315 } 316 317 static void lvts_update_irq_mask(struct lvts_ctrl *lvts_ctrl) 318 { 319 u32 masks[] = { 320 LVTS_MONINT_OFFSET_SENSOR0, 321 LVTS_MONINT_OFFSET_SENSOR1, 322 LVTS_MONINT_OFFSET_SENSOR2, 323 LVTS_MONINT_OFFSET_SENSOR3, 324 }; 325 u32 value = 0; 326 int i; 327 328 value = readl(LVTS_MONINT(lvts_ctrl->base)); 329 330 for (i = 0; i < ARRAY_SIZE(masks); i++) { 331 if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh 332 && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh) 333 value |= masks[i]; 334 else 335 value &= ~masks[i]; 336 } 337 338 writel(value, LVTS_MONINT(lvts_ctrl->base)); 339 } 340 341 static bool lvts_should_update_thresh(struct lvts_ctrl *lvts_ctrl, int high) 342 { 343 int i; 344 345 if (high > lvts_ctrl->high_thresh) 346 return true; 347 348 for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) 349 if (lvts_ctrl->sensors[i].high_thresh == lvts_ctrl->high_thresh 350 && lvts_ctrl->sensors[i].low_thresh == lvts_ctrl->low_thresh) 351 return false; 352 353 return true; 354 } 355 356 static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high) 357 { 358 struct lvts_sensor *lvts_sensor = thermal_zone_device_priv(tz); 359 struct lvts_ctrl *lvts_ctrl = container_of(lvts_sensor, struct lvts_ctrl, 360 sensors[lvts_sensor->id]); 361 const struct lvts_data *lvts_data = lvts_ctrl->lvts_data; 362 void __iomem *base = lvts_sensor->base; 363 u32 raw_low = lvts_temp_to_raw(low != -INT_MAX ? low : LVTS_MINIMUM_THRESHOLD, 364 lvts_data->temp_factor); 365 u32 raw_high = lvts_temp_to_raw(high, lvts_data->temp_factor); 366 bool should_update_thresh; 367 368 lvts_sensor->low_thresh = low; 369 lvts_sensor->high_thresh = high; 370 371 should_update_thresh = lvts_should_update_thresh(lvts_ctrl, high); 372 if (should_update_thresh) { 373 lvts_ctrl->high_thresh = high; 374 lvts_ctrl->low_thresh = low; 375 } 376 lvts_update_irq_mask(lvts_ctrl); 377 378 if (!should_update_thresh) 379 return 0; 380 381 /* 382 * Low offset temperature threshold 383 * 384 * LVTS_OFFSETL 385 * 386 * Bits: 387 * 388 * 14-0 : Raw temperature for threshold 389 */ 390 pr_debug("%s: Setting low limit temperature interrupt: %d\n", 391 thermal_zone_device_type(tz), low); 392 writel(raw_low, LVTS_OFFSETL(base)); 393 394 /* 395 * High offset temperature threshold 396 * 397 * LVTS_OFFSETH 398 * 399 * Bits: 400 * 401 * 14-0 : Raw temperature for threshold 402 */ 403 pr_debug("%s: Setting high limit temperature interrupt: %d\n", 404 thermal_zone_device_type(tz), high); 405 writel(raw_high, LVTS_OFFSETH(base)); 406 407 return 0; 408 } 409 410 static irqreturn_t lvts_ctrl_irq_handler(struct lvts_ctrl *lvts_ctrl) 411 { 412 irqreturn_t iret = IRQ_NONE; 413 u32 value; 414 u32 masks[] = { 415 LVTS_INT_SENSOR0, 416 LVTS_INT_SENSOR1, 417 LVTS_INT_SENSOR2, 418 LVTS_INT_SENSOR3 419 }; 420 int i; 421 422 /* 423 * Interrupt monitoring status 424 * 425 * LVTS_MONINTST 426 * 427 * Bits: 428 * 429 * 31 : Interrupt for stage 3 430 * 30 : Interrupt for stage 2 431 * 29 : Interrupt for state 1 432 * 28 : Interrupt using filter on sensor 3 433 * 434 * 27 : Interrupt using immediate on sensor 3 435 * 26 : Interrupt normal to hot on sensor 3 436 * 25 : Interrupt high offset on sensor 3 437 * 24 : Interrupt low offset on sensor 3 438 * 439 * 23 : Interrupt hot threshold on sensor 3 440 * 22 : Interrupt cold threshold on sensor 3 441 * 21 : Interrupt using filter on sensor 2 442 * 20 : Interrupt using filter on sensor 1 443 * 444 * 19 : Interrupt using filter on sensor 0 445 * 18 : Interrupt using immediate on sensor 2 446 * 17 : Interrupt using immediate on sensor 1 447 * 16 : Interrupt using immediate on sensor 0 448 * 449 * 15 : Interrupt device access timeout interrupt 450 * 14 : Interrupt normal to hot on sensor 2 451 * 13 : Interrupt high offset interrupt on sensor 2 452 * 12 : Interrupt low offset interrupt on sensor 2 453 * 454 * 11 : Interrupt hot threshold on sensor 2 455 * 10 : Interrupt cold threshold on sensor 2 456 * 9 : Interrupt normal to hot on sensor 1 457 * 8 : Interrupt high offset interrupt on sensor 1 458 * 459 * 7 : Interrupt low offset interrupt on sensor 1 460 * 6 : Interrupt hot threshold on sensor 1 461 * 5 : Interrupt cold threshold on sensor 1 462 * 4 : Interrupt normal to hot on sensor 0 463 * 464 * 3 : Interrupt high offset interrupt on sensor 0 465 * 2 : Interrupt low offset interrupt on sensor 0 466 * 1 : Interrupt hot threshold on sensor 0 467 * 0 : Interrupt cold threshold on sensor 0 468 * 469 * We are interested in the sensor(s) responsible of the 470 * interrupt event. We update the thermal framework with the 471 * thermal zone associated with the sensor. The framework will 472 * take care of the rest whatever the kind of interrupt, we 473 * are only interested in which sensor raised the interrupt. 474 * 475 * sensor 3 interrupt: 0001 1111 1100 0000 0000 0000 0000 0000 476 * => 0x1FC00000 477 * sensor 2 interrupt: 0000 0000 0010 0100 0111 1100 0000 0000 478 * => 0x00247C00 479 * sensor 1 interrupt: 0000 0000 0001 0010 0000 0011 1110 0000 480 * => 0X001203E0 481 * sensor 0 interrupt: 0000 0000 0000 1001 0000 0000 0001 1111 482 * => 0x0009001F 483 */ 484 value = readl(LVTS_MONINTSTS(lvts_ctrl->base)); 485 486 /* 487 * Let's figure out which sensors raised the interrupt 488 * 489 * NOTE: the masks array must be ordered with the index 490 * corresponding to the sensor id eg. index=0, mask for 491 * sensor0. 492 */ 493 for (i = 0; i < ARRAY_SIZE(masks); i++) { 494 495 if (!(value & masks[i])) 496 continue; 497 498 thermal_zone_device_update(lvts_ctrl->sensors[i].tz, 499 THERMAL_TRIP_VIOLATED); 500 iret = IRQ_HANDLED; 501 } 502 503 /* 504 * Write back to clear the interrupt status (W1C) 505 */ 506 writel(value, LVTS_MONINTSTS(lvts_ctrl->base)); 507 508 return iret; 509 } 510 511 /* 512 * Temperature interrupt handler. Even if the driver supports more 513 * interrupt modes, we use the interrupt when the temperature crosses 514 * the hot threshold the way up and the way down (modulo the 515 * hysteresis). 516 * 517 * Each thermal domain has a couple of interrupts, one for hardware 518 * reset and another one for all the thermal events happening on the 519 * different sensors. 520 * 521 * The interrupt is configured for thermal events when crossing the 522 * hot temperature limit. At each interrupt, we check in every 523 * controller if there is an interrupt pending. 524 */ 525 static irqreturn_t lvts_irq_handler(int irq, void *data) 526 { 527 struct lvts_domain *lvts_td = data; 528 irqreturn_t aux, iret = IRQ_NONE; 529 int i; 530 531 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 532 533 aux = lvts_ctrl_irq_handler(&lvts_td->lvts_ctrl[i]); 534 if (aux != IRQ_HANDLED) 535 continue; 536 537 iret = IRQ_HANDLED; 538 } 539 540 return iret; 541 } 542 543 static struct thermal_zone_device_ops lvts_ops = { 544 .get_temp = lvts_get_temp, 545 .set_trips = lvts_set_trips, 546 }; 547 548 static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, 549 const struct lvts_ctrl_data *lvts_ctrl_data) 550 { 551 struct lvts_sensor *lvts_sensor = lvts_ctrl->sensors; 552 void __iomem *msr_regs[] = { 553 LVTS_MSR0(lvts_ctrl->base), 554 LVTS_MSR1(lvts_ctrl->base), 555 LVTS_MSR2(lvts_ctrl->base), 556 LVTS_MSR3(lvts_ctrl->base) 557 }; 558 559 void __iomem *imm_regs[] = { 560 LVTS_IMMD0(lvts_ctrl->base), 561 LVTS_IMMD1(lvts_ctrl->base), 562 LVTS_IMMD2(lvts_ctrl->base), 563 LVTS_IMMD3(lvts_ctrl->base) 564 }; 565 566 int i; 567 568 for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++) { 569 570 int dt_id = lvts_ctrl_data->lvts_sensor[i].dt_id; 571 572 /* 573 * At this point, we don't know which id matches which 574 * sensor. Let's set arbitrally the id from the index. 575 */ 576 lvts_sensor[i].id = i; 577 578 /* 579 * The thermal zone registration will set the trip 580 * point interrupt in the thermal controller 581 * register. But this one will be reset in the 582 * initialization after. So we need to post pone the 583 * thermal zone creation after the controller is 584 * setup. For this reason, we store the device tree 585 * node id from the data in the sensor structure 586 */ 587 lvts_sensor[i].dt_id = dt_id; 588 589 /* 590 * We assign the base address of the thermal 591 * controller as a back pointer. So it will be 592 * accessible from the different thermal framework ops 593 * as we pass the lvts_sensor pointer as thermal zone 594 * private data. 595 */ 596 lvts_sensor[i].base = lvts_ctrl->base; 597 598 /* 599 * Each sensor has its own register address to read from. 600 */ 601 lvts_sensor[i].msr = lvts_ctrl_data->mode == LVTS_MSR_IMMEDIATE_MODE ? 602 imm_regs[i] : msr_regs[i]; 603 604 lvts_sensor[i].low_thresh = INT_MIN; 605 lvts_sensor[i].high_thresh = INT_MIN; 606 }; 607 608 lvts_ctrl->num_lvts_sensor = lvts_ctrl_data->num_lvts_sensor; 609 610 return 0; 611 } 612 613 /* 614 * The efuse blob values follows the sensor enumeration per thermal 615 * controller. The decoding of the stream is as follow: 616 * 617 * MT8192 : 618 * Stream index map for MCU Domain mt8192 : 619 * 620 * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> 621 * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 | 0x0A | 0x0B 622 * 623 * <-----sensor#2-----> <-----sensor#3-----> 624 * 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 | 0x13 625 * 626 * <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7-----> 627 * 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 | 0x22 | 0x23 628 * 629 * Stream index map for AP Domain mt8192 : 630 * 631 * <-----sensor#0-----> <-----sensor#1-----> 632 * 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A | 0x2B 633 * 634 * <-----sensor#2-----> <-----sensor#3-----> 635 * 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33 636 * 637 * <-----sensor#4-----> <-----sensor#5-----> 638 * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B 639 * 640 * <-----sensor#6-----> <-----sensor#7-----> <-----sensor#8-----> 641 * 0x3C | 0x3D | 0x3E | 0x3F | 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 642 * 643 * MT8195 : 644 * Stream index map for MCU Domain mt8195 : 645 * 646 * <-----mcu-tc#0-----> <-----sensor#0-----> <-----sensor#1-----> 647 * 0x01 | 0x02 | 0x03 | 0x04 | 0x05 | 0x06 | 0x07 | 0x08 | 0x09 648 * 649 * <-----mcu-tc#1-----> <-----sensor#2-----> <-----sensor#3-----> 650 * 0x0A | 0x0B | 0x0C | 0x0D | 0x0E | 0x0F | 0x10 | 0x11 | 0x12 651 * 652 * <-----mcu-tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> <-----sensor#7-----> 653 * 0x13 | 0x14 | 0x15 | 0x16 | 0x17 | 0x18 | 0x19 | 0x1A | 0x1B | 0x1C | 0x1D | 0x1E | 0x1F | 0x20 | 0x21 654 * 655 * Stream index map for AP Domain mt8195 : 656 * 657 * <-----ap--tc#0-----> <-----sensor#0-----> <-----sensor#1-----> 658 * 0x22 | 0x23 | 0x24 | 0x25 | 0x26 | 0x27 | 0x28 | 0x29 | 0x2A 659 * 660 * <-----ap--tc#1-----> <-----sensor#2-----> <-----sensor#3-----> 661 * 0x2B | 0x2C | 0x2D | 0x2E | 0x2F | 0x30 | 0x31 | 0x32 | 0x33 662 * 663 * <-----ap--tc#2-----> <-----sensor#4-----> <-----sensor#5-----> <-----sensor#6-----> 664 * 0x34 | 0x35 | 0x36 | 0x37 | 0x38 | 0x39 | 0x3A | 0x3B | 0x3C | 0x3D | 0x3E | 0x3F 665 * 666 * <-----ap--tc#3-----> <-----sensor#7-----> <-----sensor#8-----> 667 * 0x40 | 0x41 | 0x42 | 0x43 | 0x44 | 0x45 | 0x46 | 0x47 | 0x48 668 * 669 * Note: In some cases, values don't strictly follow a little endian ordering. 670 * The data description gives byte offsets constituting each calibration value 671 * for each sensor. 672 */ 673 static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, 674 const struct lvts_ctrl_data *lvts_ctrl_data, 675 u8 *efuse_calibration, 676 size_t calib_len) 677 { 678 int i; 679 680 for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++) { 681 const struct lvts_sensor_data *sensor = 682 &lvts_ctrl_data->lvts_sensor[i]; 683 684 if (sensor->cal_offsets[0] >= calib_len || 685 sensor->cal_offsets[1] >= calib_len || 686 sensor->cal_offsets[2] >= calib_len) 687 return -EINVAL; 688 689 lvts_ctrl->calibration[i] = 690 (efuse_calibration[sensor->cal_offsets[0]] << 0) + 691 (efuse_calibration[sensor->cal_offsets[1]] << 8) + 692 (efuse_calibration[sensor->cal_offsets[2]] << 16); 693 } 694 695 return 0; 696 } 697 698 /* 699 * The efuse bytes stream can be split into different chunk of 700 * nvmems. This function reads and concatenate those into a single 701 * buffer so it can be read sequentially when initializing the 702 * calibration data. 703 */ 704 static int lvts_calibration_read(struct device *dev, struct lvts_domain *lvts_td, 705 const struct lvts_data *lvts_data) 706 { 707 struct device_node *np = dev_of_node(dev); 708 struct nvmem_cell *cell; 709 struct property *prop; 710 const char *cell_name; 711 712 of_property_for_each_string(np, "nvmem-cell-names", prop, cell_name) { 713 size_t len; 714 u8 *efuse; 715 716 cell = of_nvmem_cell_get(np, cell_name); 717 if (IS_ERR(cell)) { 718 dev_err(dev, "Failed to get cell '%s'\n", cell_name); 719 return PTR_ERR(cell); 720 } 721 722 efuse = nvmem_cell_read(cell, &len); 723 724 nvmem_cell_put(cell); 725 726 if (IS_ERR(efuse)) { 727 dev_err(dev, "Failed to read cell '%s'\n", cell_name); 728 return PTR_ERR(efuse); 729 } 730 731 lvts_td->calib = devm_krealloc(dev, lvts_td->calib, 732 lvts_td->calib_len + len, GFP_KERNEL); 733 if (!lvts_td->calib) { 734 kfree(efuse); 735 return -ENOMEM; 736 } 737 738 memcpy(lvts_td->calib + lvts_td->calib_len, efuse, len); 739 740 lvts_td->calib_len += len; 741 742 kfree(efuse); 743 } 744 745 return 0; 746 } 747 748 static int lvts_golden_temp_init(struct device *dev, u8 *calib, int temp_offset) 749 { 750 u32 gt; 751 752 /* 753 * The golden temp information is contained in the 4th byte (index = 3) 754 * of efuse data. 755 */ 756 gt = calib[3]; 757 758 if (gt && gt < LVTS_GOLDEN_TEMP_MAX) 759 golden_temp = gt; 760 761 golden_temp_offset = golden_temp * 500 + temp_offset; 762 763 return 0; 764 } 765 766 static int lvts_ctrl_init(struct device *dev, struct lvts_domain *lvts_td, 767 const struct lvts_data *lvts_data) 768 { 769 size_t size = sizeof(*lvts_td->lvts_ctrl) * lvts_data->num_lvts_ctrl; 770 struct lvts_ctrl *lvts_ctrl; 771 int i, ret; 772 773 /* 774 * Create the calibration bytes stream from efuse data 775 */ 776 ret = lvts_calibration_read(dev, lvts_td, lvts_data); 777 if (ret) 778 return ret; 779 780 ret = lvts_golden_temp_init(dev, lvts_td->calib, lvts_data->temp_offset); 781 if (ret) 782 return ret; 783 784 lvts_ctrl = devm_kzalloc(dev, size, GFP_KERNEL); 785 if (!lvts_ctrl) 786 return -ENOMEM; 787 788 for (i = 0; i < lvts_data->num_lvts_ctrl; i++) { 789 790 lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset; 791 lvts_ctrl[i].lvts_data = lvts_data; 792 793 ret = lvts_sensor_init(dev, &lvts_ctrl[i], 794 &lvts_data->lvts_ctrl[i]); 795 if (ret) 796 return ret; 797 798 ret = lvts_calibration_init(dev, &lvts_ctrl[i], 799 &lvts_data->lvts_ctrl[i], 800 lvts_td->calib, 801 lvts_td->calib_len); 802 if (ret) 803 return ret; 804 805 /* 806 * The mode the ctrl will use to read the temperature 807 * (filtered or immediate) 808 */ 809 lvts_ctrl[i].mode = lvts_data->lvts_ctrl[i].mode; 810 811 /* 812 * The temperature to raw temperature must be done 813 * after initializing the calibration. 814 */ 815 lvts_ctrl[i].hw_tshut_raw_temp = 816 lvts_temp_to_raw(LVTS_HW_TSHUT_TEMP, 817 lvts_data->temp_factor); 818 819 lvts_ctrl[i].low_thresh = INT_MIN; 820 lvts_ctrl[i].high_thresh = INT_MIN; 821 } 822 823 /* 824 * We no longer need the efuse bytes stream, let's free it 825 */ 826 devm_kfree(dev, lvts_td->calib); 827 828 lvts_td->lvts_ctrl = lvts_ctrl; 829 lvts_td->num_lvts_ctrl = lvts_data->num_lvts_ctrl; 830 831 return 0; 832 } 833 834 /* 835 * At this point the configuration register is the only place in the 836 * driver where we write multiple values. Per hardware constraint, 837 * each write in the configuration register must be separated by a 838 * delay of 2 us. 839 */ 840 static void lvts_write_config(struct lvts_ctrl *lvts_ctrl, u32 *cmds, int nr_cmds) 841 { 842 int i; 843 844 /* 845 * Configuration register 846 */ 847 for (i = 0; i < nr_cmds; i++) { 848 writel(cmds[i], LVTS_CONFIG(lvts_ctrl->base)); 849 usleep_range(2, 4); 850 } 851 } 852 853 static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl) 854 { 855 /* 856 * LVTS_PROTCTL : Thermal Protection Sensor Selection 857 * 858 * Bits: 859 * 860 * 19-18 : Sensor to base the protection on 861 * 17-16 : Strategy: 862 * 00 : Average of 4 sensors 863 * 01 : Max of 4 sensors 864 * 10 : Selected sensor with bits 19-18 865 * 11 : Reserved 866 */ 867 writel(BIT(16), LVTS_PROTCTL(lvts_ctrl->base)); 868 869 /* 870 * LVTS_PROTTA : Stage 1 temperature threshold 871 * LVTS_PROTTB : Stage 2 temperature threshold 872 * LVTS_PROTTC : Stage 3 temperature threshold 873 * 874 * Bits: 875 * 876 * 14-0: Raw temperature threshold 877 * 878 * writel(0x0, LVTS_PROTTA(lvts_ctrl->base)); 879 * writel(0x0, LVTS_PROTTB(lvts_ctrl->base)); 880 */ 881 writel(lvts_ctrl->hw_tshut_raw_temp, LVTS_PROTTC(lvts_ctrl->base)); 882 883 /* 884 * LVTS_MONINT : Interrupt configuration register 885 * 886 * The LVTS_MONINT register layout is the same as the LVTS_MONINTSTS 887 * register, except we set the bits to enable the interrupt. 888 */ 889 writel(LVTS_MONINT_CONF, LVTS_MONINT(lvts_ctrl->base)); 890 891 return 0; 892 } 893 894 static int lvts_domain_reset(struct device *dev, struct reset_control *reset) 895 { 896 int ret; 897 898 ret = reset_control_assert(reset); 899 if (ret) 900 return ret; 901 902 return reset_control_deassert(reset); 903 } 904 905 /* 906 * Enable or disable the clocks of a specified thermal controller 907 */ 908 static int lvts_ctrl_set_enable(struct lvts_ctrl *lvts_ctrl, int enable) 909 { 910 /* 911 * LVTS_CLKEN : Internal LVTS clock 912 * 913 * Bits: 914 * 915 * 0 : enable / disable clock 916 */ 917 writel(enable, LVTS_CLKEN(lvts_ctrl->base)); 918 919 return 0; 920 } 921 922 static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl) 923 { 924 u32 id, cmds[] = { 0xC103FFFF, 0xC502FF55 }; 925 926 lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); 927 928 /* 929 * LVTS_ID : Get ID and status of the thermal controller 930 * 931 * Bits: 932 * 933 * 0-5 : thermal controller id 934 * 7 : thermal controller connection is valid 935 */ 936 id = readl(LVTS_ID(lvts_ctrl->base)); 937 if (!(id & BIT(7))) 938 return -EIO; 939 940 return 0; 941 } 942 943 static int lvts_ctrl_initialize(struct device *dev, struct lvts_ctrl *lvts_ctrl) 944 { 945 /* 946 * Write device mask: 0xC1030000 947 */ 948 u32 cmds[] = { 949 0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1, 950 0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300, 951 0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC, 952 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1 953 }; 954 955 lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); 956 957 return 0; 958 } 959 960 static int lvts_ctrl_calibrate(struct device *dev, struct lvts_ctrl *lvts_ctrl) 961 { 962 int i; 963 void __iomem *lvts_edata[] = { 964 LVTS_EDATA00(lvts_ctrl->base), 965 LVTS_EDATA01(lvts_ctrl->base), 966 LVTS_EDATA02(lvts_ctrl->base), 967 LVTS_EDATA03(lvts_ctrl->base) 968 }; 969 970 /* 971 * LVTS_EDATA0X : Efuse calibration reference value for sensor X 972 * 973 * Bits: 974 * 975 * 20-0 : Efuse value for normalization data 976 */ 977 for (i = 0; i < LVTS_SENSOR_MAX; i++) 978 writel(lvts_ctrl->calibration[i], lvts_edata[i]); 979 980 return 0; 981 } 982 983 static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_ctrl) 984 { 985 u32 value; 986 987 /* 988 * LVTS_TSSEL : Sensing point index numbering 989 * 990 * Bits: 991 * 992 * 31-24: ADC Sense 3 993 * 23-16: ADC Sense 2 994 * 15-8 : ADC Sense 1 995 * 7-0 : ADC Sense 0 996 */ 997 value = LVTS_TSSEL_CONF; 998 writel(value, LVTS_TSSEL(lvts_ctrl->base)); 999 1000 /* 1001 * LVTS_CALSCALE : ADC voltage round 1002 */ 1003 value = 0x300; 1004 value = LVTS_CALSCALE_CONF; 1005 1006 /* 1007 * LVTS_MSRCTL0 : Sensor filtering strategy 1008 * 1009 * Filters: 1010 * 1011 * 000 : One sample 1012 * 001 : Avg 2 samples 1013 * 010 : 4 samples, drop min and max, avg 2 samples 1014 * 011 : 6 samples, drop min and max, avg 4 samples 1015 * 100 : 10 samples, drop min and max, avg 8 samples 1016 * 101 : 18 samples, drop min and max, avg 16 samples 1017 * 1018 * Bits: 1019 * 1020 * 0-2 : Sensor0 filter 1021 * 3-5 : Sensor1 filter 1022 * 6-8 : Sensor2 filter 1023 * 9-11 : Sensor3 filter 1024 */ 1025 value = LVTS_HW_FILTER << 9 | LVTS_HW_FILTER << 6 | 1026 LVTS_HW_FILTER << 3 | LVTS_HW_FILTER; 1027 writel(value, LVTS_MSRCTL0(lvts_ctrl->base)); 1028 1029 /* 1030 * LVTS_MONCTL1 : Period unit and group interval configuration 1031 * 1032 * The clock source of LVTS thermal controller is 26MHz. 1033 * 1034 * The period unit is a time base for all the interval delays 1035 * specified in the registers. By default we use 12. The time 1036 * conversion is done by multiplying by 256 and 1/26.10^6 1037 * 1038 * An interval delay multiplied by the period unit gives the 1039 * duration in seconds. 1040 * 1041 * - Filter interval delay is a delay between two samples of 1042 * the same sensor. 1043 * 1044 * - Sensor interval delay is a delay between two samples of 1045 * different sensors. 1046 * 1047 * - Group interval delay is a delay between different rounds. 1048 * 1049 * For example: 1050 * If Period unit = C, filter delay = 1, sensor delay = 2, group delay = 1, 1051 * and two sensors, TS1 and TS2, are in a LVTS thermal controller 1052 * and then 1053 * Period unit time = C * 1/26M * 256 = 12 * 38.46ns * 256 = 118.149us 1054 * Filter interval delay = 1 * Period unit = 118.149us 1055 * Sensor interval delay = 2 * Period unit = 236.298us 1056 * Group interval delay = 1 * Period unit = 118.149us 1057 * 1058 * TS1 TS1 ... TS1 TS2 TS2 ... TS2 TS1... 1059 * <--> Filter interval delay 1060 * <--> Sensor interval delay 1061 * <--> Group interval delay 1062 * Bits: 1063 * 29 - 20 : Group interval 1064 * 16 - 13 : Send a single interrupt when crossing the hot threshold (1) 1065 * or an interrupt everytime the hot threshold is crossed (0) 1066 * 9 - 0 : Period unit 1067 * 1068 */ 1069 value = LVTS_GROUP_INTERVAL << 20 | LVTS_PERIOD_UNIT; 1070 writel(value, LVTS_MONCTL1(lvts_ctrl->base)); 1071 1072 /* 1073 * LVTS_MONCTL2 : Filtering and sensor interval 1074 * 1075 * Bits: 1076 * 1077 * 25-16 : Interval unit in PERIOD_UNIT between sample on 1078 * the same sensor, filter interval 1079 * 9-0 : Interval unit in PERIOD_UNIT between each sensor 1080 * 1081 */ 1082 value = LVTS_FILTER_INTERVAL << 16 | LVTS_SENSOR_INTERVAL; 1083 writel(value, LVTS_MONCTL2(lvts_ctrl->base)); 1084 1085 return lvts_irq_init(lvts_ctrl); 1086 } 1087 1088 static int lvts_ctrl_start(struct device *dev, struct lvts_ctrl *lvts_ctrl) 1089 { 1090 struct lvts_sensor *lvts_sensors = lvts_ctrl->sensors; 1091 struct thermal_zone_device *tz; 1092 u32 sensor_map = 0; 1093 int i; 1094 /* 1095 * Bitmaps to enable each sensor on immediate and filtered modes, as 1096 * described in MSRCTL1 and MONCTL0 registers below, respectively. 1097 */ 1098 u32 sensor_imm_bitmap[] = { BIT(4), BIT(5), BIT(6), BIT(9) }; 1099 u32 sensor_filt_bitmap[] = { BIT(0), BIT(1), BIT(2), BIT(3) }; 1100 1101 u32 *sensor_bitmap = lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE ? 1102 sensor_imm_bitmap : sensor_filt_bitmap; 1103 1104 for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) { 1105 1106 int dt_id = lvts_sensors[i].dt_id; 1107 1108 tz = devm_thermal_of_zone_register(dev, dt_id, &lvts_sensors[i], 1109 &lvts_ops); 1110 if (IS_ERR(tz)) { 1111 /* 1112 * This thermal zone is not described in the 1113 * device tree. It is not an error from the 1114 * thermal OF code POV, we just continue. 1115 */ 1116 if (PTR_ERR(tz) == -ENODEV) 1117 continue; 1118 1119 return PTR_ERR(tz); 1120 } 1121 1122 devm_thermal_add_hwmon_sysfs(dev, tz); 1123 1124 /* 1125 * The thermal zone pointer will be needed in the 1126 * interrupt handler, we store it in the sensor 1127 * structure. The thermal domain structure will be 1128 * passed to the interrupt handler private data as the 1129 * interrupt is shared for all the controller 1130 * belonging to the thermal domain. 1131 */ 1132 lvts_sensors[i].tz = tz; 1133 1134 /* 1135 * This sensor was correctly associated with a thermal 1136 * zone, let's set the corresponding bit in the sensor 1137 * map, so we can enable the temperature monitoring in 1138 * the hardware thermal controller. 1139 */ 1140 sensor_map |= sensor_bitmap[i]; 1141 } 1142 1143 /* 1144 * The initialization of the thermal zones give us 1145 * which sensor point to enable. If any thermal zone 1146 * was not described in the device tree, it won't be 1147 * enabled here in the sensor map. 1148 */ 1149 if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) { 1150 /* 1151 * LVTS_MSRCTL1 : Measurement control 1152 * 1153 * Bits: 1154 * 1155 * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3 1156 * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2 1157 * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1 1158 * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0 1159 * 1160 * That configuration will ignore the filtering and the delays 1161 * introduced in MONCTL1 and MONCTL2 1162 */ 1163 writel(sensor_map, LVTS_MSRCTL1(lvts_ctrl->base)); 1164 } else { 1165 /* 1166 * Bits: 1167 * 9: Single point access flow 1168 * 0-3: Enable sensing point 0-3 1169 */ 1170 writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base)); 1171 } 1172 1173 return 0; 1174 } 1175 1176 static int lvts_domain_init(struct device *dev, struct lvts_domain *lvts_td, 1177 const struct lvts_data *lvts_data) 1178 { 1179 struct lvts_ctrl *lvts_ctrl; 1180 int i, ret; 1181 1182 ret = lvts_ctrl_init(dev, lvts_td, lvts_data); 1183 if (ret) 1184 return ret; 1185 1186 ret = lvts_domain_reset(dev, lvts_td->reset); 1187 if (ret) { 1188 dev_dbg(dev, "Failed to reset domain"); 1189 return ret; 1190 } 1191 1192 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 1193 1194 lvts_ctrl = &lvts_td->lvts_ctrl[i]; 1195 1196 /* 1197 * Initialization steps: 1198 * 1199 * - Enable the clock 1200 * - Connect to the LVTS 1201 * - Initialize the LVTS 1202 * - Prepare the calibration data 1203 * - Select monitored sensors 1204 * [ Configure sampling ] 1205 * [ Configure the interrupt ] 1206 * - Start measurement 1207 */ 1208 ret = lvts_ctrl_set_enable(lvts_ctrl, true); 1209 if (ret) { 1210 dev_dbg(dev, "Failed to enable LVTS clock"); 1211 return ret; 1212 } 1213 1214 ret = lvts_ctrl_connect(dev, lvts_ctrl); 1215 if (ret) { 1216 dev_dbg(dev, "Failed to connect to LVTS controller"); 1217 return ret; 1218 } 1219 1220 ret = lvts_ctrl_initialize(dev, lvts_ctrl); 1221 if (ret) { 1222 dev_dbg(dev, "Failed to initialize controller"); 1223 return ret; 1224 } 1225 1226 ret = lvts_ctrl_calibrate(dev, lvts_ctrl); 1227 if (ret) { 1228 dev_dbg(dev, "Failed to calibrate controller"); 1229 return ret; 1230 } 1231 1232 ret = lvts_ctrl_configure(dev, lvts_ctrl); 1233 if (ret) { 1234 dev_dbg(dev, "Failed to configure controller"); 1235 return ret; 1236 } 1237 1238 ret = lvts_ctrl_start(dev, lvts_ctrl); 1239 if (ret) { 1240 dev_dbg(dev, "Failed to start controller"); 1241 return ret; 1242 } 1243 } 1244 1245 return lvts_debugfs_init(dev, lvts_td); 1246 } 1247 1248 static int lvts_probe(struct platform_device *pdev) 1249 { 1250 const struct lvts_data *lvts_data; 1251 struct lvts_domain *lvts_td; 1252 struct device *dev = &pdev->dev; 1253 struct resource *res; 1254 int irq, ret; 1255 1256 lvts_td = devm_kzalloc(dev, sizeof(*lvts_td), GFP_KERNEL); 1257 if (!lvts_td) 1258 return -ENOMEM; 1259 1260 lvts_data = of_device_get_match_data(dev); 1261 1262 lvts_td->clk = devm_clk_get_enabled(dev, NULL); 1263 if (IS_ERR(lvts_td->clk)) 1264 return dev_err_probe(dev, PTR_ERR(lvts_td->clk), "Failed to retrieve clock\n"); 1265 1266 res = platform_get_mem_or_io(pdev, 0); 1267 if (!res) 1268 return dev_err_probe(dev, (-ENXIO), "No IO resource\n"); 1269 1270 lvts_td->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1271 if (IS_ERR(lvts_td->base)) 1272 return dev_err_probe(dev, PTR_ERR(lvts_td->base), "Failed to map io resource\n"); 1273 1274 lvts_td->reset = devm_reset_control_get_by_index(dev, 0); 1275 if (IS_ERR(lvts_td->reset)) 1276 return dev_err_probe(dev, PTR_ERR(lvts_td->reset), "Failed to get reset control\n"); 1277 1278 irq = platform_get_irq(pdev, 0); 1279 if (irq < 0) 1280 return irq; 1281 1282 golden_temp_offset = lvts_data->temp_offset; 1283 1284 ret = lvts_domain_init(dev, lvts_td, lvts_data); 1285 if (ret) 1286 return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n"); 1287 1288 /* 1289 * At this point the LVTS is initialized and enabled. We can 1290 * safely enable the interrupt. 1291 */ 1292 ret = devm_request_threaded_irq(dev, irq, NULL, lvts_irq_handler, 1293 IRQF_ONESHOT, dev_name(dev), lvts_td); 1294 if (ret) 1295 return dev_err_probe(dev, ret, "Failed to request interrupt\n"); 1296 1297 platform_set_drvdata(pdev, lvts_td); 1298 1299 return 0; 1300 } 1301 1302 static void lvts_remove(struct platform_device *pdev) 1303 { 1304 struct lvts_domain *lvts_td; 1305 int i; 1306 1307 lvts_td = platform_get_drvdata(pdev); 1308 1309 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) 1310 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); 1311 1312 lvts_debugfs_exit(lvts_td); 1313 } 1314 1315 static const struct lvts_ctrl_data mt7988_lvts_ap_data_ctrl[] = { 1316 { 1317 .lvts_sensor = { 1318 { .dt_id = MT7988_CPU_0, 1319 .cal_offsets = { 0x00, 0x01, 0x02 } }, 1320 { .dt_id = MT7988_CPU_1, 1321 .cal_offsets = { 0x04, 0x05, 0x06 } }, 1322 { .dt_id = MT7988_ETH2P5G_0, 1323 .cal_offsets = { 0x08, 0x09, 0x0a } }, 1324 { .dt_id = MT7988_ETH2P5G_1, 1325 .cal_offsets = { 0x0c, 0x0d, 0x0e } } 1326 }, 1327 .num_lvts_sensor = 4, 1328 .offset = 0x0, 1329 }, 1330 { 1331 .lvts_sensor = { 1332 { .dt_id = MT7988_TOPS_0, 1333 .cal_offsets = { 0x14, 0x15, 0x16 } }, 1334 { .dt_id = MT7988_TOPS_1, 1335 .cal_offsets = { 0x18, 0x19, 0x1a } }, 1336 { .dt_id = MT7988_ETHWARP_0, 1337 .cal_offsets = { 0x1c, 0x1d, 0x1e } }, 1338 { .dt_id = MT7988_ETHWARP_1, 1339 .cal_offsets = { 0x20, 0x21, 0x22 } } 1340 }, 1341 .num_lvts_sensor = 4, 1342 .offset = 0x100, 1343 } 1344 }; 1345 1346 static int lvts_suspend(struct device *dev) 1347 { 1348 struct lvts_domain *lvts_td; 1349 int i; 1350 1351 lvts_td = dev_get_drvdata(dev); 1352 1353 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) 1354 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); 1355 1356 clk_disable_unprepare(lvts_td->clk); 1357 1358 return 0; 1359 } 1360 1361 static int lvts_resume(struct device *dev) 1362 { 1363 struct lvts_domain *lvts_td; 1364 int i, ret; 1365 1366 lvts_td = dev_get_drvdata(dev); 1367 1368 ret = clk_prepare_enable(lvts_td->clk); 1369 if (ret) 1370 return ret; 1371 1372 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) 1373 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], true); 1374 1375 return 0; 1376 } 1377 1378 static const struct lvts_ctrl_data mt8192_lvts_mcu_data_ctrl[] = { 1379 { 1380 .lvts_sensor = { 1381 { .dt_id = MT8192_MCU_BIG_CPU0, 1382 .cal_offsets = { 0x04, 0x05, 0x06 } }, 1383 { .dt_id = MT8192_MCU_BIG_CPU1, 1384 .cal_offsets = { 0x08, 0x09, 0x0a } } 1385 }, 1386 .num_lvts_sensor = 2, 1387 .offset = 0x0, 1388 .mode = LVTS_MSR_FILTERED_MODE, 1389 }, 1390 { 1391 .lvts_sensor = { 1392 { .dt_id = MT8192_MCU_BIG_CPU2, 1393 .cal_offsets = { 0x0c, 0x0d, 0x0e } }, 1394 { .dt_id = MT8192_MCU_BIG_CPU3, 1395 .cal_offsets = { 0x10, 0x11, 0x12 } } 1396 }, 1397 .num_lvts_sensor = 2, 1398 .offset = 0x100, 1399 .mode = LVTS_MSR_FILTERED_MODE, 1400 }, 1401 { 1402 .lvts_sensor = { 1403 { .dt_id = MT8192_MCU_LITTLE_CPU0, 1404 .cal_offsets = { 0x14, 0x15, 0x16 } }, 1405 { .dt_id = MT8192_MCU_LITTLE_CPU1, 1406 .cal_offsets = { 0x18, 0x19, 0x1a } }, 1407 { .dt_id = MT8192_MCU_LITTLE_CPU2, 1408 .cal_offsets = { 0x1c, 0x1d, 0x1e } }, 1409 { .dt_id = MT8192_MCU_LITTLE_CPU3, 1410 .cal_offsets = { 0x20, 0x21, 0x22 } } 1411 }, 1412 .num_lvts_sensor = 4, 1413 .offset = 0x200, 1414 .mode = LVTS_MSR_FILTERED_MODE, 1415 } 1416 }; 1417 1418 static const struct lvts_ctrl_data mt8192_lvts_ap_data_ctrl[] = { 1419 { 1420 .lvts_sensor = { 1421 { .dt_id = MT8192_AP_VPU0, 1422 .cal_offsets = { 0x24, 0x25, 0x26 } }, 1423 { .dt_id = MT8192_AP_VPU1, 1424 .cal_offsets = { 0x28, 0x29, 0x2a } } 1425 }, 1426 .num_lvts_sensor = 2, 1427 .offset = 0x0, 1428 }, 1429 { 1430 .lvts_sensor = { 1431 { .dt_id = MT8192_AP_GPU0, 1432 .cal_offsets = { 0x2c, 0x2d, 0x2e } }, 1433 { .dt_id = MT8192_AP_GPU1, 1434 .cal_offsets = { 0x30, 0x31, 0x32 } } 1435 }, 1436 .num_lvts_sensor = 2, 1437 .offset = 0x100, 1438 }, 1439 { 1440 .lvts_sensor = { 1441 { .dt_id = MT8192_AP_INFRA, 1442 .cal_offsets = { 0x34, 0x35, 0x36 } }, 1443 { .dt_id = MT8192_AP_CAM, 1444 .cal_offsets = { 0x38, 0x39, 0x3a } }, 1445 }, 1446 .num_lvts_sensor = 2, 1447 .offset = 0x200, 1448 }, 1449 { 1450 .lvts_sensor = { 1451 { .dt_id = MT8192_AP_MD0, 1452 .cal_offsets = { 0x3c, 0x3d, 0x3e } }, 1453 { .dt_id = MT8192_AP_MD1, 1454 .cal_offsets = { 0x40, 0x41, 0x42 } }, 1455 { .dt_id = MT8192_AP_MD2, 1456 .cal_offsets = { 0x44, 0x45, 0x46 } } 1457 }, 1458 .num_lvts_sensor = 3, 1459 .offset = 0x300, 1460 } 1461 }; 1462 1463 static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = { 1464 { 1465 .lvts_sensor = { 1466 { .dt_id = MT8195_MCU_BIG_CPU0, 1467 .cal_offsets = { 0x04, 0x05, 0x06 } }, 1468 { .dt_id = MT8195_MCU_BIG_CPU1, 1469 .cal_offsets = { 0x07, 0x08, 0x09 } } 1470 }, 1471 .num_lvts_sensor = 2, 1472 .offset = 0x0, 1473 }, 1474 { 1475 .lvts_sensor = { 1476 { .dt_id = MT8195_MCU_BIG_CPU2, 1477 .cal_offsets = { 0x0d, 0x0e, 0x0f } }, 1478 { .dt_id = MT8195_MCU_BIG_CPU3, 1479 .cal_offsets = { 0x10, 0x11, 0x12 } } 1480 }, 1481 .num_lvts_sensor = 2, 1482 .offset = 0x100, 1483 }, 1484 { 1485 .lvts_sensor = { 1486 { .dt_id = MT8195_MCU_LITTLE_CPU0, 1487 .cal_offsets = { 0x16, 0x17, 0x18 } }, 1488 { .dt_id = MT8195_MCU_LITTLE_CPU1, 1489 .cal_offsets = { 0x19, 0x1a, 0x1b } }, 1490 { .dt_id = MT8195_MCU_LITTLE_CPU2, 1491 .cal_offsets = { 0x1c, 0x1d, 0x1e } }, 1492 { .dt_id = MT8195_MCU_LITTLE_CPU3, 1493 .cal_offsets = { 0x1f, 0x20, 0x21 } } 1494 }, 1495 .num_lvts_sensor = 4, 1496 .offset = 0x200, 1497 } 1498 }; 1499 1500 static const struct lvts_ctrl_data mt8195_lvts_ap_data_ctrl[] = { 1501 { 1502 .lvts_sensor = { 1503 { .dt_id = MT8195_AP_VPU0, 1504 .cal_offsets = { 0x25, 0x26, 0x27 } }, 1505 { .dt_id = MT8195_AP_VPU1, 1506 .cal_offsets = { 0x28, 0x29, 0x2a } } 1507 }, 1508 .num_lvts_sensor = 2, 1509 .offset = 0x0, 1510 }, 1511 { 1512 .lvts_sensor = { 1513 { .dt_id = MT8195_AP_GPU0, 1514 .cal_offsets = { 0x2e, 0x2f, 0x30 } }, 1515 { .dt_id = MT8195_AP_GPU1, 1516 .cal_offsets = { 0x31, 0x32, 0x33 } } 1517 }, 1518 .num_lvts_sensor = 2, 1519 .offset = 0x100, 1520 }, 1521 { 1522 .lvts_sensor = { 1523 { .dt_id = MT8195_AP_VDEC, 1524 .cal_offsets = { 0x37, 0x38, 0x39 } }, 1525 { .dt_id = MT8195_AP_IMG, 1526 .cal_offsets = { 0x3a, 0x3b, 0x3c } }, 1527 { .dt_id = MT8195_AP_INFRA, 1528 .cal_offsets = { 0x3d, 0x3e, 0x3f } } 1529 }, 1530 .num_lvts_sensor = 3, 1531 .offset = 0x200, 1532 }, 1533 { 1534 .lvts_sensor = { 1535 { .dt_id = MT8195_AP_CAM0, 1536 .cal_offsets = { 0x43, 0x44, 0x45 } }, 1537 { .dt_id = MT8195_AP_CAM1, 1538 .cal_offsets = { 0x46, 0x47, 0x48 } } 1539 }, 1540 .num_lvts_sensor = 2, 1541 .offset = 0x300, 1542 } 1543 }; 1544 1545 static const struct lvts_data mt7988_lvts_ap_data = { 1546 .lvts_ctrl = mt7988_lvts_ap_data_ctrl, 1547 .num_lvts_ctrl = ARRAY_SIZE(mt7988_lvts_ap_data_ctrl), 1548 .temp_factor = LVTS_COEFF_A_MT7988, 1549 .temp_offset = LVTS_COEFF_B_MT7988, 1550 }; 1551 1552 static const struct lvts_data mt8192_lvts_mcu_data = { 1553 .lvts_ctrl = mt8192_lvts_mcu_data_ctrl, 1554 .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_mcu_data_ctrl), 1555 .temp_factor = LVTS_COEFF_A_MT8195, 1556 .temp_offset = LVTS_COEFF_B_MT8195, 1557 }; 1558 1559 static const struct lvts_data mt8192_lvts_ap_data = { 1560 .lvts_ctrl = mt8192_lvts_ap_data_ctrl, 1561 .num_lvts_ctrl = ARRAY_SIZE(mt8192_lvts_ap_data_ctrl), 1562 .temp_factor = LVTS_COEFF_A_MT8195, 1563 .temp_offset = LVTS_COEFF_B_MT8195, 1564 }; 1565 1566 static const struct lvts_data mt8195_lvts_mcu_data = { 1567 .lvts_ctrl = mt8195_lvts_mcu_data_ctrl, 1568 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl), 1569 .temp_factor = LVTS_COEFF_A_MT8195, 1570 .temp_offset = LVTS_COEFF_B_MT8195, 1571 }; 1572 1573 static const struct lvts_data mt8195_lvts_ap_data = { 1574 .lvts_ctrl = mt8195_lvts_ap_data_ctrl, 1575 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_ap_data_ctrl), 1576 .temp_factor = LVTS_COEFF_A_MT8195, 1577 .temp_offset = LVTS_COEFF_B_MT8195, 1578 }; 1579 1580 static const struct of_device_id lvts_of_match[] = { 1581 { .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data }, 1582 { .compatible = "mediatek,mt8192-lvts-mcu", .data = &mt8192_lvts_mcu_data }, 1583 { .compatible = "mediatek,mt8192-lvts-ap", .data = &mt8192_lvts_ap_data }, 1584 { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data }, 1585 { .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data }, 1586 {}, 1587 }; 1588 MODULE_DEVICE_TABLE(of, lvts_of_match); 1589 1590 static const struct dev_pm_ops lvts_pm_ops = { 1591 NOIRQ_SYSTEM_SLEEP_PM_OPS(lvts_suspend, lvts_resume) 1592 }; 1593 1594 static struct platform_driver lvts_driver = { 1595 .probe = lvts_probe, 1596 .remove_new = lvts_remove, 1597 .driver = { 1598 .name = "mtk-lvts-thermal", 1599 .of_match_table = lvts_of_match, 1600 .pm = &lvts_pm_ops, 1601 }, 1602 }; 1603 module_platform_driver(lvts_driver); 1604 1605 MODULE_AUTHOR("Balsam CHIHI <bchihi@baylibre.com>"); 1606 MODULE_DESCRIPTION("MediaTek LVTS Thermal Driver"); 1607 MODULE_LICENSE("GPL"); 1608