1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2023 MediaTek Inc. 4 * Author: Balsam CHIHI <bchihi@baylibre.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/clk-provider.h> 9 #include <linux/delay.h> 10 #include <linux/debugfs.h> 11 #include <linux/init.h> 12 #include <linux/interrupt.h> 13 #include <linux/iopoll.h> 14 #include <linux/kernel.h> 15 #include <linux/nvmem-consumer.h> 16 #include <linux/of_device.h> 17 #include <linux/platform_device.h> 18 #include <linux/reset.h> 19 #include <linux/thermal.h> 20 #include <dt-bindings/thermal/mediatek,lvts-thermal.h> 21 22 #define LVTS_MONCTL0(__base) (__base + 0x0000) 23 #define LVTS_MONCTL1(__base) (__base + 0x0004) 24 #define LVTS_MONCTL2(__base) (__base + 0x0008) 25 #define LVTS_MONINT(__base) (__base + 0x000C) 26 #define LVTS_MONINTSTS(__base) (__base + 0x0010) 27 #define LVTS_MONIDET0(__base) (__base + 0x0014) 28 #define LVTS_MONIDET1(__base) (__base + 0x0018) 29 #define LVTS_MONIDET2(__base) (__base + 0x001C) 30 #define LVTS_MONIDET3(__base) (__base + 0x0020) 31 #define LVTS_H2NTHRE(__base) (__base + 0x0024) 32 #define LVTS_HTHRE(__base) (__base + 0x0028) 33 #define LVTS_OFFSETH(__base) (__base + 0x0030) 34 #define LVTS_OFFSETL(__base) (__base + 0x0034) 35 #define LVTS_MSRCTL0(__base) (__base + 0x0038) 36 #define LVTS_MSRCTL1(__base) (__base + 0x003C) 37 #define LVTS_TSSEL(__base) (__base + 0x0040) 38 #define LVTS_CALSCALE(__base) (__base + 0x0048) 39 #define LVTS_ID(__base) (__base + 0x004C) 40 #define LVTS_CONFIG(__base) (__base + 0x0050) 41 #define LVTS_EDATA00(__base) (__base + 0x0054) 42 #define LVTS_EDATA01(__base) (__base + 0x0058) 43 #define LVTS_EDATA02(__base) (__base + 0x005C) 44 #define LVTS_EDATA03(__base) (__base + 0x0060) 45 #define LVTS_MSR0(__base) (__base + 0x0090) 46 #define LVTS_MSR1(__base) (__base + 0x0094) 47 #define LVTS_MSR2(__base) (__base + 0x0098) 48 #define LVTS_MSR3(__base) (__base + 0x009C) 49 #define LVTS_IMMD0(__base) (__base + 0x00A0) 50 #define LVTS_IMMD1(__base) (__base + 0x00A4) 51 #define LVTS_IMMD2(__base) (__base + 0x00A8) 52 #define LVTS_IMMD3(__base) (__base + 0x00AC) 53 #define LVTS_PROTCTL(__base) (__base + 0x00C0) 54 #define LVTS_PROTTA(__base) (__base + 0x00C4) 55 #define LVTS_PROTTB(__base) (__base + 0x00C8) 56 #define LVTS_PROTTC(__base) (__base + 0x00CC) 57 #define LVTS_CLKEN(__base) (__base + 0x00E4) 58 59 #define LVTS_PERIOD_UNIT ((118 * 1000) / (256 * 38)) 60 #define LVTS_GROUP_INTERVAL 1 61 #define LVTS_FILTER_INTERVAL 1 62 #define LVTS_SENSOR_INTERVAL 1 63 #define LVTS_HW_FILTER 0x2 64 #define LVTS_TSSEL_CONF 0x13121110 65 #define LVTS_CALSCALE_CONF 0x300 66 #define LVTS_MONINT_CONF 0x9FBF7BDE 67 68 #define LVTS_INT_SENSOR0 0x0009001F 69 #define LVTS_INT_SENSOR1 0X000881F0 70 #define LVTS_INT_SENSOR2 0x00247C00 71 #define LVTS_INT_SENSOR3 0x1FC00000 72 73 #define LVTS_SENSOR_MAX 4 74 #define LVTS_GOLDEN_TEMP_MAX 62 75 #define LVTS_GOLDEN_TEMP_DEFAULT 50 76 #define LVTS_COEFF_A -250460 77 #define LVTS_COEFF_B 250460 78 79 #define LVTS_MSR_IMMEDIATE_MODE 0 80 #define LVTS_MSR_FILTERED_MODE 1 81 82 #define LVTS_HW_SHUTDOWN_MT8195 105000 83 84 static int golden_temp = LVTS_GOLDEN_TEMP_DEFAULT; 85 static int coeff_b = LVTS_COEFF_B; 86 87 struct lvts_sensor_data { 88 int dt_id; 89 }; 90 91 struct lvts_ctrl_data { 92 struct lvts_sensor_data lvts_sensor[LVTS_SENSOR_MAX]; 93 int cal_offset[LVTS_SENSOR_MAX]; 94 int hw_tshut_temp; 95 int num_lvts_sensor; 96 int offset; 97 int mode; 98 }; 99 100 struct lvts_data { 101 const struct lvts_ctrl_data *lvts_ctrl; 102 int num_lvts_ctrl; 103 }; 104 105 struct lvts_sensor { 106 struct thermal_zone_device *tz; 107 void __iomem *msr; 108 void __iomem *base; 109 int id; 110 int dt_id; 111 }; 112 113 struct lvts_ctrl { 114 struct lvts_sensor sensors[LVTS_SENSOR_MAX]; 115 u32 calibration[LVTS_SENSOR_MAX]; 116 u32 hw_tshut_raw_temp; 117 int num_lvts_sensor; 118 int mode; 119 void __iomem *base; 120 }; 121 122 struct lvts_domain { 123 struct lvts_ctrl *lvts_ctrl; 124 struct reset_control *reset; 125 struct clk *clk; 126 int num_lvts_ctrl; 127 void __iomem *base; 128 size_t calib_len; 129 u8 *calib; 130 #ifdef CONFIG_DEBUG_FS 131 struct dentry *dom_dentry; 132 #endif 133 }; 134 135 #ifdef CONFIG_MTK_LVTS_THERMAL_DEBUGFS 136 137 #define LVTS_DEBUG_FS_REGS(__reg) \ 138 { \ 139 .name = __stringify(__reg), \ 140 .offset = __reg(0), \ 141 } 142 143 static const struct debugfs_reg32 lvts_regs[] = { 144 LVTS_DEBUG_FS_REGS(LVTS_MONCTL0), 145 LVTS_DEBUG_FS_REGS(LVTS_MONCTL1), 146 LVTS_DEBUG_FS_REGS(LVTS_MONCTL2), 147 LVTS_DEBUG_FS_REGS(LVTS_MONINT), 148 LVTS_DEBUG_FS_REGS(LVTS_MONINTSTS), 149 LVTS_DEBUG_FS_REGS(LVTS_MONIDET0), 150 LVTS_DEBUG_FS_REGS(LVTS_MONIDET1), 151 LVTS_DEBUG_FS_REGS(LVTS_MONIDET2), 152 LVTS_DEBUG_FS_REGS(LVTS_MONIDET3), 153 LVTS_DEBUG_FS_REGS(LVTS_H2NTHRE), 154 LVTS_DEBUG_FS_REGS(LVTS_HTHRE), 155 LVTS_DEBUG_FS_REGS(LVTS_OFFSETH), 156 LVTS_DEBUG_FS_REGS(LVTS_OFFSETL), 157 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL0), 158 LVTS_DEBUG_FS_REGS(LVTS_MSRCTL1), 159 LVTS_DEBUG_FS_REGS(LVTS_TSSEL), 160 LVTS_DEBUG_FS_REGS(LVTS_CALSCALE), 161 LVTS_DEBUG_FS_REGS(LVTS_ID), 162 LVTS_DEBUG_FS_REGS(LVTS_CONFIG), 163 LVTS_DEBUG_FS_REGS(LVTS_EDATA00), 164 LVTS_DEBUG_FS_REGS(LVTS_EDATA01), 165 LVTS_DEBUG_FS_REGS(LVTS_EDATA02), 166 LVTS_DEBUG_FS_REGS(LVTS_EDATA03), 167 LVTS_DEBUG_FS_REGS(LVTS_MSR0), 168 LVTS_DEBUG_FS_REGS(LVTS_MSR1), 169 LVTS_DEBUG_FS_REGS(LVTS_MSR2), 170 LVTS_DEBUG_FS_REGS(LVTS_MSR3), 171 LVTS_DEBUG_FS_REGS(LVTS_IMMD0), 172 LVTS_DEBUG_FS_REGS(LVTS_IMMD1), 173 LVTS_DEBUG_FS_REGS(LVTS_IMMD2), 174 LVTS_DEBUG_FS_REGS(LVTS_IMMD3), 175 LVTS_DEBUG_FS_REGS(LVTS_PROTCTL), 176 LVTS_DEBUG_FS_REGS(LVTS_PROTTA), 177 LVTS_DEBUG_FS_REGS(LVTS_PROTTB), 178 LVTS_DEBUG_FS_REGS(LVTS_PROTTC), 179 LVTS_DEBUG_FS_REGS(LVTS_CLKEN), 180 }; 181 182 static int lvts_debugfs_init(struct device *dev, struct lvts_domain *lvts_td) 183 { 184 struct debugfs_regset32 *regset; 185 struct lvts_ctrl *lvts_ctrl; 186 struct dentry *dentry; 187 char name[64]; 188 int i; 189 190 lvts_td->dom_dentry = debugfs_create_dir(dev_name(dev), NULL); 191 if (!lvts_td->dom_dentry) 192 return 0; 193 194 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 195 196 lvts_ctrl = &lvts_td->lvts_ctrl[i]; 197 198 sprintf(name, "controller%d", i); 199 dentry = debugfs_create_dir(name, lvts_td->dom_dentry); 200 if (!dentry) 201 continue; 202 203 regset = devm_kzalloc(dev, sizeof(*regset), GFP_KERNEL); 204 if (!regset) 205 continue; 206 207 regset->base = lvts_ctrl->base; 208 regset->regs = lvts_regs; 209 regset->nregs = ARRAY_SIZE(lvts_regs); 210 211 debugfs_create_regset32("registers", 0400, dentry, regset); 212 } 213 214 return 0; 215 } 216 217 static void lvts_debugfs_exit(struct lvts_domain *lvts_td) 218 { 219 debugfs_remove_recursive(lvts_td->dom_dentry); 220 } 221 222 #else 223 224 static inline int lvts_debugfs_init(struct device *dev, 225 struct lvts_domain *lvts_td) 226 { 227 return 0; 228 } 229 230 static void lvts_debugfs_exit(struct lvts_domain *lvts_td) { } 231 232 #endif 233 234 static int lvts_raw_to_temp(u32 raw_temp) 235 { 236 int temperature; 237 238 temperature = ((s64)(raw_temp & 0xFFFF) * LVTS_COEFF_A) >> 14; 239 temperature += coeff_b; 240 241 return temperature; 242 } 243 244 static u32 lvts_temp_to_raw(int temperature) 245 { 246 u32 raw_temp = ((s64)(coeff_b - temperature)) << 14; 247 248 raw_temp = div_s64(raw_temp, -LVTS_COEFF_A); 249 250 return raw_temp; 251 } 252 253 static int lvts_get_temp(struct thermal_zone_device *tz, int *temp) 254 { 255 struct lvts_sensor *lvts_sensor = tz->devdata; 256 void __iomem *msr = lvts_sensor->msr; 257 u32 value; 258 259 /* 260 * Measurement registers: 261 * 262 * LVTS_MSR[0-3] / LVTS_IMMD[0-3] 263 * 264 * Bits: 265 * 266 * 32-17: Unused 267 * 16 : Valid temperature 268 * 15-0 : Raw temperature 269 */ 270 value = readl(msr); 271 272 /* 273 * As the thermal zone temperature will read before the 274 * hardware sensor is fully initialized, we have to check the 275 * validity of the temperature returned when reading the 276 * measurement register. The thermal controller will set the 277 * valid bit temperature only when it is totally initialized. 278 * 279 * Otherwise, we may end up with garbage values out of the 280 * functionning temperature and directly jump to a system 281 * shutdown. 282 */ 283 if (!(value & BIT(16))) 284 return -EAGAIN; 285 286 *temp = lvts_raw_to_temp(value & 0xFFFF); 287 288 return 0; 289 } 290 291 static int lvts_set_trips(struct thermal_zone_device *tz, int low, int high) 292 { 293 struct lvts_sensor *lvts_sensor = tz->devdata; 294 void __iomem *base = lvts_sensor->base; 295 u32 raw_low = lvts_temp_to_raw(low); 296 u32 raw_high = lvts_temp_to_raw(high); 297 298 /* 299 * Hot to normal temperature threshold 300 * 301 * LVTS_H2NTHRE 302 * 303 * Bits: 304 * 305 * 14-0 : Raw temperature for threshold 306 */ 307 if (low != -INT_MAX) { 308 dev_dbg(&tz->device, "Setting low limit temperature interrupt: %d\n", low); 309 writel(raw_low, LVTS_H2NTHRE(base)); 310 } 311 312 /* 313 * Hot temperature threshold 314 * 315 * LVTS_HTHRE 316 * 317 * Bits: 318 * 319 * 14-0 : Raw temperature for threshold 320 */ 321 dev_dbg(&tz->device, "Setting high limit temperature interrupt: %d\n", high); 322 writel(raw_high, LVTS_HTHRE(base)); 323 324 return 0; 325 } 326 327 static irqreturn_t lvts_ctrl_irq_handler(struct lvts_ctrl *lvts_ctrl) 328 { 329 irqreturn_t iret = IRQ_NONE; 330 u32 value; 331 u32 masks[] = { 332 LVTS_INT_SENSOR0, 333 LVTS_INT_SENSOR1, 334 LVTS_INT_SENSOR2, 335 LVTS_INT_SENSOR3 336 }; 337 int i; 338 339 /* 340 * Interrupt monitoring status 341 * 342 * LVTS_MONINTST 343 * 344 * Bits: 345 * 346 * 31 : Interrupt for stage 3 347 * 30 : Interrupt for stage 2 348 * 29 : Interrupt for state 1 349 * 28 : Interrupt using filter on sensor 3 350 * 351 * 27 : Interrupt using immediate on sensor 3 352 * 26 : Interrupt normal to hot on sensor 3 353 * 25 : Interrupt high offset on sensor 3 354 * 24 : Interrupt low offset on sensor 3 355 * 356 * 23 : Interrupt hot threshold on sensor 3 357 * 22 : Interrupt cold threshold on sensor 3 358 * 21 : Interrupt using filter on sensor 2 359 * 20 : Interrupt using filter on sensor 1 360 * 361 * 19 : Interrupt using filter on sensor 0 362 * 18 : Interrupt using immediate on sensor 2 363 * 17 : Interrupt using immediate on sensor 1 364 * 16 : Interrupt using immediate on sensor 0 365 * 366 * 15 : Interrupt device access timeout interrupt 367 * 14 : Interrupt normal to hot on sensor 2 368 * 13 : Interrupt high offset interrupt on sensor 2 369 * 12 : Interrupt low offset interrupt on sensor 2 370 * 371 * 11 : Interrupt hot threshold on sensor 2 372 * 10 : Interrupt cold threshold on sensor 2 373 * 9 : Interrupt normal to hot on sensor 1 374 * 8 : Interrupt high offset interrupt on sensor 1 375 * 376 * 7 : Interrupt low offset interrupt on sensor 1 377 * 6 : Interrupt hot threshold on sensor 1 378 * 5 : Interrupt cold threshold on sensor 1 379 * 4 : Interrupt normal to hot on sensor 0 380 * 381 * 3 : Interrupt high offset interrupt on sensor 0 382 * 2 : Interrupt low offset interrupt on sensor 0 383 * 1 : Interrupt hot threshold on sensor 0 384 * 0 : Interrupt cold threshold on sensor 0 385 * 386 * We are interested in the sensor(s) responsible of the 387 * interrupt event. We update the thermal framework with the 388 * thermal zone associated with the sensor. The framework will 389 * take care of the rest whatever the kind of interrupt, we 390 * are only interested in which sensor raised the interrupt. 391 * 392 * sensor 3 interrupt: 0001 1111 1100 0000 0000 0000 0000 0000 393 * => 0x1FC00000 394 * sensor 2 interrupt: 0000 0000 0010 0100 0111 1100 0000 0000 395 * => 0x00247C00 396 * sensor 1 interrupt: 0000 0000 0001 0001 0000 0011 1110 0000 397 * => 0X000881F0 398 * sensor 0 interrupt: 0000 0000 0000 1001 0000 0000 0001 1111 399 * => 0x0009001F 400 */ 401 value = readl(LVTS_MONINTSTS(lvts_ctrl->base)); 402 403 /* 404 * Let's figure out which sensors raised the interrupt 405 * 406 * NOTE: the masks array must be ordered with the index 407 * corresponding to the sensor id eg. index=0, mask for 408 * sensor0. 409 */ 410 for (i = 0; i < ARRAY_SIZE(masks); i++) { 411 412 if (!(value & masks[i])) 413 continue; 414 415 thermal_zone_device_update(lvts_ctrl->sensors[i].tz, 416 THERMAL_TRIP_VIOLATED); 417 iret = IRQ_HANDLED; 418 } 419 420 /* 421 * Write back to clear the interrupt status (W1C) 422 */ 423 writel(value, LVTS_MONINTSTS(lvts_ctrl->base)); 424 425 return iret; 426 } 427 428 /* 429 * Temperature interrupt handler. Even if the driver supports more 430 * interrupt modes, we use the interrupt when the temperature crosses 431 * the hot threshold the way up and the way down (modulo the 432 * hysteresis). 433 * 434 * Each thermal domain has a couple of interrupts, one for hardware 435 * reset and another one for all the thermal events happening on the 436 * different sensors. 437 * 438 * The interrupt is configured for thermal events when crossing the 439 * hot temperature limit. At each interrupt, we check in every 440 * controller if there is an interrupt pending. 441 */ 442 static irqreturn_t lvts_irq_handler(int irq, void *data) 443 { 444 struct lvts_domain *lvts_td = data; 445 irqreturn_t aux, iret = IRQ_NONE; 446 int i; 447 448 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 449 450 aux = lvts_ctrl_irq_handler(lvts_td->lvts_ctrl); 451 if (aux != IRQ_HANDLED) 452 continue; 453 454 iret = IRQ_HANDLED; 455 } 456 457 return iret; 458 } 459 460 static struct thermal_zone_device_ops lvts_ops = { 461 .get_temp = lvts_get_temp, 462 .set_trips = lvts_set_trips, 463 }; 464 465 static int lvts_sensor_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, 466 const struct lvts_ctrl_data *lvts_ctrl_data) 467 { 468 struct lvts_sensor *lvts_sensor = lvts_ctrl->sensors; 469 void __iomem *msr_regs[] = { 470 LVTS_MSR0(lvts_ctrl->base), 471 LVTS_MSR1(lvts_ctrl->base), 472 LVTS_MSR2(lvts_ctrl->base), 473 LVTS_MSR3(lvts_ctrl->base) 474 }; 475 476 void __iomem *imm_regs[] = { 477 LVTS_IMMD0(lvts_ctrl->base), 478 LVTS_IMMD1(lvts_ctrl->base), 479 LVTS_IMMD2(lvts_ctrl->base), 480 LVTS_IMMD3(lvts_ctrl->base) 481 }; 482 483 int i; 484 485 for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++) { 486 487 int dt_id = lvts_ctrl_data->lvts_sensor[i].dt_id; 488 489 /* 490 * At this point, we don't know which id matches which 491 * sensor. Let's set arbitrally the id from the index. 492 */ 493 lvts_sensor[i].id = i; 494 495 /* 496 * The thermal zone registration will set the trip 497 * point interrupt in the thermal controller 498 * register. But this one will be reset in the 499 * initialization after. So we need to post pone the 500 * thermal zone creation after the controller is 501 * setup. For this reason, we store the device tree 502 * node id from the data in the sensor structure 503 */ 504 lvts_sensor[i].dt_id = dt_id; 505 506 /* 507 * We assign the base address of the thermal 508 * controller as a back pointer. So it will be 509 * accessible from the different thermal framework ops 510 * as we pass the lvts_sensor pointer as thermal zone 511 * private data. 512 */ 513 lvts_sensor[i].base = lvts_ctrl->base; 514 515 /* 516 * Each sensor has its own register address to read from. 517 */ 518 lvts_sensor[i].msr = lvts_ctrl_data->mode == LVTS_MSR_IMMEDIATE_MODE ? 519 imm_regs[i] : msr_regs[i]; 520 }; 521 522 lvts_ctrl->num_lvts_sensor = lvts_ctrl_data->num_lvts_sensor; 523 524 return 0; 525 } 526 527 /* 528 * The efuse blob values follows the sensor enumeration per thermal 529 * controller. The decoding of the stream is as follow: 530 * 531 * <--?-> <----big0 ???---> <-sensor0-> <-0-> 532 * ------------------------------------------ 533 * index in the stream: : | 0x0 | 0x1 | 0x2 | 0x3 | 0x4 | 0x5 | 0x6 | 534 * ------------------------------------------ 535 * 536 * <--sensor1--><-0-> <----big1 ???---> <-sen 537 * ------------------------------------------ 538 * | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD | 539 * ------------------------------------------ 540 * 541 * sor0-> <-0-> <-sensor1-> <-0-> .......... 542 * ------------------------------------------ 543 * | 0x7 | 0x8 | 0x9 | 0xA | 0xB | OxC | OxD | 544 * ------------------------------------------ 545 * 546 * And so on ... 547 * 548 * The data description gives the offset of the calibration data in 549 * this bytes stream for each sensor. 550 * 551 * Each thermal controller can handle up to 4 sensors max, we don't 552 * care if there are less as the array of calibration is sized to 4 553 * anyway. The unused sensor slot will be zeroed. 554 */ 555 static int lvts_calibration_init(struct device *dev, struct lvts_ctrl *lvts_ctrl, 556 const struct lvts_ctrl_data *lvts_ctrl_data, 557 u8 *efuse_calibration) 558 { 559 int i; 560 561 for (i = 0; i < lvts_ctrl_data->num_lvts_sensor; i++) 562 memcpy(&lvts_ctrl->calibration[i], 563 efuse_calibration + lvts_ctrl_data->cal_offset[i], 2); 564 565 return 0; 566 } 567 568 /* 569 * The efuse bytes stream can be split into different chunk of 570 * nvmems. This function reads and concatenate those into a single 571 * buffer so it can be read sequentially when initializing the 572 * calibration data. 573 */ 574 static int lvts_calibration_read(struct device *dev, struct lvts_domain *lvts_td, 575 const struct lvts_data *lvts_data) 576 { 577 struct device_node *np = dev_of_node(dev); 578 struct nvmem_cell *cell; 579 struct property *prop; 580 const char *cell_name; 581 582 of_property_for_each_string(np, "nvmem-cell-names", prop, cell_name) { 583 size_t len; 584 u8 *efuse; 585 586 cell = of_nvmem_cell_get(np, cell_name); 587 if (IS_ERR(cell)) { 588 dev_err(dev, "Failed to get cell '%s'\n", cell_name); 589 return PTR_ERR(cell); 590 } 591 592 efuse = nvmem_cell_read(cell, &len); 593 594 nvmem_cell_put(cell); 595 596 if (IS_ERR(efuse)) { 597 dev_err(dev, "Failed to read cell '%s'\n", cell_name); 598 return PTR_ERR(efuse); 599 } 600 601 lvts_td->calib = devm_krealloc(dev, lvts_td->calib, 602 lvts_td->calib_len + len, GFP_KERNEL); 603 if (!lvts_td->calib) 604 return -ENOMEM; 605 606 memcpy(lvts_td->calib + lvts_td->calib_len, efuse, len); 607 608 lvts_td->calib_len += len; 609 610 kfree(efuse); 611 } 612 613 return 0; 614 } 615 616 static int lvts_golden_temp_init(struct device *dev, u32 *value) 617 { 618 u32 gt; 619 620 gt = (*value) >> 24; 621 622 if (gt && gt < LVTS_GOLDEN_TEMP_MAX) 623 golden_temp = gt; 624 625 coeff_b = golden_temp * 500 + LVTS_COEFF_B; 626 627 return 0; 628 } 629 630 static int lvts_ctrl_init(struct device *dev, struct lvts_domain *lvts_td, 631 const struct lvts_data *lvts_data) 632 { 633 size_t size = sizeof(*lvts_td->lvts_ctrl) * lvts_data->num_lvts_ctrl; 634 struct lvts_ctrl *lvts_ctrl; 635 int i, ret; 636 637 /* 638 * Create the calibration bytes stream from efuse data 639 */ 640 ret = lvts_calibration_read(dev, lvts_td, lvts_data); 641 if (ret) 642 return ret; 643 644 /* 645 * The golden temp information is contained in the first chunk 646 * of efuse data. 647 */ 648 ret = lvts_golden_temp_init(dev, (u32 *)lvts_td->calib); 649 if (ret) 650 return ret; 651 652 lvts_ctrl = devm_kzalloc(dev, size, GFP_KERNEL); 653 if (!lvts_ctrl) 654 return -ENOMEM; 655 656 for (i = 0; i < lvts_data->num_lvts_ctrl; i++) { 657 658 lvts_ctrl[i].base = lvts_td->base + lvts_data->lvts_ctrl[i].offset; 659 660 ret = lvts_sensor_init(dev, &lvts_ctrl[i], 661 &lvts_data->lvts_ctrl[i]); 662 if (ret) 663 return ret; 664 665 ret = lvts_calibration_init(dev, &lvts_ctrl[i], 666 &lvts_data->lvts_ctrl[i], 667 lvts_td->calib); 668 if (ret) 669 return ret; 670 671 /* 672 * The mode the ctrl will use to read the temperature 673 * (filtered or immediate) 674 */ 675 lvts_ctrl[i].mode = lvts_data->lvts_ctrl[i].mode; 676 677 /* 678 * The temperature to raw temperature must be done 679 * after initializing the calibration. 680 */ 681 lvts_ctrl[i].hw_tshut_raw_temp = 682 lvts_temp_to_raw(lvts_data->lvts_ctrl[i].hw_tshut_temp); 683 } 684 685 /* 686 * We no longer need the efuse bytes stream, let's free it 687 */ 688 devm_kfree(dev, lvts_td->calib); 689 690 lvts_td->lvts_ctrl = lvts_ctrl; 691 lvts_td->num_lvts_ctrl = lvts_data->num_lvts_ctrl; 692 693 return 0; 694 } 695 696 /* 697 * At this point the configuration register is the only place in the 698 * driver where we write multiple values. Per hardware constraint, 699 * each write in the configuration register must be separated by a 700 * delay of 2 us. 701 */ 702 static void lvts_write_config(struct lvts_ctrl *lvts_ctrl, u32 *cmds, int nr_cmds) 703 { 704 int i; 705 706 /* 707 * Configuration register 708 */ 709 for (i = 0; i < nr_cmds; i++) { 710 writel(cmds[i], LVTS_CONFIG(lvts_ctrl->base)); 711 usleep_range(2, 4); 712 } 713 } 714 715 static int lvts_irq_init(struct lvts_ctrl *lvts_ctrl) 716 { 717 /* 718 * LVTS_PROTCTL : Thermal Protection Sensor Selection 719 * 720 * Bits: 721 * 722 * 19-18 : Sensor to base the protection on 723 * 17-16 : Strategy: 724 * 00 : Average of 4 sensors 725 * 01 : Max of 4 sensors 726 * 10 : Selected sensor with bits 19-18 727 * 11 : Reserved 728 */ 729 writel(BIT(16), LVTS_PROTCTL(lvts_ctrl->base)); 730 731 /* 732 * LVTS_PROTTA : Stage 1 temperature threshold 733 * LVTS_PROTTB : Stage 2 temperature threshold 734 * LVTS_PROTTC : Stage 3 temperature threshold 735 * 736 * Bits: 737 * 738 * 14-0: Raw temperature threshold 739 * 740 * writel(0x0, LVTS_PROTTA(lvts_ctrl->base)); 741 * writel(0x0, LVTS_PROTTB(lvts_ctrl->base)); 742 */ 743 writel(lvts_ctrl->hw_tshut_raw_temp, LVTS_PROTTC(lvts_ctrl->base)); 744 745 /* 746 * LVTS_MONINT : Interrupt configuration register 747 * 748 * The LVTS_MONINT register layout is the same as the LVTS_MONINTSTS 749 * register, except we set the bits to enable the interrupt. 750 */ 751 writel(LVTS_MONINT_CONF, LVTS_MONINT(lvts_ctrl->base)); 752 753 return 0; 754 } 755 756 static int lvts_domain_reset(struct device *dev, struct reset_control *reset) 757 { 758 int ret; 759 760 ret = reset_control_assert(reset); 761 if (ret) 762 return ret; 763 764 return reset_control_deassert(reset); 765 } 766 767 /* 768 * Enable or disable the clocks of a specified thermal controller 769 */ 770 static int lvts_ctrl_set_enable(struct lvts_ctrl *lvts_ctrl, int enable) 771 { 772 /* 773 * LVTS_CLKEN : Internal LVTS clock 774 * 775 * Bits: 776 * 777 * 0 : enable / disable clock 778 */ 779 writel(enable, LVTS_CLKEN(lvts_ctrl->base)); 780 781 return 0; 782 } 783 784 static int lvts_ctrl_connect(struct device *dev, struct lvts_ctrl *lvts_ctrl) 785 { 786 u32 id, cmds[] = { 0xC103FFFF, 0xC502FF55 }; 787 788 lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); 789 790 /* 791 * LVTS_ID : Get ID and status of the thermal controller 792 * 793 * Bits: 794 * 795 * 0-5 : thermal controller id 796 * 7 : thermal controller connection is valid 797 */ 798 id = readl(LVTS_ID(lvts_ctrl->base)); 799 if (!(id & BIT(7))) 800 return -EIO; 801 802 return 0; 803 } 804 805 static int lvts_ctrl_initialize(struct device *dev, struct lvts_ctrl *lvts_ctrl) 806 { 807 /* 808 * Write device mask: 0xC1030000 809 */ 810 u32 cmds[] = { 811 0xC1030E01, 0xC1030CFC, 0xC1030A8C, 0xC103098D, 0xC10308F1, 812 0xC10307A6, 0xC10306B8, 0xC1030500, 0xC1030420, 0xC1030300, 813 0xC1030030, 0xC10300F6, 0xC1030050, 0xC1030060, 0xC10300AC, 814 0xC10300FC, 0xC103009D, 0xC10300F1, 0xC10300E1 815 }; 816 817 lvts_write_config(lvts_ctrl, cmds, ARRAY_SIZE(cmds)); 818 819 return 0; 820 } 821 822 static int lvts_ctrl_calibrate(struct device *dev, struct lvts_ctrl *lvts_ctrl) 823 { 824 int i; 825 void __iomem *lvts_edata[] = { 826 LVTS_EDATA00(lvts_ctrl->base), 827 LVTS_EDATA01(lvts_ctrl->base), 828 LVTS_EDATA02(lvts_ctrl->base), 829 LVTS_EDATA03(lvts_ctrl->base) 830 }; 831 832 /* 833 * LVTS_EDATA0X : Efuse calibration reference value for sensor X 834 * 835 * Bits: 836 * 837 * 20-0 : Efuse value for normalization data 838 */ 839 for (i = 0; i < LVTS_SENSOR_MAX; i++) 840 writel(lvts_ctrl->calibration[i], lvts_edata[i]); 841 842 return 0; 843 } 844 845 static int lvts_ctrl_configure(struct device *dev, struct lvts_ctrl *lvts_ctrl) 846 { 847 u32 value; 848 849 /* 850 * LVTS_TSSEL : Sensing point index numbering 851 * 852 * Bits: 853 * 854 * 31-24: ADC Sense 3 855 * 23-16: ADC Sense 2 856 * 15-8 : ADC Sense 1 857 * 7-0 : ADC Sense 0 858 */ 859 value = LVTS_TSSEL_CONF; 860 writel(value, LVTS_TSSEL(lvts_ctrl->base)); 861 862 /* 863 * LVTS_CALSCALE : ADC voltage round 864 */ 865 value = 0x300; 866 value = LVTS_CALSCALE_CONF; 867 868 /* 869 * LVTS_MSRCTL0 : Sensor filtering strategy 870 * 871 * Filters: 872 * 873 * 000 : One sample 874 * 001 : Avg 2 samples 875 * 010 : 4 samples, drop min and max, avg 2 samples 876 * 011 : 6 samples, drop min and max, avg 4 samples 877 * 100 : 10 samples, drop min and max, avg 8 samples 878 * 101 : 18 samples, drop min and max, avg 16 samples 879 * 880 * Bits: 881 * 882 * 0-2 : Sensor0 filter 883 * 3-5 : Sensor1 filter 884 * 6-8 : Sensor2 filter 885 * 9-11 : Sensor3 filter 886 */ 887 value = LVTS_HW_FILTER << 9 | LVTS_HW_FILTER << 6 | 888 LVTS_HW_FILTER << 3 | LVTS_HW_FILTER; 889 writel(value, LVTS_MSRCTL0(lvts_ctrl->base)); 890 891 /* 892 * LVTS_MSRCTL1 : Measurement control 893 * 894 * Bits: 895 * 896 * 9: Ignore MSRCTL0 config and do immediate measurement on sensor3 897 * 6: Ignore MSRCTL0 config and do immediate measurement on sensor2 898 * 5: Ignore MSRCTL0 config and do immediate measurement on sensor1 899 * 4: Ignore MSRCTL0 config and do immediate measurement on sensor0 900 * 901 * That configuration will ignore the filtering and the delays 902 * introduced below in MONCTL1 and MONCTL2 903 */ 904 if (lvts_ctrl->mode == LVTS_MSR_IMMEDIATE_MODE) { 905 value = BIT(9) | BIT(6) | BIT(5) | BIT(4); 906 writel(value, LVTS_MSRCTL1(lvts_ctrl->base)); 907 } 908 909 /* 910 * LVTS_MONCTL1 : Period unit and group interval configuration 911 * 912 * The clock source of LVTS thermal controller is 26MHz. 913 * 914 * The period unit is a time base for all the interval delays 915 * specified in the registers. By default we use 12. The time 916 * conversion is done by multiplying by 256 and 1/26.10^6 917 * 918 * An interval delay multiplied by the period unit gives the 919 * duration in seconds. 920 * 921 * - Filter interval delay is a delay between two samples of 922 * the same sensor. 923 * 924 * - Sensor interval delay is a delay between two samples of 925 * different sensors. 926 * 927 * - Group interval delay is a delay between different rounds. 928 * 929 * For example: 930 * If Period unit = C, filter delay = 1, sensor delay = 2, group delay = 1, 931 * and two sensors, TS1 and TS2, are in a LVTS thermal controller 932 * and then 933 * Period unit time = C * 1/26M * 256 = 12 * 38.46ns * 256 = 118.149us 934 * Filter interval delay = 1 * Period unit = 118.149us 935 * Sensor interval delay = 2 * Period unit = 236.298us 936 * Group interval delay = 1 * Period unit = 118.149us 937 * 938 * TS1 TS1 ... TS1 TS2 TS2 ... TS2 TS1... 939 * <--> Filter interval delay 940 * <--> Sensor interval delay 941 * <--> Group interval delay 942 * Bits: 943 * 29 - 20 : Group interval 944 * 16 - 13 : Send a single interrupt when crossing the hot threshold (1) 945 * or an interrupt everytime the hot threshold is crossed (0) 946 * 9 - 0 : Period unit 947 * 948 */ 949 value = LVTS_GROUP_INTERVAL << 20 | LVTS_PERIOD_UNIT; 950 writel(value, LVTS_MONCTL1(lvts_ctrl->base)); 951 952 /* 953 * LVTS_MONCTL2 : Filtering and sensor interval 954 * 955 * Bits: 956 * 957 * 25-16 : Interval unit in PERIOD_UNIT between sample on 958 * the same sensor, filter interval 959 * 9-0 : Interval unit in PERIOD_UNIT between each sensor 960 * 961 */ 962 value = LVTS_FILTER_INTERVAL << 16 | LVTS_SENSOR_INTERVAL; 963 writel(value, LVTS_MONCTL2(lvts_ctrl->base)); 964 965 return lvts_irq_init(lvts_ctrl); 966 } 967 968 static int lvts_ctrl_start(struct device *dev, struct lvts_ctrl *lvts_ctrl) 969 { 970 struct lvts_sensor *lvts_sensors = lvts_ctrl->sensors; 971 struct thermal_zone_device *tz; 972 u32 sensor_map = 0; 973 int i; 974 975 for (i = 0; i < lvts_ctrl->num_lvts_sensor; i++) { 976 977 int dt_id = lvts_sensors[i].dt_id; 978 979 tz = devm_thermal_of_zone_register(dev, dt_id, &lvts_sensors[i], 980 &lvts_ops); 981 if (IS_ERR(tz)) { 982 /* 983 * This thermal zone is not described in the 984 * device tree. It is not an error from the 985 * thermal OF code POV, we just continue. 986 */ 987 if (PTR_ERR(tz) == -ENODEV) 988 continue; 989 990 return PTR_ERR(tz); 991 } 992 993 /* 994 * The thermal zone pointer will be needed in the 995 * interrupt handler, we store it in the sensor 996 * structure. The thermal domain structure will be 997 * passed to the interrupt handler private data as the 998 * interrupt is shared for all the controller 999 * belonging to the thermal domain. 1000 */ 1001 lvts_sensors[i].tz = tz; 1002 1003 /* 1004 * This sensor was correctly associated with a thermal 1005 * zone, let's set the corresponding bit in the sensor 1006 * map, so we can enable the temperature monitoring in 1007 * the hardware thermal controller. 1008 */ 1009 sensor_map |= BIT(i); 1010 } 1011 1012 /* 1013 * Bits: 1014 * 9: Single point access flow 1015 * 0-3: Enable sensing point 0-3 1016 * 1017 * The initialization of the thermal zones give us 1018 * which sensor point to enable. If any thermal zone 1019 * was not described in the device tree, it won't be 1020 * enabled here in the sensor map. 1021 */ 1022 writel(sensor_map | BIT(9), LVTS_MONCTL0(lvts_ctrl->base)); 1023 1024 return 0; 1025 } 1026 1027 static int lvts_domain_init(struct device *dev, struct lvts_domain *lvts_td, 1028 const struct lvts_data *lvts_data) 1029 { 1030 struct lvts_ctrl *lvts_ctrl; 1031 int i, ret; 1032 1033 ret = lvts_ctrl_init(dev, lvts_td, lvts_data); 1034 if (ret) 1035 return ret; 1036 1037 ret = lvts_domain_reset(dev, lvts_td->reset); 1038 if (ret) { 1039 dev_dbg(dev, "Failed to reset domain"); 1040 return ret; 1041 } 1042 1043 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) { 1044 1045 lvts_ctrl = &lvts_td->lvts_ctrl[i]; 1046 1047 /* 1048 * Initialization steps: 1049 * 1050 * - Enable the clock 1051 * - Connect to the LVTS 1052 * - Initialize the LVTS 1053 * - Prepare the calibration data 1054 * - Select monitored sensors 1055 * [ Configure sampling ] 1056 * [ Configure the interrupt ] 1057 * - Start measurement 1058 */ 1059 ret = lvts_ctrl_set_enable(lvts_ctrl, true); 1060 if (ret) { 1061 dev_dbg(dev, "Failed to enable LVTS clock"); 1062 return ret; 1063 } 1064 1065 ret = lvts_ctrl_connect(dev, lvts_ctrl); 1066 if (ret) { 1067 dev_dbg(dev, "Failed to connect to LVTS controller"); 1068 return ret; 1069 } 1070 1071 ret = lvts_ctrl_initialize(dev, lvts_ctrl); 1072 if (ret) { 1073 dev_dbg(dev, "Failed to initialize controller"); 1074 return ret; 1075 } 1076 1077 ret = lvts_ctrl_calibrate(dev, lvts_ctrl); 1078 if (ret) { 1079 dev_dbg(dev, "Failed to calibrate controller"); 1080 return ret; 1081 } 1082 1083 ret = lvts_ctrl_configure(dev, lvts_ctrl); 1084 if (ret) { 1085 dev_dbg(dev, "Failed to configure controller"); 1086 return ret; 1087 } 1088 1089 ret = lvts_ctrl_start(dev, lvts_ctrl); 1090 if (ret) { 1091 dev_dbg(dev, "Failed to start controller"); 1092 return ret; 1093 } 1094 } 1095 1096 return lvts_debugfs_init(dev, lvts_td); 1097 } 1098 1099 static int lvts_probe(struct platform_device *pdev) 1100 { 1101 const struct lvts_data *lvts_data; 1102 struct lvts_domain *lvts_td; 1103 struct device *dev = &pdev->dev; 1104 struct resource *res; 1105 int irq, ret; 1106 1107 lvts_td = devm_kzalloc(dev, sizeof(*lvts_td), GFP_KERNEL); 1108 if (!lvts_td) 1109 return -ENOMEM; 1110 1111 lvts_data = of_device_get_match_data(dev); 1112 1113 lvts_td->clk = devm_clk_get_enabled(dev, NULL); 1114 if (IS_ERR(lvts_td->clk)) 1115 return dev_err_probe(dev, PTR_ERR(lvts_td->clk), "Failed to retrieve clock\n"); 1116 1117 res = platform_get_mem_or_io(pdev, 0); 1118 if (!res) 1119 return dev_err_probe(dev, (-ENXIO), "No IO resource\n"); 1120 1121 lvts_td->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1122 if (IS_ERR(lvts_td->base)) 1123 return dev_err_probe(dev, PTR_ERR(lvts_td->base), "Failed to map io resource\n"); 1124 1125 lvts_td->reset = devm_reset_control_get_by_index(dev, 0); 1126 if (IS_ERR(lvts_td->reset)) 1127 return dev_err_probe(dev, PTR_ERR(lvts_td->reset), "Failed to get reset control\n"); 1128 1129 irq = platform_get_irq(pdev, 0); 1130 if (irq < 0) 1131 return dev_err_probe(dev, irq, "No irq resource\n"); 1132 1133 ret = lvts_domain_init(dev, lvts_td, lvts_data); 1134 if (ret) 1135 return dev_err_probe(dev, ret, "Failed to initialize the lvts domain\n"); 1136 1137 /* 1138 * At this point the LVTS is initialized and enabled. We can 1139 * safely enable the interrupt. 1140 */ 1141 ret = devm_request_threaded_irq(dev, irq, NULL, lvts_irq_handler, 1142 IRQF_ONESHOT, dev_name(dev), lvts_td); 1143 if (ret) 1144 return dev_err_probe(dev, ret, "Failed to request interrupt\n"); 1145 1146 platform_set_drvdata(pdev, lvts_td); 1147 1148 return 0; 1149 } 1150 1151 static int lvts_remove(struct platform_device *pdev) 1152 { 1153 struct lvts_domain *lvts_td; 1154 int i; 1155 1156 lvts_td = platform_get_drvdata(pdev); 1157 1158 for (i = 0; i < lvts_td->num_lvts_ctrl; i++) 1159 lvts_ctrl_set_enable(&lvts_td->lvts_ctrl[i], false); 1160 1161 lvts_debugfs_exit(lvts_td); 1162 1163 return 0; 1164 } 1165 1166 static const struct lvts_ctrl_data mt8195_lvts_data_ctrl[] = { 1167 { 1168 .cal_offset = { 0x04, 0x07 }, 1169 .lvts_sensor = { 1170 { .dt_id = MT8195_MCU_BIG_CPU0 }, 1171 { .dt_id = MT8195_MCU_BIG_CPU1 } 1172 }, 1173 .num_lvts_sensor = 2, 1174 .offset = 0x0, 1175 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1176 }, 1177 { 1178 .cal_offset = { 0x0d, 0x10 }, 1179 .lvts_sensor = { 1180 { .dt_id = MT8195_MCU_BIG_CPU2 }, 1181 { .dt_id = MT8195_MCU_BIG_CPU3 } 1182 }, 1183 .num_lvts_sensor = 2, 1184 .offset = 0x100, 1185 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1186 }, 1187 { 1188 .cal_offset = { 0x16, 0x19, 0x1c, 0x1f }, 1189 .lvts_sensor = { 1190 { .dt_id = MT8195_MCU_LITTLE_CPU0 }, 1191 { .dt_id = MT8195_MCU_LITTLE_CPU1 }, 1192 { .dt_id = MT8195_MCU_LITTLE_CPU2 }, 1193 { .dt_id = MT8195_MCU_LITTLE_CPU3 } 1194 }, 1195 .num_lvts_sensor = 4, 1196 .offset = 0x200, 1197 .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT8195, 1198 } 1199 }; 1200 1201 static const struct lvts_data mt8195_lvts_mcu_data = { 1202 .lvts_ctrl = mt8195_lvts_data_ctrl, 1203 .num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_data_ctrl), 1204 }; 1205 1206 static const struct of_device_id lvts_of_match[] = { 1207 { .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data }, 1208 {}, 1209 }; 1210 MODULE_DEVICE_TABLE(of, lvts_of_match); 1211 1212 static struct platform_driver lvts_driver = { 1213 .probe = lvts_probe, 1214 .remove = lvts_remove, 1215 .driver = { 1216 .name = "mtk-lvts-thermal", 1217 .of_match_table = lvts_of_match, 1218 }, 1219 }; 1220 module_platform_driver(lvts_driver); 1221 1222 MODULE_AUTHOR("Balsam CHIHI <bchihi@baylibre.com>"); 1223 MODULE_DESCRIPTION("MediaTek LVTS Thermal Driver"); 1224 MODULE_LICENSE("GPL"); 1225