1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * processor_thermal_device.h 4 * Copyright (c) 2020, Intel Corporation. 5 */ 6 7 #ifndef __PROCESSOR_THERMAL_DEVICE_H__ 8 #define __PROCESSOR_THERMAL_DEVICE_H__ 9 10 #include <linux/intel_rapl.h> 11 12 #define PCI_DEVICE_ID_INTEL_ADL_THERMAL 0x461d 13 #define PCI_DEVICE_ID_INTEL_ARL_S_THERMAL 0xAD03 14 #define PCI_DEVICE_ID_INTEL_BDW_THERMAL 0x1603 15 #define PCI_DEVICE_ID_INTEL_BSW_THERMAL 0x22DC 16 17 #define PCI_DEVICE_ID_INTEL_BXT0_THERMAL 0x0A8C 18 #define PCI_DEVICE_ID_INTEL_BXT1_THERMAL 0x1A8C 19 #define PCI_DEVICE_ID_INTEL_BXTX_THERMAL 0x4A8C 20 #define PCI_DEVICE_ID_INTEL_BXTP_THERMAL 0x5A8C 21 22 #define PCI_DEVICE_ID_INTEL_CNL_THERMAL 0x5a03 23 #define PCI_DEVICE_ID_INTEL_CFL_THERMAL 0x3E83 24 #define PCI_DEVICE_ID_INTEL_GLK_THERMAL 0x318C 25 #define PCI_DEVICE_ID_INTEL_HSB_THERMAL 0x0A03 26 #define PCI_DEVICE_ID_INTEL_ICL_THERMAL 0x8a03 27 #define PCI_DEVICE_ID_INTEL_JSL_THERMAL 0x4E03 28 #define PCI_DEVICE_ID_INTEL_LNLM_THERMAL 0x641D 29 #define PCI_DEVICE_ID_INTEL_MTLP_THERMAL 0x7D03 30 #define PCI_DEVICE_ID_INTEL_NVL_H_THERMAL 0xD703 31 #define PCI_DEVICE_ID_INTEL_NVL_S_THERMAL 0xAD03 32 #define PCI_DEVICE_ID_INTEL_RPL_THERMAL 0xA71D 33 #define PCI_DEVICE_ID_INTEL_SKL_THERMAL 0x1903 34 #define PCI_DEVICE_ID_INTEL_TGL_THERMAL 0x9A03 35 #define PCI_DEVICE_ID_INTEL_PTL_THERMAL 0xB01D 36 #define PCI_DEVICE_ID_INTEL_WCL_THERMAL 0xFD1D 37 38 struct power_config { 39 u32 index; 40 u32 min_uw; 41 u32 max_uw; 42 u32 tmin_us; 43 u32 tmax_us; 44 u32 step_uw; 45 }; 46 47 struct proc_thermal_device { 48 struct device *dev; 49 struct acpi_device *adev; 50 struct power_config power_limits[2]; 51 struct int34x_thermal_zone *int340x_zone; 52 struct intel_soc_dts_sensors *soc_dts; 53 u32 mmio_feature_mask; 54 void __iomem *mmio_base; 55 void *priv_data; 56 }; 57 58 struct rapl_mmio_regs { 59 u64 reg_unit; 60 u64 regs[RAPL_DOMAIN_MAX][RAPL_DOMAIN_REG_MAX]; 61 int limits[RAPL_DOMAIN_MAX]; 62 }; 63 64 #define PROC_THERMAL_FEATURE_NONE 0x00 65 #define PROC_THERMAL_FEATURE_RAPL 0x01 66 #define PROC_THERMAL_FEATURE_FIVR 0x02 67 #define PROC_THERMAL_FEATURE_DVFS 0x04 68 #define PROC_THERMAL_FEATURE_WT_REQ 0x08 69 #define PROC_THERMAL_FEATURE_DLVR 0x10 70 #define PROC_THERMAL_FEATURE_WT_HINT 0x20 71 #define PROC_THERMAL_FEATURE_POWER_FLOOR 0x40 72 #define PROC_THERMAL_FEATURE_MSI_SUPPORT 0x80 73 #define PROC_THERMAL_FEATURE_PTC 0x100 74 #define PROC_THERMAL_FEATURE_SOC_POWER_SLIDER 0x200 75 76 #if IS_ENABLED(CONFIG_PROC_THERMAL_MMIO_RAPL) 77 int proc_thermal_rapl_add(struct pci_dev *pdev, struct proc_thermal_device *proc_priv); 78 void proc_thermal_rapl_remove(void); 79 #else 80 static int __maybe_unused proc_thermal_rapl_add(struct pci_dev *pdev, 81 struct proc_thermal_device *proc_priv) 82 { 83 return 0; 84 } 85 86 static void __maybe_unused proc_thermal_rapl_remove(void) 87 { 88 } 89 #endif 90 91 int proc_thermal_rfim_add(struct pci_dev *pdev, struct proc_thermal_device *proc_priv); 92 void proc_thermal_rfim_remove(struct pci_dev *pdev); 93 94 int proc_thermal_wt_req_add(struct pci_dev *pdev, struct proc_thermal_device *proc_priv); 95 void proc_thermal_wt_req_remove(struct pci_dev *pdev); 96 97 #define MBOX_CMD_WORKLOAD_TYPE_READ 0x0E 98 #define MBOX_CMD_WORKLOAD_TYPE_WRITE 0x0F 99 100 #define MBOX_DATA_BIT_AC_DC 30 101 #define MBOX_DATA_BIT_VALID 31 102 103 #define SOC_WT_RES_INT_STATUS_OFFSET 0x5B18 104 #define SOC_WT_RES_INT_STATUS_MASK GENMASK_ULL(3, 2) 105 106 int proc_thermal_read_power_floor_status(struct proc_thermal_device *proc_priv); 107 int proc_thermal_power_floor_set_state(struct proc_thermal_device *proc_priv, bool enable); 108 bool proc_thermal_power_floor_get_state(struct proc_thermal_device *proc_priv); 109 void proc_thermal_power_floor_intr_callback(struct pci_dev *pdev, 110 struct proc_thermal_device *proc_priv); 111 bool proc_thermal_check_power_floor_intr(struct proc_thermal_device *proc_priv); 112 113 int processor_thermal_send_mbox_read_cmd(struct pci_dev *pdev, u16 id, u64 *resp); 114 int processor_thermal_send_mbox_write_cmd(struct pci_dev *pdev, u16 id, u32 data); 115 int processor_thermal_mbox_interrupt_config(struct pci_dev *pdev, bool enable, int enable_bit, 116 int time_window); 117 int proc_thermal_add(struct device *dev, struct proc_thermal_device *priv); 118 void proc_thermal_remove(struct proc_thermal_device *proc_priv); 119 120 int proc_thermal_wt_hint_add(struct pci_dev *pdev, struct proc_thermal_device *proc_priv); 121 void proc_thermal_wt_hint_remove(struct pci_dev *pdev); 122 void proc_thermal_wt_intr_callback(struct pci_dev *pdev, struct proc_thermal_device *proc_priv); 123 bool proc_thermal_check_wt_intr(struct proc_thermal_device *proc_priv); 124 125 int proc_thermal_suspend(struct device *dev); 126 int proc_thermal_resume(struct device *dev); 127 int proc_thermal_mmio_add(struct pci_dev *pdev, 128 struct proc_thermal_device *proc_priv, 129 kernel_ulong_t feature_mask); 130 void proc_thermal_mmio_remove(struct pci_dev *pdev, struct proc_thermal_device *proc_priv); 131 int proc_thermal_ptc_add(struct pci_dev *pdev, struct proc_thermal_device *proc_priv); 132 void proc_thermal_ptc_remove(struct pci_dev *pdev); 133 134 int proc_thermal_soc_power_slider_add(struct pci_dev *pdev, struct proc_thermal_device *proc_priv); 135 void proc_thermal_soc_power_slider_suspend(struct proc_thermal_device *proc_priv); 136 void proc_thermal_soc_power_slider_resume(struct proc_thermal_device *proc_priv); 137 138 #endif 139