1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright 2020 NXP. 4 * 5 * Author: Anson Huang <Anson.Huang@nxp.com> 6 */ 7 8 #include <linux/bitfield.h> 9 #include <linux/clk.h> 10 #include <linux/err.h> 11 #include <linux/io.h> 12 #include <linux/module.h> 13 #include <linux/nvmem-consumer.h> 14 #include <linux/of.h> 15 #include <linux/platform_device.h> 16 #include <linux/slab.h> 17 #include <linux/thermal.h> 18 19 #include "thermal_hwmon.h" 20 21 #define TER 0x0 /* TMU enable */ 22 #define TPS 0x4 23 #define TRITSR 0x20 /* TMU immediate temp */ 24 /* TMU calibration data registers */ 25 #define TASR 0x28 26 #define TASR_BUF_SLOPE_MASK GENMASK(19, 16) 27 #define TASR_BUF_VREF_MASK GENMASK(4, 0) /* TMU_V1 */ 28 #define TASR_BUF_VERF_SEL_MASK GENMASK(1, 0) /* TMU_V2 */ 29 #define TCALIV(n) (0x30 + ((n) * 4)) 30 #define TCALIV_EN BIT(31) 31 #define TCALIV_HR_MASK GENMASK(23, 16) /* TMU_V1 */ 32 #define TCALIV_RT_MASK GENMASK(7, 0) /* TMU_V1 */ 33 #define TCALIV_SNSR105C_MASK GENMASK(27, 16) /* TMU_V2 */ 34 #define TCALIV_SNSR25C_MASK GENMASK(11, 0) /* TMU_V2 */ 35 #define TRIM 0x3c 36 #define TRIM_BJT_CUR_MASK GENMASK(23, 20) 37 #define TRIM_BGR_MASK GENMASK(31, 28) 38 #define TRIM_VLSB_MASK GENMASK(15, 12) 39 #define TRIM_EN_CH BIT(7) 40 41 #define TER_ADC_PD BIT(30) 42 #define TER_EN BIT(31) 43 #define TRITSR_TEMP0_VAL_MASK GENMASK(7, 0) 44 #define TRITSR_TEMP1_VAL_MASK GENMASK(23, 16) 45 46 #define PROBE_SEL_ALL GENMASK(31, 30) 47 48 #define probe_status_offset(x) (30 + x) 49 #define SIGN_BIT BIT(7) 50 #define TEMP_VAL_MASK GENMASK(6, 0) 51 52 /* TMU OCOTP calibration data bitfields */ 53 #define ANA0_EN BIT(25) 54 #define ANA0_BUF_VREF_MASK GENMASK(24, 20) 55 #define ANA0_BUF_SLOPE_MASK GENMASK(19, 16) 56 #define ANA0_HR_MASK GENMASK(15, 8) 57 #define ANA0_RT_MASK GENMASK(7, 0) 58 #define TRIM2_VLSB_MASK GENMASK(23, 20) 59 #define TRIM2_BGR_MASK GENMASK(19, 16) 60 #define TRIM2_BJT_CUR_MASK GENMASK(15, 12) 61 #define TRIM2_BUF_SLOP_SEL_MASK GENMASK(11, 8) 62 #define TRIM2_BUF_VERF_SEL_MASK GENMASK(7, 6) 63 #define TRIM3_TCA25_0_LSB_MASK GENMASK(31, 28) 64 #define TRIM3_TCA40_0_MASK GENMASK(27, 16) 65 #define TRIM4_TCA40_1_MASK GENMASK(31, 20) 66 #define TRIM4_TCA105_0_MASK GENMASK(19, 8) 67 #define TRIM4_TCA25_0_MSB_MASK GENMASK(7, 0) 68 #define TRIM5_TCA105_1_MASK GENMASK(23, 12) 69 #define TRIM5_TCA25_1_MASK GENMASK(11, 0) 70 71 #define VER1_TEMP_LOW_LIMIT 10000 72 #define VER2_TEMP_LOW_LIMIT -40000 73 #define VER2_TEMP_HIGH_LIMIT 125000 74 75 #define TMU_VER1 0x1 76 #define TMU_VER2 0x2 77 78 struct thermal_soc_data { 79 u32 num_sensors; 80 u32 version; 81 int (*get_temp)(void *, int *); 82 }; 83 84 struct tmu_sensor { 85 struct imx8mm_tmu *priv; 86 u32 hw_id; 87 struct thermal_zone_device *tzd; 88 }; 89 90 struct imx8mm_tmu { 91 void __iomem *base; 92 struct clk *clk; 93 const struct thermal_soc_data *socdata; 94 struct tmu_sensor sensors[]; 95 }; 96 97 static int imx8mm_tmu_get_temp(void *data, int *temp) 98 { 99 struct tmu_sensor *sensor = data; 100 struct imx8mm_tmu *tmu = sensor->priv; 101 u32 val; 102 103 val = readl_relaxed(tmu->base + TRITSR) & TRITSR_TEMP0_VAL_MASK; 104 105 /* 106 * Do not validate against the V bit (bit 31) due to errata 107 * ERR051272: TMU: Bit 31 of registers TMU_TSCR/TMU_TRITSR/TMU_TRATSR invalid 108 */ 109 110 *temp = val * 1000; 111 if (*temp < VER1_TEMP_LOW_LIMIT || *temp > VER2_TEMP_HIGH_LIMIT) 112 return -EAGAIN; 113 114 return 0; 115 } 116 117 static int imx8mp_tmu_get_temp(void *data, int *temp) 118 { 119 struct tmu_sensor *sensor = data; 120 struct imx8mm_tmu *tmu = sensor->priv; 121 unsigned long val; 122 bool ready; 123 124 val = readl_relaxed(tmu->base + TRITSR); 125 ready = test_bit(probe_status_offset(sensor->hw_id), &val); 126 if (!ready) 127 return -EAGAIN; 128 129 val = sensor->hw_id ? FIELD_GET(TRITSR_TEMP1_VAL_MASK, val) : 130 FIELD_GET(TRITSR_TEMP0_VAL_MASK, val); 131 if (val & SIGN_BIT) /* negative */ 132 val = (~(val & TEMP_VAL_MASK) + 1); 133 134 *temp = val * 1000; 135 if (*temp < VER2_TEMP_LOW_LIMIT || *temp > VER2_TEMP_HIGH_LIMIT) 136 return -EAGAIN; 137 138 return 0; 139 } 140 141 static int tmu_get_temp(struct thermal_zone_device *tz, int *temp) 142 { 143 struct tmu_sensor *sensor = thermal_zone_device_priv(tz); 144 struct imx8mm_tmu *tmu = sensor->priv; 145 146 return tmu->socdata->get_temp(sensor, temp); 147 } 148 149 static const struct thermal_zone_device_ops tmu_tz_ops = { 150 .get_temp = tmu_get_temp, 151 }; 152 153 static void imx8mm_tmu_enable(struct imx8mm_tmu *tmu, bool enable) 154 { 155 u32 val; 156 157 val = readl_relaxed(tmu->base + TER); 158 val = enable ? (val | TER_EN) : (val & ~TER_EN); 159 if (tmu->socdata->version == TMU_VER2) 160 val = enable ? (val & ~TER_ADC_PD) : (val | TER_ADC_PD); 161 writel_relaxed(val, tmu->base + TER); 162 } 163 164 static void imx8mm_tmu_probe_sel_all(struct imx8mm_tmu *tmu) 165 { 166 u32 val; 167 168 val = readl_relaxed(tmu->base + TPS); 169 val |= PROBE_SEL_ALL; 170 writel_relaxed(val, tmu->base + TPS); 171 } 172 173 static int imx8mm_tmu_probe_set_calib_v1(struct platform_device *pdev, 174 struct imx8mm_tmu *tmu) 175 { 176 struct device *dev = &pdev->dev; 177 u32 ana0; 178 int ret; 179 180 ret = nvmem_cell_read_u32(&pdev->dev, "calib", &ana0); 181 if (ret) { 182 dev_warn(dev, "Failed to read OCOTP nvmem cell (%d).\n", ret); 183 return ret; 184 } 185 186 writel(FIELD_PREP(TASR_BUF_VREF_MASK, 187 FIELD_GET(ANA0_BUF_VREF_MASK, ana0)) | 188 FIELD_PREP(TASR_BUF_SLOPE_MASK, 189 FIELD_GET(ANA0_BUF_SLOPE_MASK, ana0)), 190 tmu->base + TASR); 191 192 writel(FIELD_PREP(TCALIV_RT_MASK, FIELD_GET(ANA0_RT_MASK, ana0)) | 193 FIELD_PREP(TCALIV_HR_MASK, FIELD_GET(ANA0_HR_MASK, ana0)) | 194 ((ana0 & ANA0_EN) ? TCALIV_EN : 0), 195 tmu->base + TCALIV(0)); 196 197 return 0; 198 } 199 200 static int imx8mm_tmu_probe_set_calib_v2(struct platform_device *pdev, 201 struct imx8mm_tmu *tmu) 202 { 203 struct device *dev = &pdev->dev; 204 struct nvmem_cell *cell; 205 u32 trim[4] = { 0 }; 206 size_t len; 207 void *buf; 208 209 cell = nvmem_cell_get(dev, "calib"); 210 if (IS_ERR(cell)) 211 return PTR_ERR(cell); 212 213 buf = nvmem_cell_read(cell, &len); 214 nvmem_cell_put(cell); 215 216 if (IS_ERR(buf)) 217 return PTR_ERR(buf); 218 219 memcpy(trim, buf, min(len, sizeof(trim))); 220 kfree(buf); 221 222 if (len != 16) { 223 dev_err(dev, 224 "OCOTP nvmem cell length is %zu, must be 16.\n", len); 225 return -EINVAL; 226 } 227 228 /* Blank sample hardware */ 229 if (!trim[0] && !trim[1] && !trim[2] && !trim[3]) { 230 /* Use a default 25C binary codes */ 231 writel(FIELD_PREP(TCALIV_SNSR25C_MASK, 0x63c), 232 tmu->base + TCALIV(0)); 233 writel(FIELD_PREP(TCALIV_SNSR25C_MASK, 0x63c), 234 tmu->base + TCALIV(1)); 235 return 0; 236 } 237 238 writel(FIELD_PREP(TASR_BUF_VERF_SEL_MASK, 239 FIELD_GET(TRIM2_BUF_VERF_SEL_MASK, trim[0])) | 240 FIELD_PREP(TASR_BUF_SLOPE_MASK, 241 FIELD_GET(TRIM2_BUF_SLOP_SEL_MASK, trim[0])), 242 tmu->base + TASR); 243 244 writel(FIELD_PREP(TRIM_BJT_CUR_MASK, 245 FIELD_GET(TRIM2_BJT_CUR_MASK, trim[0])) | 246 FIELD_PREP(TRIM_BGR_MASK, FIELD_GET(TRIM2_BGR_MASK, trim[0])) | 247 FIELD_PREP(TRIM_VLSB_MASK, FIELD_GET(TRIM2_VLSB_MASK, trim[0])) | 248 TRIM_EN_CH, 249 tmu->base + TRIM); 250 251 writel(FIELD_PREP(TCALIV_SNSR25C_MASK, 252 FIELD_GET(TRIM3_TCA25_0_LSB_MASK, trim[1]) | 253 (FIELD_GET(TRIM4_TCA25_0_MSB_MASK, trim[2]) << 4)) | 254 FIELD_PREP(TCALIV_SNSR105C_MASK, 255 FIELD_GET(TRIM4_TCA105_0_MASK, trim[2])), 256 tmu->base + TCALIV(0)); 257 258 writel(FIELD_PREP(TCALIV_SNSR25C_MASK, 259 FIELD_GET(TRIM5_TCA25_1_MASK, trim[3])) | 260 FIELD_PREP(TCALIV_SNSR105C_MASK, 261 FIELD_GET(TRIM5_TCA105_1_MASK, trim[3])), 262 tmu->base + TCALIV(1)); 263 264 writel(FIELD_PREP(TCALIV_SNSR25C_MASK, 265 FIELD_GET(TRIM3_TCA40_0_MASK, trim[1])) | 266 FIELD_PREP(TCALIV_SNSR105C_MASK, 267 FIELD_GET(TRIM4_TCA40_1_MASK, trim[2])), 268 tmu->base + TCALIV(2)); 269 270 return 0; 271 } 272 273 static int imx8mm_tmu_probe_set_calib(struct platform_device *pdev, 274 struct imx8mm_tmu *tmu) 275 { 276 struct device *dev = &pdev->dev; 277 278 /* 279 * Lack of calibration data OCOTP reference is not considered 280 * fatal to retain compatibility with old DTs. It is however 281 * strongly recommended to update such old DTs to get correct 282 * temperature compensation values for each SoC. 283 */ 284 if (!of_property_present(pdev->dev.of_node, "nvmem-cells")) { 285 dev_warn(dev, 286 "No OCOTP nvmem reference found, SoC-specific calibration not loaded. Please update your DT.\n"); 287 return 0; 288 } 289 290 if (tmu->socdata->version == TMU_VER1) 291 return imx8mm_tmu_probe_set_calib_v1(pdev, tmu); 292 293 return imx8mm_tmu_probe_set_calib_v2(pdev, tmu); 294 } 295 296 static int imx8mm_tmu_probe(struct platform_device *pdev) 297 { 298 const struct thermal_soc_data *data; 299 struct imx8mm_tmu *tmu; 300 int ret; 301 int i; 302 303 data = of_device_get_match_data(&pdev->dev); 304 305 tmu = devm_kzalloc(&pdev->dev, struct_size(tmu, sensors, 306 data->num_sensors), GFP_KERNEL); 307 if (!tmu) 308 return -ENOMEM; 309 310 tmu->socdata = data; 311 312 tmu->base = devm_platform_ioremap_resource(pdev, 0); 313 if (IS_ERR(tmu->base)) 314 return PTR_ERR(tmu->base); 315 316 tmu->clk = devm_clk_get(&pdev->dev, NULL); 317 if (IS_ERR(tmu->clk)) 318 return dev_err_probe(&pdev->dev, PTR_ERR(tmu->clk), 319 "failed to get tmu clock\n"); 320 321 ret = clk_prepare_enable(tmu->clk); 322 if (ret) { 323 dev_err(&pdev->dev, "failed to enable tmu clock: %d\n", ret); 324 return ret; 325 } 326 327 /* disable the monitor during initialization */ 328 imx8mm_tmu_enable(tmu, false); 329 330 for (i = 0; i < data->num_sensors; i++) { 331 tmu->sensors[i].priv = tmu; 332 tmu->sensors[i].tzd = 333 devm_thermal_of_zone_register(&pdev->dev, i, 334 &tmu->sensors[i], 335 &tmu_tz_ops); 336 if (IS_ERR(tmu->sensors[i].tzd)) { 337 ret = PTR_ERR(tmu->sensors[i].tzd); 338 dev_err(&pdev->dev, 339 "failed to register thermal zone sensor[%d]: %d\n", 340 i, ret); 341 goto disable_clk; 342 } 343 tmu->sensors[i].hw_id = i; 344 345 devm_thermal_add_hwmon_sysfs(&pdev->dev, tmu->sensors[i].tzd); 346 } 347 348 platform_set_drvdata(pdev, tmu); 349 350 ret = imx8mm_tmu_probe_set_calib(pdev, tmu); 351 if (ret) 352 goto disable_clk; 353 354 /* enable all the probes for V2 TMU */ 355 if (tmu->socdata->version == TMU_VER2) 356 imx8mm_tmu_probe_sel_all(tmu); 357 358 /* enable the monitor */ 359 imx8mm_tmu_enable(tmu, true); 360 361 return 0; 362 363 disable_clk: 364 clk_disable_unprepare(tmu->clk); 365 return ret; 366 } 367 368 static int imx8mm_tmu_remove(struct platform_device *pdev) 369 { 370 struct imx8mm_tmu *tmu = platform_get_drvdata(pdev); 371 372 /* disable TMU */ 373 imx8mm_tmu_enable(tmu, false); 374 375 clk_disable_unprepare(tmu->clk); 376 platform_set_drvdata(pdev, NULL); 377 378 return 0; 379 } 380 381 static struct thermal_soc_data imx8mm_tmu_data = { 382 .num_sensors = 1, 383 .version = TMU_VER1, 384 .get_temp = imx8mm_tmu_get_temp, 385 }; 386 387 static struct thermal_soc_data imx8mp_tmu_data = { 388 .num_sensors = 2, 389 .version = TMU_VER2, 390 .get_temp = imx8mp_tmu_get_temp, 391 }; 392 393 static const struct of_device_id imx8mm_tmu_table[] = { 394 { .compatible = "fsl,imx8mm-tmu", .data = &imx8mm_tmu_data, }, 395 { .compatible = "fsl,imx8mp-tmu", .data = &imx8mp_tmu_data, }, 396 { }, 397 }; 398 MODULE_DEVICE_TABLE(of, imx8mm_tmu_table); 399 400 static struct platform_driver imx8mm_tmu = { 401 .driver = { 402 .name = "i.mx8mm_thermal", 403 .of_match_table = imx8mm_tmu_table, 404 }, 405 .probe = imx8mm_tmu_probe, 406 .remove = imx8mm_tmu_remove, 407 }; 408 module_platform_driver(imx8mm_tmu); 409 410 MODULE_AUTHOR("Anson Huang <Anson.Huang@nxp.com>"); 411 MODULE_DESCRIPTION("i.MX8MM Thermal Monitor Unit driver"); 412 MODULE_LICENSE("GPL v2"); 413