1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Xilinx AXIS FIFO: interface to the Xilinx AXI-Stream FIFO IP core 4 * 5 * Copyright (C) 2018 Jacob Feder 6 * 7 * Authors: Jacob Feder <jacobsfeder@gmail.com> 8 * 9 * See Xilinx PG080 document for IP details 10 */ 11 12 /* ---------------------------- 13 * includes 14 * ---------------------------- 15 */ 16 17 #include <linux/kernel.h> 18 #include <linux/wait.h> 19 #include <linux/mutex.h> 20 #include <linux/device.h> 21 #include <linux/cdev.h> 22 #include <linux/init.h> 23 #include <linux/module.h> 24 #include <linux/slab.h> 25 #include <linux/io.h> 26 #include <linux/moduleparam.h> 27 #include <linux/interrupt.h> 28 #include <linux/param.h> 29 #include <linux/fs.h> 30 #include <linux/types.h> 31 #include <linux/uaccess.h> 32 #include <linux/jiffies.h> 33 #include <linux/miscdevice.h> 34 35 #include <linux/of_address.h> 36 #include <linux/of_device.h> 37 #include <linux/of_platform.h> 38 39 /* ---------------------------- 40 * driver parameters 41 * ---------------------------- 42 */ 43 44 #define DRIVER_NAME "axis_fifo" 45 46 #define READ_BUF_SIZE 128U /* read buffer length in words */ 47 #define WRITE_BUF_SIZE 128U /* write buffer length in words */ 48 49 /* ---------------------------- 50 * IP register offsets 51 * ---------------------------- 52 */ 53 54 #define XLLF_ISR_OFFSET 0x00000000 /* Interrupt Status */ 55 #define XLLF_IER_OFFSET 0x00000004 /* Interrupt Enable */ 56 57 #define XLLF_TDFR_OFFSET 0x00000008 /* Transmit Reset */ 58 #define XLLF_TDFV_OFFSET 0x0000000c /* Transmit Vacancy */ 59 #define XLLF_TDFD_OFFSET 0x00000010 /* Transmit Data */ 60 #define XLLF_TLR_OFFSET 0x00000014 /* Transmit Length */ 61 62 #define XLLF_RDFR_OFFSET 0x00000018 /* Receive Reset */ 63 #define XLLF_RDFO_OFFSET 0x0000001c /* Receive Occupancy */ 64 #define XLLF_RDFD_OFFSET 0x00000020 /* Receive Data */ 65 #define XLLF_RLR_OFFSET 0x00000024 /* Receive Length */ 66 #define XLLF_SRR_OFFSET 0x00000028 /* Local Link Reset */ 67 #define XLLF_TDR_OFFSET 0x0000002C /* Transmit Destination */ 68 #define XLLF_RDR_OFFSET 0x00000030 /* Receive Destination */ 69 70 /* ---------------------------- 71 * reset register masks 72 * ---------------------------- 73 */ 74 75 #define XLLF_RDFR_RESET_MASK 0x000000a5 /* receive reset value */ 76 #define XLLF_TDFR_RESET_MASK 0x000000a5 /* Transmit reset value */ 77 #define XLLF_SRR_RESET_MASK 0x000000a5 /* Local Link reset value */ 78 79 /* ---------------------------- 80 * interrupt masks 81 * ---------------------------- 82 */ 83 84 #define XLLF_INT_RPURE_MASK 0x80000000 /* Receive under-read */ 85 #define XLLF_INT_RPORE_MASK 0x40000000 /* Receive over-read */ 86 #define XLLF_INT_RPUE_MASK 0x20000000 /* Receive underrun (empty) */ 87 #define XLLF_INT_TPOE_MASK 0x10000000 /* Transmit overrun */ 88 #define XLLF_INT_TC_MASK 0x08000000 /* Transmit complete */ 89 #define XLLF_INT_RC_MASK 0x04000000 /* Receive complete */ 90 #define XLLF_INT_TSE_MASK 0x02000000 /* Transmit length mismatch */ 91 #define XLLF_INT_TRC_MASK 0x01000000 /* Transmit reset complete */ 92 #define XLLF_INT_RRC_MASK 0x00800000 /* Receive reset complete */ 93 #define XLLF_INT_TFPF_MASK 0x00400000 /* Tx FIFO Programmable Full */ 94 #define XLLF_INT_TFPE_MASK 0x00200000 /* Tx FIFO Programmable Empty */ 95 #define XLLF_INT_RFPF_MASK 0x00100000 /* Rx FIFO Programmable Full */ 96 #define XLLF_INT_RFPE_MASK 0x00080000 /* Rx FIFO Programmable Empty */ 97 #define XLLF_INT_ALL_MASK 0xfff80000 /* All the ints */ 98 #define XLLF_INT_ERROR_MASK 0xf2000000 /* Error status ints */ 99 #define XLLF_INT_RXERROR_MASK 0xe0000000 /* Receive Error status ints */ 100 #define XLLF_INT_TXERROR_MASK 0x12000000 /* Transmit Error status ints */ 101 102 /* ---------------------------- 103 * globals 104 * ---------------------------- 105 */ 106 static int read_timeout = 1000; /* ms to wait before read() times out */ 107 static int write_timeout = 1000; /* ms to wait before write() times out */ 108 109 /* ---------------------------- 110 * module command-line arguments 111 * ---------------------------- 112 */ 113 114 module_param(read_timeout, int, 0444); 115 MODULE_PARM_DESC(read_timeout, "ms to wait before blocking read() timing out; set to -1 for no timeout"); 116 module_param(write_timeout, int, 0444); 117 MODULE_PARM_DESC(write_timeout, "ms to wait before blocking write() timing out; set to -1 for no timeout"); 118 119 /* ---------------------------- 120 * types 121 * ---------------------------- 122 */ 123 124 struct axis_fifo { 125 int irq; /* interrupt */ 126 void __iomem *base_addr; /* kernel space memory */ 127 128 unsigned int rx_fifo_depth; /* max words in the receive fifo */ 129 unsigned int tx_fifo_depth; /* max words in the transmit fifo */ 130 int has_rx_fifo; /* whether the IP has the rx fifo enabled */ 131 int has_tx_fifo; /* whether the IP has the tx fifo enabled */ 132 133 wait_queue_head_t read_queue; /* wait queue for asynchronos read */ 134 struct mutex read_lock; /* lock for reading */ 135 wait_queue_head_t write_queue; /* wait queue for asynchronos write */ 136 struct mutex write_lock; /* lock for writing */ 137 unsigned int write_flags; /* write file flags */ 138 unsigned int read_flags; /* read file flags */ 139 140 struct device *dt_device; /* device created from the device tree */ 141 struct miscdevice miscdev; 142 }; 143 144 /* ---------------------------- 145 * sysfs entries 146 * ---------------------------- 147 */ 148 149 static ssize_t sysfs_write(struct device *dev, const char *buf, 150 size_t count, unsigned int addr_offset) 151 { 152 struct axis_fifo *fifo = dev_get_drvdata(dev); 153 unsigned long tmp; 154 int rc; 155 156 rc = kstrtoul(buf, 0, &tmp); 157 if (rc < 0) 158 return rc; 159 160 iowrite32(tmp, fifo->base_addr + addr_offset); 161 162 return count; 163 } 164 165 static ssize_t sysfs_read(struct device *dev, char *buf, 166 unsigned int addr_offset) 167 { 168 struct axis_fifo *fifo = dev_get_drvdata(dev); 169 unsigned int read_val; 170 unsigned int len; 171 char tmp[32]; 172 173 read_val = ioread32(fifo->base_addr + addr_offset); 174 len = snprintf(tmp, sizeof(tmp), "0x%x\n", read_val); 175 memcpy(buf, tmp, len); 176 177 return len; 178 } 179 180 static ssize_t isr_store(struct device *dev, struct device_attribute *attr, 181 const char *buf, size_t count) 182 { 183 return sysfs_write(dev, buf, count, XLLF_ISR_OFFSET); 184 } 185 186 static ssize_t isr_show(struct device *dev, 187 struct device_attribute *attr, char *buf) 188 { 189 return sysfs_read(dev, buf, XLLF_ISR_OFFSET); 190 } 191 192 static DEVICE_ATTR_RW(isr); 193 194 static ssize_t ier_store(struct device *dev, struct device_attribute *attr, 195 const char *buf, size_t count) 196 { 197 return sysfs_write(dev, buf, count, XLLF_IER_OFFSET); 198 } 199 200 static ssize_t ier_show(struct device *dev, 201 struct device_attribute *attr, char *buf) 202 { 203 return sysfs_read(dev, buf, XLLF_IER_OFFSET); 204 } 205 206 static DEVICE_ATTR_RW(ier); 207 208 static ssize_t tdfr_store(struct device *dev, struct device_attribute *attr, 209 const char *buf, size_t count) 210 { 211 return sysfs_write(dev, buf, count, XLLF_TDFR_OFFSET); 212 } 213 214 static DEVICE_ATTR_WO(tdfr); 215 216 static ssize_t tdfv_show(struct device *dev, 217 struct device_attribute *attr, char *buf) 218 { 219 return sysfs_read(dev, buf, XLLF_TDFV_OFFSET); 220 } 221 222 static DEVICE_ATTR_RO(tdfv); 223 224 static ssize_t tdfd_store(struct device *dev, struct device_attribute *attr, 225 const char *buf, size_t count) 226 { 227 return sysfs_write(dev, buf, count, XLLF_TDFD_OFFSET); 228 } 229 230 static DEVICE_ATTR_WO(tdfd); 231 232 static ssize_t tlr_store(struct device *dev, struct device_attribute *attr, 233 const char *buf, size_t count) 234 { 235 return sysfs_write(dev, buf, count, XLLF_TLR_OFFSET); 236 } 237 238 static DEVICE_ATTR_WO(tlr); 239 240 static ssize_t rdfr_store(struct device *dev, struct device_attribute *attr, 241 const char *buf, size_t count) 242 { 243 return sysfs_write(dev, buf, count, XLLF_RDFR_OFFSET); 244 } 245 246 static DEVICE_ATTR_WO(rdfr); 247 248 static ssize_t rdfo_show(struct device *dev, 249 struct device_attribute *attr, char *buf) 250 { 251 return sysfs_read(dev, buf, XLLF_RDFO_OFFSET); 252 } 253 254 static DEVICE_ATTR_RO(rdfo); 255 256 static ssize_t rdfd_show(struct device *dev, 257 struct device_attribute *attr, char *buf) 258 { 259 return sysfs_read(dev, buf, XLLF_RDFD_OFFSET); 260 } 261 262 static DEVICE_ATTR_RO(rdfd); 263 264 static ssize_t rlr_show(struct device *dev, 265 struct device_attribute *attr, char *buf) 266 { 267 return sysfs_read(dev, buf, XLLF_RLR_OFFSET); 268 } 269 270 static DEVICE_ATTR_RO(rlr); 271 272 static ssize_t srr_store(struct device *dev, struct device_attribute *attr, 273 const char *buf, size_t count) 274 { 275 return sysfs_write(dev, buf, count, XLLF_SRR_OFFSET); 276 } 277 278 static DEVICE_ATTR_WO(srr); 279 280 static ssize_t tdr_store(struct device *dev, struct device_attribute *attr, 281 const char *buf, size_t count) 282 { 283 return sysfs_write(dev, buf, count, XLLF_TDR_OFFSET); 284 } 285 286 static DEVICE_ATTR_WO(tdr); 287 288 static ssize_t rdr_show(struct device *dev, 289 struct device_attribute *attr, char *buf) 290 { 291 return sysfs_read(dev, buf, XLLF_RDR_OFFSET); 292 } 293 294 static DEVICE_ATTR_RO(rdr); 295 296 static struct attribute *axis_fifo_attrs[] = { 297 &dev_attr_isr.attr, 298 &dev_attr_ier.attr, 299 &dev_attr_tdfr.attr, 300 &dev_attr_tdfv.attr, 301 &dev_attr_tdfd.attr, 302 &dev_attr_tlr.attr, 303 &dev_attr_rdfr.attr, 304 &dev_attr_rdfo.attr, 305 &dev_attr_rdfd.attr, 306 &dev_attr_rlr.attr, 307 &dev_attr_srr.attr, 308 &dev_attr_tdr.attr, 309 &dev_attr_rdr.attr, 310 NULL, 311 }; 312 313 static const struct attribute_group axis_fifo_attrs_group = { 314 .name = "ip_registers", 315 .attrs = axis_fifo_attrs, 316 }; 317 318 static const struct attribute_group *axis_fifo_attrs_groups[] = { 319 &axis_fifo_attrs_group, 320 NULL, 321 }; 322 323 /* ---------------------------- 324 * implementation 325 * ---------------------------- 326 */ 327 328 static void reset_ip_core(struct axis_fifo *fifo) 329 { 330 iowrite32(XLLF_SRR_RESET_MASK, fifo->base_addr + XLLF_SRR_OFFSET); 331 iowrite32(XLLF_TDFR_RESET_MASK, fifo->base_addr + XLLF_TDFR_OFFSET); 332 iowrite32(XLLF_RDFR_RESET_MASK, fifo->base_addr + XLLF_RDFR_OFFSET); 333 iowrite32(XLLF_INT_TC_MASK | XLLF_INT_RC_MASK | XLLF_INT_RPURE_MASK | 334 XLLF_INT_RPORE_MASK | XLLF_INT_RPUE_MASK | 335 XLLF_INT_TPOE_MASK | XLLF_INT_TSE_MASK, 336 fifo->base_addr + XLLF_IER_OFFSET); 337 iowrite32(XLLF_INT_ALL_MASK, fifo->base_addr + XLLF_ISR_OFFSET); 338 } 339 340 /** 341 * axis_fifo_read() - Read a packet from AXIS-FIFO character device. 342 * @f: Open file. 343 * @buf: User space buffer to read to. 344 * @len: User space buffer length. 345 * @off: Buffer offset. 346 * 347 * As defined by the device's documentation, we need to check the device's 348 * occupancy before reading the length register and then the data. All these 349 * operations must be executed atomically, in order and one after the other 350 * without missing any. 351 * 352 * Returns the number of bytes read from the device or negative error code 353 * on failure. 354 */ 355 static ssize_t axis_fifo_read(struct file *f, char __user *buf, 356 size_t len, loff_t *off) 357 { 358 struct axis_fifo *fifo = (struct axis_fifo *)f->private_data; 359 size_t bytes_available; 360 unsigned int words_available; 361 unsigned int copied; 362 unsigned int copy; 363 unsigned int i; 364 int ret; 365 u32 tmp_buf[READ_BUF_SIZE]; 366 367 if (fifo->read_flags & O_NONBLOCK) { 368 /* 369 * Device opened in non-blocking mode. Try to lock it and then 370 * check if any packet is available. 371 */ 372 if (!mutex_trylock(&fifo->read_lock)) 373 return -EAGAIN; 374 375 if (!ioread32(fifo->base_addr + XLLF_RDFO_OFFSET)) { 376 ret = -EAGAIN; 377 goto end_unlock; 378 } 379 } else { 380 /* opened in blocking mode 381 * wait for a packet available interrupt (or timeout) 382 * if nothing is currently available 383 */ 384 mutex_lock(&fifo->read_lock); 385 ret = wait_event_interruptible_timeout(fifo->read_queue, 386 ioread32(fifo->base_addr + XLLF_RDFO_OFFSET), 387 (read_timeout >= 0) ? 388 msecs_to_jiffies(read_timeout) : 389 MAX_SCHEDULE_TIMEOUT); 390 391 if (ret <= 0) { 392 if (ret == 0) { 393 ret = -EAGAIN; 394 } else if (ret != -ERESTARTSYS) { 395 dev_err(fifo->dt_device, "wait_event_interruptible_timeout() error in read (ret=%i)\n", 396 ret); 397 } 398 399 goto end_unlock; 400 } 401 } 402 403 bytes_available = ioread32(fifo->base_addr + XLLF_RLR_OFFSET); 404 if (!bytes_available) { 405 dev_err(fifo->dt_device, "received a packet of length 0 - fifo core will be reset\n"); 406 reset_ip_core(fifo); 407 ret = -EIO; 408 goto end_unlock; 409 } 410 411 if (bytes_available > len) { 412 dev_err(fifo->dt_device, "user read buffer too small (available bytes=%zu user buffer bytes=%zu) - fifo core will be reset\n", 413 bytes_available, len); 414 reset_ip_core(fifo); 415 ret = -EINVAL; 416 goto end_unlock; 417 } 418 419 if (bytes_available % sizeof(u32)) { 420 /* this probably can't happen unless IP 421 * registers were previously mishandled 422 */ 423 dev_err(fifo->dt_device, "received a packet that isn't word-aligned - fifo core will be reset\n"); 424 reset_ip_core(fifo); 425 ret = -EIO; 426 goto end_unlock; 427 } 428 429 words_available = bytes_available / sizeof(u32); 430 431 /* read data into an intermediate buffer, copying the contents 432 * to userspace when the buffer is full 433 */ 434 copied = 0; 435 while (words_available > 0) { 436 copy = min(words_available, READ_BUF_SIZE); 437 438 for (i = 0; i < copy; i++) { 439 tmp_buf[i] = ioread32(fifo->base_addr + 440 XLLF_RDFD_OFFSET); 441 } 442 443 if (copy_to_user(buf + copied * sizeof(u32), tmp_buf, 444 copy * sizeof(u32))) { 445 reset_ip_core(fifo); 446 ret = -EFAULT; 447 goto end_unlock; 448 } 449 450 copied += copy; 451 words_available -= copy; 452 } 453 454 ret = bytes_available; 455 456 end_unlock: 457 mutex_unlock(&fifo->read_lock); 458 459 return ret; 460 } 461 462 /** 463 * axis_fifo_write() - Write buffer to AXIS-FIFO character device. 464 * @f: Open file. 465 * @buf: User space buffer to write to the device. 466 * @len: User space buffer length. 467 * @off: Buffer offset. 468 * 469 * As defined by the device's documentation, we need to write to the device's 470 * data buffer then to the device's packet length register atomically. Also, 471 * we need to lock before checking if the device has available space to avoid 472 * any concurrency issue. 473 * 474 * Returns the number of bytes written to the device or negative error code 475 * on failure. 476 */ 477 static ssize_t axis_fifo_write(struct file *f, const char __user *buf, 478 size_t len, loff_t *off) 479 { 480 struct axis_fifo *fifo = (struct axis_fifo *)f->private_data; 481 unsigned int words_to_write; 482 unsigned int copied; 483 unsigned int copy; 484 unsigned int i; 485 int ret; 486 u32 tmp_buf[WRITE_BUF_SIZE]; 487 488 if (len % sizeof(u32)) { 489 dev_err(fifo->dt_device, 490 "tried to send a packet that isn't word-aligned\n"); 491 return -EINVAL; 492 } 493 494 words_to_write = len / sizeof(u32); 495 496 if (!words_to_write) { 497 dev_err(fifo->dt_device, 498 "tried to send a packet of length 0\n"); 499 return -EINVAL; 500 } 501 502 if (words_to_write > fifo->tx_fifo_depth) { 503 dev_err(fifo->dt_device, "tried to write more words [%u] than slots in the fifo buffer [%u]\n", 504 words_to_write, fifo->tx_fifo_depth); 505 return -EINVAL; 506 } 507 508 if (fifo->write_flags & O_NONBLOCK) { 509 /* 510 * Device opened in non-blocking mode. Try to lock it and then 511 * check if there is any room to write the given buffer. 512 */ 513 if (!mutex_trylock(&fifo->write_lock)) 514 return -EAGAIN; 515 516 if (words_to_write > ioread32(fifo->base_addr + 517 XLLF_TDFV_OFFSET)) { 518 ret = -EAGAIN; 519 goto end_unlock; 520 } 521 } else { 522 /* opened in blocking mode */ 523 524 /* wait for an interrupt (or timeout) if there isn't 525 * currently enough room in the fifo 526 */ 527 mutex_lock(&fifo->write_lock); 528 ret = wait_event_interruptible_timeout(fifo->write_queue, 529 ioread32(fifo->base_addr + XLLF_TDFV_OFFSET) 530 >= words_to_write, 531 (write_timeout >= 0) ? 532 msecs_to_jiffies(write_timeout) : 533 MAX_SCHEDULE_TIMEOUT); 534 535 if (ret <= 0) { 536 if (ret == 0) { 537 ret = -EAGAIN; 538 } else if (ret != -ERESTARTSYS) { 539 dev_err(fifo->dt_device, "wait_event_interruptible_timeout() error in write (ret=%i)\n", 540 ret); 541 } 542 543 goto end_unlock; 544 } 545 } 546 547 /* write data from an intermediate buffer into the fifo IP, refilling 548 * the buffer with userspace data as needed 549 */ 550 copied = 0; 551 while (words_to_write > 0) { 552 copy = min(words_to_write, WRITE_BUF_SIZE); 553 554 if (copy_from_user(tmp_buf, buf + copied * sizeof(u32), 555 copy * sizeof(u32))) { 556 reset_ip_core(fifo); 557 ret = -EFAULT; 558 goto end_unlock; 559 } 560 561 for (i = 0; i < copy; i++) 562 iowrite32(tmp_buf[i], fifo->base_addr + 563 XLLF_TDFD_OFFSET); 564 565 copied += copy; 566 words_to_write -= copy; 567 } 568 569 ret = copied * sizeof(u32); 570 571 /* write packet size to fifo */ 572 iowrite32(ret, fifo->base_addr + XLLF_TLR_OFFSET); 573 574 end_unlock: 575 mutex_unlock(&fifo->write_lock); 576 577 return ret; 578 } 579 580 static irqreturn_t axis_fifo_irq(int irq, void *dw) 581 { 582 struct axis_fifo *fifo = (struct axis_fifo *)dw; 583 unsigned int pending_interrupts; 584 585 do { 586 pending_interrupts = ioread32(fifo->base_addr + 587 XLLF_IER_OFFSET) & 588 ioread32(fifo->base_addr 589 + XLLF_ISR_OFFSET); 590 if (pending_interrupts & XLLF_INT_RC_MASK) { 591 /* packet received */ 592 593 /* wake the reader process if it is waiting */ 594 wake_up(&fifo->read_queue); 595 596 /* clear interrupt */ 597 iowrite32(XLLF_INT_RC_MASK & XLLF_INT_ALL_MASK, 598 fifo->base_addr + XLLF_ISR_OFFSET); 599 } else if (pending_interrupts & XLLF_INT_TC_MASK) { 600 /* packet sent */ 601 602 /* wake the writer process if it is waiting */ 603 wake_up(&fifo->write_queue); 604 605 iowrite32(XLLF_INT_TC_MASK & XLLF_INT_ALL_MASK, 606 fifo->base_addr + XLLF_ISR_OFFSET); 607 } else if (pending_interrupts & XLLF_INT_TFPF_MASK) { 608 /* transmit fifo programmable full */ 609 610 iowrite32(XLLF_INT_TFPF_MASK & XLLF_INT_ALL_MASK, 611 fifo->base_addr + XLLF_ISR_OFFSET); 612 } else if (pending_interrupts & XLLF_INT_TFPE_MASK) { 613 /* transmit fifo programmable empty */ 614 615 iowrite32(XLLF_INT_TFPE_MASK & XLLF_INT_ALL_MASK, 616 fifo->base_addr + XLLF_ISR_OFFSET); 617 } else if (pending_interrupts & XLLF_INT_RFPF_MASK) { 618 /* receive fifo programmable full */ 619 620 iowrite32(XLLF_INT_RFPF_MASK & XLLF_INT_ALL_MASK, 621 fifo->base_addr + XLLF_ISR_OFFSET); 622 } else if (pending_interrupts & XLLF_INT_RFPE_MASK) { 623 /* receive fifo programmable empty */ 624 625 iowrite32(XLLF_INT_RFPE_MASK & XLLF_INT_ALL_MASK, 626 fifo->base_addr + XLLF_ISR_OFFSET); 627 } else if (pending_interrupts & XLLF_INT_TRC_MASK) { 628 /* transmit reset complete interrupt */ 629 630 iowrite32(XLLF_INT_TRC_MASK & XLLF_INT_ALL_MASK, 631 fifo->base_addr + XLLF_ISR_OFFSET); 632 } else if (pending_interrupts & XLLF_INT_RRC_MASK) { 633 /* receive reset complete interrupt */ 634 635 iowrite32(XLLF_INT_RRC_MASK & XLLF_INT_ALL_MASK, 636 fifo->base_addr + XLLF_ISR_OFFSET); 637 } else if (pending_interrupts & XLLF_INT_RPURE_MASK) { 638 /* receive fifo under-read error interrupt */ 639 dev_err(fifo->dt_device, 640 "receive under-read interrupt\n"); 641 642 iowrite32(XLLF_INT_RPURE_MASK & XLLF_INT_ALL_MASK, 643 fifo->base_addr + XLLF_ISR_OFFSET); 644 } else if (pending_interrupts & XLLF_INT_RPORE_MASK) { 645 /* receive over-read error interrupt */ 646 dev_err(fifo->dt_device, 647 "receive over-read interrupt\n"); 648 649 iowrite32(XLLF_INT_RPORE_MASK & XLLF_INT_ALL_MASK, 650 fifo->base_addr + XLLF_ISR_OFFSET); 651 } else if (pending_interrupts & XLLF_INT_RPUE_MASK) { 652 /* receive underrun error interrupt */ 653 dev_err(fifo->dt_device, 654 "receive underrun error interrupt\n"); 655 656 iowrite32(XLLF_INT_RPUE_MASK & XLLF_INT_ALL_MASK, 657 fifo->base_addr + XLLF_ISR_OFFSET); 658 } else if (pending_interrupts & XLLF_INT_TPOE_MASK) { 659 /* transmit overrun error interrupt */ 660 dev_err(fifo->dt_device, 661 "transmit overrun error interrupt\n"); 662 663 iowrite32(XLLF_INT_TPOE_MASK & XLLF_INT_ALL_MASK, 664 fifo->base_addr + XLLF_ISR_OFFSET); 665 } else if (pending_interrupts & XLLF_INT_TSE_MASK) { 666 /* transmit length mismatch error interrupt */ 667 dev_err(fifo->dt_device, 668 "transmit length mismatch error interrupt\n"); 669 670 iowrite32(XLLF_INT_TSE_MASK & XLLF_INT_ALL_MASK, 671 fifo->base_addr + XLLF_ISR_OFFSET); 672 } else if (pending_interrupts) { 673 /* unknown interrupt type */ 674 dev_err(fifo->dt_device, 675 "unknown interrupt(s) 0x%x\n", 676 pending_interrupts); 677 678 iowrite32(XLLF_INT_ALL_MASK, 679 fifo->base_addr + XLLF_ISR_OFFSET); 680 } 681 } while (pending_interrupts); 682 683 return IRQ_HANDLED; 684 } 685 686 static int axis_fifo_open(struct inode *inod, struct file *f) 687 { 688 struct axis_fifo *fifo = container_of(f->private_data, 689 struct axis_fifo, miscdev); 690 f->private_data = fifo; 691 692 if (((f->f_flags & O_ACCMODE) == O_WRONLY) || 693 ((f->f_flags & O_ACCMODE) == O_RDWR)) { 694 if (fifo->has_tx_fifo) { 695 fifo->write_flags = f->f_flags; 696 } else { 697 dev_err(fifo->dt_device, "tried to open device for write but the transmit fifo is disabled\n"); 698 return -EPERM; 699 } 700 } 701 702 if (((f->f_flags & O_ACCMODE) == O_RDONLY) || 703 ((f->f_flags & O_ACCMODE) == O_RDWR)) { 704 if (fifo->has_rx_fifo) { 705 fifo->read_flags = f->f_flags; 706 } else { 707 dev_err(fifo->dt_device, "tried to open device for read but the receive fifo is disabled\n"); 708 return -EPERM; 709 } 710 } 711 712 return 0; 713 } 714 715 static int axis_fifo_close(struct inode *inod, struct file *f) 716 { 717 f->private_data = NULL; 718 719 return 0; 720 } 721 722 static const struct file_operations fops = { 723 .owner = THIS_MODULE, 724 .open = axis_fifo_open, 725 .release = axis_fifo_close, 726 .read = axis_fifo_read, 727 .write = axis_fifo_write 728 }; 729 730 /* read named property from the device tree */ 731 static int get_dts_property(struct axis_fifo *fifo, 732 char *name, unsigned int *var) 733 { 734 int rc; 735 736 rc = of_property_read_u32(fifo->dt_device->of_node, name, var); 737 if (rc) { 738 dev_err(fifo->dt_device, "couldn't read IP dts property '%s'", 739 name); 740 return rc; 741 } 742 dev_dbg(fifo->dt_device, "dts property '%s' = %u\n", 743 name, *var); 744 745 return 0; 746 } 747 748 static int axis_fifo_parse_dt(struct axis_fifo *fifo) 749 { 750 int ret; 751 unsigned int value; 752 753 ret = get_dts_property(fifo, "xlnx,axi-str-rxd-tdata-width", &value); 754 if (ret) { 755 dev_err(fifo->dt_device, "missing xlnx,axi-str-rxd-tdata-width property\n"); 756 goto end; 757 } else if (value != 32) { 758 dev_err(fifo->dt_device, "xlnx,axi-str-rxd-tdata-width only supports 32 bits\n"); 759 ret = -EIO; 760 goto end; 761 } 762 763 ret = get_dts_property(fifo, "xlnx,axi-str-txd-tdata-width", &value); 764 if (ret) { 765 dev_err(fifo->dt_device, "missing xlnx,axi-str-txd-tdata-width property\n"); 766 goto end; 767 } else if (value != 32) { 768 dev_err(fifo->dt_device, "xlnx,axi-str-txd-tdata-width only supports 32 bits\n"); 769 ret = -EIO; 770 goto end; 771 } 772 773 ret = get_dts_property(fifo, "xlnx,rx-fifo-depth", 774 &fifo->rx_fifo_depth); 775 if (ret) { 776 dev_err(fifo->dt_device, "missing xlnx,rx-fifo-depth property\n"); 777 ret = -EIO; 778 goto end; 779 } 780 781 ret = get_dts_property(fifo, "xlnx,tx-fifo-depth", 782 &fifo->tx_fifo_depth); 783 if (ret) { 784 dev_err(fifo->dt_device, "missing xlnx,tx-fifo-depth property\n"); 785 ret = -EIO; 786 goto end; 787 } 788 789 /* IP sets TDFV to fifo depth - 4 so we will do the same */ 790 fifo->tx_fifo_depth -= 4; 791 792 ret = get_dts_property(fifo, "xlnx,use-rx-data", &fifo->has_rx_fifo); 793 if (ret) { 794 dev_err(fifo->dt_device, "missing xlnx,use-rx-data property\n"); 795 ret = -EIO; 796 goto end; 797 } 798 799 ret = get_dts_property(fifo, "xlnx,use-tx-data", &fifo->has_tx_fifo); 800 if (ret) { 801 dev_err(fifo->dt_device, "missing xlnx,use-tx-data property\n"); 802 ret = -EIO; 803 goto end; 804 } 805 806 end: 807 return ret; 808 } 809 810 static int axis_fifo_probe(struct platform_device *pdev) 811 { 812 struct resource *r_mem; /* IO mem resources */ 813 struct device *dev = &pdev->dev; /* OS device (from device tree) */ 814 struct axis_fifo *fifo = NULL; 815 char *device_name; 816 int rc = 0; /* error return value */ 817 818 /* ---------------------------- 819 * init wrapper device 820 * ---------------------------- 821 */ 822 823 device_name = devm_kzalloc(dev, 32, GFP_KERNEL); 824 if (!device_name) 825 return -ENOMEM; 826 827 /* allocate device wrapper memory */ 828 fifo = devm_kzalloc(dev, sizeof(*fifo), GFP_KERNEL); 829 if (!fifo) 830 return -ENOMEM; 831 832 dev_set_drvdata(dev, fifo); 833 fifo->dt_device = dev; 834 835 init_waitqueue_head(&fifo->read_queue); 836 init_waitqueue_head(&fifo->write_queue); 837 838 mutex_init(&fifo->read_lock); 839 mutex_init(&fifo->write_lock); 840 841 /* ---------------------------- 842 * init device memory space 843 * ---------------------------- 844 */ 845 846 /* get iospace for the device */ 847 r_mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 848 if (!r_mem) { 849 dev_err(fifo->dt_device, "invalid address\n"); 850 rc = -ENODEV; 851 goto err_initial; 852 } 853 854 /* request physical memory */ 855 fifo->base_addr = devm_ioremap_resource(fifo->dt_device, r_mem); 856 if (IS_ERR(fifo->base_addr)) { 857 rc = PTR_ERR(fifo->base_addr); 858 goto err_initial; 859 } 860 861 dev_dbg(fifo->dt_device, "remapped memory to 0x%p\n", fifo->base_addr); 862 863 /* create unique device name */ 864 snprintf(device_name, 32, "%s_%pa", DRIVER_NAME, &r_mem->start); 865 dev_dbg(fifo->dt_device, "device name [%s]\n", device_name); 866 867 /* ---------------------------- 868 * init IP 869 * ---------------------------- 870 */ 871 872 rc = axis_fifo_parse_dt(fifo); 873 if (rc) 874 goto err_initial; 875 876 reset_ip_core(fifo); 877 878 /* ---------------------------- 879 * init device interrupts 880 * ---------------------------- 881 */ 882 883 /* get IRQ resource */ 884 rc = platform_get_irq(pdev, 0); 885 if (rc < 0) 886 goto err_initial; 887 888 /* request IRQ */ 889 fifo->irq = rc; 890 rc = devm_request_irq(fifo->dt_device, fifo->irq, &axis_fifo_irq, 0, 891 DRIVER_NAME, fifo); 892 if (rc) { 893 dev_err(fifo->dt_device, "couldn't allocate interrupt %i\n", 894 fifo->irq); 895 goto err_initial; 896 } 897 898 /* ---------------------------- 899 * init char device 900 * ---------------------------- 901 */ 902 903 /* create character device */ 904 fifo->miscdev.fops = &fops; 905 fifo->miscdev.minor = MISC_DYNAMIC_MINOR; 906 fifo->miscdev.name = device_name; 907 fifo->miscdev.groups = axis_fifo_attrs_groups; 908 fifo->miscdev.parent = dev; 909 rc = misc_register(&fifo->miscdev); 910 if (rc < 0) 911 goto err_initial; 912 913 dev_info(fifo->dt_device, "axis-fifo created at %pa mapped to 0x%pa, irq=%i\n", 914 &r_mem->start, &fifo->base_addr, fifo->irq); 915 916 return 0; 917 918 err_initial: 919 dev_set_drvdata(dev, NULL); 920 return rc; 921 } 922 923 static int axis_fifo_remove(struct platform_device *pdev) 924 { 925 struct device *dev = &pdev->dev; 926 struct axis_fifo *fifo = dev_get_drvdata(dev); 927 928 misc_deregister(&fifo->miscdev); 929 dev_set_drvdata(dev, NULL); 930 931 return 0; 932 } 933 934 static const struct of_device_id axis_fifo_of_match[] = { 935 { .compatible = "xlnx,axi-fifo-mm-s-4.1", }, 936 {}, 937 }; 938 MODULE_DEVICE_TABLE(of, axis_fifo_of_match); 939 940 static struct platform_driver axis_fifo_driver = { 941 .driver = { 942 .name = DRIVER_NAME, 943 .of_match_table = axis_fifo_of_match, 944 }, 945 .probe = axis_fifo_probe, 946 .remove = axis_fifo_remove, 947 }; 948 949 static int __init axis_fifo_init(void) 950 { 951 pr_info("axis-fifo driver loaded with parameters read_timeout = %i, write_timeout = %i\n", 952 read_timeout, write_timeout); 953 return platform_driver_register(&axis_fifo_driver); 954 } 955 956 module_init(axis_fifo_init); 957 958 static void __exit axis_fifo_exit(void) 959 { 960 platform_driver_unregister(&axis_fifo_driver); 961 } 962 963 module_exit(axis_fifo_exit); 964 965 MODULE_LICENSE("GPL"); 966 MODULE_AUTHOR("Jacob Feder <jacobsfeder@gmail.com>"); 967 MODULE_DESCRIPTION("Xilinx AXI-Stream FIFO v4.1 IP core driver"); 968