xref: /linux/drivers/ssb/main.c (revision 4c62e9764ab403d42f9b8871b1241fe7812f19d4)
1 /*
2  * Sonics Silicon Backplane
3  * Subsystem core
4  *
5  * Copyright 2005, Broadcom Corporation
6  * Copyright 2006, 2007, Michael Buesch <m@bues.ch>
7  *
8  * Licensed under the GNU/GPL. See COPYING for details.
9  */
10 
11 #include "ssb_private.h"
12 
13 #include <linux/delay.h>
14 #include <linux/io.h>
15 #include <linux/module.h>
16 #include <linux/platform_device.h>
17 #include <linux/ssb/ssb.h>
18 #include <linux/ssb/ssb_regs.h>
19 #include <linux/ssb/ssb_driver_gige.h>
20 #include <linux/dma-mapping.h>
21 #include <linux/pci.h>
22 #include <linux/mmc/sdio_func.h>
23 #include <linux/slab.h>
24 
25 #include <pcmcia/cistpl.h>
26 #include <pcmcia/ds.h>
27 
28 
29 MODULE_DESCRIPTION("Sonics Silicon Backplane driver");
30 MODULE_LICENSE("GPL");
31 
32 
33 /* Temporary list of yet-to-be-attached buses */
34 static LIST_HEAD(attach_queue);
35 /* List if running buses */
36 static LIST_HEAD(buses);
37 /* Software ID counter */
38 static unsigned int next_busnumber;
39 /* buses_mutes locks the two buslists and the next_busnumber.
40  * Don't lock this directly, but use ssb_buses_[un]lock() below. */
41 static DEFINE_MUTEX(buses_mutex);
42 
43 /* There are differences in the codeflow, if the bus is
44  * initialized from early boot, as various needed services
45  * are not available early. This is a mechanism to delay
46  * these initializations to after early boot has finished.
47  * It's also used to avoid mutex locking, as that's not
48  * available and needed early. */
49 static bool ssb_is_early_boot = 1;
50 
51 static void ssb_buses_lock(void);
52 static void ssb_buses_unlock(void);
53 
54 
55 #ifdef CONFIG_SSB_PCIHOST
56 struct ssb_bus *ssb_pci_dev_to_bus(struct pci_dev *pdev)
57 {
58 	struct ssb_bus *bus;
59 
60 	ssb_buses_lock();
61 	list_for_each_entry(bus, &buses, list) {
62 		if (bus->bustype == SSB_BUSTYPE_PCI &&
63 		    bus->host_pci == pdev)
64 			goto found;
65 	}
66 	bus = NULL;
67 found:
68 	ssb_buses_unlock();
69 
70 	return bus;
71 }
72 #endif /* CONFIG_SSB_PCIHOST */
73 
74 #ifdef CONFIG_SSB_PCMCIAHOST
75 struct ssb_bus *ssb_pcmcia_dev_to_bus(struct pcmcia_device *pdev)
76 {
77 	struct ssb_bus *bus;
78 
79 	ssb_buses_lock();
80 	list_for_each_entry(bus, &buses, list) {
81 		if (bus->bustype == SSB_BUSTYPE_PCMCIA &&
82 		    bus->host_pcmcia == pdev)
83 			goto found;
84 	}
85 	bus = NULL;
86 found:
87 	ssb_buses_unlock();
88 
89 	return bus;
90 }
91 #endif /* CONFIG_SSB_PCMCIAHOST */
92 
93 #ifdef CONFIG_SSB_SDIOHOST
94 struct ssb_bus *ssb_sdio_func_to_bus(struct sdio_func *func)
95 {
96 	struct ssb_bus *bus;
97 
98 	ssb_buses_lock();
99 	list_for_each_entry(bus, &buses, list) {
100 		if (bus->bustype == SSB_BUSTYPE_SDIO &&
101 		    bus->host_sdio == func)
102 			goto found;
103 	}
104 	bus = NULL;
105 found:
106 	ssb_buses_unlock();
107 
108 	return bus;
109 }
110 #endif /* CONFIG_SSB_SDIOHOST */
111 
112 int ssb_for_each_bus_call(unsigned long data,
113 			  int (*func)(struct ssb_bus *bus, unsigned long data))
114 {
115 	struct ssb_bus *bus;
116 	int res;
117 
118 	ssb_buses_lock();
119 	list_for_each_entry(bus, &buses, list) {
120 		res = func(bus, data);
121 		if (res >= 0) {
122 			ssb_buses_unlock();
123 			return res;
124 		}
125 	}
126 	ssb_buses_unlock();
127 
128 	return -ENODEV;
129 }
130 
131 static struct ssb_device *ssb_device_get(struct ssb_device *dev)
132 {
133 	if (dev)
134 		get_device(dev->dev);
135 	return dev;
136 }
137 
138 static void ssb_device_put(struct ssb_device *dev)
139 {
140 	if (dev)
141 		put_device(dev->dev);
142 }
143 
144 static int ssb_device_resume(struct device *dev)
145 {
146 	struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
147 	struct ssb_driver *ssb_drv;
148 	int err = 0;
149 
150 	if (dev->driver) {
151 		ssb_drv = drv_to_ssb_drv(dev->driver);
152 		if (ssb_drv && ssb_drv->resume)
153 			err = ssb_drv->resume(ssb_dev);
154 		if (err)
155 			goto out;
156 	}
157 out:
158 	return err;
159 }
160 
161 static int ssb_device_suspend(struct device *dev, pm_message_t state)
162 {
163 	struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
164 	struct ssb_driver *ssb_drv;
165 	int err = 0;
166 
167 	if (dev->driver) {
168 		ssb_drv = drv_to_ssb_drv(dev->driver);
169 		if (ssb_drv && ssb_drv->suspend)
170 			err = ssb_drv->suspend(ssb_dev, state);
171 		if (err)
172 			goto out;
173 	}
174 out:
175 	return err;
176 }
177 
178 int ssb_bus_resume(struct ssb_bus *bus)
179 {
180 	int err;
181 
182 	/* Reset HW state information in memory, so that HW is
183 	 * completely reinitialized. */
184 	bus->mapped_device = NULL;
185 #ifdef CONFIG_SSB_DRIVER_PCICORE
186 	bus->pcicore.setup_done = 0;
187 #endif
188 
189 	err = ssb_bus_powerup(bus, 0);
190 	if (err)
191 		return err;
192 	err = ssb_pcmcia_hardware_setup(bus);
193 	if (err) {
194 		ssb_bus_may_powerdown(bus);
195 		return err;
196 	}
197 	ssb_chipco_resume(&bus->chipco);
198 	ssb_bus_may_powerdown(bus);
199 
200 	return 0;
201 }
202 EXPORT_SYMBOL(ssb_bus_resume);
203 
204 int ssb_bus_suspend(struct ssb_bus *bus)
205 {
206 	ssb_chipco_suspend(&bus->chipco);
207 	ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
208 
209 	return 0;
210 }
211 EXPORT_SYMBOL(ssb_bus_suspend);
212 
213 #ifdef CONFIG_SSB_SPROM
214 /** ssb_devices_freeze - Freeze all devices on the bus.
215  *
216  * After freezing no device driver will be handling a device
217  * on this bus anymore. ssb_devices_thaw() must be called after
218  * a successful freeze to reactivate the devices.
219  *
220  * @bus: The bus.
221  * @ctx: Context structure. Pass this to ssb_devices_thaw().
222  */
223 int ssb_devices_freeze(struct ssb_bus *bus, struct ssb_freeze_context *ctx)
224 {
225 	struct ssb_device *sdev;
226 	struct ssb_driver *sdrv;
227 	unsigned int i;
228 
229 	memset(ctx, 0, sizeof(*ctx));
230 	ctx->bus = bus;
231 	SSB_WARN_ON(bus->nr_devices > ARRAY_SIZE(ctx->device_frozen));
232 
233 	for (i = 0; i < bus->nr_devices; i++) {
234 		sdev = ssb_device_get(&bus->devices[i]);
235 
236 		if (!sdev->dev || !sdev->dev->driver ||
237 		    !device_is_registered(sdev->dev)) {
238 			ssb_device_put(sdev);
239 			continue;
240 		}
241 		sdrv = drv_to_ssb_drv(sdev->dev->driver);
242 		if (SSB_WARN_ON(!sdrv->remove))
243 			continue;
244 		sdrv->remove(sdev);
245 		ctx->device_frozen[i] = 1;
246 	}
247 
248 	return 0;
249 }
250 
251 /** ssb_devices_thaw - Unfreeze all devices on the bus.
252  *
253  * This will re-attach the device drivers and re-init the devices.
254  *
255  * @ctx: The context structure from ssb_devices_freeze()
256  */
257 int ssb_devices_thaw(struct ssb_freeze_context *ctx)
258 {
259 	struct ssb_bus *bus = ctx->bus;
260 	struct ssb_device *sdev;
261 	struct ssb_driver *sdrv;
262 	unsigned int i;
263 	int err, result = 0;
264 
265 	for (i = 0; i < bus->nr_devices; i++) {
266 		if (!ctx->device_frozen[i])
267 			continue;
268 		sdev = &bus->devices[i];
269 
270 		if (SSB_WARN_ON(!sdev->dev || !sdev->dev->driver))
271 			continue;
272 		sdrv = drv_to_ssb_drv(sdev->dev->driver);
273 		if (SSB_WARN_ON(!sdrv || !sdrv->probe))
274 			continue;
275 
276 		err = sdrv->probe(sdev, &sdev->id);
277 		if (err) {
278 			ssb_printk(KERN_ERR PFX "Failed to thaw device %s\n",
279 				   dev_name(sdev->dev));
280 			result = err;
281 		}
282 		ssb_device_put(sdev);
283 	}
284 
285 	return result;
286 }
287 #endif /* CONFIG_SSB_SPROM */
288 
289 static void ssb_device_shutdown(struct device *dev)
290 {
291 	struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
292 	struct ssb_driver *ssb_drv;
293 
294 	if (!dev->driver)
295 		return;
296 	ssb_drv = drv_to_ssb_drv(dev->driver);
297 	if (ssb_drv && ssb_drv->shutdown)
298 		ssb_drv->shutdown(ssb_dev);
299 }
300 
301 static int ssb_device_remove(struct device *dev)
302 {
303 	struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
304 	struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
305 
306 	if (ssb_drv && ssb_drv->remove)
307 		ssb_drv->remove(ssb_dev);
308 	ssb_device_put(ssb_dev);
309 
310 	return 0;
311 }
312 
313 static int ssb_device_probe(struct device *dev)
314 {
315 	struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
316 	struct ssb_driver *ssb_drv = drv_to_ssb_drv(dev->driver);
317 	int err = 0;
318 
319 	ssb_device_get(ssb_dev);
320 	if (ssb_drv && ssb_drv->probe)
321 		err = ssb_drv->probe(ssb_dev, &ssb_dev->id);
322 	if (err)
323 		ssb_device_put(ssb_dev);
324 
325 	return err;
326 }
327 
328 static int ssb_match_devid(const struct ssb_device_id *tabid,
329 			   const struct ssb_device_id *devid)
330 {
331 	if ((tabid->vendor != devid->vendor) &&
332 	    tabid->vendor != SSB_ANY_VENDOR)
333 		return 0;
334 	if ((tabid->coreid != devid->coreid) &&
335 	    tabid->coreid != SSB_ANY_ID)
336 		return 0;
337 	if ((tabid->revision != devid->revision) &&
338 	    tabid->revision != SSB_ANY_REV)
339 		return 0;
340 	return 1;
341 }
342 
343 static int ssb_bus_match(struct device *dev, struct device_driver *drv)
344 {
345 	struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
346 	struct ssb_driver *ssb_drv = drv_to_ssb_drv(drv);
347 	const struct ssb_device_id *id;
348 
349 	for (id = ssb_drv->id_table;
350 	     id->vendor || id->coreid || id->revision;
351 	     id++) {
352 		if (ssb_match_devid(id, &ssb_dev->id))
353 			return 1; /* found */
354 	}
355 
356 	return 0;
357 }
358 
359 static int ssb_device_uevent(struct device *dev, struct kobj_uevent_env *env)
360 {
361 	struct ssb_device *ssb_dev = dev_to_ssb_dev(dev);
362 
363 	if (!dev)
364 		return -ENODEV;
365 
366 	return add_uevent_var(env,
367 			     "MODALIAS=ssb:v%04Xid%04Xrev%02X",
368 			     ssb_dev->id.vendor, ssb_dev->id.coreid,
369 			     ssb_dev->id.revision);
370 }
371 
372 #define ssb_config_attr(attrib, field, format_string) \
373 static ssize_t \
374 attrib##_show(struct device *dev, struct device_attribute *attr, char *buf) \
375 { \
376 	return sprintf(buf, format_string, dev_to_ssb_dev(dev)->field); \
377 }
378 
379 ssb_config_attr(core_num, core_index, "%u\n")
380 ssb_config_attr(coreid, id.coreid, "0x%04x\n")
381 ssb_config_attr(vendor, id.vendor, "0x%04x\n")
382 ssb_config_attr(revision, id.revision, "%u\n")
383 ssb_config_attr(irq, irq, "%u\n")
384 static ssize_t
385 name_show(struct device *dev, struct device_attribute *attr, char *buf)
386 {
387 	return sprintf(buf, "%s\n",
388 		       ssb_core_name(dev_to_ssb_dev(dev)->id.coreid));
389 }
390 
391 static struct device_attribute ssb_device_attrs[] = {
392 	__ATTR_RO(name),
393 	__ATTR_RO(core_num),
394 	__ATTR_RO(coreid),
395 	__ATTR_RO(vendor),
396 	__ATTR_RO(revision),
397 	__ATTR_RO(irq),
398 	__ATTR_NULL,
399 };
400 
401 static struct bus_type ssb_bustype = {
402 	.name		= "ssb",
403 	.match		= ssb_bus_match,
404 	.probe		= ssb_device_probe,
405 	.remove		= ssb_device_remove,
406 	.shutdown	= ssb_device_shutdown,
407 	.suspend	= ssb_device_suspend,
408 	.resume		= ssb_device_resume,
409 	.uevent		= ssb_device_uevent,
410 	.dev_attrs	= ssb_device_attrs,
411 };
412 
413 static void ssb_buses_lock(void)
414 {
415 	/* See the comment at the ssb_is_early_boot definition */
416 	if (!ssb_is_early_boot)
417 		mutex_lock(&buses_mutex);
418 }
419 
420 static void ssb_buses_unlock(void)
421 {
422 	/* See the comment at the ssb_is_early_boot definition */
423 	if (!ssb_is_early_boot)
424 		mutex_unlock(&buses_mutex);
425 }
426 
427 static void ssb_devices_unregister(struct ssb_bus *bus)
428 {
429 	struct ssb_device *sdev;
430 	int i;
431 
432 	for (i = bus->nr_devices - 1; i >= 0; i--) {
433 		sdev = &(bus->devices[i]);
434 		if (sdev->dev)
435 			device_unregister(sdev->dev);
436 	}
437 
438 #ifdef CONFIG_SSB_EMBEDDED
439 	if (bus->bustype == SSB_BUSTYPE_SSB)
440 		platform_device_unregister(bus->watchdog);
441 #endif
442 }
443 
444 void ssb_bus_unregister(struct ssb_bus *bus)
445 {
446 	ssb_buses_lock();
447 	ssb_devices_unregister(bus);
448 	list_del(&bus->list);
449 	ssb_buses_unlock();
450 
451 	ssb_pcmcia_exit(bus);
452 	ssb_pci_exit(bus);
453 	ssb_iounmap(bus);
454 }
455 EXPORT_SYMBOL(ssb_bus_unregister);
456 
457 static void ssb_release_dev(struct device *dev)
458 {
459 	struct __ssb_dev_wrapper *devwrap;
460 
461 	devwrap = container_of(dev, struct __ssb_dev_wrapper, dev);
462 	kfree(devwrap);
463 }
464 
465 static int ssb_devices_register(struct ssb_bus *bus)
466 {
467 	struct ssb_device *sdev;
468 	struct device *dev;
469 	struct __ssb_dev_wrapper *devwrap;
470 	int i, err = 0;
471 	int dev_idx = 0;
472 
473 	for (i = 0; i < bus->nr_devices; i++) {
474 		sdev = &(bus->devices[i]);
475 
476 		/* We don't register SSB-system devices to the kernel,
477 		 * as the drivers for them are built into SSB. */
478 		switch (sdev->id.coreid) {
479 		case SSB_DEV_CHIPCOMMON:
480 		case SSB_DEV_PCI:
481 		case SSB_DEV_PCIE:
482 		case SSB_DEV_PCMCIA:
483 		case SSB_DEV_MIPS:
484 		case SSB_DEV_MIPS_3302:
485 		case SSB_DEV_EXTIF:
486 			continue;
487 		}
488 
489 		devwrap = kzalloc(sizeof(*devwrap), GFP_KERNEL);
490 		if (!devwrap) {
491 			ssb_printk(KERN_ERR PFX
492 				   "Could not allocate device\n");
493 			err = -ENOMEM;
494 			goto error;
495 		}
496 		dev = &devwrap->dev;
497 		devwrap->sdev = sdev;
498 
499 		dev->release = ssb_release_dev;
500 		dev->bus = &ssb_bustype;
501 		dev_set_name(dev, "ssb%u:%d", bus->busnumber, dev_idx);
502 
503 		switch (bus->bustype) {
504 		case SSB_BUSTYPE_PCI:
505 #ifdef CONFIG_SSB_PCIHOST
506 			sdev->irq = bus->host_pci->irq;
507 			dev->parent = &bus->host_pci->dev;
508 			sdev->dma_dev = dev->parent;
509 #endif
510 			break;
511 		case SSB_BUSTYPE_PCMCIA:
512 #ifdef CONFIG_SSB_PCMCIAHOST
513 			sdev->irq = bus->host_pcmcia->irq;
514 			dev->parent = &bus->host_pcmcia->dev;
515 #endif
516 			break;
517 		case SSB_BUSTYPE_SDIO:
518 #ifdef CONFIG_SSB_SDIOHOST
519 			dev->parent = &bus->host_sdio->dev;
520 #endif
521 			break;
522 		case SSB_BUSTYPE_SSB:
523 			dev->dma_mask = &dev->coherent_dma_mask;
524 			sdev->dma_dev = dev;
525 			break;
526 		}
527 
528 		sdev->dev = dev;
529 		err = device_register(dev);
530 		if (err) {
531 			ssb_printk(KERN_ERR PFX
532 				   "Could not register %s\n",
533 				   dev_name(dev));
534 			/* Set dev to NULL to not unregister
535 			 * dev on error unwinding. */
536 			sdev->dev = NULL;
537 			kfree(devwrap);
538 			goto error;
539 		}
540 		dev_idx++;
541 	}
542 
543 	return 0;
544 error:
545 	/* Unwind the already registered devices. */
546 	ssb_devices_unregister(bus);
547 	return err;
548 }
549 
550 /* Needs ssb_buses_lock() */
551 static int __devinit ssb_attach_queued_buses(void)
552 {
553 	struct ssb_bus *bus, *n;
554 	int err = 0;
555 	int drop_them_all = 0;
556 
557 	list_for_each_entry_safe(bus, n, &attach_queue, list) {
558 		if (drop_them_all) {
559 			list_del(&bus->list);
560 			continue;
561 		}
562 		/* Can't init the PCIcore in ssb_bus_register(), as that
563 		 * is too early in boot for embedded systems
564 		 * (no udelay() available). So do it here in attach stage.
565 		 */
566 		err = ssb_bus_powerup(bus, 0);
567 		if (err)
568 			goto error;
569 		ssb_pcicore_init(&bus->pcicore);
570 		if (bus->bustype == SSB_BUSTYPE_SSB)
571 			ssb_watchdog_register(bus);
572 		ssb_bus_may_powerdown(bus);
573 
574 		err = ssb_devices_register(bus);
575 error:
576 		if (err) {
577 			drop_them_all = 1;
578 			list_del(&bus->list);
579 			continue;
580 		}
581 		list_move_tail(&bus->list, &buses);
582 	}
583 
584 	return err;
585 }
586 
587 static u8 ssb_ssb_read8(struct ssb_device *dev, u16 offset)
588 {
589 	struct ssb_bus *bus = dev->bus;
590 
591 	offset += dev->core_index * SSB_CORE_SIZE;
592 	return readb(bus->mmio + offset);
593 }
594 
595 static u16 ssb_ssb_read16(struct ssb_device *dev, u16 offset)
596 {
597 	struct ssb_bus *bus = dev->bus;
598 
599 	offset += dev->core_index * SSB_CORE_SIZE;
600 	return readw(bus->mmio + offset);
601 }
602 
603 static u32 ssb_ssb_read32(struct ssb_device *dev, u16 offset)
604 {
605 	struct ssb_bus *bus = dev->bus;
606 
607 	offset += dev->core_index * SSB_CORE_SIZE;
608 	return readl(bus->mmio + offset);
609 }
610 
611 #ifdef CONFIG_SSB_BLOCKIO
612 static void ssb_ssb_block_read(struct ssb_device *dev, void *buffer,
613 			       size_t count, u16 offset, u8 reg_width)
614 {
615 	struct ssb_bus *bus = dev->bus;
616 	void __iomem *addr;
617 
618 	offset += dev->core_index * SSB_CORE_SIZE;
619 	addr = bus->mmio + offset;
620 
621 	switch (reg_width) {
622 	case sizeof(u8): {
623 		u8 *buf = buffer;
624 
625 		while (count) {
626 			*buf = __raw_readb(addr);
627 			buf++;
628 			count--;
629 		}
630 		break;
631 	}
632 	case sizeof(u16): {
633 		__le16 *buf = buffer;
634 
635 		SSB_WARN_ON(count & 1);
636 		while (count) {
637 			*buf = (__force __le16)__raw_readw(addr);
638 			buf++;
639 			count -= 2;
640 		}
641 		break;
642 	}
643 	case sizeof(u32): {
644 		__le32 *buf = buffer;
645 
646 		SSB_WARN_ON(count & 3);
647 		while (count) {
648 			*buf = (__force __le32)__raw_readl(addr);
649 			buf++;
650 			count -= 4;
651 		}
652 		break;
653 	}
654 	default:
655 		SSB_WARN_ON(1);
656 	}
657 }
658 #endif /* CONFIG_SSB_BLOCKIO */
659 
660 static void ssb_ssb_write8(struct ssb_device *dev, u16 offset, u8 value)
661 {
662 	struct ssb_bus *bus = dev->bus;
663 
664 	offset += dev->core_index * SSB_CORE_SIZE;
665 	writeb(value, bus->mmio + offset);
666 }
667 
668 static void ssb_ssb_write16(struct ssb_device *dev, u16 offset, u16 value)
669 {
670 	struct ssb_bus *bus = dev->bus;
671 
672 	offset += dev->core_index * SSB_CORE_SIZE;
673 	writew(value, bus->mmio + offset);
674 }
675 
676 static void ssb_ssb_write32(struct ssb_device *dev, u16 offset, u32 value)
677 {
678 	struct ssb_bus *bus = dev->bus;
679 
680 	offset += dev->core_index * SSB_CORE_SIZE;
681 	writel(value, bus->mmio + offset);
682 }
683 
684 #ifdef CONFIG_SSB_BLOCKIO
685 static void ssb_ssb_block_write(struct ssb_device *dev, const void *buffer,
686 				size_t count, u16 offset, u8 reg_width)
687 {
688 	struct ssb_bus *bus = dev->bus;
689 	void __iomem *addr;
690 
691 	offset += dev->core_index * SSB_CORE_SIZE;
692 	addr = bus->mmio + offset;
693 
694 	switch (reg_width) {
695 	case sizeof(u8): {
696 		const u8 *buf = buffer;
697 
698 		while (count) {
699 			__raw_writeb(*buf, addr);
700 			buf++;
701 			count--;
702 		}
703 		break;
704 	}
705 	case sizeof(u16): {
706 		const __le16 *buf = buffer;
707 
708 		SSB_WARN_ON(count & 1);
709 		while (count) {
710 			__raw_writew((__force u16)(*buf), addr);
711 			buf++;
712 			count -= 2;
713 		}
714 		break;
715 	}
716 	case sizeof(u32): {
717 		const __le32 *buf = buffer;
718 
719 		SSB_WARN_ON(count & 3);
720 		while (count) {
721 			__raw_writel((__force u32)(*buf), addr);
722 			buf++;
723 			count -= 4;
724 		}
725 		break;
726 	}
727 	default:
728 		SSB_WARN_ON(1);
729 	}
730 }
731 #endif /* CONFIG_SSB_BLOCKIO */
732 
733 /* Ops for the plain SSB bus without a host-device (no PCI or PCMCIA). */
734 static const struct ssb_bus_ops ssb_ssb_ops = {
735 	.read8		= ssb_ssb_read8,
736 	.read16		= ssb_ssb_read16,
737 	.read32		= ssb_ssb_read32,
738 	.write8		= ssb_ssb_write8,
739 	.write16	= ssb_ssb_write16,
740 	.write32	= ssb_ssb_write32,
741 #ifdef CONFIG_SSB_BLOCKIO
742 	.block_read	= ssb_ssb_block_read,
743 	.block_write	= ssb_ssb_block_write,
744 #endif
745 };
746 
747 static int ssb_fetch_invariants(struct ssb_bus *bus,
748 				ssb_invariants_func_t get_invariants)
749 {
750 	struct ssb_init_invariants iv;
751 	int err;
752 
753 	memset(&iv, 0, sizeof(iv));
754 	err = get_invariants(bus, &iv);
755 	if (err)
756 		goto out;
757 	memcpy(&bus->boardinfo, &iv.boardinfo, sizeof(iv.boardinfo));
758 	memcpy(&bus->sprom, &iv.sprom, sizeof(iv.sprom));
759 	bus->has_cardbus_slot = iv.has_cardbus_slot;
760 out:
761 	return err;
762 }
763 
764 static int __devinit ssb_bus_register(struct ssb_bus *bus,
765 				      ssb_invariants_func_t get_invariants,
766 				      unsigned long baseaddr)
767 {
768 	int err;
769 
770 	spin_lock_init(&bus->bar_lock);
771 	INIT_LIST_HEAD(&bus->list);
772 #ifdef CONFIG_SSB_EMBEDDED
773 	spin_lock_init(&bus->gpio_lock);
774 #endif
775 
776 	/* Powerup the bus */
777 	err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
778 	if (err)
779 		goto out;
780 
781 	/* Init SDIO-host device (if any), before the scan */
782 	err = ssb_sdio_init(bus);
783 	if (err)
784 		goto err_disable_xtal;
785 
786 	ssb_buses_lock();
787 	bus->busnumber = next_busnumber;
788 	/* Scan for devices (cores) */
789 	err = ssb_bus_scan(bus, baseaddr);
790 	if (err)
791 		goto err_sdio_exit;
792 
793 	/* Init PCI-host device (if any) */
794 	err = ssb_pci_init(bus);
795 	if (err)
796 		goto err_unmap;
797 	/* Init PCMCIA-host device (if any) */
798 	err = ssb_pcmcia_init(bus);
799 	if (err)
800 		goto err_pci_exit;
801 
802 	/* Initialize basic system devices (if available) */
803 	err = ssb_bus_powerup(bus, 0);
804 	if (err)
805 		goto err_pcmcia_exit;
806 	ssb_chipcommon_init(&bus->chipco);
807 	ssb_extif_init(&bus->extif);
808 	ssb_mipscore_init(&bus->mipscore);
809 	err = ssb_gpio_init(bus);
810 	if (err == -ENOTSUPP)
811 		ssb_dprintk(KERN_DEBUG PFX "GPIO driver not activated\n");
812 	else if (err)
813 		ssb_dprintk(KERN_ERR PFX
814 			   "Error registering GPIO driver: %i\n", err);
815 	err = ssb_fetch_invariants(bus, get_invariants);
816 	if (err) {
817 		ssb_bus_may_powerdown(bus);
818 		goto err_pcmcia_exit;
819 	}
820 	ssb_bus_may_powerdown(bus);
821 
822 	/* Queue it for attach.
823 	 * See the comment at the ssb_is_early_boot definition. */
824 	list_add_tail(&bus->list, &attach_queue);
825 	if (!ssb_is_early_boot) {
826 		/* This is not early boot, so we must attach the bus now */
827 		err = ssb_attach_queued_buses();
828 		if (err)
829 			goto err_dequeue;
830 	}
831 	next_busnumber++;
832 	ssb_buses_unlock();
833 
834 out:
835 	return err;
836 
837 err_dequeue:
838 	list_del(&bus->list);
839 err_pcmcia_exit:
840 	ssb_pcmcia_exit(bus);
841 err_pci_exit:
842 	ssb_pci_exit(bus);
843 err_unmap:
844 	ssb_iounmap(bus);
845 err_sdio_exit:
846 	ssb_sdio_exit(bus);
847 err_disable_xtal:
848 	ssb_buses_unlock();
849 	ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
850 	return err;
851 }
852 
853 #ifdef CONFIG_SSB_PCIHOST
854 int __devinit ssb_bus_pcibus_register(struct ssb_bus *bus,
855 				      struct pci_dev *host_pci)
856 {
857 	int err;
858 
859 	bus->bustype = SSB_BUSTYPE_PCI;
860 	bus->host_pci = host_pci;
861 	bus->ops = &ssb_pci_ops;
862 
863 	err = ssb_bus_register(bus, ssb_pci_get_invariants, 0);
864 	if (!err) {
865 		ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
866 			   "PCI device %s\n", dev_name(&host_pci->dev));
867 	} else {
868 		ssb_printk(KERN_ERR PFX "Failed to register PCI version"
869 			   " of SSB with error %d\n", err);
870 	}
871 
872 	return err;
873 }
874 EXPORT_SYMBOL(ssb_bus_pcibus_register);
875 #endif /* CONFIG_SSB_PCIHOST */
876 
877 #ifdef CONFIG_SSB_PCMCIAHOST
878 int __devinit ssb_bus_pcmciabus_register(struct ssb_bus *bus,
879 					 struct pcmcia_device *pcmcia_dev,
880 					 unsigned long baseaddr)
881 {
882 	int err;
883 
884 	bus->bustype = SSB_BUSTYPE_PCMCIA;
885 	bus->host_pcmcia = pcmcia_dev;
886 	bus->ops = &ssb_pcmcia_ops;
887 
888 	err = ssb_bus_register(bus, ssb_pcmcia_get_invariants, baseaddr);
889 	if (!err) {
890 		ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
891 			   "PCMCIA device %s\n", pcmcia_dev->devname);
892 	}
893 
894 	return err;
895 }
896 EXPORT_SYMBOL(ssb_bus_pcmciabus_register);
897 #endif /* CONFIG_SSB_PCMCIAHOST */
898 
899 #ifdef CONFIG_SSB_SDIOHOST
900 int __devinit ssb_bus_sdiobus_register(struct ssb_bus *bus,
901 				       struct sdio_func *func,
902 				       unsigned int quirks)
903 {
904 	int err;
905 
906 	bus->bustype = SSB_BUSTYPE_SDIO;
907 	bus->host_sdio = func;
908 	bus->ops = &ssb_sdio_ops;
909 	bus->quirks = quirks;
910 
911 	err = ssb_bus_register(bus, ssb_sdio_get_invariants, ~0);
912 	if (!err) {
913 		ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found on "
914 			   "SDIO device %s\n", sdio_func_id(func));
915 	}
916 
917 	return err;
918 }
919 EXPORT_SYMBOL(ssb_bus_sdiobus_register);
920 #endif /* CONFIG_SSB_PCMCIAHOST */
921 
922 int __devinit ssb_bus_ssbbus_register(struct ssb_bus *bus,
923 				      unsigned long baseaddr,
924 				      ssb_invariants_func_t get_invariants)
925 {
926 	int err;
927 
928 	bus->bustype = SSB_BUSTYPE_SSB;
929 	bus->ops = &ssb_ssb_ops;
930 
931 	err = ssb_bus_register(bus, get_invariants, baseaddr);
932 	if (!err) {
933 		ssb_printk(KERN_INFO PFX "Sonics Silicon Backplane found at "
934 			   "address 0x%08lX\n", baseaddr);
935 	}
936 
937 	return err;
938 }
939 
940 int __ssb_driver_register(struct ssb_driver *drv, struct module *owner)
941 {
942 	drv->drv.name = drv->name;
943 	drv->drv.bus = &ssb_bustype;
944 	drv->drv.owner = owner;
945 
946 	return driver_register(&drv->drv);
947 }
948 EXPORT_SYMBOL(__ssb_driver_register);
949 
950 void ssb_driver_unregister(struct ssb_driver *drv)
951 {
952 	driver_unregister(&drv->drv);
953 }
954 EXPORT_SYMBOL(ssb_driver_unregister);
955 
956 void ssb_set_devtypedata(struct ssb_device *dev, void *data)
957 {
958 	struct ssb_bus *bus = dev->bus;
959 	struct ssb_device *ent;
960 	int i;
961 
962 	for (i = 0; i < bus->nr_devices; i++) {
963 		ent = &(bus->devices[i]);
964 		if (ent->id.vendor != dev->id.vendor)
965 			continue;
966 		if (ent->id.coreid != dev->id.coreid)
967 			continue;
968 
969 		ent->devtypedata = data;
970 	}
971 }
972 EXPORT_SYMBOL(ssb_set_devtypedata);
973 
974 static u32 clkfactor_f6_resolve(u32 v)
975 {
976 	/* map the magic values */
977 	switch (v) {
978 	case SSB_CHIPCO_CLK_F6_2:
979 		return 2;
980 	case SSB_CHIPCO_CLK_F6_3:
981 		return 3;
982 	case SSB_CHIPCO_CLK_F6_4:
983 		return 4;
984 	case SSB_CHIPCO_CLK_F6_5:
985 		return 5;
986 	case SSB_CHIPCO_CLK_F6_6:
987 		return 6;
988 	case SSB_CHIPCO_CLK_F6_7:
989 		return 7;
990 	}
991 	return 0;
992 }
993 
994 /* Calculate the speed the backplane would run at a given set of clockcontrol values */
995 u32 ssb_calc_clock_rate(u32 plltype, u32 n, u32 m)
996 {
997 	u32 n1, n2, clock, m1, m2, m3, mc;
998 
999 	n1 = (n & SSB_CHIPCO_CLK_N1);
1000 	n2 = ((n & SSB_CHIPCO_CLK_N2) >> SSB_CHIPCO_CLK_N2_SHIFT);
1001 
1002 	switch (plltype) {
1003 	case SSB_PLLTYPE_6: /* 100/200 or 120/240 only */
1004 		if (m & SSB_CHIPCO_CLK_T6_MMASK)
1005 			return SSB_CHIPCO_CLK_T6_M1;
1006 		return SSB_CHIPCO_CLK_T6_M0;
1007 	case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
1008 	case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
1009 	case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
1010 	case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
1011 		n1 = clkfactor_f6_resolve(n1);
1012 		n2 += SSB_CHIPCO_CLK_F5_BIAS;
1013 		break;
1014 	case SSB_PLLTYPE_2: /* 48Mhz, 4 dividers */
1015 		n1 += SSB_CHIPCO_CLK_T2_BIAS;
1016 		n2 += SSB_CHIPCO_CLK_T2_BIAS;
1017 		SSB_WARN_ON(!((n1 >= 2) && (n1 <= 7)));
1018 		SSB_WARN_ON(!((n2 >= 5) && (n2 <= 23)));
1019 		break;
1020 	case SSB_PLLTYPE_5: /* 25Mhz, 4 dividers */
1021 		return 100000000;
1022 	default:
1023 		SSB_WARN_ON(1);
1024 	}
1025 
1026 	switch (plltype) {
1027 	case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
1028 	case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
1029 		clock = SSB_CHIPCO_CLK_BASE2 * n1 * n2;
1030 		break;
1031 	default:
1032 		clock = SSB_CHIPCO_CLK_BASE1 * n1 * n2;
1033 	}
1034 	if (!clock)
1035 		return 0;
1036 
1037 	m1 = (m & SSB_CHIPCO_CLK_M1);
1038 	m2 = ((m & SSB_CHIPCO_CLK_M2) >> SSB_CHIPCO_CLK_M2_SHIFT);
1039 	m3 = ((m & SSB_CHIPCO_CLK_M3) >> SSB_CHIPCO_CLK_M3_SHIFT);
1040 	mc = ((m & SSB_CHIPCO_CLK_MC) >> SSB_CHIPCO_CLK_MC_SHIFT);
1041 
1042 	switch (plltype) {
1043 	case SSB_PLLTYPE_1: /* 48Mhz base, 3 dividers */
1044 	case SSB_PLLTYPE_3: /* 25Mhz, 2 dividers */
1045 	case SSB_PLLTYPE_4: /* 48Mhz, 4 dividers */
1046 	case SSB_PLLTYPE_7: /* 25Mhz, 4 dividers */
1047 		m1 = clkfactor_f6_resolve(m1);
1048 		if ((plltype == SSB_PLLTYPE_1) ||
1049 		    (plltype == SSB_PLLTYPE_3))
1050 			m2 += SSB_CHIPCO_CLK_F5_BIAS;
1051 		else
1052 			m2 = clkfactor_f6_resolve(m2);
1053 		m3 = clkfactor_f6_resolve(m3);
1054 
1055 		switch (mc) {
1056 		case SSB_CHIPCO_CLK_MC_BYPASS:
1057 			return clock;
1058 		case SSB_CHIPCO_CLK_MC_M1:
1059 			return (clock / m1);
1060 		case SSB_CHIPCO_CLK_MC_M1M2:
1061 			return (clock / (m1 * m2));
1062 		case SSB_CHIPCO_CLK_MC_M1M2M3:
1063 			return (clock / (m1 * m2 * m3));
1064 		case SSB_CHIPCO_CLK_MC_M1M3:
1065 			return (clock / (m1 * m3));
1066 		}
1067 		return 0;
1068 	case SSB_PLLTYPE_2:
1069 		m1 += SSB_CHIPCO_CLK_T2_BIAS;
1070 		m2 += SSB_CHIPCO_CLK_T2M2_BIAS;
1071 		m3 += SSB_CHIPCO_CLK_T2_BIAS;
1072 		SSB_WARN_ON(!((m1 >= 2) && (m1 <= 7)));
1073 		SSB_WARN_ON(!((m2 >= 3) && (m2 <= 10)));
1074 		SSB_WARN_ON(!((m3 >= 2) && (m3 <= 7)));
1075 
1076 		if (!(mc & SSB_CHIPCO_CLK_T2MC_M1BYP))
1077 			clock /= m1;
1078 		if (!(mc & SSB_CHIPCO_CLK_T2MC_M2BYP))
1079 			clock /= m2;
1080 		if (!(mc & SSB_CHIPCO_CLK_T2MC_M3BYP))
1081 			clock /= m3;
1082 		return clock;
1083 	default:
1084 		SSB_WARN_ON(1);
1085 	}
1086 	return 0;
1087 }
1088 
1089 /* Get the current speed the backplane is running at */
1090 u32 ssb_clockspeed(struct ssb_bus *bus)
1091 {
1092 	u32 rate;
1093 	u32 plltype;
1094 	u32 clkctl_n, clkctl_m;
1095 
1096 	if (bus->chipco.capabilities & SSB_CHIPCO_CAP_PMU)
1097 		return ssb_pmu_get_controlclock(&bus->chipco);
1098 
1099 	if (ssb_extif_available(&bus->extif))
1100 		ssb_extif_get_clockcontrol(&bus->extif, &plltype,
1101 					   &clkctl_n, &clkctl_m);
1102 	else if (bus->chipco.dev)
1103 		ssb_chipco_get_clockcontrol(&bus->chipco, &plltype,
1104 					    &clkctl_n, &clkctl_m);
1105 	else
1106 		return 0;
1107 
1108 	if (bus->chip_id == 0x5365) {
1109 		rate = 100000000;
1110 	} else {
1111 		rate = ssb_calc_clock_rate(plltype, clkctl_n, clkctl_m);
1112 		if (plltype == SSB_PLLTYPE_3) /* 25Mhz, 2 dividers */
1113 			rate /= 2;
1114 	}
1115 
1116 	return rate;
1117 }
1118 EXPORT_SYMBOL(ssb_clockspeed);
1119 
1120 static u32 ssb_tmslow_reject_bitmask(struct ssb_device *dev)
1121 {
1122 	u32 rev = ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_SSBREV;
1123 
1124 	/* The REJECT bit seems to be different for Backplane rev 2.3 */
1125 	switch (rev) {
1126 	case SSB_IDLOW_SSBREV_22:
1127 	case SSB_IDLOW_SSBREV_24:
1128 	case SSB_IDLOW_SSBREV_26:
1129 		return SSB_TMSLOW_REJECT;
1130 	case SSB_IDLOW_SSBREV_23:
1131 		return SSB_TMSLOW_REJECT_23;
1132 	case SSB_IDLOW_SSBREV_25:     /* TODO - find the proper REJECT bit */
1133 	case SSB_IDLOW_SSBREV_27:     /* same here */
1134 		return SSB_TMSLOW_REJECT;	/* this is a guess */
1135 	default:
1136 		WARN(1, KERN_INFO "ssb: Backplane Revision 0x%.8X\n", rev);
1137 	}
1138 	return (SSB_TMSLOW_REJECT | SSB_TMSLOW_REJECT_23);
1139 }
1140 
1141 int ssb_device_is_enabled(struct ssb_device *dev)
1142 {
1143 	u32 val;
1144 	u32 reject;
1145 
1146 	reject = ssb_tmslow_reject_bitmask(dev);
1147 	val = ssb_read32(dev, SSB_TMSLOW);
1148 	val &= SSB_TMSLOW_CLOCK | SSB_TMSLOW_RESET | reject;
1149 
1150 	return (val == SSB_TMSLOW_CLOCK);
1151 }
1152 EXPORT_SYMBOL(ssb_device_is_enabled);
1153 
1154 static void ssb_flush_tmslow(struct ssb_device *dev)
1155 {
1156 	/* Make _really_ sure the device has finished the TMSLOW
1157 	 * register write transaction, as we risk running into
1158 	 * a machine check exception otherwise.
1159 	 * Do this by reading the register back to commit the
1160 	 * PCI write and delay an additional usec for the device
1161 	 * to react to the change. */
1162 	ssb_read32(dev, SSB_TMSLOW);
1163 	udelay(1);
1164 }
1165 
1166 void ssb_device_enable(struct ssb_device *dev, u32 core_specific_flags)
1167 {
1168 	u32 val;
1169 
1170 	ssb_device_disable(dev, core_specific_flags);
1171 	ssb_write32(dev, SSB_TMSLOW,
1172 		    SSB_TMSLOW_RESET | SSB_TMSLOW_CLOCK |
1173 		    SSB_TMSLOW_FGC | core_specific_flags);
1174 	ssb_flush_tmslow(dev);
1175 
1176 	/* Clear SERR if set. This is a hw bug workaround. */
1177 	if (ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_SERR)
1178 		ssb_write32(dev, SSB_TMSHIGH, 0);
1179 
1180 	val = ssb_read32(dev, SSB_IMSTATE);
1181 	if (val & (SSB_IMSTATE_IBE | SSB_IMSTATE_TO)) {
1182 		val &= ~(SSB_IMSTATE_IBE | SSB_IMSTATE_TO);
1183 		ssb_write32(dev, SSB_IMSTATE, val);
1184 	}
1185 
1186 	ssb_write32(dev, SSB_TMSLOW,
1187 		    SSB_TMSLOW_CLOCK | SSB_TMSLOW_FGC |
1188 		    core_specific_flags);
1189 	ssb_flush_tmslow(dev);
1190 
1191 	ssb_write32(dev, SSB_TMSLOW, SSB_TMSLOW_CLOCK |
1192 		    core_specific_flags);
1193 	ssb_flush_tmslow(dev);
1194 }
1195 EXPORT_SYMBOL(ssb_device_enable);
1196 
1197 /* Wait for bitmask in a register to get set or cleared.
1198  * timeout is in units of ten-microseconds */
1199 static int ssb_wait_bits(struct ssb_device *dev, u16 reg, u32 bitmask,
1200 			 int timeout, int set)
1201 {
1202 	int i;
1203 	u32 val;
1204 
1205 	for (i = 0; i < timeout; i++) {
1206 		val = ssb_read32(dev, reg);
1207 		if (set) {
1208 			if ((val & bitmask) == bitmask)
1209 				return 0;
1210 		} else {
1211 			if (!(val & bitmask))
1212 				return 0;
1213 		}
1214 		udelay(10);
1215 	}
1216 	printk(KERN_ERR PFX "Timeout waiting for bitmask %08X on "
1217 			    "register %04X to %s.\n",
1218 	       bitmask, reg, (set ? "set" : "clear"));
1219 
1220 	return -ETIMEDOUT;
1221 }
1222 
1223 void ssb_device_disable(struct ssb_device *dev, u32 core_specific_flags)
1224 {
1225 	u32 reject, val;
1226 
1227 	if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_RESET)
1228 		return;
1229 
1230 	reject = ssb_tmslow_reject_bitmask(dev);
1231 
1232 	if (ssb_read32(dev, SSB_TMSLOW) & SSB_TMSLOW_CLOCK) {
1233 		ssb_write32(dev, SSB_TMSLOW, reject | SSB_TMSLOW_CLOCK);
1234 		ssb_wait_bits(dev, SSB_TMSLOW, reject, 1000, 1);
1235 		ssb_wait_bits(dev, SSB_TMSHIGH, SSB_TMSHIGH_BUSY, 1000, 0);
1236 
1237 		if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
1238 			val = ssb_read32(dev, SSB_IMSTATE);
1239 			val |= SSB_IMSTATE_REJECT;
1240 			ssb_write32(dev, SSB_IMSTATE, val);
1241 			ssb_wait_bits(dev, SSB_IMSTATE, SSB_IMSTATE_BUSY, 1000,
1242 				      0);
1243 		}
1244 
1245 		ssb_write32(dev, SSB_TMSLOW,
1246 			SSB_TMSLOW_FGC | SSB_TMSLOW_CLOCK |
1247 			reject | SSB_TMSLOW_RESET |
1248 			core_specific_flags);
1249 		ssb_flush_tmslow(dev);
1250 
1251 		if (ssb_read32(dev, SSB_IDLOW) & SSB_IDLOW_INITIATOR) {
1252 			val = ssb_read32(dev, SSB_IMSTATE);
1253 			val &= ~SSB_IMSTATE_REJECT;
1254 			ssb_write32(dev, SSB_IMSTATE, val);
1255 		}
1256 	}
1257 
1258 	ssb_write32(dev, SSB_TMSLOW,
1259 		    reject | SSB_TMSLOW_RESET |
1260 		    core_specific_flags);
1261 	ssb_flush_tmslow(dev);
1262 }
1263 EXPORT_SYMBOL(ssb_device_disable);
1264 
1265 /* Some chipsets need routing known for PCIe and 64-bit DMA */
1266 static bool ssb_dma_translation_special_bit(struct ssb_device *dev)
1267 {
1268 	u16 chip_id = dev->bus->chip_id;
1269 
1270 	if (dev->id.coreid == SSB_DEV_80211) {
1271 		return (chip_id == 0x4322 || chip_id == 43221 ||
1272 			chip_id == 43231 || chip_id == 43222);
1273 	}
1274 
1275 	return 0;
1276 }
1277 
1278 u32 ssb_dma_translation(struct ssb_device *dev)
1279 {
1280 	switch (dev->bus->bustype) {
1281 	case SSB_BUSTYPE_SSB:
1282 		return 0;
1283 	case SSB_BUSTYPE_PCI:
1284 		if (pci_is_pcie(dev->bus->host_pci) &&
1285 		    ssb_read32(dev, SSB_TMSHIGH) & SSB_TMSHIGH_DMA64) {
1286 			return SSB_PCIE_DMA_H32;
1287 		} else {
1288 			if (ssb_dma_translation_special_bit(dev))
1289 				return SSB_PCIE_DMA_H32;
1290 			else
1291 				return SSB_PCI_DMA;
1292 		}
1293 	default:
1294 		__ssb_dma_not_implemented(dev);
1295 	}
1296 	return 0;
1297 }
1298 EXPORT_SYMBOL(ssb_dma_translation);
1299 
1300 int ssb_bus_may_powerdown(struct ssb_bus *bus)
1301 {
1302 	struct ssb_chipcommon *cc;
1303 	int err = 0;
1304 
1305 	/* On buses where more than one core may be working
1306 	 * at a time, we must not powerdown stuff if there are
1307 	 * still cores that may want to run. */
1308 	if (bus->bustype == SSB_BUSTYPE_SSB)
1309 		goto out;
1310 
1311 	cc = &bus->chipco;
1312 
1313 	if (!cc->dev)
1314 		goto out;
1315 	if (cc->dev->id.revision < 5)
1316 		goto out;
1317 
1318 	ssb_chipco_set_clockmode(cc, SSB_CLKMODE_SLOW);
1319 	err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 0);
1320 	if (err)
1321 		goto error;
1322 out:
1323 #ifdef CONFIG_SSB_DEBUG
1324 	bus->powered_up = 0;
1325 #endif
1326 	return err;
1327 error:
1328 	ssb_printk(KERN_ERR PFX "Bus powerdown failed\n");
1329 	goto out;
1330 }
1331 EXPORT_SYMBOL(ssb_bus_may_powerdown);
1332 
1333 int ssb_bus_powerup(struct ssb_bus *bus, bool dynamic_pctl)
1334 {
1335 	int err;
1336 	enum ssb_clkmode mode;
1337 
1338 	err = ssb_pci_xtal(bus, SSB_GPIO_XTAL | SSB_GPIO_PLL, 1);
1339 	if (err)
1340 		goto error;
1341 
1342 #ifdef CONFIG_SSB_DEBUG
1343 	bus->powered_up = 1;
1344 #endif
1345 
1346 	mode = dynamic_pctl ? SSB_CLKMODE_DYNAMIC : SSB_CLKMODE_FAST;
1347 	ssb_chipco_set_clockmode(&bus->chipco, mode);
1348 
1349 	return 0;
1350 error:
1351 	ssb_printk(KERN_ERR PFX "Bus powerup failed\n");
1352 	return err;
1353 }
1354 EXPORT_SYMBOL(ssb_bus_powerup);
1355 
1356 static void ssb_broadcast_value(struct ssb_device *dev,
1357 				u32 address, u32 data)
1358 {
1359 #ifdef CONFIG_SSB_DRIVER_PCICORE
1360 	/* This is used for both, PCI and ChipCommon core, so be careful. */
1361 	BUILD_BUG_ON(SSB_PCICORE_BCAST_ADDR != SSB_CHIPCO_BCAST_ADDR);
1362 	BUILD_BUG_ON(SSB_PCICORE_BCAST_DATA != SSB_CHIPCO_BCAST_DATA);
1363 #endif
1364 
1365 	ssb_write32(dev, SSB_CHIPCO_BCAST_ADDR, address);
1366 	ssb_read32(dev, SSB_CHIPCO_BCAST_ADDR); /* flush */
1367 	ssb_write32(dev, SSB_CHIPCO_BCAST_DATA, data);
1368 	ssb_read32(dev, SSB_CHIPCO_BCAST_DATA); /* flush */
1369 }
1370 
1371 void ssb_commit_settings(struct ssb_bus *bus)
1372 {
1373 	struct ssb_device *dev;
1374 
1375 #ifdef CONFIG_SSB_DRIVER_PCICORE
1376 	dev = bus->chipco.dev ? bus->chipco.dev : bus->pcicore.dev;
1377 #else
1378 	dev = bus->chipco.dev;
1379 #endif
1380 	if (WARN_ON(!dev))
1381 		return;
1382 	/* This forces an update of the cached registers. */
1383 	ssb_broadcast_value(dev, 0xFD8, 0);
1384 }
1385 EXPORT_SYMBOL(ssb_commit_settings);
1386 
1387 u32 ssb_admatch_base(u32 adm)
1388 {
1389 	u32 base = 0;
1390 
1391 	switch (adm & SSB_ADM_TYPE) {
1392 	case SSB_ADM_TYPE0:
1393 		base = (adm & SSB_ADM_BASE0);
1394 		break;
1395 	case SSB_ADM_TYPE1:
1396 		SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1397 		base = (adm & SSB_ADM_BASE1);
1398 		break;
1399 	case SSB_ADM_TYPE2:
1400 		SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1401 		base = (adm & SSB_ADM_BASE2);
1402 		break;
1403 	default:
1404 		SSB_WARN_ON(1);
1405 	}
1406 
1407 	return base;
1408 }
1409 EXPORT_SYMBOL(ssb_admatch_base);
1410 
1411 u32 ssb_admatch_size(u32 adm)
1412 {
1413 	u32 size = 0;
1414 
1415 	switch (adm & SSB_ADM_TYPE) {
1416 	case SSB_ADM_TYPE0:
1417 		size = ((adm & SSB_ADM_SZ0) >> SSB_ADM_SZ0_SHIFT);
1418 		break;
1419 	case SSB_ADM_TYPE1:
1420 		SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1421 		size = ((adm & SSB_ADM_SZ1) >> SSB_ADM_SZ1_SHIFT);
1422 		break;
1423 	case SSB_ADM_TYPE2:
1424 		SSB_WARN_ON(adm & SSB_ADM_NEG); /* unsupported */
1425 		size = ((adm & SSB_ADM_SZ2) >> SSB_ADM_SZ2_SHIFT);
1426 		break;
1427 	default:
1428 		SSB_WARN_ON(1);
1429 	}
1430 	size = (1 << (size + 1));
1431 
1432 	return size;
1433 }
1434 EXPORT_SYMBOL(ssb_admatch_size);
1435 
1436 static int __init ssb_modinit(void)
1437 {
1438 	int err;
1439 
1440 	/* See the comment at the ssb_is_early_boot definition */
1441 	ssb_is_early_boot = 0;
1442 	err = bus_register(&ssb_bustype);
1443 	if (err)
1444 		return err;
1445 
1446 	/* Maybe we already registered some buses at early boot.
1447 	 * Check for this and attach them
1448 	 */
1449 	ssb_buses_lock();
1450 	err = ssb_attach_queued_buses();
1451 	ssb_buses_unlock();
1452 	if (err) {
1453 		bus_unregister(&ssb_bustype);
1454 		goto out;
1455 	}
1456 
1457 	err = b43_pci_ssb_bridge_init();
1458 	if (err) {
1459 		ssb_printk(KERN_ERR "Broadcom 43xx PCI-SSB-bridge "
1460 			   "initialization failed\n");
1461 		/* don't fail SSB init because of this */
1462 		err = 0;
1463 	}
1464 	err = ssb_gige_init();
1465 	if (err) {
1466 		ssb_printk(KERN_ERR "SSB Broadcom Gigabit Ethernet "
1467 			   "driver initialization failed\n");
1468 		/* don't fail SSB init because of this */
1469 		err = 0;
1470 	}
1471 out:
1472 	return err;
1473 }
1474 /* ssb must be initialized after PCI but before the ssb drivers.
1475  * That means we must use some initcall between subsys_initcall
1476  * and device_initcall. */
1477 fs_initcall(ssb_modinit);
1478 
1479 static void __exit ssb_modexit(void)
1480 {
1481 	ssb_gige_exit();
1482 	b43_pci_ssb_bridge_exit();
1483 	bus_unregister(&ssb_bustype);
1484 }
1485 module_exit(ssb_modexit)
1486