1 /* 2 * Sonics Silicon Backplane 3 * Broadcom PCI-core driver 4 * 5 * Copyright 2005, Broadcom Corporation 6 * Copyright 2006, 2007, Michael Buesch <m@bues.ch> 7 * 8 * Licensed under the GNU/GPL. See COPYING for details. 9 */ 10 11 #include <linux/ssb/ssb.h> 12 #include <linux/pci.h> 13 #include <linux/export.h> 14 #include <linux/delay.h> 15 #include <linux/ssb/ssb_embedded.h> 16 17 #include "ssb_private.h" 18 19 static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address); 20 static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data); 21 static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address); 22 static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device, 23 u8 address, u16 data); 24 25 static inline 26 u32 pcicore_read32(struct ssb_pcicore *pc, u16 offset) 27 { 28 return ssb_read32(pc->dev, offset); 29 } 30 31 static inline 32 void pcicore_write32(struct ssb_pcicore *pc, u16 offset, u32 value) 33 { 34 ssb_write32(pc->dev, offset, value); 35 } 36 37 static inline 38 u16 pcicore_read16(struct ssb_pcicore *pc, u16 offset) 39 { 40 return ssb_read16(pc->dev, offset); 41 } 42 43 static inline 44 void pcicore_write16(struct ssb_pcicore *pc, u16 offset, u16 value) 45 { 46 ssb_write16(pc->dev, offset, value); 47 } 48 49 /************************************************** 50 * Code for hostmode operation. 51 **************************************************/ 52 53 #ifdef CONFIG_SSB_PCICORE_HOSTMODE 54 55 #include <asm/paccess.h> 56 /* Probe a 32bit value on the bus and catch bus exceptions. 57 * Returns nonzero on a bus exception. 58 * This is MIPS specific */ 59 #define mips_busprobe32(val, addr) get_dbe((val), ((u32 *)(addr))) 60 61 /* Assume one-hot slot wiring */ 62 #define SSB_PCI_SLOT_MAX 16 63 64 /* Global lock is OK, as we won't have more than one extpci anyway. */ 65 static DEFINE_SPINLOCK(cfgspace_lock); 66 /* Core to access the external PCI config space. Can only have one. */ 67 static struct ssb_pcicore *extpci_core; 68 69 70 static u32 get_cfgspace_addr(struct ssb_pcicore *pc, 71 unsigned int bus, unsigned int dev, 72 unsigned int func, unsigned int off) 73 { 74 u32 addr = 0; 75 u32 tmp; 76 77 /* We do only have one cardbus device behind the bridge. */ 78 if (pc->cardbusmode && (dev > 1)) 79 goto out; 80 81 if (bus == 0) { 82 /* Type 0 transaction */ 83 if (unlikely(dev >= SSB_PCI_SLOT_MAX)) 84 goto out; 85 /* Slide the window */ 86 tmp = SSB_PCICORE_SBTOPCI_CFG0; 87 tmp |= ((1 << (dev + 16)) & SSB_PCICORE_SBTOPCI1_MASK); 88 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, tmp); 89 /* Calculate the address */ 90 addr = SSB_PCI_CFG; 91 addr |= ((1 << (dev + 16)) & ~SSB_PCICORE_SBTOPCI1_MASK); 92 addr |= (func << 8); 93 addr |= (off & ~3); 94 } else { 95 /* Type 1 transaction */ 96 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, 97 SSB_PCICORE_SBTOPCI_CFG1); 98 /* Calculate the address */ 99 addr = SSB_PCI_CFG; 100 addr |= (bus << 16); 101 addr |= (dev << 11); 102 addr |= (func << 8); 103 addr |= (off & ~3); 104 } 105 out: 106 return addr; 107 } 108 109 static int ssb_extpci_read_config(struct ssb_pcicore *pc, 110 unsigned int bus, unsigned int dev, 111 unsigned int func, unsigned int off, 112 void *buf, int len) 113 { 114 int err = -EINVAL; 115 u32 addr, val; 116 void __iomem *mmio; 117 118 SSB_WARN_ON(!pc->hostmode); 119 if (unlikely(len != 1 && len != 2 && len != 4)) 120 goto out; 121 addr = get_cfgspace_addr(pc, bus, dev, func, off); 122 if (unlikely(!addr)) 123 goto out; 124 err = -ENOMEM; 125 mmio = ioremap_nocache(addr, len); 126 if (!mmio) 127 goto out; 128 129 if (mips_busprobe32(val, mmio)) { 130 val = 0xffffffff; 131 goto unmap; 132 } 133 134 val = readl(mmio); 135 val >>= (8 * (off & 3)); 136 137 switch (len) { 138 case 1: 139 *((u8 *)buf) = (u8)val; 140 break; 141 case 2: 142 *((u16 *)buf) = (u16)val; 143 break; 144 case 4: 145 *((u32 *)buf) = (u32)val; 146 break; 147 } 148 err = 0; 149 unmap: 150 iounmap(mmio); 151 out: 152 return err; 153 } 154 155 static int ssb_extpci_write_config(struct ssb_pcicore *pc, 156 unsigned int bus, unsigned int dev, 157 unsigned int func, unsigned int off, 158 const void *buf, int len) 159 { 160 int err = -EINVAL; 161 u32 addr, val = 0; 162 void __iomem *mmio; 163 164 SSB_WARN_ON(!pc->hostmode); 165 if (unlikely(len != 1 && len != 2 && len != 4)) 166 goto out; 167 addr = get_cfgspace_addr(pc, bus, dev, func, off); 168 if (unlikely(!addr)) 169 goto out; 170 err = -ENOMEM; 171 mmio = ioremap_nocache(addr, len); 172 if (!mmio) 173 goto out; 174 175 if (mips_busprobe32(val, mmio)) { 176 val = 0xffffffff; 177 goto unmap; 178 } 179 180 switch (len) { 181 case 1: 182 val = readl(mmio); 183 val &= ~(0xFF << (8 * (off & 3))); 184 val |= *((const u8 *)buf) << (8 * (off & 3)); 185 break; 186 case 2: 187 val = readl(mmio); 188 val &= ~(0xFFFF << (8 * (off & 3))); 189 val |= *((const u16 *)buf) << (8 * (off & 3)); 190 break; 191 case 4: 192 val = *((const u32 *)buf); 193 break; 194 } 195 writel(val, mmio); 196 197 err = 0; 198 unmap: 199 iounmap(mmio); 200 out: 201 return err; 202 } 203 204 static int ssb_pcicore_read_config(struct pci_bus *bus, unsigned int devfn, 205 int reg, int size, u32 *val) 206 { 207 unsigned long flags; 208 int err; 209 210 spin_lock_irqsave(&cfgspace_lock, flags); 211 err = ssb_extpci_read_config(extpci_core, bus->number, PCI_SLOT(devfn), 212 PCI_FUNC(devfn), reg, val, size); 213 spin_unlock_irqrestore(&cfgspace_lock, flags); 214 215 return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; 216 } 217 218 static int ssb_pcicore_write_config(struct pci_bus *bus, unsigned int devfn, 219 int reg, int size, u32 val) 220 { 221 unsigned long flags; 222 int err; 223 224 spin_lock_irqsave(&cfgspace_lock, flags); 225 err = ssb_extpci_write_config(extpci_core, bus->number, PCI_SLOT(devfn), 226 PCI_FUNC(devfn), reg, &val, size); 227 spin_unlock_irqrestore(&cfgspace_lock, flags); 228 229 return err ? PCIBIOS_DEVICE_NOT_FOUND : PCIBIOS_SUCCESSFUL; 230 } 231 232 static struct pci_ops ssb_pcicore_pciops = { 233 .read = ssb_pcicore_read_config, 234 .write = ssb_pcicore_write_config, 235 }; 236 237 static struct resource ssb_pcicore_mem_resource = { 238 .name = "SSB PCIcore external memory", 239 .start = SSB_PCI_DMA, 240 .end = SSB_PCI_DMA + SSB_PCI_DMA_SZ - 1, 241 .flags = IORESOURCE_MEM | IORESOURCE_PCI_FIXED, 242 }; 243 244 static struct resource ssb_pcicore_io_resource = { 245 .name = "SSB PCIcore external I/O", 246 .start = 0x100, 247 .end = 0x7FF, 248 .flags = IORESOURCE_IO | IORESOURCE_PCI_FIXED, 249 }; 250 251 static struct pci_controller ssb_pcicore_controller = { 252 .pci_ops = &ssb_pcicore_pciops, 253 .io_resource = &ssb_pcicore_io_resource, 254 .mem_resource = &ssb_pcicore_mem_resource, 255 }; 256 257 /* This function is called when doing a pci_enable_device(). 258 * We must first check if the device is a device on the PCI-core bridge. */ 259 int ssb_pcicore_plat_dev_init(struct pci_dev *d) 260 { 261 if (d->bus->ops != &ssb_pcicore_pciops) { 262 /* This is not a device on the PCI-core bridge. */ 263 return -ENODEV; 264 } 265 266 ssb_info("PCI: Fixing up device %s\n", pci_name(d)); 267 268 /* Fix up interrupt lines */ 269 d->irq = ssb_mips_irq(extpci_core->dev) + 2; 270 pci_write_config_byte(d, PCI_INTERRUPT_LINE, d->irq); 271 272 return 0; 273 } 274 275 /* Early PCI fixup for a device on the PCI-core bridge. */ 276 static void ssb_pcicore_fixup_pcibridge(struct pci_dev *dev) 277 { 278 u8 lat; 279 280 if (dev->bus->ops != &ssb_pcicore_pciops) { 281 /* This is not a device on the PCI-core bridge. */ 282 return; 283 } 284 if (dev->bus->number != 0 || PCI_SLOT(dev->devfn) != 0) 285 return; 286 287 ssb_info("PCI: Fixing up bridge %s\n", pci_name(dev)); 288 289 /* Enable PCI bridge bus mastering and memory space */ 290 pci_set_master(dev); 291 if (pcibios_enable_device(dev, ~0) < 0) { 292 ssb_err("PCI: SSB bridge enable failed\n"); 293 return; 294 } 295 296 /* Enable PCI bridge BAR1 prefetch and burst */ 297 pci_write_config_dword(dev, SSB_BAR1_CONTROL, 3); 298 299 /* Make sure our latency is high enough to handle the devices behind us */ 300 lat = 168; 301 ssb_info("PCI: Fixing latency timer of device %s to %u\n", 302 pci_name(dev), lat); 303 pci_write_config_byte(dev, PCI_LATENCY_TIMER, lat); 304 } 305 DECLARE_PCI_FIXUP_EARLY(PCI_ANY_ID, PCI_ANY_ID, ssb_pcicore_fixup_pcibridge); 306 307 /* PCI device IRQ mapping. */ 308 int ssb_pcicore_pcibios_map_irq(const struct pci_dev *dev, u8 slot, u8 pin) 309 { 310 if (dev->bus->ops != &ssb_pcicore_pciops) { 311 /* This is not a device on the PCI-core bridge. */ 312 return -ENODEV; 313 } 314 return ssb_mips_irq(extpci_core->dev) + 2; 315 } 316 317 static void ssb_pcicore_init_hostmode(struct ssb_pcicore *pc) 318 { 319 u32 val; 320 321 if (WARN_ON(extpci_core)) 322 return; 323 extpci_core = pc; 324 325 ssb_dbg("PCIcore in host mode found\n"); 326 /* Reset devices on the external PCI bus */ 327 val = SSB_PCICORE_CTL_RST_OE; 328 val |= SSB_PCICORE_CTL_CLK_OE; 329 pcicore_write32(pc, SSB_PCICORE_CTL, val); 330 val |= SSB_PCICORE_CTL_CLK; /* Clock on */ 331 pcicore_write32(pc, SSB_PCICORE_CTL, val); 332 udelay(150); /* Assertion time demanded by the PCI standard */ 333 val |= SSB_PCICORE_CTL_RST; /* Deassert RST# */ 334 pcicore_write32(pc, SSB_PCICORE_CTL, val); 335 val = SSB_PCICORE_ARBCTL_INTERN; 336 pcicore_write32(pc, SSB_PCICORE_ARBCTL, val); 337 udelay(1); /* Assertion time demanded by the PCI standard */ 338 339 if (pc->dev->bus->has_cardbus_slot) { 340 ssb_dbg("CardBus slot detected\n"); 341 pc->cardbusmode = 1; 342 /* GPIO 1 resets the bridge */ 343 ssb_gpio_out(pc->dev->bus, 1, 1); 344 ssb_gpio_outen(pc->dev->bus, 1, 1); 345 pcicore_write16(pc, SSB_PCICORE_SPROM(0), 346 pcicore_read16(pc, SSB_PCICORE_SPROM(0)) 347 | 0x0400); 348 } 349 350 /* 64MB I/O window */ 351 pcicore_write32(pc, SSB_PCICORE_SBTOPCI0, 352 SSB_PCICORE_SBTOPCI_IO); 353 /* 64MB config space */ 354 pcicore_write32(pc, SSB_PCICORE_SBTOPCI1, 355 SSB_PCICORE_SBTOPCI_CFG0); 356 /* 1GB memory window */ 357 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, 358 SSB_PCICORE_SBTOPCI_MEM | SSB_PCI_DMA); 359 360 /* 361 * Accessing PCI config without a proper delay after devices reset (not 362 * GPIO reset) was causing reboots on WRT300N v1.0 (BCM4704). 363 * Tested delay 850 us lowered reboot chance to 50-80%, 1000 us fixed it 364 * completely. Flushing all writes was also tested but with no luck. 365 * The same problem was reported for WRT350N v1 (BCM4705), so we just 366 * sleep here unconditionally. 367 */ 368 usleep_range(1000, 2000); 369 370 /* Enable PCI bridge BAR0 prefetch and burst */ 371 val = PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; 372 ssb_extpci_write_config(pc, 0, 0, 0, PCI_COMMAND, &val, 2); 373 /* Clear error conditions */ 374 val = 0; 375 ssb_extpci_write_config(pc, 0, 0, 0, PCI_STATUS, &val, 2); 376 377 /* Enable PCI interrupts */ 378 pcicore_write32(pc, SSB_PCICORE_IMASK, 379 SSB_PCICORE_IMASK_INTA); 380 381 /* Ok, ready to run, register it to the system. 382 * The following needs change, if we want to port hostmode 383 * to non-MIPS platform. */ 384 ssb_pcicore_controller.io_map_base = (unsigned long)ioremap_nocache(SSB_PCI_MEM, 0x04000000); 385 set_io_port_base(ssb_pcicore_controller.io_map_base); 386 /* Give some time to the PCI controller to configure itself with the new 387 * values. Not waiting at this point causes crashes of the machine. */ 388 mdelay(10); 389 register_pci_controller(&ssb_pcicore_controller); 390 } 391 392 static int pcicore_is_in_hostmode(struct ssb_pcicore *pc) 393 { 394 struct ssb_bus *bus = pc->dev->bus; 395 u16 chipid_top; 396 u32 tmp; 397 398 chipid_top = (bus->chip_id & 0xFF00); 399 if (chipid_top != 0x4700 && 400 chipid_top != 0x5300) 401 return 0; 402 403 if (bus->sprom.boardflags_lo & SSB_PCICORE_BFL_NOPCI) 404 return 0; 405 406 /* The 200-pin BCM4712 package does not bond out PCI. Even when 407 * PCI is bonded out, some boards may leave the pins floating. */ 408 if (bus->chip_id == 0x4712) { 409 if (bus->chip_package == SSB_CHIPPACK_BCM4712S) 410 return 0; 411 if (bus->chip_package == SSB_CHIPPACK_BCM4712M) 412 return 0; 413 } 414 if (bus->chip_id == 0x5350) 415 return 0; 416 417 return !mips_busprobe32(tmp, (bus->mmio + (pc->dev->core_index * SSB_CORE_SIZE))); 418 } 419 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */ 420 421 /************************************************** 422 * Workarounds. 423 **************************************************/ 424 425 static void ssb_pcicore_fix_sprom_core_index(struct ssb_pcicore *pc) 426 { 427 u16 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(0)); 428 if (((tmp & 0xF000) >> 12) != pc->dev->core_index) { 429 tmp &= ~0xF000; 430 tmp |= (pc->dev->core_index << 12); 431 pcicore_write16(pc, SSB_PCICORE_SPROM(0), tmp); 432 } 433 } 434 435 static u8 ssb_pcicore_polarity_workaround(struct ssb_pcicore *pc) 436 { 437 return (ssb_pcie_read(pc, 0x204) & 0x10) ? 0xC0 : 0x80; 438 } 439 440 static void ssb_pcicore_serdes_workaround(struct ssb_pcicore *pc) 441 { 442 const u8 serdes_pll_device = 0x1D; 443 const u8 serdes_rx_device = 0x1F; 444 u16 tmp; 445 446 ssb_pcie_mdio_write(pc, serdes_rx_device, 1 /* Control */, 447 ssb_pcicore_polarity_workaround(pc)); 448 tmp = ssb_pcie_mdio_read(pc, serdes_pll_device, 1 /* Control */); 449 if (tmp & 0x4000) 450 ssb_pcie_mdio_write(pc, serdes_pll_device, 1, tmp & ~0x4000); 451 } 452 453 static void ssb_pcicore_pci_setup_workarounds(struct ssb_pcicore *pc) 454 { 455 struct ssb_device *pdev = pc->dev; 456 struct ssb_bus *bus = pdev->bus; 457 u32 tmp; 458 459 tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2); 460 tmp |= SSB_PCICORE_SBTOPCI_PREF; 461 tmp |= SSB_PCICORE_SBTOPCI_BURST; 462 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp); 463 464 if (pdev->id.revision < 5) { 465 tmp = ssb_read32(pdev, SSB_IMCFGLO); 466 tmp &= ~SSB_IMCFGLO_SERTO; 467 tmp |= 2; 468 tmp &= ~SSB_IMCFGLO_REQTO; 469 tmp |= 3 << SSB_IMCFGLO_REQTO_SHIFT; 470 ssb_write32(pdev, SSB_IMCFGLO, tmp); 471 ssb_commit_settings(bus); 472 } else if (pdev->id.revision >= 11) { 473 tmp = pcicore_read32(pc, SSB_PCICORE_SBTOPCI2); 474 tmp |= SSB_PCICORE_SBTOPCI_MRM; 475 pcicore_write32(pc, SSB_PCICORE_SBTOPCI2, tmp); 476 } 477 } 478 479 static void ssb_pcicore_pcie_setup_workarounds(struct ssb_pcicore *pc) 480 { 481 u32 tmp; 482 u8 rev = pc->dev->id.revision; 483 484 if (rev == 0 || rev == 1) { 485 /* TLP Workaround register. */ 486 tmp = ssb_pcie_read(pc, 0x4); 487 tmp |= 0x8; 488 ssb_pcie_write(pc, 0x4, tmp); 489 } 490 if (rev == 1) { 491 /* DLLP Link Control register. */ 492 tmp = ssb_pcie_read(pc, 0x100); 493 tmp |= 0x40; 494 ssb_pcie_write(pc, 0x100, tmp); 495 } 496 497 if (rev == 0) { 498 const u8 serdes_rx_device = 0x1F; 499 500 ssb_pcie_mdio_write(pc, serdes_rx_device, 501 2 /* Timer */, 0x8128); 502 ssb_pcie_mdio_write(pc, serdes_rx_device, 503 6 /* CDR */, 0x0100); 504 ssb_pcie_mdio_write(pc, serdes_rx_device, 505 7 /* CDR BW */, 0x1466); 506 } else if (rev == 3 || rev == 4 || rev == 5) { 507 /* TODO: DLLP Power Management Threshold */ 508 ssb_pcicore_serdes_workaround(pc); 509 /* TODO: ASPM */ 510 } else if (rev == 7) { 511 /* TODO: No PLL down */ 512 } 513 514 if (rev >= 6) { 515 /* Miscellaneous Configuration Fixup */ 516 tmp = pcicore_read16(pc, SSB_PCICORE_SPROM(5)); 517 if (!(tmp & 0x8000)) 518 pcicore_write16(pc, SSB_PCICORE_SPROM(5), 519 tmp | 0x8000); 520 } 521 } 522 523 /************************************************** 524 * Generic and Clientmode operation code. 525 **************************************************/ 526 527 static void ssb_pcicore_init_clientmode(struct ssb_pcicore *pc) 528 { 529 struct ssb_device *pdev = pc->dev; 530 struct ssb_bus *bus = pdev->bus; 531 532 if (bus->bustype == SSB_BUSTYPE_PCI) 533 ssb_pcicore_fix_sprom_core_index(pc); 534 535 /* Disable PCI interrupts. */ 536 ssb_write32(pdev, SSB_INTVEC, 0); 537 538 /* Additional PCIe always once-executed workarounds */ 539 if (pc->dev->id.coreid == SSB_DEV_PCIE) { 540 ssb_pcicore_serdes_workaround(pc); 541 /* TODO: ASPM */ 542 /* TODO: Clock Request Update */ 543 } 544 } 545 546 void ssb_pcicore_init(struct ssb_pcicore *pc) 547 { 548 struct ssb_device *dev = pc->dev; 549 550 if (!dev) 551 return; 552 if (!ssb_device_is_enabled(dev)) 553 ssb_device_enable(dev, 0); 554 555 #ifdef CONFIG_SSB_PCICORE_HOSTMODE 556 pc->hostmode = pcicore_is_in_hostmode(pc); 557 if (pc->hostmode) 558 ssb_pcicore_init_hostmode(pc); 559 #endif /* CONFIG_SSB_PCICORE_HOSTMODE */ 560 if (!pc->hostmode) 561 ssb_pcicore_init_clientmode(pc); 562 } 563 564 static u32 ssb_pcie_read(struct ssb_pcicore *pc, u32 address) 565 { 566 pcicore_write32(pc, 0x130, address); 567 return pcicore_read32(pc, 0x134); 568 } 569 570 static void ssb_pcie_write(struct ssb_pcicore *pc, u32 address, u32 data) 571 { 572 pcicore_write32(pc, 0x130, address); 573 pcicore_write32(pc, 0x134, data); 574 } 575 576 static void ssb_pcie_mdio_set_phy(struct ssb_pcicore *pc, u8 phy) 577 { 578 const u16 mdio_control = 0x128; 579 const u16 mdio_data = 0x12C; 580 u32 v; 581 int i; 582 583 v = (1 << 30); /* Start of Transaction */ 584 v |= (1 << 28); /* Write Transaction */ 585 v |= (1 << 17); /* Turnaround */ 586 v |= (0x1F << 18); 587 v |= (phy << 4); 588 pcicore_write32(pc, mdio_data, v); 589 590 udelay(10); 591 for (i = 0; i < 200; i++) { 592 v = pcicore_read32(pc, mdio_control); 593 if (v & 0x100 /* Trans complete */) 594 break; 595 msleep(1); 596 } 597 } 598 599 static u16 ssb_pcie_mdio_read(struct ssb_pcicore *pc, u8 device, u8 address) 600 { 601 const u16 mdio_control = 0x128; 602 const u16 mdio_data = 0x12C; 603 int max_retries = 10; 604 u16 ret = 0; 605 u32 v; 606 int i; 607 608 v = 0x80; /* Enable Preamble Sequence */ 609 v |= 0x2; /* MDIO Clock Divisor */ 610 pcicore_write32(pc, mdio_control, v); 611 612 if (pc->dev->id.revision >= 10) { 613 max_retries = 200; 614 ssb_pcie_mdio_set_phy(pc, device); 615 } 616 617 v = (1 << 30); /* Start of Transaction */ 618 v |= (1 << 29); /* Read Transaction */ 619 v |= (1 << 17); /* Turnaround */ 620 if (pc->dev->id.revision < 10) 621 v |= (u32)device << 22; 622 v |= (u32)address << 18; 623 pcicore_write32(pc, mdio_data, v); 624 /* Wait for the device to complete the transaction */ 625 udelay(10); 626 for (i = 0; i < max_retries; i++) { 627 v = pcicore_read32(pc, mdio_control); 628 if (v & 0x100 /* Trans complete */) { 629 udelay(10); 630 ret = pcicore_read32(pc, mdio_data); 631 break; 632 } 633 msleep(1); 634 } 635 pcicore_write32(pc, mdio_control, 0); 636 return ret; 637 } 638 639 static void ssb_pcie_mdio_write(struct ssb_pcicore *pc, u8 device, 640 u8 address, u16 data) 641 { 642 const u16 mdio_control = 0x128; 643 const u16 mdio_data = 0x12C; 644 int max_retries = 10; 645 u32 v; 646 int i; 647 648 v = 0x80; /* Enable Preamble Sequence */ 649 v |= 0x2; /* MDIO Clock Divisor */ 650 pcicore_write32(pc, mdio_control, v); 651 652 if (pc->dev->id.revision >= 10) { 653 max_retries = 200; 654 ssb_pcie_mdio_set_phy(pc, device); 655 } 656 657 v = (1 << 30); /* Start of Transaction */ 658 v |= (1 << 28); /* Write Transaction */ 659 v |= (1 << 17); /* Turnaround */ 660 if (pc->dev->id.revision < 10) 661 v |= (u32)device << 22; 662 v |= (u32)address << 18; 663 v |= data; 664 pcicore_write32(pc, mdio_data, v); 665 /* Wait for the device to complete the transaction */ 666 udelay(10); 667 for (i = 0; i < max_retries; i++) { 668 v = pcicore_read32(pc, mdio_control); 669 if (v & 0x100 /* Trans complete */) 670 break; 671 msleep(1); 672 } 673 pcicore_write32(pc, mdio_control, 0); 674 } 675 676 int ssb_pcicore_dev_irqvecs_enable(struct ssb_pcicore *pc, 677 struct ssb_device *dev) 678 { 679 struct ssb_device *pdev = pc->dev; 680 struct ssb_bus *bus; 681 int err = 0; 682 u32 tmp; 683 684 if (dev->bus->bustype != SSB_BUSTYPE_PCI) { 685 /* This SSB device is not on a PCI host-bus. So the IRQs are 686 * not routed through the PCI core. 687 * So we must not enable routing through the PCI core. */ 688 goto out; 689 } 690 691 if (!pdev) 692 goto out; 693 bus = pdev->bus; 694 695 might_sleep_if(pdev->id.coreid != SSB_DEV_PCI); 696 697 /* Enable interrupts for this device. */ 698 if ((pdev->id.revision >= 6) || (pdev->id.coreid == SSB_DEV_PCIE)) { 699 u32 coremask; 700 701 /* Calculate the "coremask" for the device. */ 702 coremask = (1 << dev->core_index); 703 704 SSB_WARN_ON(bus->bustype != SSB_BUSTYPE_PCI); 705 err = pci_read_config_dword(bus->host_pci, SSB_PCI_IRQMASK, &tmp); 706 if (err) 707 goto out; 708 tmp |= coremask << 8; 709 err = pci_write_config_dword(bus->host_pci, SSB_PCI_IRQMASK, tmp); 710 if (err) 711 goto out; 712 } else { 713 u32 intvec; 714 715 intvec = ssb_read32(pdev, SSB_INTVEC); 716 tmp = ssb_read32(dev, SSB_TPSFLAG); 717 tmp &= SSB_TPSFLAG_BPFLAG; 718 intvec |= (1 << tmp); 719 ssb_write32(pdev, SSB_INTVEC, intvec); 720 } 721 722 /* Setup PCIcore operation. */ 723 if (pc->setup_done) 724 goto out; 725 if (pdev->id.coreid == SSB_DEV_PCI) { 726 ssb_pcicore_pci_setup_workarounds(pc); 727 } else { 728 WARN_ON(pdev->id.coreid != SSB_DEV_PCIE); 729 ssb_pcicore_pcie_setup_workarounds(pc); 730 } 731 pc->setup_done = 1; 732 out: 733 return err; 734 } 735 EXPORT_SYMBOL(ssb_pcicore_dev_irqvecs_enable); 736