1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2012-2015, 2017, 2021, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/bitfield.h> 7 #include <linux/bitmap.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/interrupt.h> 11 #include <linux/io.h> 12 #include <linux/irqchip/chained_irq.h> 13 #include <linux/irqdomain.h> 14 #include <linux/irq.h> 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/of.h> 18 #include <linux/of_address.h> 19 #include <linux/of_irq.h> 20 #include <linux/platform_device.h> 21 #include <linux/slab.h> 22 #include <linux/spmi.h> 23 24 /* PMIC Arbiter configuration registers */ 25 #define PMIC_ARB_VERSION 0x0000 26 #define PMIC_ARB_VERSION_V2_MIN 0x20010000 27 #define PMIC_ARB_VERSION_V3_MIN 0x30000000 28 #define PMIC_ARB_VERSION_V5_MIN 0x50000000 29 #define PMIC_ARB_VERSION_V7_MIN 0x70000000 30 #define PMIC_ARB_VERSION_V8_MIN 0x80000000 31 #define PMIC_ARB_INT_EN 0x0004 32 33 #define PMIC_ARB_FEATURES 0x0004 34 #define PMIC_ARB_FEATURES_PERIPH_MASK GENMASK(10, 0) 35 #define PMIC_ARB_FEATURES_V8_PERIPH_MASK GENMASK(12, 0) 36 37 /* PMIC Arbiter channel registers offsets */ 38 #define PMIC_ARB_CMD 0x00 39 #define PMIC_ARB_CONFIG 0x04 40 #define PMIC_ARB_STATUS 0x08 41 #define PMIC_ARB_WDATA0 0x10 42 #define PMIC_ARB_WDATA1 0x14 43 #define PMIC_ARB_RDATA0 0x18 44 #define PMIC_ARB_RDATA1 0x1C 45 46 /* Mapping Table */ 47 #define SPMI_MAPPING_TABLE_REG(N) (0x0B00 + (4 * (N))) 48 #define SPMI_MAPPING_BIT_INDEX(X) (((X) >> 18) & 0xF) 49 #define SPMI_MAPPING_BIT_IS_0_FLAG(X) (((X) >> 17) & 0x1) 50 #define SPMI_MAPPING_BIT_IS_0_RESULT(X) (((X) >> 9) & 0xFF) 51 #define SPMI_MAPPING_BIT_IS_1_FLAG(X) (((X) >> 8) & 0x1) 52 #define SPMI_MAPPING_BIT_IS_1_RESULT(X) (((X) >> 0) & 0xFF) 53 54 #define SPMI_MAPPING_TABLE_TREE_DEPTH 16 /* Maximum of 16-bits */ 55 #define PMIC_ARB_MAX_PPID BIT(13) 56 #define PMIC_ARB_APID_VALID BIT(15) 57 #define PMIC_ARB_CHAN_IS_IRQ_OWNER_MASK BIT(24) 58 #define PMIC_ARB_V8_CHAN_IS_IRQ_OWNER_MASK BIT(31) 59 60 #define INVALID_EE 0xFF 61 62 /* Ownership Table */ 63 #define SPMI_OWNERSHIP_PERIPH2OWNER(X) ((X) & 0x7) 64 65 /* Channel Status fields */ 66 enum pmic_arb_chnl_status { 67 PMIC_ARB_STATUS_DONE = BIT(0), 68 PMIC_ARB_STATUS_FAILURE = BIT(1), 69 PMIC_ARB_STATUS_DENIED = BIT(2), 70 PMIC_ARB_STATUS_DROPPED = BIT(3), 71 }; 72 73 /* Command register fields */ 74 #define PMIC_ARB_CMD_MAX_BYTE_COUNT 8 75 76 /* Command Opcodes */ 77 enum pmic_arb_cmd_op_code { 78 PMIC_ARB_OP_EXT_WRITEL = 0, 79 PMIC_ARB_OP_EXT_READL = 1, 80 PMIC_ARB_OP_EXT_WRITE = 2, 81 PMIC_ARB_OP_RESET = 3, 82 PMIC_ARB_OP_SLEEP = 4, 83 PMIC_ARB_OP_SHUTDOWN = 5, 84 PMIC_ARB_OP_WAKEUP = 6, 85 PMIC_ARB_OP_AUTHENTICATE = 7, 86 PMIC_ARB_OP_MSTR_READ = 8, 87 PMIC_ARB_OP_MSTR_WRITE = 9, 88 PMIC_ARB_OP_EXT_READ = 13, 89 PMIC_ARB_OP_WRITE = 14, 90 PMIC_ARB_OP_READ = 15, 91 PMIC_ARB_OP_ZERO_WRITE = 16, 92 }; 93 94 /* 95 * PMIC arbiter version 5 uses different register offsets for read/write vs 96 * observer channels. 97 */ 98 enum pmic_arb_channel { 99 PMIC_ARB_CHANNEL_RW, 100 PMIC_ARB_CHANNEL_OBS, 101 }; 102 103 #define PMIC_ARB_MAX_BUSES 4 104 105 /* Maximum number of support PMIC peripherals */ 106 #define PMIC_ARB_MAX_PERIPHS 512 107 #define PMIC_ARB_MAX_PERIPHS_V7 1024 108 #define PMIC_ARB_MAX_PERIPHS_V8 8192 109 #define PMIC_ARB_TIMEOUT_US 1000 110 #define PMIC_ARB_MAX_TRANS_BYTES (8) 111 112 #define PMIC_ARB_APID_MASK 0xFF 113 #define PMIC_ARB_PPID_MASK GENMASK(11, 0) 114 #define PMIC_ARB_V8_PPID_MASK GENMASK(12, 0) 115 116 /* interrupt enable bit */ 117 #define SPMI_PIC_ACC_ENABLE_BIT BIT(0) 118 119 #define HWIRQ_SID_MASK GENMASK(28, 24) 120 #define HWIRQ_PID_MASK GENMASK(23, 16) 121 #define HWIRQ_IRQID_MASK GENMASK(15, 13) 122 #define HWIRQ_APID_MASK GENMASK(12, 0) 123 124 #define spec_to_hwirq(slave_id, periph_id, irq_id, apid) \ 125 (FIELD_PREP(HWIRQ_SID_MASK, (slave_id)) | \ 126 FIELD_PREP(HWIRQ_PID_MASK, (periph_id)) | \ 127 FIELD_PREP(HWIRQ_IRQID_MASK, (irq_id)) | \ 128 FIELD_PREP(HWIRQ_APID_MASK, (apid))) 129 130 #define hwirq_to_sid(hwirq) FIELD_GET(HWIRQ_SID_MASK, (hwirq)) 131 #define hwirq_to_per(hwirq) FIELD_GET(HWIRQ_PID_MASK, (hwirq)) 132 #define hwirq_to_irq(hwirq) FIELD_GET(HWIRQ_IRQID_MASK, (hwirq)) 133 #define hwirq_to_apid(hwirq) FIELD_GET(HWIRQ_APID_MASK, (hwirq)) 134 135 struct pmic_arb_ver_ops; 136 137 struct apid_data { 138 u16 ppid; 139 u8 write_ee; 140 u8 irq_ee; 141 }; 142 143 struct spmi_pmic_arb; 144 145 /** 146 * struct spmi_pmic_arb_bus - SPMI PMIC Arbiter Bus object 147 * 148 * @pmic_arb: the SPMI PMIC Arbiter the bus belongs to. 149 * @domain: irq domain object for PMIC IRQ domain 150 * @intr: address of the SPMI interrupt control registers. 151 * @cnfg: address of the PMIC Arbiter configuration registers. 152 * @apid_owner: on v8: address of APID owner mapping table registers 153 * @spmic: spmi controller registered for this bus 154 * @lock: lock to synchronize accesses. 155 * @base_apid: on v7 and v8: minimum APID associated with the 156 * particular SPMI bus instance 157 * @apid_count: on v5, v7 and v8: number of APIDs associated with the 158 * particular SPMI bus instance 159 * @mapping_table: in-memory copy of PPID -> APID mapping table. 160 * @mapping_table_valid:bitmap containing valid-only periphs 161 * @ppid_to_apid: in-memory copy of PPID -> APID mapping table. 162 * @last_apid: Highest value APID in use 163 * @apid_data: Table of data for all APIDs 164 * @min_apid: minimum APID (used for bounding IRQ search) 165 * @max_apid: maximum APID 166 * @irq: PMIC ARB interrupt. 167 * @id: unique ID of the bus 168 */ 169 struct spmi_pmic_arb_bus { 170 struct spmi_pmic_arb *pmic_arb; 171 struct irq_domain *domain; 172 void __iomem *intr; 173 void __iomem *cnfg; 174 void __iomem *apid_owner; 175 struct spmi_controller *spmic; 176 raw_spinlock_t lock; 177 u16 base_apid; 178 int apid_count; 179 u32 *mapping_table; 180 DECLARE_BITMAP(mapping_table_valid, PMIC_ARB_MAX_PERIPHS); 181 u16 *ppid_to_apid; 182 u16 last_apid; 183 struct apid_data *apid_data; 184 u16 min_apid; 185 u16 max_apid; 186 int irq; 187 u8 id; 188 }; 189 190 /** 191 * struct spmi_pmic_arb - SPMI PMIC Arbiter object 192 * 193 * @rd_base: on v1 "core", on v2 "observer" register base off DT. 194 * @wr_base: on v1 "core", on v2 "chnls" register base off DT. 195 * @core: core register base for v2 and above only (see above) 196 * @core_size: core register base size 197 * @apid_map: on v8, APID mapping table register base 198 * @channel: execution environment channel to use for accesses. 199 * @ee: the current Execution Environment 200 * @ver_ops: version dependent operations. 201 * @max_periphs: Number of elements in apid_data[] 202 * @buses: per arbiter buses instances 203 * @buses_available: number of buses registered 204 */ 205 struct spmi_pmic_arb { 206 void __iomem *rd_base; 207 void __iomem *wr_base; 208 void __iomem *core; 209 resource_size_t core_size; 210 void __iomem *apid_map; 211 u8 channel; 212 u8 ee; 213 const struct pmic_arb_ver_ops *ver_ops; 214 int max_periphs; 215 struct spmi_pmic_arb_bus *buses[PMIC_ARB_MAX_BUSES]; 216 int buses_available; 217 }; 218 219 /** 220 * struct pmic_arb_ver_ops - version dependent functionality. 221 * 222 * @ver_str: version string. 223 * @get_core_resources: initializes the core, observer and channels 224 * @get_bus_resources: requests per-SPMI bus register resources 225 * @init_apid: finds the apid base and count 226 * @ppid_to_apid: finds the apid for a given ppid. 227 * @non_data_cmd: on v1 issues an spmi non-data command. 228 * on v2 no HW support, returns -EOPNOTSUPP. 229 * @offset: on v1 offset of per-ee channel. 230 * on v2 offset of per-ee and per-ppid channel. 231 * @fmt_cmd: formats a GENI/SPMI command. 232 * @owner_acc_status: on v1 address of PMIC_ARB_SPMI_PIC_OWNERm_ACC_STATUSn 233 * on v2 address of SPMI_PIC_OWNERm_ACC_STATUSn. 234 * @acc_enable: on v1 address of PMIC_ARB_SPMI_PIC_ACC_ENABLEn 235 * on v2 address of SPMI_PIC_ACC_ENABLEn. 236 * @irq_status: on v1 address of PMIC_ARB_SPMI_PIC_IRQ_STATUSn 237 * on v2 address of SPMI_PIC_IRQ_STATUSn. 238 * @irq_clear: on v1 address of PMIC_ARB_SPMI_PIC_IRQ_CLEARn 239 * on v2 address of SPMI_PIC_IRQ_CLEARn. 240 * @apid_map_offset: offset of PMIC_ARB_REG_CHNLn 241 * @apid_owner: on v2 and later address of SPMI_PERIPHn_2OWNER_TABLE_REG 242 */ 243 struct pmic_arb_ver_ops { 244 const char *ver_str; 245 int (*get_core_resources)(struct platform_device *pdev, void __iomem *core); 246 int (*get_bus_resources)(struct platform_device *pdev, 247 struct device_node *node, 248 struct spmi_pmic_arb_bus *bus); 249 int (*init_apid)(struct spmi_pmic_arb_bus *bus, int index); 250 int (*ppid_to_apid)(struct spmi_pmic_arb_bus *bus, u16 ppid); 251 /* spmi commands (read_cmd, write_cmd, cmd) functionality */ 252 int (*offset)(struct spmi_pmic_arb_bus *bus, u8 sid, u16 addr, 253 enum pmic_arb_channel ch_type); 254 u32 (*fmt_cmd)(u8 opc, u8 sid, u16 addr, u8 bc); 255 int (*non_data_cmd)(struct spmi_controller *ctrl, u8 opc, u8 sid); 256 /* Interrupts controller functionality (offset of PIC registers) */ 257 void __iomem *(*owner_acc_status)(struct spmi_pmic_arb_bus *bus, u8 m, 258 u16 n); 259 void __iomem *(*acc_enable)(struct spmi_pmic_arb_bus *bus, u16 n); 260 void __iomem *(*irq_status)(struct spmi_pmic_arb_bus *bus, u16 n); 261 void __iomem *(*irq_clear)(struct spmi_pmic_arb_bus *bus, u16 n); 262 u32 (*apid_map_offset)(u16 n); 263 void __iomem *(*apid_owner)(struct spmi_pmic_arb_bus *bus, u16 n); 264 }; 265 266 static inline void pmic_arb_base_write(struct spmi_pmic_arb *pmic_arb, 267 u32 offset, u32 val) 268 { 269 writel_relaxed(val, pmic_arb->wr_base + offset); 270 } 271 272 static inline void pmic_arb_set_rd_cmd(struct spmi_pmic_arb *pmic_arb, 273 u32 offset, u32 val) 274 { 275 writel_relaxed(val, pmic_arb->rd_base + offset); 276 } 277 278 /** 279 * pmic_arb_read_data: reads pmic-arb's register and copy 1..4 bytes to buf 280 * @pmic_arb: the SPMI PMIC arbiter 281 * @bc: byte count -1. range: 0..3 282 * @reg: register's address 283 * @buf: output parameter, length must be bc + 1 284 */ 285 static void 286 pmic_arb_read_data(struct spmi_pmic_arb *pmic_arb, u8 *buf, u32 reg, u8 bc) 287 { 288 u32 data = __raw_readl(pmic_arb->rd_base + reg); 289 290 memcpy(buf, &data, (bc & 3) + 1); 291 } 292 293 /** 294 * pmic_arb_write_data: write 1..4 bytes from buf to pmic-arb's register 295 * @pmic_arb: the SPMI PMIC arbiter 296 * @bc: byte-count -1. range: 0..3. 297 * @reg: register's address. 298 * @buf: buffer to write. length must be bc + 1. 299 */ 300 static void pmic_arb_write_data(struct spmi_pmic_arb *pmic_arb, const u8 *buf, 301 u32 reg, u8 bc) 302 { 303 u32 data = 0; 304 305 memcpy(&data, buf, (bc & 3) + 1); 306 __raw_writel(data, pmic_arb->wr_base + reg); 307 } 308 309 static int pmic_arb_wait_for_done(struct spmi_controller *ctrl, 310 void __iomem *base, u8 sid, u16 addr, 311 enum pmic_arb_channel ch_type) 312 { 313 struct spmi_pmic_arb_bus *bus = spmi_controller_get_drvdata(ctrl); 314 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 315 u32 status = 0; 316 u32 timeout = PMIC_ARB_TIMEOUT_US; 317 u32 offset; 318 int rc; 319 320 rc = pmic_arb->ver_ops->offset(bus, sid, addr, ch_type); 321 if (rc < 0) 322 return rc; 323 324 offset = rc; 325 offset += PMIC_ARB_STATUS; 326 327 while (timeout--) { 328 status = readl_relaxed(base + offset); 329 330 if (status & PMIC_ARB_STATUS_DONE) { 331 if (status & PMIC_ARB_STATUS_DENIED) { 332 dev_err(&ctrl->dev, "%s: %#x %#x: transaction denied (%#x)\n", 333 __func__, sid, addr, status); 334 return -EPERM; 335 } 336 337 if (status & PMIC_ARB_STATUS_FAILURE) { 338 dev_err(&ctrl->dev, "%s: %#x %#x: transaction failed (%#x) reg: 0x%x\n", 339 __func__, sid, addr, status, offset); 340 WARN_ON(1); 341 return -EIO; 342 } 343 344 if (status & PMIC_ARB_STATUS_DROPPED) { 345 dev_err(&ctrl->dev, "%s: %#x %#x: transaction dropped (%#x)\n", 346 __func__, sid, addr, status); 347 return -EIO; 348 } 349 350 return 0; 351 } 352 udelay(1); 353 } 354 355 dev_err(&ctrl->dev, "%s: %#x %#x %#x: timeout, status %#x\n", 356 __func__, bus->id, sid, addr, status); 357 return -ETIMEDOUT; 358 } 359 360 static int 361 pmic_arb_non_data_cmd_v1(struct spmi_controller *ctrl, u8 opc, u8 sid) 362 { 363 struct spmi_pmic_arb_bus *bus = spmi_controller_get_drvdata(ctrl); 364 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 365 unsigned long flags; 366 u32 cmd; 367 int rc; 368 u32 offset; 369 370 rc = pmic_arb->ver_ops->offset(bus, sid, 0, PMIC_ARB_CHANNEL_RW); 371 if (rc < 0) 372 return rc; 373 374 offset = rc; 375 cmd = ((opc | 0x40) << 27) | ((sid & 0xf) << 20); 376 377 raw_spin_lock_irqsave(&bus->lock, flags); 378 pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd); 379 rc = pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, 0, 380 PMIC_ARB_CHANNEL_RW); 381 raw_spin_unlock_irqrestore(&bus->lock, flags); 382 383 return rc; 384 } 385 386 static int 387 pmic_arb_non_data_cmd_v2(struct spmi_controller *ctrl, u8 opc, u8 sid) 388 { 389 return -EOPNOTSUPP; 390 } 391 392 /* Non-data command */ 393 static int pmic_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid) 394 { 395 struct spmi_pmic_arb *pmic_arb = spmi_controller_get_drvdata(ctrl); 396 397 dev_dbg(&ctrl->dev, "cmd op:0x%x sid:%d\n", opc, sid); 398 399 /* Check for valid non-data command */ 400 if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP) 401 return -EINVAL; 402 403 return pmic_arb->ver_ops->non_data_cmd(ctrl, opc, sid); 404 } 405 406 static int pmic_arb_fmt_read_cmd(struct spmi_pmic_arb_bus *bus, u8 opc, u8 sid, 407 u16 addr, size_t len, u32 *cmd, u32 *offset) 408 { 409 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 410 u8 bc = len - 1; 411 int rc; 412 413 rc = pmic_arb->ver_ops->offset(bus, sid, addr, 414 PMIC_ARB_CHANNEL_OBS); 415 if (rc < 0) 416 return rc; 417 418 *offset = rc; 419 if (bc >= PMIC_ARB_MAX_TRANS_BYTES) { 420 dev_err(&bus->spmic->dev, "pmic-arb supports 1..%d bytes per trans, but:%zu requested\n", 421 PMIC_ARB_MAX_TRANS_BYTES, len); 422 return -EINVAL; 423 } 424 425 /* Check the opcode */ 426 if (opc >= 0x60 && opc <= 0x7F) 427 opc = PMIC_ARB_OP_READ; 428 else if (opc >= 0x20 && opc <= 0x2F) 429 opc = PMIC_ARB_OP_EXT_READ; 430 else if (opc >= 0x38 && opc <= 0x3F) 431 opc = PMIC_ARB_OP_EXT_READL; 432 else 433 return -EINVAL; 434 435 *cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc); 436 437 return 0; 438 } 439 440 static int pmic_arb_read_cmd_unlocked(struct spmi_controller *ctrl, u32 cmd, 441 u32 offset, u8 sid, u16 addr, u8 *buf, 442 size_t len) 443 { 444 struct spmi_pmic_arb_bus *bus = spmi_controller_get_drvdata(ctrl); 445 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 446 u8 bc = len - 1; 447 int rc; 448 449 pmic_arb_set_rd_cmd(pmic_arb, offset + PMIC_ARB_CMD, cmd); 450 rc = pmic_arb_wait_for_done(ctrl, pmic_arb->rd_base, sid, addr, 451 PMIC_ARB_CHANNEL_OBS); 452 if (rc) 453 return rc; 454 455 pmic_arb_read_data(pmic_arb, buf, offset + PMIC_ARB_RDATA0, 456 min_t(u8, bc, 3)); 457 458 if (bc > 3) 459 pmic_arb_read_data(pmic_arb, buf + 4, offset + PMIC_ARB_RDATA1, 460 bc - 4); 461 return 0; 462 } 463 464 static int pmic_arb_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid, 465 u16 addr, u8 *buf, size_t len) 466 { 467 struct spmi_pmic_arb_bus *bus = spmi_controller_get_drvdata(ctrl); 468 unsigned long flags; 469 u32 cmd, offset; 470 int rc; 471 472 rc = pmic_arb_fmt_read_cmd(bus, opc, sid, addr, len, &cmd, 473 &offset); 474 if (rc) 475 return rc; 476 477 raw_spin_lock_irqsave(&bus->lock, flags); 478 rc = pmic_arb_read_cmd_unlocked(ctrl, cmd, offset, sid, addr, buf, len); 479 raw_spin_unlock_irqrestore(&bus->lock, flags); 480 481 return rc; 482 } 483 484 static int pmic_arb_fmt_write_cmd(struct spmi_pmic_arb_bus *bus, u8 opc, 485 u8 sid, u16 addr, size_t len, u32 *cmd, 486 u32 *offset) 487 { 488 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 489 u8 bc = len - 1; 490 int rc; 491 492 rc = pmic_arb->ver_ops->offset(bus, sid, addr, 493 PMIC_ARB_CHANNEL_RW); 494 if (rc < 0) 495 return rc; 496 497 *offset = rc; 498 if (bc >= PMIC_ARB_MAX_TRANS_BYTES) { 499 dev_err(&bus->spmic->dev, "pmic-arb supports 1..%d bytes per trans, but:%zu requested\n", 500 PMIC_ARB_MAX_TRANS_BYTES, len); 501 return -EINVAL; 502 } 503 504 /* Check the opcode */ 505 if (opc >= 0x40 && opc <= 0x5F) 506 opc = PMIC_ARB_OP_WRITE; 507 else if (opc <= 0x0F) 508 opc = PMIC_ARB_OP_EXT_WRITE; 509 else if (opc >= 0x30 && opc <= 0x37) 510 opc = PMIC_ARB_OP_EXT_WRITEL; 511 else if (opc >= 0x80) 512 opc = PMIC_ARB_OP_ZERO_WRITE; 513 else 514 return -EINVAL; 515 516 *cmd = pmic_arb->ver_ops->fmt_cmd(opc, sid, addr, bc); 517 518 return 0; 519 } 520 521 static int pmic_arb_write_cmd_unlocked(struct spmi_controller *ctrl, u32 cmd, 522 u32 offset, u8 sid, u16 addr, 523 const u8 *buf, size_t len) 524 { 525 struct spmi_pmic_arb_bus *bus = spmi_controller_get_drvdata(ctrl); 526 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 527 u8 bc = len - 1; 528 529 /* Write data to FIFOs */ 530 pmic_arb_write_data(pmic_arb, buf, offset + PMIC_ARB_WDATA0, 531 min_t(u8, bc, 3)); 532 if (bc > 3) 533 pmic_arb_write_data(pmic_arb, buf + 4, offset + PMIC_ARB_WDATA1, 534 bc - 4); 535 536 /* Start the transaction */ 537 pmic_arb_base_write(pmic_arb, offset + PMIC_ARB_CMD, cmd); 538 return pmic_arb_wait_for_done(ctrl, pmic_arb->wr_base, sid, addr, 539 PMIC_ARB_CHANNEL_RW); 540 } 541 542 static int pmic_arb_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid, 543 u16 addr, const u8 *buf, size_t len) 544 { 545 struct spmi_pmic_arb_bus *bus = spmi_controller_get_drvdata(ctrl); 546 unsigned long flags; 547 u32 cmd, offset; 548 int rc; 549 550 rc = pmic_arb_fmt_write_cmd(bus, opc, sid, addr, len, &cmd, 551 &offset); 552 if (rc) 553 return rc; 554 555 raw_spin_lock_irqsave(&bus->lock, flags); 556 rc = pmic_arb_write_cmd_unlocked(ctrl, cmd, offset, sid, addr, buf, 557 len); 558 raw_spin_unlock_irqrestore(&bus->lock, flags); 559 560 return rc; 561 } 562 563 static int pmic_arb_masked_write(struct spmi_controller *ctrl, u8 sid, u16 addr, 564 const u8 *buf, const u8 *mask, size_t len) 565 { 566 struct spmi_pmic_arb_bus *bus = spmi_controller_get_drvdata(ctrl); 567 u32 read_cmd, read_offset, write_cmd, write_offset; 568 u8 temp[PMIC_ARB_MAX_TRANS_BYTES]; 569 unsigned long flags; 570 int rc, i; 571 572 rc = pmic_arb_fmt_read_cmd(bus, SPMI_CMD_EXT_READL, sid, addr, len, 573 &read_cmd, &read_offset); 574 if (rc) 575 return rc; 576 577 rc = pmic_arb_fmt_write_cmd(bus, SPMI_CMD_EXT_WRITEL, sid, addr, 578 len, &write_cmd, &write_offset); 579 if (rc) 580 return rc; 581 582 raw_spin_lock_irqsave(&bus->lock, flags); 583 rc = pmic_arb_read_cmd_unlocked(ctrl, read_cmd, read_offset, sid, addr, 584 temp, len); 585 if (rc) 586 goto done; 587 588 for (i = 0; i < len; i++) 589 temp[i] = (temp[i] & ~mask[i]) | (buf[i] & mask[i]); 590 591 rc = pmic_arb_write_cmd_unlocked(ctrl, write_cmd, write_offset, sid, 592 addr, temp, len); 593 done: 594 raw_spin_unlock_irqrestore(&bus->lock, flags); 595 596 return rc; 597 } 598 599 enum qpnpint_regs { 600 QPNPINT_REG_RT_STS = 0x10, 601 QPNPINT_REG_SET_TYPE = 0x11, 602 QPNPINT_REG_POLARITY_HIGH = 0x12, 603 QPNPINT_REG_POLARITY_LOW = 0x13, 604 QPNPINT_REG_LATCHED_CLR = 0x14, 605 QPNPINT_REG_EN_SET = 0x15, 606 QPNPINT_REG_EN_CLR = 0x16, 607 QPNPINT_REG_LATCHED_STS = 0x18, 608 }; 609 610 struct spmi_pmic_arb_qpnpint_type { 611 u8 type; /* 1 -> edge */ 612 u8 polarity_high; 613 u8 polarity_low; 614 } __packed; 615 616 /* Simplified accessor functions for irqchip callbacks */ 617 static void qpnpint_spmi_write(struct irq_data *d, u8 reg, void *buf, 618 size_t len) 619 { 620 struct spmi_pmic_arb_bus *bus = irq_data_get_irq_chip_data(d); 621 u8 sid = hwirq_to_sid(d->hwirq); 622 u8 per = hwirq_to_per(d->hwirq); 623 624 if (pmic_arb_write_cmd(bus->spmic, SPMI_CMD_EXT_WRITEL, sid, 625 (per << 8) + reg, buf, len)) 626 dev_err_ratelimited(&bus->spmic->dev, "failed irqchip transaction on %x\n", 627 d->irq); 628 } 629 630 static void qpnpint_spmi_read(struct irq_data *d, u8 reg, void *buf, size_t len) 631 { 632 struct spmi_pmic_arb_bus *bus = irq_data_get_irq_chip_data(d); 633 u8 sid = hwirq_to_sid(d->hwirq); 634 u8 per = hwirq_to_per(d->hwirq); 635 636 if (pmic_arb_read_cmd(bus->spmic, SPMI_CMD_EXT_READL, sid, 637 (per << 8) + reg, buf, len)) 638 dev_err_ratelimited(&bus->spmic->dev, "failed irqchip transaction on %x\n", 639 d->irq); 640 } 641 642 static int qpnpint_spmi_masked_write(struct irq_data *d, u8 reg, 643 const void *buf, const void *mask, 644 size_t len) 645 { 646 struct spmi_pmic_arb_bus *bus = irq_data_get_irq_chip_data(d); 647 u8 sid = hwirq_to_sid(d->hwirq); 648 u8 per = hwirq_to_per(d->hwirq); 649 int rc; 650 651 rc = pmic_arb_masked_write(bus->spmic, sid, (per << 8) + reg, buf, 652 mask, len); 653 if (rc) 654 dev_err_ratelimited(&bus->spmic->dev, "failed irqchip transaction on %x rc=%d\n", 655 d->irq, rc); 656 return rc; 657 } 658 659 static void cleanup_irq(struct spmi_pmic_arb_bus *bus, u16 apid, int id) 660 { 661 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 662 u16 ppid = bus->apid_data[apid].ppid; 663 u8 sid = ppid >> 8; 664 u8 per = ppid & 0xFF; 665 u8 irq_mask = BIT(id); 666 667 dev_err_ratelimited(&bus->spmic->dev, "%s apid=%d sid=0x%x per=0x%x irq=%d\n", 668 __func__, apid, sid, per, id); 669 writel_relaxed(irq_mask, pmic_arb->ver_ops->irq_clear(bus, apid)); 670 } 671 672 static int periph_interrupt(struct spmi_pmic_arb_bus *bus, u16 apid) 673 { 674 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 675 unsigned int irq; 676 u32 status, id; 677 int handled = 0; 678 u8 sid = (bus->apid_data[apid].ppid >> 8) & 0x1F; 679 u8 per = bus->apid_data[apid].ppid & 0xFF; 680 681 status = readl_relaxed(pmic_arb->ver_ops->irq_status(bus, apid)); 682 while (status) { 683 id = ffs(status) - 1; 684 status &= ~BIT(id); 685 irq = irq_find_mapping(bus->domain, 686 spec_to_hwirq(sid, per, id, apid)); 687 if (irq == 0) { 688 cleanup_irq(bus, apid, id); 689 continue; 690 } 691 generic_handle_irq(irq); 692 handled++; 693 } 694 695 return handled; 696 } 697 698 static void pmic_arb_chained_irq(struct irq_desc *desc) 699 { 700 struct spmi_pmic_arb_bus *bus = irq_desc_get_handler_data(desc); 701 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 702 const struct pmic_arb_ver_ops *ver_ops = pmic_arb->ver_ops; 703 struct irq_chip *chip = irq_desc_get_chip(desc); 704 int first = bus->min_apid; 705 int last = bus->max_apid; 706 /* 707 * acc_offset will be non-zero for the secondary SPMI bus instance on 708 * v7 and v8 controllers. 709 */ 710 int acc_offset = bus->base_apid >> 5; 711 u8 ee = pmic_arb->ee; 712 u32 status, enable, handled = 0; 713 int i, id, apid; 714 /* status based dispatch */ 715 bool acc_valid = false; 716 u32 irq_status = 0; 717 718 chained_irq_enter(chip, desc); 719 720 for (i = first >> 5; i <= last >> 5; ++i) { 721 status = readl_relaxed(ver_ops->owner_acc_status(bus, ee, i - acc_offset)); 722 if (status) 723 acc_valid = true; 724 725 while (status) { 726 id = ffs(status) - 1; 727 status &= ~BIT(id); 728 apid = id + i * 32; 729 if (apid < first || apid > last) { 730 WARN_ONCE(true, "spurious spmi irq received for apid=%d\n", 731 apid); 732 continue; 733 } 734 enable = readl_relaxed( 735 ver_ops->acc_enable(bus, apid)); 736 if (enable & SPMI_PIC_ACC_ENABLE_BIT) 737 if (periph_interrupt(bus, apid) != 0) 738 handled++; 739 } 740 } 741 742 /* ACC_STATUS is empty but IRQ fired check IRQ_STATUS */ 743 if (!acc_valid) { 744 for (i = first; i <= last; i++) { 745 /* skip if APPS is not irq owner */ 746 if (bus->apid_data[i].irq_ee != pmic_arb->ee) 747 continue; 748 749 irq_status = readl_relaxed( 750 ver_ops->irq_status(bus, i)); 751 if (irq_status) { 752 enable = readl_relaxed( 753 ver_ops->acc_enable(bus, i)); 754 if (enable & SPMI_PIC_ACC_ENABLE_BIT) { 755 dev_dbg(&bus->spmic->dev, 756 "Dispatching IRQ for apid=%d status=%x\n", 757 i, irq_status); 758 if (periph_interrupt(bus, i) != 0) 759 handled++; 760 } 761 } 762 } 763 } 764 765 if (handled == 0) 766 handle_bad_irq(desc); 767 768 chained_irq_exit(chip, desc); 769 } 770 771 static void qpnpint_irq_ack(struct irq_data *d) 772 { 773 struct spmi_pmic_arb_bus *bus = irq_data_get_irq_chip_data(d); 774 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 775 u8 irq = hwirq_to_irq(d->hwirq); 776 u16 apid = hwirq_to_apid(d->hwirq); 777 u8 data; 778 779 writel_relaxed(BIT(irq), pmic_arb->ver_ops->irq_clear(bus, apid)); 780 781 data = BIT(irq); 782 qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &data, 1); 783 } 784 785 static void qpnpint_irq_mask(struct irq_data *d) 786 { 787 u8 irq = hwirq_to_irq(d->hwirq); 788 u8 data = BIT(irq); 789 790 qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &data, 1); 791 } 792 793 static void qpnpint_irq_unmask(struct irq_data *d) 794 { 795 struct spmi_pmic_arb_bus *bus = irq_data_get_irq_chip_data(d); 796 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 797 const struct pmic_arb_ver_ops *ver_ops = pmic_arb->ver_ops; 798 u8 irq = hwirq_to_irq(d->hwirq); 799 u16 apid = hwirq_to_apid(d->hwirq); 800 u8 buf[2]; 801 802 writel_relaxed(SPMI_PIC_ACC_ENABLE_BIT, 803 ver_ops->acc_enable(bus, apid)); 804 805 qpnpint_spmi_read(d, QPNPINT_REG_EN_SET, &buf[0], 1); 806 if (!(buf[0] & BIT(irq))) { 807 /* 808 * Since the interrupt is currently disabled, write to both the 809 * LATCHED_CLR and EN_SET registers so that a spurious interrupt 810 * cannot be triggered when the interrupt is enabled 811 */ 812 buf[0] = BIT(irq); 813 buf[1] = BIT(irq); 814 qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &buf, 2); 815 } 816 } 817 818 static int qpnpint_irq_set_type(struct irq_data *d, unsigned int flow_type) 819 { 820 struct spmi_pmic_arb_qpnpint_type type = {0}; 821 struct spmi_pmic_arb_qpnpint_type mask; 822 irq_flow_handler_t flow_handler; 823 u8 irq_bit = BIT(hwirq_to_irq(d->hwirq)); 824 int rc; 825 826 if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) { 827 type.type = irq_bit; 828 if (flow_type & IRQF_TRIGGER_RISING) 829 type.polarity_high = irq_bit; 830 if (flow_type & IRQF_TRIGGER_FALLING) 831 type.polarity_low = irq_bit; 832 833 flow_handler = handle_edge_irq; 834 } else { 835 if ((flow_type & (IRQF_TRIGGER_HIGH)) && 836 (flow_type & (IRQF_TRIGGER_LOW))) 837 return -EINVAL; 838 839 if (flow_type & IRQF_TRIGGER_HIGH) 840 type.polarity_high = irq_bit; 841 else 842 type.polarity_low = irq_bit; 843 844 flow_handler = handle_level_irq; 845 } 846 847 mask.type = irq_bit; 848 mask.polarity_high = irq_bit; 849 mask.polarity_low = irq_bit; 850 851 rc = qpnpint_spmi_masked_write(d, QPNPINT_REG_SET_TYPE, &type, &mask, 852 sizeof(type)); 853 irq_set_handler_locked(d, flow_handler); 854 855 return rc; 856 } 857 858 static int qpnpint_irq_set_wake(struct irq_data *d, unsigned int on) 859 { 860 struct spmi_pmic_arb_bus *bus = irq_data_get_irq_chip_data(d); 861 862 return irq_set_irq_wake(bus->irq, on); 863 } 864 865 static int qpnpint_get_irqchip_state(struct irq_data *d, 866 enum irqchip_irq_state which, 867 bool *state) 868 { 869 u8 irq = hwirq_to_irq(d->hwirq); 870 u8 status = 0; 871 872 if (which != IRQCHIP_STATE_LINE_LEVEL) 873 return -EINVAL; 874 875 qpnpint_spmi_read(d, QPNPINT_REG_RT_STS, &status, 1); 876 *state = !!(status & BIT(irq)); 877 878 return 0; 879 } 880 881 static int qpnpint_irq_domain_activate(struct irq_domain *domain, 882 struct irq_data *d, bool reserve) 883 { 884 struct spmi_pmic_arb_bus *bus = irq_data_get_irq_chip_data(d); 885 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 886 u16 periph = hwirq_to_per(d->hwirq); 887 u16 apid = hwirq_to_apid(d->hwirq); 888 u16 sid = hwirq_to_sid(d->hwirq); 889 u16 irq = hwirq_to_irq(d->hwirq); 890 u8 buf; 891 892 if (bus->apid_data[apid].irq_ee != pmic_arb->ee) { 893 dev_err(&bus->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u: ee=%u but owner=%u\n", 894 sid, periph, irq, pmic_arb->ee, 895 bus->apid_data[apid].irq_ee); 896 return -ENODEV; 897 } 898 899 buf = BIT(irq); 900 qpnpint_spmi_write(d, QPNPINT_REG_EN_CLR, &buf, 1); 901 qpnpint_spmi_write(d, QPNPINT_REG_LATCHED_CLR, &buf, 1); 902 903 return 0; 904 } 905 906 static struct irq_chip pmic_arb_irqchip = { 907 .name = "pmic_arb", 908 .irq_ack = qpnpint_irq_ack, 909 .irq_mask = qpnpint_irq_mask, 910 .irq_unmask = qpnpint_irq_unmask, 911 .irq_set_type = qpnpint_irq_set_type, 912 .irq_set_wake = qpnpint_irq_set_wake, 913 .irq_get_irqchip_state = qpnpint_get_irqchip_state, 914 .flags = IRQCHIP_MASK_ON_SUSPEND, 915 }; 916 917 static int qpnpint_irq_domain_translate(struct irq_domain *d, 918 struct irq_fwspec *fwspec, 919 unsigned long *out_hwirq, 920 unsigned int *out_type) 921 { 922 struct spmi_pmic_arb_bus *bus = d->host_data; 923 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 924 u32 *intspec = fwspec->param; 925 u16 apid, ppid; 926 int rc; 927 928 dev_dbg(&bus->spmic->dev, "intspec[0] 0x%1x intspec[1] 0x%02x intspec[2] 0x%02x\n", 929 intspec[0], intspec[1], intspec[2]); 930 931 if (irq_domain_get_of_node(d) != bus->spmic->dev.of_node) 932 return -EINVAL; 933 if (fwspec->param_count != 4) 934 return -EINVAL; 935 if (intspec[0] > FIELD_MAX(HWIRQ_SID_MASK) || intspec[1] > FIELD_MAX(HWIRQ_PID_MASK) || 936 intspec[2] > FIELD_MAX(HWIRQ_IRQID_MASK)) 937 return -EINVAL; 938 939 ppid = intspec[0] << 8 | intspec[1]; 940 rc = pmic_arb->ver_ops->ppid_to_apid(bus, ppid); 941 if (rc < 0) { 942 dev_err(&bus->spmic->dev, "failed to xlate sid = %#x, periph = %#x, irq = %u rc = %d\n", 943 intspec[0], intspec[1], intspec[2], rc); 944 return rc; 945 } 946 947 apid = rc; 948 /* Keep track of {max,min}_apid for bounding search during interrupt */ 949 if (apid > bus->max_apid) 950 bus->max_apid = apid; 951 if (apid < bus->min_apid) 952 bus->min_apid = apid; 953 954 *out_hwirq = spec_to_hwirq(intspec[0], intspec[1], intspec[2], apid); 955 *out_type = intspec[3] & IRQ_TYPE_SENSE_MASK; 956 957 dev_dbg(&bus->spmic->dev, "out_hwirq = %lu\n", *out_hwirq); 958 959 return 0; 960 } 961 962 static struct lock_class_key qpnpint_irq_lock_class, qpnpint_irq_request_class; 963 964 static void qpnpint_irq_domain_map(struct spmi_pmic_arb_bus *bus, 965 struct irq_domain *domain, unsigned int virq, 966 irq_hw_number_t hwirq, unsigned int type) 967 { 968 irq_flow_handler_t handler; 969 970 dev_dbg(&bus->spmic->dev, "virq = %u, hwirq = %lu, type = %u\n", 971 virq, hwirq, type); 972 973 if (type & IRQ_TYPE_EDGE_BOTH) 974 handler = handle_edge_irq; 975 else 976 handler = handle_level_irq; 977 978 979 irq_set_lockdep_class(virq, &qpnpint_irq_lock_class, 980 &qpnpint_irq_request_class); 981 irq_domain_set_info(domain, virq, hwirq, &pmic_arb_irqchip, bus, 982 handler, NULL, NULL); 983 } 984 985 static int qpnpint_irq_domain_alloc(struct irq_domain *domain, 986 unsigned int virq, unsigned int nr_irqs, 987 void *data) 988 { 989 struct spmi_pmic_arb_bus *bus = domain->host_data; 990 struct irq_fwspec *fwspec = data; 991 irq_hw_number_t hwirq; 992 unsigned int type; 993 int ret, i; 994 995 ret = qpnpint_irq_domain_translate(domain, fwspec, &hwirq, &type); 996 if (ret) 997 return ret; 998 999 for (i = 0; i < nr_irqs; i++) 1000 qpnpint_irq_domain_map(bus, domain, virq + i, hwirq + i, 1001 type); 1002 1003 return 0; 1004 } 1005 1006 static int pmic_arb_init_apid_min_max(struct spmi_pmic_arb_bus *bus) 1007 { 1008 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1009 1010 /* 1011 * Initialize max_apid/min_apid to the opposite bounds, during 1012 * the irq domain translation, we are sure to update these 1013 */ 1014 bus->max_apid = 0; 1015 bus->min_apid = pmic_arb->max_periphs - 1; 1016 1017 return 0; 1018 } 1019 1020 static int pmic_arb_get_core_resources_v1(struct platform_device *pdev, 1021 void __iomem *core) 1022 { 1023 struct spmi_pmic_arb *pmic_arb = platform_get_drvdata(pdev); 1024 1025 pmic_arb->wr_base = core; 1026 pmic_arb->rd_base = core; 1027 1028 pmic_arb->max_periphs = PMIC_ARB_MAX_PERIPHS; 1029 1030 return 0; 1031 } 1032 1033 static int pmic_arb_init_apid_v1(struct spmi_pmic_arb_bus *bus, int index) 1034 { 1035 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1036 u32 *mapping_table; 1037 1038 if (index) { 1039 dev_err(&bus->spmic->dev, "Unsupported buses count %d detected\n", 1040 index); 1041 return -EINVAL; 1042 } 1043 1044 mapping_table = devm_kcalloc(&bus->spmic->dev, pmic_arb->max_periphs, 1045 sizeof(*mapping_table), GFP_KERNEL); 1046 if (!mapping_table) 1047 return -ENOMEM; 1048 1049 bus->mapping_table = mapping_table; 1050 1051 return pmic_arb_init_apid_min_max(bus); 1052 } 1053 1054 static int pmic_arb_ppid_to_apid_v1(struct spmi_pmic_arb_bus *bus, u16 ppid) 1055 { 1056 u32 *mapping_table = bus->mapping_table; 1057 int index = 0, i; 1058 u16 apid_valid; 1059 u16 apid; 1060 u32 data; 1061 1062 apid_valid = bus->ppid_to_apid[ppid]; 1063 if (apid_valid & PMIC_ARB_APID_VALID) { 1064 apid = apid_valid & ~PMIC_ARB_APID_VALID; 1065 return apid; 1066 } 1067 1068 for (i = 0; i < SPMI_MAPPING_TABLE_TREE_DEPTH; ++i) { 1069 if (!test_and_set_bit(index, bus->mapping_table_valid)) 1070 mapping_table[index] = readl_relaxed(bus->cnfg + 1071 SPMI_MAPPING_TABLE_REG(index)); 1072 1073 data = mapping_table[index]; 1074 1075 if (ppid & BIT(SPMI_MAPPING_BIT_INDEX(data))) { 1076 if (SPMI_MAPPING_BIT_IS_1_FLAG(data)) { 1077 index = SPMI_MAPPING_BIT_IS_1_RESULT(data); 1078 } else { 1079 apid = SPMI_MAPPING_BIT_IS_1_RESULT(data); 1080 bus->ppid_to_apid[ppid] 1081 = apid | PMIC_ARB_APID_VALID; 1082 bus->apid_data[apid].ppid = ppid; 1083 return apid; 1084 } 1085 } else { 1086 if (SPMI_MAPPING_BIT_IS_0_FLAG(data)) { 1087 index = SPMI_MAPPING_BIT_IS_0_RESULT(data); 1088 } else { 1089 apid = SPMI_MAPPING_BIT_IS_0_RESULT(data); 1090 bus->ppid_to_apid[ppid] 1091 = apid | PMIC_ARB_APID_VALID; 1092 bus->apid_data[apid].ppid = ppid; 1093 return apid; 1094 } 1095 } 1096 } 1097 1098 return -ENODEV; 1099 } 1100 1101 /* v1 offset per ee */ 1102 static int pmic_arb_offset_v1(struct spmi_pmic_arb_bus *bus, u8 sid, u16 addr, 1103 enum pmic_arb_channel ch_type) 1104 { 1105 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1106 return 0x800 + 0x80 * pmic_arb->channel; 1107 } 1108 1109 static u16 pmic_arb_find_apid(struct spmi_pmic_arb_bus *bus, u16 ppid) 1110 { 1111 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1112 struct apid_data *apidd = &bus->apid_data[bus->last_apid]; 1113 u32 regval, offset; 1114 u16 id, apid; 1115 1116 for (apid = bus->last_apid; ; apid++, apidd++) { 1117 offset = pmic_arb->ver_ops->apid_map_offset(apid); 1118 if (offset >= pmic_arb->core_size) 1119 break; 1120 1121 regval = readl_relaxed(pmic_arb->ver_ops->apid_owner(bus, 1122 apid)); 1123 apidd->irq_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval); 1124 apidd->write_ee = apidd->irq_ee; 1125 1126 regval = readl_relaxed(pmic_arb->core + offset); 1127 if (!regval) 1128 continue; 1129 1130 id = (regval >> 8) & PMIC_ARB_PPID_MASK; 1131 bus->ppid_to_apid[id] = apid | PMIC_ARB_APID_VALID; 1132 apidd->ppid = id; 1133 if (id == ppid) { 1134 apid |= PMIC_ARB_APID_VALID; 1135 break; 1136 } 1137 } 1138 bus->last_apid = apid & ~PMIC_ARB_APID_VALID; 1139 1140 return apid; 1141 } 1142 1143 static int pmic_arb_get_obsrvr_chnls_v2(struct platform_device *pdev) 1144 { 1145 struct spmi_pmic_arb *pmic_arb = platform_get_drvdata(pdev); 1146 1147 pmic_arb->rd_base = devm_platform_ioremap_resource_byname(pdev, "obsrvr"); 1148 if (IS_ERR(pmic_arb->rd_base)) 1149 return PTR_ERR(pmic_arb->rd_base); 1150 1151 pmic_arb->wr_base = devm_platform_ioremap_resource_byname(pdev, "chnls"); 1152 if (IS_ERR(pmic_arb->wr_base)) 1153 return PTR_ERR(pmic_arb->wr_base); 1154 1155 return 0; 1156 } 1157 1158 static int pmic_arb_get_core_resources_v2(struct platform_device *pdev, 1159 void __iomem *core) 1160 { 1161 struct spmi_pmic_arb *pmic_arb = platform_get_drvdata(pdev); 1162 1163 pmic_arb->core = core; 1164 1165 pmic_arb->max_periphs = PMIC_ARB_MAX_PERIPHS; 1166 1167 return pmic_arb_get_obsrvr_chnls_v2(pdev); 1168 } 1169 1170 static int pmic_arb_ppid_to_apid_v2(struct spmi_pmic_arb_bus *bus, u16 ppid) 1171 { 1172 u16 apid_valid; 1173 1174 apid_valid = bus->ppid_to_apid[ppid]; 1175 if (!(apid_valid & PMIC_ARB_APID_VALID)) 1176 apid_valid = pmic_arb_find_apid(bus, ppid); 1177 if (!(apid_valid & PMIC_ARB_APID_VALID)) 1178 return -ENODEV; 1179 1180 return apid_valid & ~PMIC_ARB_APID_VALID; 1181 } 1182 1183 static int _pmic_arb_read_apid_map(struct spmi_pmic_arb_bus *bus, 1184 void __iomem *ppid_base, unsigned long ppid_mask, 1185 u8 ppid_shift, unsigned long irq_owner_mask) 1186 { 1187 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1188 struct apid_data *apidd; 1189 struct apid_data *prev_apidd; 1190 u16 i, apid, ppid, apid_max; 1191 bool valid, is_irq_ee; 1192 u32 regval, offset; 1193 1194 /* 1195 * In order to allow multiple EEs to write to a single PPID in arbiter 1196 * version 5,7 and 8, there can be more than one APID mapped to each PPID. 1197 * The owner field for each of these mappings specifies the EE which is 1198 * allowed to write to the APID. The owner of the last (highest) APID 1199 * which has the IRQ owner bit set for a given PPID will receive 1200 * interrupts from the PPID. 1201 * 1202 * In arbiter version 7, the APID numbering space is divided between 1203 * the primary bus (0) and secondary bus (1) such that: 1204 * APID = 0 to N-1 are assigned to the primary bus 1205 * APID = N to N+M-1 are assigned to the secondary bus 1206 * where N = number of APIDs supported by the primary bus and 1207 * M = number of APIDs supported by the secondary bus 1208 * 1209 * In arbiter version 8, the APID numbering space is divided between 1210 * the SPMI buses according to this mapping: 1211 * APID = 0 to N-1 --> bus 0 1212 * APID = N to N+M-1 --> bus 1 1213 * APID = N+M to N+M+P-1 --> bus 2 1214 * APID = N+M+P to N+M+P+Q-1 --> bus 3 1215 * where N = number of APIDs supported by bus 0 1216 * M = number of APIDs supported by bus 1 1217 * P = number of APIDs supported by bus 2 1218 * Q = number of APIDs supported by bus 3 1219 */ 1220 1221 apidd = &bus->apid_data[bus->base_apid]; 1222 apid_max = bus->base_apid + bus->apid_count; 1223 for (i = bus->base_apid; i < apid_max; i++, apidd++) { 1224 offset = pmic_arb->ver_ops->apid_map_offset(i); 1225 if (offset >= pmic_arb->core_size) 1226 break; 1227 regval = readl_relaxed(ppid_base + offset); 1228 if (!regval) 1229 continue; 1230 ppid = (regval >> ppid_shift) & ppid_mask; 1231 is_irq_ee = regval & irq_owner_mask; 1232 1233 regval = readl_relaxed(pmic_arb->ver_ops->apid_owner(bus, i)); 1234 apidd->write_ee = SPMI_OWNERSHIP_PERIPH2OWNER(regval); 1235 1236 apidd->irq_ee = is_irq_ee ? apidd->write_ee : INVALID_EE; 1237 1238 valid = bus->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID; 1239 apid = bus->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID; 1240 prev_apidd = &bus->apid_data[apid]; 1241 1242 if (!valid || apidd->write_ee == pmic_arb->ee) { 1243 /* First PPID mapping or one for this EE */ 1244 bus->ppid_to_apid[ppid] = i | PMIC_ARB_APID_VALID; 1245 } else if (valid && is_irq_ee && 1246 prev_apidd->write_ee == pmic_arb->ee) { 1247 /* 1248 * Duplicate PPID mapping after the one for this EE; 1249 * override the irq owner 1250 */ 1251 prev_apidd->irq_ee = apidd->irq_ee; 1252 } 1253 1254 apidd->ppid = ppid; 1255 bus->last_apid = i; 1256 } 1257 1258 /* Dump the mapping table for debug purposes. */ 1259 dev_dbg(&bus->spmic->dev, "PPID APID Write-EE IRQ-EE\n"); 1260 for (ppid = 0; ppid < PMIC_ARB_MAX_PPID; ppid++) { 1261 apid = bus->ppid_to_apid[ppid]; 1262 if (apid & PMIC_ARB_APID_VALID) { 1263 apid &= ~PMIC_ARB_APID_VALID; 1264 apidd = &bus->apid_data[apid]; 1265 dev_dbg(&bus->spmic->dev, "%#03X %3u %2u %2u\n", 1266 ppid, apid, apidd->write_ee, apidd->irq_ee); 1267 } 1268 } 1269 1270 return 0; 1271 } 1272 1273 static int pmic_arb_read_apid_map_v5(struct spmi_pmic_arb_bus *bus) 1274 { 1275 return _pmic_arb_read_apid_map(bus, bus->pmic_arb->core, PMIC_ARB_PPID_MASK, 1276 8, PMIC_ARB_CHAN_IS_IRQ_OWNER_MASK); 1277 } 1278 1279 static int pmic_arb_ppid_to_apid_v5(struct spmi_pmic_arb_bus *bus, u16 ppid) 1280 { 1281 if (!(bus->ppid_to_apid[ppid] & PMIC_ARB_APID_VALID)) 1282 return -ENODEV; 1283 1284 return bus->ppid_to_apid[ppid] & ~PMIC_ARB_APID_VALID; 1285 } 1286 1287 /* v2 offset per ppid and per ee */ 1288 static int pmic_arb_offset_v2(struct spmi_pmic_arb_bus *bus, u8 sid, u16 addr, 1289 enum pmic_arb_channel ch_type) 1290 { 1291 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1292 u16 apid; 1293 u16 ppid; 1294 int rc; 1295 1296 ppid = sid << 8 | ((addr >> 8) & 0xFF); 1297 rc = pmic_arb_ppid_to_apid_v2(bus, ppid); 1298 if (rc < 0) 1299 return rc; 1300 1301 apid = rc; 1302 return 0x1000 * pmic_arb->ee + 0x8000 * apid; 1303 } 1304 1305 static int pmic_arb_init_apid_v5(struct spmi_pmic_arb_bus *bus, int index) 1306 { 1307 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1308 int ret; 1309 1310 if (index) { 1311 dev_err(&bus->spmic->dev, "Unsupported buses count %d detected\n", 1312 index); 1313 return -EINVAL; 1314 } 1315 1316 bus->base_apid = 0; 1317 bus->apid_count = readl_relaxed(pmic_arb->core + PMIC_ARB_FEATURES) & 1318 PMIC_ARB_FEATURES_PERIPH_MASK; 1319 1320 if (bus->base_apid + bus->apid_count > pmic_arb->max_periphs) { 1321 dev_err(&bus->spmic->dev, "Unsupported APID count %d detected\n", 1322 bus->base_apid + bus->apid_count); 1323 return -EINVAL; 1324 } 1325 1326 ret = pmic_arb_init_apid_min_max(bus); 1327 if (ret) 1328 return ret; 1329 1330 ret = pmic_arb_read_apid_map_v5(bus); 1331 if (ret) { 1332 dev_err(&bus->spmic->dev, "could not read APID->PPID mapping table, rc= %d\n", 1333 ret); 1334 return ret; 1335 } 1336 1337 return 0; 1338 } 1339 1340 /* 1341 * v5 offset per ee and per apid for observer channels and per apid for 1342 * read/write channels. 1343 */ 1344 static int pmic_arb_offset_v5(struct spmi_pmic_arb_bus *bus, u8 sid, u16 addr, 1345 enum pmic_arb_channel ch_type) 1346 { 1347 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1348 u16 apid; 1349 int rc; 1350 u32 offset = 0; 1351 u16 ppid = (sid << 8) | (addr >> 8); 1352 1353 rc = pmic_arb_ppid_to_apid_v5(bus, ppid); 1354 if (rc < 0) 1355 return rc; 1356 1357 apid = rc; 1358 switch (ch_type) { 1359 case PMIC_ARB_CHANNEL_OBS: 1360 offset = 0x10000 * pmic_arb->ee + 0x80 * apid; 1361 break; 1362 case PMIC_ARB_CHANNEL_RW: 1363 if (bus->apid_data[apid].write_ee != pmic_arb->ee) { 1364 dev_err(&bus->spmic->dev, "disallowed SPMI write to sid=%u, addr=0x%04X\n", 1365 sid, addr); 1366 return -EPERM; 1367 } 1368 offset = 0x10000 * apid; 1369 break; 1370 } 1371 1372 return offset; 1373 } 1374 1375 static int pmic_arb_get_core_resources_v7(struct platform_device *pdev, 1376 void __iomem *core) 1377 { 1378 struct spmi_pmic_arb *pmic_arb = platform_get_drvdata(pdev); 1379 1380 pmic_arb->core = core; 1381 1382 pmic_arb->max_periphs = PMIC_ARB_MAX_PERIPHS_V7; 1383 1384 return pmic_arb_get_obsrvr_chnls_v2(pdev); 1385 } 1386 1387 static int _pmic_arb_init_apid_v7(struct spmi_pmic_arb_bus *bus, int index, 1388 int max_buses, unsigned long periph_mask) 1389 { 1390 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1391 int i; 1392 1393 if (index < 0 || index >= max_buses) { 1394 dev_err(&bus->spmic->dev, "Unsupported bus index %d detected\n", 1395 index); 1396 return -EINVAL; 1397 } 1398 1399 bus->base_apid = 0; 1400 bus->apid_count = 0; 1401 for (i = 0; i <= index; i++) { 1402 bus->base_apid += bus->apid_count; 1403 bus->apid_count = readl_relaxed(pmic_arb->core + 1404 PMIC_ARB_FEATURES + i * 4) & 1405 periph_mask; 1406 } 1407 1408 if (bus->apid_count == 0) { 1409 dev_err(&bus->spmic->dev, "Bus %d not implemented\n", index); 1410 return -EINVAL; 1411 } else if (bus->base_apid + bus->apid_count > pmic_arb->max_periphs) { 1412 dev_err(&bus->spmic->dev, "Unsupported max APID %d detected\n", 1413 bus->base_apid + bus->apid_count); 1414 return -EINVAL; 1415 } 1416 1417 return pmic_arb_init_apid_min_max(bus); 1418 } 1419 1420 /* 1421 * Arbiter v7 supports 2 buses. Each bus will get a different apid count, read 1422 * from different registers. 1423 */ 1424 static int pmic_arb_init_apid_v7(struct spmi_pmic_arb_bus *bus, int index) 1425 { 1426 int ret = _pmic_arb_init_apid_v7(bus, index, 2, PMIC_ARB_FEATURES_PERIPH_MASK); 1427 if (ret) 1428 return ret; 1429 1430 ret = pmic_arb_read_apid_map_v5(bus); 1431 if (ret) { 1432 dev_err(&bus->spmic->dev, "could not read APID->PPID mapping table, rc= %d\n", 1433 ret); 1434 return ret; 1435 } 1436 1437 return 0; 1438 } 1439 1440 /* 1441 * v7 offset per ee and per apid for observer channels and per apid for 1442 * read/write channels. 1443 */ 1444 static int pmic_arb_offset_v7(struct spmi_pmic_arb_bus *bus, u8 sid, u16 addr, 1445 enum pmic_arb_channel ch_type) 1446 { 1447 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1448 u16 apid; 1449 int rc; 1450 u32 offset = 0; 1451 u16 ppid = (sid << 8) | (addr >> 8); 1452 1453 rc = pmic_arb->ver_ops->ppid_to_apid(bus, ppid); 1454 if (rc < 0) 1455 return rc; 1456 1457 apid = rc; 1458 switch (ch_type) { 1459 case PMIC_ARB_CHANNEL_OBS: 1460 offset = 0x8000 * pmic_arb->ee + 0x20 * apid; 1461 break; 1462 case PMIC_ARB_CHANNEL_RW: 1463 if (bus->apid_data[apid].write_ee != pmic_arb->ee) { 1464 dev_err(&bus->spmic->dev, "disallowed SPMI write to sid=%u, addr=0x%04X\n", 1465 sid, addr); 1466 return -EPERM; 1467 } 1468 offset = 0x1000 * apid; 1469 break; 1470 } 1471 1472 return offset; 1473 } 1474 1475 static int pmic_arb_get_core_resources_v8(struct platform_device *pdev, 1476 void __iomem *core) 1477 { 1478 struct spmi_pmic_arb *pmic_arb = platform_get_drvdata(pdev); 1479 1480 pmic_arb->apid_map = devm_platform_ioremap_resource_byname(pdev, "chnl_map"); 1481 if (IS_ERR(pmic_arb->apid_map)) 1482 return PTR_ERR(pmic_arb->apid_map); 1483 1484 pmic_arb->core = core; 1485 1486 pmic_arb->max_periphs = PMIC_ARB_MAX_PERIPHS_V8; 1487 1488 return pmic_arb_get_obsrvr_chnls_v2(pdev); 1489 } 1490 1491 static int pmic_arb_get_bus_resources_v8(struct platform_device *pdev, 1492 struct device_node *node, 1493 struct spmi_pmic_arb_bus *bus) 1494 { 1495 int index; 1496 1497 index = of_property_match_string(node, "reg-names", "chnl_owner"); 1498 if (index < 0) { 1499 dev_err(&pdev->dev, "chnl_owner reg region missing\n"); 1500 return -EINVAL; 1501 } 1502 1503 bus->apid_owner = devm_of_iomap(&pdev->dev, node, index, NULL); 1504 1505 return PTR_ERR_OR_ZERO(bus->apid_owner); 1506 } 1507 1508 static int pmic_arb_read_apid_map_v8(struct spmi_pmic_arb_bus *bus) 1509 { 1510 return _pmic_arb_read_apid_map(bus, bus->pmic_arb->apid_map, 1511 PMIC_ARB_V8_PPID_MASK, 0, 1512 PMIC_ARB_V8_CHAN_IS_IRQ_OWNER_MASK); 1513 } 1514 1515 /* 1516 * Arbiter v8 supports up to 4 buses. Each bus will get a different apid count, read 1517 * from different registers. 1518 */ 1519 static int pmic_arb_init_apid_v8(struct spmi_pmic_arb_bus *bus, int index) 1520 { 1521 int ret = _pmic_arb_init_apid_v7(bus, index, 4, 1522 PMIC_ARB_FEATURES_V8_PERIPH_MASK); 1523 if (ret) 1524 return ret; 1525 1526 ret = pmic_arb_read_apid_map_v8(bus); 1527 if (ret) { 1528 dev_err(&bus->spmic->dev, "could not read APID->PPID mapping table, rc= %d\n", 1529 ret); 1530 return ret; 1531 } 1532 1533 return 0; 1534 } 1535 1536 /* 1537 * v8 offset per ee and per apid for observer channels and per apid for 1538 * read/write channels. 1539 */ 1540 static int pmic_arb_offset_v8(struct spmi_pmic_arb_bus *bus, u8 sid, u16 addr, 1541 enum pmic_arb_channel ch_type) 1542 { 1543 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1544 u16 apid; 1545 int rc; 1546 u32 offset = 0; 1547 u16 ppid = (sid << 8) | (addr >> 8); 1548 1549 rc = pmic_arb->ver_ops->ppid_to_apid(bus, ppid); 1550 if (rc < 0) 1551 return rc; 1552 1553 apid = rc; 1554 switch (ch_type) { 1555 case PMIC_ARB_CHANNEL_OBS: 1556 offset = 0x40000 * pmic_arb->ee + 0x20 * apid; 1557 break; 1558 case PMIC_ARB_CHANNEL_RW: 1559 if (bus->apid_data[apid].write_ee != pmic_arb->ee) { 1560 dev_err(&bus->spmic->dev, "disallowed SPMI write to sid=%u, addr=0x%04X\n", 1561 sid, addr); 1562 return -EPERM; 1563 } 1564 offset = 0x200 * apid; 1565 break; 1566 } 1567 1568 return offset; 1569 } 1570 1571 static u32 pmic_arb_fmt_cmd_v1(u8 opc, u8 sid, u16 addr, u8 bc) 1572 { 1573 return (opc << 27) | ((sid & 0xf) << 20) | (addr << 4) | (bc & 0x7); 1574 } 1575 1576 static u32 pmic_arb_fmt_cmd_v2(u8 opc, u8 sid, u16 addr, u8 bc) 1577 { 1578 return (opc << 27) | ((addr & 0xff) << 4) | (bc & 0x7); 1579 } 1580 1581 static void __iomem * 1582 pmic_arb_owner_acc_status_v1(struct spmi_pmic_arb_bus *bus, u8 m, u16 n) 1583 { 1584 return bus->intr + 0x20 * m + 0x4 * n; 1585 } 1586 1587 static void __iomem * 1588 pmic_arb_owner_acc_status_v2(struct spmi_pmic_arb_bus *bus, u8 m, u16 n) 1589 { 1590 return bus->intr + 0x100000 + 0x1000 * m + 0x4 * n; 1591 } 1592 1593 static void __iomem * 1594 pmic_arb_owner_acc_status_v3(struct spmi_pmic_arb_bus *bus, u8 m, u16 n) 1595 { 1596 return bus->intr + 0x200000 + 0x1000 * m + 0x4 * n; 1597 } 1598 1599 static void __iomem * 1600 pmic_arb_owner_acc_status_v5(struct spmi_pmic_arb_bus *bus, u8 m, u16 n) 1601 { 1602 return bus->intr + 0x10000 * m + 0x4 * n; 1603 } 1604 1605 static void __iomem * 1606 pmic_arb_owner_acc_status_v7(struct spmi_pmic_arb_bus *bus, u8 m, u16 n) 1607 { 1608 return bus->intr + 0x1000 * m + 0x4 * n; 1609 } 1610 1611 static void __iomem * 1612 pmic_arb_acc_enable_v1(struct spmi_pmic_arb_bus *bus, u16 n) 1613 { 1614 return bus->intr + 0x200 + 0x4 * n; 1615 } 1616 1617 static void __iomem * 1618 pmic_arb_acc_enable_v2(struct spmi_pmic_arb_bus *bus, u16 n) 1619 { 1620 return bus->intr + 0x1000 * n; 1621 } 1622 1623 static void __iomem * 1624 pmic_arb_acc_enable_v5(struct spmi_pmic_arb_bus *bus, u16 n) 1625 { 1626 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1627 return pmic_arb->wr_base + 0x100 + 0x10000 * n; 1628 } 1629 1630 static void __iomem * 1631 pmic_arb_acc_enable_v7(struct spmi_pmic_arb_bus *bus, u16 n) 1632 { 1633 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1634 return pmic_arb->wr_base + 0x100 + 0x1000 * n; 1635 } 1636 1637 static void __iomem * 1638 pmic_arb_acc_enable_v8(struct spmi_pmic_arb_bus *bus, u16 n) 1639 { 1640 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1641 1642 return pmic_arb->wr_base + 0x100 + 0x200 * n; 1643 } 1644 1645 static void __iomem * 1646 pmic_arb_irq_status_v1(struct spmi_pmic_arb_bus *bus, u16 n) 1647 { 1648 return bus->intr + 0x600 + 0x4 * n; 1649 } 1650 1651 static void __iomem * 1652 pmic_arb_irq_status_v2(struct spmi_pmic_arb_bus *bus, u16 n) 1653 { 1654 return bus->intr + 0x4 + 0x1000 * n; 1655 } 1656 1657 static void __iomem * 1658 pmic_arb_irq_status_v5(struct spmi_pmic_arb_bus *bus, u16 n) 1659 { 1660 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1661 return pmic_arb->wr_base + 0x104 + 0x10000 * n; 1662 } 1663 1664 static void __iomem * 1665 pmic_arb_irq_status_v7(struct spmi_pmic_arb_bus *bus, u16 n) 1666 { 1667 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1668 return pmic_arb->wr_base + 0x104 + 0x1000 * n; 1669 } 1670 1671 static void __iomem * 1672 pmic_arb_irq_status_v8(struct spmi_pmic_arb_bus *bus, u16 n) 1673 { 1674 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1675 1676 return pmic_arb->wr_base + 0x104 + 0x200 * n; 1677 } 1678 1679 static void __iomem * 1680 pmic_arb_irq_clear_v1(struct spmi_pmic_arb_bus *bus, u16 n) 1681 { 1682 return bus->intr + 0xA00 + 0x4 * n; 1683 } 1684 1685 static void __iomem * 1686 pmic_arb_irq_clear_v2(struct spmi_pmic_arb_bus *bus, u16 n) 1687 { 1688 return bus->intr + 0x8 + 0x1000 * n; 1689 } 1690 1691 static void __iomem * 1692 pmic_arb_irq_clear_v5(struct spmi_pmic_arb_bus *bus, u16 n) 1693 { 1694 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1695 return pmic_arb->wr_base + 0x108 + 0x10000 * n; 1696 } 1697 1698 static void __iomem * 1699 pmic_arb_irq_clear_v7(struct spmi_pmic_arb_bus *bus, u16 n) 1700 { 1701 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1702 return pmic_arb->wr_base + 0x108 + 0x1000 * n; 1703 } 1704 1705 static void __iomem * 1706 pmic_arb_irq_clear_v8(struct spmi_pmic_arb_bus *bus, u16 n) 1707 { 1708 struct spmi_pmic_arb *pmic_arb = bus->pmic_arb; 1709 1710 return pmic_arb->wr_base + 0x108 + 0x200 * n; 1711 } 1712 1713 static u32 pmic_arb_apid_map_offset_v2(u16 n) 1714 { 1715 return 0x800 + 0x4 * n; 1716 } 1717 1718 static u32 pmic_arb_apid_map_offset_v5(u16 n) 1719 { 1720 return 0x900 + 0x4 * n; 1721 } 1722 1723 static u32 pmic_arb_apid_map_offset_v7(u16 n) 1724 { 1725 return 0x2000 + 0x4 * n; 1726 } 1727 1728 static u32 pmic_arb_apid_map_offset_v8(u16 n) 1729 { 1730 /* For v8, offset is from "chnl_map" base register, not "core". */ 1731 return 0x4 * n; 1732 } 1733 1734 static void __iomem * 1735 pmic_arb_apid_owner_v2(struct spmi_pmic_arb_bus *bus, u16 n) 1736 { 1737 return bus->cnfg + 0x700 + 0x4 * n; 1738 } 1739 1740 /* 1741 * For arbiter version 7 and 8, APID ownership table registers have independent 1742 * numbering space for each SPMI bus instance, so each is indexed starting from 1743 * 0. 1744 */ 1745 static void __iomem * 1746 pmic_arb_apid_owner_v7(struct spmi_pmic_arb_bus *bus, u16 n) 1747 { 1748 return bus->cnfg + 0x4 * (n - bus->base_apid); 1749 } 1750 1751 static void __iomem * 1752 pmic_arb_apid_owner_v8(struct spmi_pmic_arb_bus *bus, u16 n) 1753 { 1754 return bus->apid_owner + 0x4 * (n - bus->base_apid); 1755 } 1756 1757 static const struct pmic_arb_ver_ops pmic_arb_v1 = { 1758 .ver_str = "v1", 1759 .get_core_resources = pmic_arb_get_core_resources_v1, 1760 .init_apid = pmic_arb_init_apid_v1, 1761 .ppid_to_apid = pmic_arb_ppid_to_apid_v1, 1762 .non_data_cmd = pmic_arb_non_data_cmd_v1, 1763 .offset = pmic_arb_offset_v1, 1764 .fmt_cmd = pmic_arb_fmt_cmd_v1, 1765 .owner_acc_status = pmic_arb_owner_acc_status_v1, 1766 .acc_enable = pmic_arb_acc_enable_v1, 1767 .irq_status = pmic_arb_irq_status_v1, 1768 .irq_clear = pmic_arb_irq_clear_v1, 1769 .apid_map_offset = pmic_arb_apid_map_offset_v2, 1770 .apid_owner = pmic_arb_apid_owner_v2, 1771 }; 1772 1773 static const struct pmic_arb_ver_ops pmic_arb_v2 = { 1774 .ver_str = "v2", 1775 .get_core_resources = pmic_arb_get_core_resources_v2, 1776 .init_apid = pmic_arb_init_apid_v1, 1777 .ppid_to_apid = pmic_arb_ppid_to_apid_v2, 1778 .non_data_cmd = pmic_arb_non_data_cmd_v2, 1779 .offset = pmic_arb_offset_v2, 1780 .fmt_cmd = pmic_arb_fmt_cmd_v2, 1781 .owner_acc_status = pmic_arb_owner_acc_status_v2, 1782 .acc_enable = pmic_arb_acc_enable_v2, 1783 .irq_status = pmic_arb_irq_status_v2, 1784 .irq_clear = pmic_arb_irq_clear_v2, 1785 .apid_map_offset = pmic_arb_apid_map_offset_v2, 1786 .apid_owner = pmic_arb_apid_owner_v2, 1787 }; 1788 1789 static const struct pmic_arb_ver_ops pmic_arb_v3 = { 1790 .ver_str = "v3", 1791 .get_core_resources = pmic_arb_get_core_resources_v2, 1792 .init_apid = pmic_arb_init_apid_v1, 1793 .ppid_to_apid = pmic_arb_ppid_to_apid_v2, 1794 .non_data_cmd = pmic_arb_non_data_cmd_v2, 1795 .offset = pmic_arb_offset_v2, 1796 .fmt_cmd = pmic_arb_fmt_cmd_v2, 1797 .owner_acc_status = pmic_arb_owner_acc_status_v3, 1798 .acc_enable = pmic_arb_acc_enable_v2, 1799 .irq_status = pmic_arb_irq_status_v2, 1800 .irq_clear = pmic_arb_irq_clear_v2, 1801 .apid_map_offset = pmic_arb_apid_map_offset_v2, 1802 .apid_owner = pmic_arb_apid_owner_v2, 1803 }; 1804 1805 static const struct pmic_arb_ver_ops pmic_arb_v5 = { 1806 .ver_str = "v5", 1807 .get_core_resources = pmic_arb_get_core_resources_v2, 1808 .init_apid = pmic_arb_init_apid_v5, 1809 .ppid_to_apid = pmic_arb_ppid_to_apid_v5, 1810 .non_data_cmd = pmic_arb_non_data_cmd_v2, 1811 .offset = pmic_arb_offset_v5, 1812 .fmt_cmd = pmic_arb_fmt_cmd_v2, 1813 .owner_acc_status = pmic_arb_owner_acc_status_v5, 1814 .acc_enable = pmic_arb_acc_enable_v5, 1815 .irq_status = pmic_arb_irq_status_v5, 1816 .irq_clear = pmic_arb_irq_clear_v5, 1817 .apid_map_offset = pmic_arb_apid_map_offset_v5, 1818 .apid_owner = pmic_arb_apid_owner_v2, 1819 }; 1820 1821 static const struct pmic_arb_ver_ops pmic_arb_v7 = { 1822 .ver_str = "v7", 1823 .get_core_resources = pmic_arb_get_core_resources_v7, 1824 .init_apid = pmic_arb_init_apid_v7, 1825 .ppid_to_apid = pmic_arb_ppid_to_apid_v5, 1826 .non_data_cmd = pmic_arb_non_data_cmd_v2, 1827 .offset = pmic_arb_offset_v7, 1828 .fmt_cmd = pmic_arb_fmt_cmd_v2, 1829 .owner_acc_status = pmic_arb_owner_acc_status_v7, 1830 .acc_enable = pmic_arb_acc_enable_v7, 1831 .irq_status = pmic_arb_irq_status_v7, 1832 .irq_clear = pmic_arb_irq_clear_v7, 1833 .apid_map_offset = pmic_arb_apid_map_offset_v7, 1834 .apid_owner = pmic_arb_apid_owner_v7, 1835 }; 1836 1837 static const struct pmic_arb_ver_ops pmic_arb_v8 = { 1838 .ver_str = "v8", 1839 .get_core_resources = pmic_arb_get_core_resources_v8, 1840 .get_bus_resources = pmic_arb_get_bus_resources_v8, 1841 .init_apid = pmic_arb_init_apid_v8, 1842 .ppid_to_apid = pmic_arb_ppid_to_apid_v5, 1843 .non_data_cmd = pmic_arb_non_data_cmd_v2, 1844 .offset = pmic_arb_offset_v8, 1845 .fmt_cmd = pmic_arb_fmt_cmd_v2, 1846 .owner_acc_status = pmic_arb_owner_acc_status_v7, 1847 .acc_enable = pmic_arb_acc_enable_v8, 1848 .irq_status = pmic_arb_irq_status_v8, 1849 .irq_clear = pmic_arb_irq_clear_v8, 1850 .apid_map_offset = pmic_arb_apid_map_offset_v8, 1851 .apid_owner = pmic_arb_apid_owner_v8, 1852 }; 1853 1854 static const struct irq_domain_ops pmic_arb_irq_domain_ops = { 1855 .activate = qpnpint_irq_domain_activate, 1856 .alloc = qpnpint_irq_domain_alloc, 1857 .free = irq_domain_free_irqs_common, 1858 .translate = qpnpint_irq_domain_translate, 1859 }; 1860 1861 static int spmi_pmic_arb_bus_init(struct platform_device *pdev, 1862 struct device_node *node, 1863 struct spmi_pmic_arb *pmic_arb) 1864 { 1865 int bus_index = pmic_arb->buses_available; 1866 struct spmi_pmic_arb_bus *bus; 1867 struct device *dev = &pdev->dev; 1868 struct spmi_controller *ctrl; 1869 void __iomem *intr; 1870 void __iomem *cnfg; 1871 int index, ret; 1872 int irq; 1873 1874 ctrl = devm_spmi_controller_alloc(dev, sizeof(*bus)); 1875 if (IS_ERR(ctrl)) 1876 return PTR_ERR(ctrl); 1877 1878 ctrl->cmd = pmic_arb_cmd; 1879 ctrl->read_cmd = pmic_arb_read_cmd; 1880 ctrl->write_cmd = pmic_arb_write_cmd; 1881 1882 bus = spmi_controller_get_drvdata(ctrl); 1883 1884 pmic_arb->buses[bus_index] = bus; 1885 1886 raw_spin_lock_init(&bus->lock); 1887 1888 bus->ppid_to_apid = devm_kcalloc(dev, PMIC_ARB_MAX_PPID, 1889 sizeof(*bus->ppid_to_apid), 1890 GFP_KERNEL); 1891 if (!bus->ppid_to_apid) 1892 return -ENOMEM; 1893 1894 bus->apid_data = devm_kcalloc(dev, pmic_arb->max_periphs, 1895 sizeof(*bus->apid_data), 1896 GFP_KERNEL); 1897 if (!bus->apid_data) 1898 return -ENOMEM; 1899 1900 index = of_property_match_string(node, "reg-names", "cnfg"); 1901 if (index < 0) { 1902 dev_err(dev, "cnfg reg region missing\n"); 1903 return -EINVAL; 1904 } 1905 1906 cnfg = devm_of_iomap(dev, node, index, NULL); 1907 if (IS_ERR(cnfg)) 1908 return PTR_ERR(cnfg); 1909 1910 index = of_property_match_string(node, "reg-names", "intr"); 1911 if (index < 0) { 1912 dev_err(dev, "intr reg region missing\n"); 1913 return -EINVAL; 1914 } 1915 1916 intr = devm_of_iomap(dev, node, index, NULL); 1917 if (IS_ERR(intr)) 1918 return PTR_ERR(intr); 1919 1920 irq = of_irq_get_byname(node, "periph_irq"); 1921 if (irq <= 0) 1922 return irq ?: -ENXIO; 1923 1924 bus->pmic_arb = pmic_arb; 1925 bus->intr = intr; 1926 bus->cnfg = cnfg; 1927 bus->irq = irq; 1928 bus->spmic = ctrl; 1929 bus->id = bus_index; 1930 1931 if (pmic_arb->ver_ops->get_bus_resources) { 1932 ret = pmic_arb->ver_ops->get_bus_resources(pdev, node, bus); 1933 if (ret) 1934 return ret; 1935 } 1936 1937 ret = pmic_arb->ver_ops->init_apid(bus, bus_index); 1938 if (ret) 1939 return ret; 1940 1941 dev_dbg(&pdev->dev, "adding irq domain for bus %d\n", bus_index); 1942 1943 bus->domain = irq_domain_create_tree(of_fwnode_handle(node), &pmic_arb_irq_domain_ops, bus); 1944 if (!bus->domain) { 1945 dev_err(&pdev->dev, "unable to create irq_domain\n"); 1946 return -ENOMEM; 1947 } 1948 1949 irq_set_chained_handler_and_data(bus->irq, 1950 pmic_arb_chained_irq, bus); 1951 1952 ctrl->dev.of_node = node; 1953 dev_set_name(&ctrl->dev, "spmi-%d", bus_index); 1954 1955 ret = devm_spmi_controller_add(dev, ctrl); 1956 if (ret) 1957 return ret; 1958 1959 pmic_arb->buses_available++; 1960 1961 return 0; 1962 } 1963 1964 static int spmi_pmic_arb_register_buses(struct spmi_pmic_arb *pmic_arb, 1965 struct platform_device *pdev) 1966 { 1967 struct device *dev = &pdev->dev; 1968 struct device_node *node = dev->of_node; 1969 int ret; 1970 1971 /* legacy mode doesn't provide child node for the bus */ 1972 if (of_device_is_compatible(node, "qcom,spmi-pmic-arb")) 1973 return spmi_pmic_arb_bus_init(pdev, node, pmic_arb); 1974 1975 for_each_available_child_of_node_scoped(node, child) { 1976 if (of_node_name_eq(child, "spmi")) { 1977 ret = spmi_pmic_arb_bus_init(pdev, child, pmic_arb); 1978 if (ret) 1979 return ret; 1980 } 1981 } 1982 1983 return ret; 1984 } 1985 1986 static void spmi_pmic_arb_deregister_buses(struct spmi_pmic_arb *pmic_arb) 1987 { 1988 int i; 1989 1990 for (i = 0; i < pmic_arb->buses_available; i++) { 1991 struct spmi_pmic_arb_bus *bus = pmic_arb->buses[i]; 1992 1993 irq_set_chained_handler_and_data(bus->irq, 1994 NULL, NULL); 1995 irq_domain_remove(bus->domain); 1996 } 1997 } 1998 1999 static int spmi_pmic_arb_probe(struct platform_device *pdev) 2000 { 2001 struct spmi_pmic_arb *pmic_arb; 2002 struct device *dev = &pdev->dev; 2003 struct resource *res; 2004 void __iomem *core; 2005 u32 channel, ee, hw_ver; 2006 int err; 2007 2008 pmic_arb = devm_kzalloc(dev, sizeof(*pmic_arb), GFP_KERNEL); 2009 if (!pmic_arb) 2010 return -ENOMEM; 2011 2012 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "core"); 2013 core = devm_ioremap(dev, res->start, resource_size(res)); 2014 if (!core) 2015 return -ENOMEM; 2016 2017 pmic_arb->core_size = resource_size(res); 2018 2019 platform_set_drvdata(pdev, pmic_arb); 2020 2021 hw_ver = readl_relaxed(core + PMIC_ARB_VERSION); 2022 2023 if (hw_ver < PMIC_ARB_VERSION_V2_MIN) 2024 pmic_arb->ver_ops = &pmic_arb_v1; 2025 else if (hw_ver < PMIC_ARB_VERSION_V3_MIN) 2026 pmic_arb->ver_ops = &pmic_arb_v2; 2027 else if (hw_ver < PMIC_ARB_VERSION_V5_MIN) 2028 pmic_arb->ver_ops = &pmic_arb_v3; 2029 else if (hw_ver < PMIC_ARB_VERSION_V7_MIN) 2030 pmic_arb->ver_ops = &pmic_arb_v5; 2031 else if (hw_ver < PMIC_ARB_VERSION_V8_MIN) 2032 pmic_arb->ver_ops = &pmic_arb_v7; 2033 else 2034 pmic_arb->ver_ops = &pmic_arb_v8; 2035 2036 err = pmic_arb->ver_ops->get_core_resources(pdev, core); 2037 if (err) 2038 return err; 2039 2040 dev_info(dev, "PMIC arbiter version %s (0x%x)\n", 2041 pmic_arb->ver_ops->ver_str, hw_ver); 2042 2043 err = of_property_read_u32(pdev->dev.of_node, "qcom,channel", &channel); 2044 if (err) { 2045 dev_err(&pdev->dev, "channel unspecified.\n"); 2046 return err; 2047 } 2048 2049 if (channel > 5) { 2050 dev_err(&pdev->dev, "invalid channel (%u) specified.\n", 2051 channel); 2052 return -EINVAL; 2053 } 2054 2055 pmic_arb->channel = channel; 2056 2057 err = of_property_read_u32(pdev->dev.of_node, "qcom,ee", &ee); 2058 if (err) { 2059 dev_err(&pdev->dev, "EE unspecified.\n"); 2060 return err; 2061 } 2062 2063 if (ee > 5) { 2064 dev_err(&pdev->dev, "invalid EE (%u) specified\n", ee); 2065 return -EINVAL; 2066 } 2067 2068 pmic_arb->ee = ee; 2069 2070 return spmi_pmic_arb_register_buses(pmic_arb, pdev); 2071 } 2072 2073 static void spmi_pmic_arb_remove(struct platform_device *pdev) 2074 { 2075 struct spmi_pmic_arb *pmic_arb = platform_get_drvdata(pdev); 2076 2077 spmi_pmic_arb_deregister_buses(pmic_arb); 2078 } 2079 2080 static const struct of_device_id spmi_pmic_arb_match_table[] = { 2081 { .compatible = "qcom,spmi-pmic-arb", }, 2082 { .compatible = "qcom,x1e80100-spmi-pmic-arb", }, 2083 { .compatible = "qcom,glymur-spmi-pmic-arb", }, 2084 {}, 2085 }; 2086 MODULE_DEVICE_TABLE(of, spmi_pmic_arb_match_table); 2087 2088 static struct platform_driver spmi_pmic_arb_driver = { 2089 .probe = spmi_pmic_arb_probe, 2090 .remove = spmi_pmic_arb_remove, 2091 .driver = { 2092 .name = "spmi_pmic_arb", 2093 .of_match_table = spmi_pmic_arb_match_table, 2094 }, 2095 }; 2096 module_platform_driver(spmi_pmic_arb_driver); 2097 2098 MODULE_DESCRIPTION("Qualcomm MSM SPMI Controller (PMIC Arbiter) driver"); 2099 MODULE_LICENSE("GPL v2"); 2100 MODULE_ALIAS("platform:spmi_pmic_arb"); 2101