1 // SPDX-License-Identifier: GPL-2.0 2 // 3 // Copyright (c) 2021 MediaTek Inc. 4 // Copyright (c) 2025 Collabora Ltd 5 // AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> 6 7 #include <linux/clk.h> 8 #include <linux/interrupt.h> 9 #include <linux/iopoll.h> 10 #include <linux/irq.h> 11 #include <linux/irqdomain.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_irq.h> 15 #include <linux/platform_device.h> 16 #include <linux/property.h> 17 #include <linux/spmi.h> 18 #include <linux/irqchip/chained_irq.h> 19 20 #define SWINF_IDLE 0x00 21 #define SWINF_WFVLDCLR 0x06 22 23 #define GET_SWINF(x) (((x) >> 1) & 0x7) 24 25 #define PMIF_CMD_REG_0 0 26 #define PMIF_CMD_REG 1 27 #define PMIF_CMD_EXT_REG 2 28 #define PMIF_CMD_EXT_REG_LONG 3 29 30 #define PMIF_DELAY_US 2 31 #define PMIF_TIMEOUT_US (10 * 1000) 32 33 #define PMIF_CHAN_OFFSET 0x5 34 #define PMIF_RCS_IRQ_MASK GENMASK(7, 0) 35 36 #define PMIF_MAX_BUSES 2 37 #define PMIF_MAX_CLKS 3 38 39 #define SPMI_OP_ST_BUSY 1 40 41 struct ch_reg { 42 u32 ch_sta; 43 u32 wdata; 44 u32 rdata; 45 u32 ch_send; 46 u32 ch_rdy; 47 }; 48 49 struct pmif_data { 50 const u32 *regs; 51 const u32 *spmimst_regs; 52 u32 soc_chan; 53 u8 spmi_ver; 54 u32 num_spmi_buses; 55 }; 56 57 struct pmif_bus { 58 void __iomem *base; 59 void __iomem *spmimst_base; 60 struct spmi_controller *ctrl; 61 struct irq_domain *dom; 62 int irq; 63 struct clk_bulk_data clks[PMIF_MAX_CLKS]; 64 size_t nclks; 65 u8 irq_min_sid; 66 u8 irq_max_sid; 67 u16 irq_en; 68 raw_spinlock_t lock; 69 }; 70 71 struct pmif { 72 struct pmif_bus bus[PMIF_MAX_BUSES]; 73 struct ch_reg chan; 74 const struct pmif_data *data; 75 }; 76 77 static const char * const pmif_clock_names[] = { 78 "pmif_sys_ck", "pmif_tmr_ck", "spmimst_clk_mux", 79 }; 80 81 enum pmif_regs { 82 PMIF_INIT_DONE, 83 PMIF_INF_EN, 84 PMIF_ARB_EN, 85 PMIF_CMDISSUE_EN, 86 PMIF_TIMER_CTRL, 87 PMIF_SPI_MODE_CTRL, 88 PMIF_IRQ_EVENT_EN_0, 89 PMIF_IRQ_FLAG_0, 90 PMIF_IRQ_CLR_0, 91 PMIF_IRQ_EVENT_EN_1, 92 PMIF_IRQ_FLAG_1, 93 PMIF_IRQ_CLR_1, 94 PMIF_IRQ_EVENT_EN_2, 95 PMIF_IRQ_FLAG_2, 96 PMIF_IRQ_CLR_2, 97 PMIF_IRQ_EVENT_EN_3, 98 PMIF_IRQ_FLAG_3, 99 PMIF_IRQ_CLR_3, 100 PMIF_IRQ_EVENT_EN_4, 101 PMIF_IRQ_FLAG_4, 102 PMIF_IRQ_CLR_4, 103 PMIF_WDT_EVENT_EN_0, 104 PMIF_WDT_FLAG_0, 105 PMIF_WDT_EVENT_EN_1, 106 PMIF_WDT_FLAG_1, 107 PMIF_SWINF_0_STA, 108 PMIF_SWINF_0_WDATA_31_0, 109 PMIF_SWINF_0_RDATA_31_0, 110 PMIF_SWINF_0_ACC, 111 PMIF_SWINF_0_VLD_CLR, 112 PMIF_SWINF_1_STA, 113 PMIF_SWINF_1_WDATA_31_0, 114 PMIF_SWINF_1_RDATA_31_0, 115 PMIF_SWINF_1_ACC, 116 PMIF_SWINF_1_VLD_CLR, 117 PMIF_SWINF_2_STA, 118 PMIF_SWINF_2_WDATA_31_0, 119 PMIF_SWINF_2_RDATA_31_0, 120 PMIF_SWINF_2_ACC, 121 PMIF_SWINF_2_VLD_CLR, 122 PMIF_SWINF_3_STA, 123 PMIF_SWINF_3_WDATA_31_0, 124 PMIF_SWINF_3_RDATA_31_0, 125 PMIF_SWINF_3_ACC, 126 PMIF_SWINF_3_VLD_CLR, 127 }; 128 129 static const u32 mt6873_regs[] = { 130 [PMIF_INIT_DONE] = 0x0000, 131 [PMIF_INF_EN] = 0x0024, 132 [PMIF_ARB_EN] = 0x0150, 133 [PMIF_CMDISSUE_EN] = 0x03B4, 134 [PMIF_TIMER_CTRL] = 0x03E0, 135 [PMIF_SPI_MODE_CTRL] = 0x0400, 136 [PMIF_IRQ_EVENT_EN_0] = 0x0418, 137 [PMIF_IRQ_FLAG_0] = 0x0420, 138 [PMIF_IRQ_CLR_0] = 0x0424, 139 [PMIF_IRQ_EVENT_EN_1] = 0x0428, 140 [PMIF_IRQ_FLAG_1] = 0x0430, 141 [PMIF_IRQ_CLR_1] = 0x0434, 142 [PMIF_IRQ_EVENT_EN_2] = 0x0438, 143 [PMIF_IRQ_FLAG_2] = 0x0440, 144 [PMIF_IRQ_CLR_2] = 0x0444, 145 [PMIF_IRQ_EVENT_EN_3] = 0x0448, 146 [PMIF_IRQ_FLAG_3] = 0x0450, 147 [PMIF_IRQ_CLR_3] = 0x0454, 148 [PMIF_IRQ_EVENT_EN_4] = 0x0458, 149 [PMIF_IRQ_FLAG_4] = 0x0460, 150 [PMIF_IRQ_CLR_4] = 0x0464, 151 [PMIF_WDT_EVENT_EN_0] = 0x046C, 152 [PMIF_WDT_FLAG_0] = 0x0470, 153 [PMIF_WDT_EVENT_EN_1] = 0x0474, 154 [PMIF_WDT_FLAG_1] = 0x0478, 155 [PMIF_SWINF_0_ACC] = 0x0C00, 156 [PMIF_SWINF_0_WDATA_31_0] = 0x0C04, 157 [PMIF_SWINF_0_RDATA_31_0] = 0x0C14, 158 [PMIF_SWINF_0_VLD_CLR] = 0x0C24, 159 [PMIF_SWINF_0_STA] = 0x0C28, 160 [PMIF_SWINF_1_ACC] = 0x0C40, 161 [PMIF_SWINF_1_WDATA_31_0] = 0x0C44, 162 [PMIF_SWINF_1_RDATA_31_0] = 0x0C54, 163 [PMIF_SWINF_1_VLD_CLR] = 0x0C64, 164 [PMIF_SWINF_1_STA] = 0x0C68, 165 [PMIF_SWINF_2_ACC] = 0x0C80, 166 [PMIF_SWINF_2_WDATA_31_0] = 0x0C84, 167 [PMIF_SWINF_2_RDATA_31_0] = 0x0C94, 168 [PMIF_SWINF_2_VLD_CLR] = 0x0CA4, 169 [PMIF_SWINF_2_STA] = 0x0CA8, 170 [PMIF_SWINF_3_ACC] = 0x0CC0, 171 [PMIF_SWINF_3_WDATA_31_0] = 0x0CC4, 172 [PMIF_SWINF_3_RDATA_31_0] = 0x0CD4, 173 [PMIF_SWINF_3_VLD_CLR] = 0x0CE4, 174 [PMIF_SWINF_3_STA] = 0x0CE8, 175 }; 176 177 static const u32 mt8195_regs[] = { 178 [PMIF_INIT_DONE] = 0x0000, 179 [PMIF_INF_EN] = 0x0024, 180 [PMIF_ARB_EN] = 0x0150, 181 [PMIF_CMDISSUE_EN] = 0x03B8, 182 [PMIF_TIMER_CTRL] = 0x03E4, 183 [PMIF_SPI_MODE_CTRL] = 0x0408, 184 [PMIF_IRQ_EVENT_EN_0] = 0x0420, 185 [PMIF_IRQ_FLAG_0] = 0x0428, 186 [PMIF_IRQ_CLR_0] = 0x042C, 187 [PMIF_IRQ_EVENT_EN_1] = 0x0430, 188 [PMIF_IRQ_FLAG_1] = 0x0438, 189 [PMIF_IRQ_CLR_1] = 0x043C, 190 [PMIF_IRQ_EVENT_EN_2] = 0x0440, 191 [PMIF_IRQ_FLAG_2] = 0x0448, 192 [PMIF_IRQ_CLR_2] = 0x044C, 193 [PMIF_IRQ_EVENT_EN_3] = 0x0450, 194 [PMIF_IRQ_FLAG_3] = 0x0458, 195 [PMIF_IRQ_CLR_3] = 0x045C, 196 [PMIF_IRQ_EVENT_EN_4] = 0x0460, 197 [PMIF_IRQ_FLAG_4] = 0x0468, 198 [PMIF_IRQ_CLR_4] = 0x046C, 199 [PMIF_WDT_EVENT_EN_0] = 0x0474, 200 [PMIF_WDT_FLAG_0] = 0x0478, 201 [PMIF_WDT_EVENT_EN_1] = 0x047C, 202 [PMIF_WDT_FLAG_1] = 0x0480, 203 [PMIF_SWINF_0_ACC] = 0x0800, 204 [PMIF_SWINF_0_WDATA_31_0] = 0x0804, 205 [PMIF_SWINF_0_RDATA_31_0] = 0x0814, 206 [PMIF_SWINF_0_VLD_CLR] = 0x0824, 207 [PMIF_SWINF_0_STA] = 0x0828, 208 [PMIF_SWINF_1_ACC] = 0x0840, 209 [PMIF_SWINF_1_WDATA_31_0] = 0x0844, 210 [PMIF_SWINF_1_RDATA_31_0] = 0x0854, 211 [PMIF_SWINF_1_VLD_CLR] = 0x0864, 212 [PMIF_SWINF_1_STA] = 0x0868, 213 [PMIF_SWINF_2_ACC] = 0x0880, 214 [PMIF_SWINF_2_WDATA_31_0] = 0x0884, 215 [PMIF_SWINF_2_RDATA_31_0] = 0x0894, 216 [PMIF_SWINF_2_VLD_CLR] = 0x08A4, 217 [PMIF_SWINF_2_STA] = 0x08A8, 218 [PMIF_SWINF_3_ACC] = 0x08C0, 219 [PMIF_SWINF_3_WDATA_31_0] = 0x08C4, 220 [PMIF_SWINF_3_RDATA_31_0] = 0x08D4, 221 [PMIF_SWINF_3_VLD_CLR] = 0x08E4, 222 [PMIF_SWINF_3_STA] = 0x08E8, 223 }; 224 225 enum spmi_regs { 226 SPMI_OP_ST_CTRL, 227 SPMI_GRP_ID_EN, 228 SPMI_OP_ST_STA, 229 SPMI_MST_SAMPL, 230 SPMI_MST_REQ_EN, 231 SPMI_REC_CTRL, 232 SPMI_REC0, 233 SPMI_REC1, 234 SPMI_REC2, 235 SPMI_REC3, 236 SPMI_REC4, 237 SPMI_MST_DBG, 238 239 /* MT8195 spmi regs */ 240 SPMI_MST_RCS_CTRL, 241 SPMI_SLV_3_0_EINT, 242 SPMI_SLV_7_4_EINT, 243 SPMI_SLV_B_8_EINT, 244 SPMI_SLV_F_C_EINT, 245 SPMI_REC_CMD_DEC, 246 SPMI_DEC_DBG, 247 }; 248 249 static const u32 mt6873_spmi_regs[] = { 250 [SPMI_OP_ST_CTRL] = 0x0000, 251 [SPMI_GRP_ID_EN] = 0x0004, 252 [SPMI_OP_ST_STA] = 0x0008, 253 [SPMI_MST_SAMPL] = 0x000c, 254 [SPMI_MST_REQ_EN] = 0x0010, 255 [SPMI_REC_CTRL] = 0x0040, 256 [SPMI_REC0] = 0x0044, 257 [SPMI_REC1] = 0x0048, 258 [SPMI_REC2] = 0x004c, 259 [SPMI_REC3] = 0x0050, 260 [SPMI_REC4] = 0x0054, 261 [SPMI_MST_DBG] = 0x00fc, 262 }; 263 264 static const u32 mt8195_spmi_regs[] = { 265 [SPMI_OP_ST_CTRL] = 0x0000, 266 [SPMI_GRP_ID_EN] = 0x0004, 267 [SPMI_OP_ST_STA] = 0x0008, 268 [SPMI_MST_SAMPL] = 0x000C, 269 [SPMI_MST_REQ_EN] = 0x0010, 270 [SPMI_MST_RCS_CTRL] = 0x0014, 271 [SPMI_SLV_3_0_EINT] = 0x0020, 272 [SPMI_SLV_7_4_EINT] = 0x0024, 273 [SPMI_SLV_B_8_EINT] = 0x0028, 274 [SPMI_SLV_F_C_EINT] = 0x002C, 275 [SPMI_REC_CTRL] = 0x0040, 276 [SPMI_REC0] = 0x0044, 277 [SPMI_REC1] = 0x0048, 278 [SPMI_REC2] = 0x004C, 279 [SPMI_REC3] = 0x0050, 280 [SPMI_REC4] = 0x0054, 281 [SPMI_REC_CMD_DEC] = 0x005C, 282 [SPMI_DEC_DBG] = 0x00F8, 283 [SPMI_MST_DBG] = 0x00FC, 284 }; 285 286 static inline struct pmif *to_mtk_pmif(struct spmi_controller *ctrl) 287 { 288 return dev_get_drvdata(ctrl->dev.parent); 289 } 290 291 static u32 pmif_readl(struct pmif *arb, struct pmif_bus *pbus, enum pmif_regs reg) 292 { 293 return readl(pbus->base + arb->data->regs[reg]); 294 } 295 296 static void pmif_writel(struct pmif *arb, struct pmif_bus *pbus, 297 u32 val, enum pmif_regs reg) 298 { 299 writel(val, pbus->base + arb->data->regs[reg]); 300 } 301 302 static u32 mtk_spmi_readl(struct pmif *arb, struct pmif_bus *pbus, enum spmi_regs reg) 303 { 304 return readl(pbus->spmimst_base + arb->data->spmimst_regs[reg]); 305 } 306 307 static void mtk_spmi_writel(struct pmif *arb, struct pmif_bus *pbus, 308 u32 val, enum spmi_regs reg) 309 { 310 writel(val, pbus->spmimst_base + arb->data->spmimst_regs[reg]); 311 } 312 313 static bool pmif_is_fsm_vldclr(struct pmif *arb, struct pmif_bus *pbus) 314 { 315 u32 reg_rdata; 316 317 reg_rdata = pmif_readl(arb, pbus, arb->chan.ch_sta); 318 319 return GET_SWINF(reg_rdata) == SWINF_WFVLDCLR; 320 } 321 322 static int pmif_arb_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid) 323 { 324 struct pmif_bus *pbus = spmi_controller_get_drvdata(ctrl); 325 struct pmif *arb = to_mtk_pmif(ctrl); 326 u32 rdata, cmd; 327 int ret; 328 329 /* Check the opcode */ 330 if (opc < SPMI_CMD_RESET || opc > SPMI_CMD_WAKEUP) 331 return -EINVAL; 332 333 cmd = opc - SPMI_CMD_RESET; 334 335 mtk_spmi_writel(arb, pbus, (cmd << 0x4) | sid, SPMI_OP_ST_CTRL); 336 ret = readl_poll_timeout_atomic(pbus->spmimst_base + arb->data->spmimst_regs[SPMI_OP_ST_STA], 337 rdata, (rdata & SPMI_OP_ST_BUSY) == SPMI_OP_ST_BUSY, 338 PMIF_DELAY_US, PMIF_TIMEOUT_US); 339 if (ret < 0) 340 dev_err(&ctrl->dev, "timeout, err = %d\n", ret); 341 342 return ret; 343 } 344 345 static int pmif_spmi_read_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid, 346 u16 addr, u8 *buf, size_t len) 347 { 348 struct pmif_bus *pbus = spmi_controller_get_drvdata(ctrl); 349 struct pmif *arb = to_mtk_pmif(ctrl); 350 struct ch_reg *inf_reg; 351 int ret; 352 u32 data, cmd; 353 unsigned long flags; 354 355 /* Check for argument validation. */ 356 if (sid & ~0xf) { 357 dev_err(&ctrl->dev, "exceed the max slv id\n"); 358 return -EINVAL; 359 } 360 361 if (len > 4) { 362 dev_err(&ctrl->dev, "pmif supports 1..4 bytes per trans, but:%zu requested", len); 363 return -EINVAL; 364 } 365 366 if (opc >= 0x60 && opc <= 0x7f) 367 opc = PMIF_CMD_REG; 368 else if ((opc >= 0x20 && opc <= 0x2f) || (opc >= 0x38 && opc <= 0x3f)) 369 opc = PMIF_CMD_EXT_REG_LONG; 370 else 371 return -EINVAL; 372 373 raw_spin_lock_irqsave(&pbus->lock, flags); 374 /* Wait for Software Interface FSM state to be IDLE. */ 375 inf_reg = &arb->chan; 376 ret = readl_poll_timeout_atomic(pbus->base + arb->data->regs[inf_reg->ch_sta], 377 data, GET_SWINF(data) == SWINF_IDLE, 378 PMIF_DELAY_US, PMIF_TIMEOUT_US); 379 if (ret < 0) { 380 /* set channel ready if the data has transferred */ 381 if (pmif_is_fsm_vldclr(arb, pbus)) 382 pmif_writel(arb, pbus, 1, inf_reg->ch_rdy); 383 raw_spin_unlock_irqrestore(&pbus->lock, flags); 384 dev_err(&ctrl->dev, "failed to wait for SWINF_IDLE\n"); 385 return ret; 386 } 387 388 /* Send the command. */ 389 cmd = (opc << 30) | (sid << 24) | ((len - 1) << 16) | addr; 390 pmif_writel(arb, pbus, cmd, inf_reg->ch_send); 391 392 /* 393 * Wait for Software Interface FSM state to be WFVLDCLR, 394 * read the data and clear the valid flag. 395 */ 396 ret = readl_poll_timeout_atomic(pbus->base + arb->data->regs[inf_reg->ch_sta], 397 data, GET_SWINF(data) == SWINF_WFVLDCLR, 398 PMIF_DELAY_US, PMIF_TIMEOUT_US); 399 if (ret < 0) { 400 raw_spin_unlock_irqrestore(&pbus->lock, flags); 401 dev_err(&ctrl->dev, "failed to wait for SWINF_WFVLDCLR\n"); 402 return ret; 403 } 404 405 data = pmif_readl(arb, pbus, inf_reg->rdata); 406 pmif_writel(arb, pbus, 1, inf_reg->ch_rdy); 407 raw_spin_unlock_irqrestore(&pbus->lock, flags); 408 409 memcpy(buf, &data, len); 410 411 return 0; 412 } 413 414 static int pmif_spmi_write_cmd(struct spmi_controller *ctrl, u8 opc, u8 sid, 415 u16 addr, const u8 *buf, size_t len) 416 { 417 struct pmif_bus *pbus = spmi_controller_get_drvdata(ctrl); 418 struct pmif *arb = to_mtk_pmif(ctrl); 419 struct ch_reg *inf_reg; 420 int ret; 421 u32 data, wdata, cmd; 422 unsigned long flags; 423 424 /* Check for argument validation. */ 425 if (unlikely(sid & ~0xf)) { 426 dev_err(&ctrl->dev, "exceed the max slv id\n"); 427 return -EINVAL; 428 } 429 430 if (len > 4) { 431 dev_err(&ctrl->dev, "pmif supports 1..4 bytes per trans, but:%zu requested", len); 432 433 return -EINVAL; 434 } 435 436 /* Check the opcode */ 437 if (opc >= 0x40 && opc <= 0x5F) 438 opc = PMIF_CMD_REG; 439 else if ((opc <= 0xF) || (opc >= 0x30 && opc <= 0x37)) 440 opc = PMIF_CMD_EXT_REG_LONG; 441 else if (opc >= 0x80) 442 opc = PMIF_CMD_REG_0; 443 else 444 return -EINVAL; 445 446 /* Set the write data. */ 447 memcpy(&wdata, buf, len); 448 449 raw_spin_lock_irqsave(&pbus->lock, flags); 450 /* Wait for Software Interface FSM state to be IDLE. */ 451 inf_reg = &arb->chan; 452 ret = readl_poll_timeout_atomic(pbus->base + arb->data->regs[inf_reg->ch_sta], 453 data, GET_SWINF(data) == SWINF_IDLE, 454 PMIF_DELAY_US, PMIF_TIMEOUT_US); 455 if (ret < 0) { 456 /* set channel ready if the data has transferred */ 457 if (pmif_is_fsm_vldclr(arb, pbus)) 458 pmif_writel(arb, pbus, 1, inf_reg->ch_rdy); 459 raw_spin_unlock_irqrestore(&pbus->lock, flags); 460 dev_err(&ctrl->dev, "failed to wait for SWINF_IDLE\n"); 461 return ret; 462 } 463 464 pmif_writel(arb, pbus, wdata, inf_reg->wdata); 465 466 /* Send the command. */ 467 cmd = (opc << 30) | BIT(29) | (sid << 24) | ((len - 1) << 16) | addr; 468 pmif_writel(arb, pbus, cmd, inf_reg->ch_send); 469 raw_spin_unlock_irqrestore(&pbus->lock, flags); 470 471 return 0; 472 } 473 474 static void mtk_spmi_handle_chained_irq(struct irq_desc *desc) 475 { 476 struct pmif_bus *pbus = irq_desc_get_handler_data(desc); 477 struct irq_chip *chip = irq_desc_get_chip(desc); 478 struct pmif *arb = to_mtk_pmif(pbus->ctrl); 479 u8 regidx_min, regidx_max; 480 bool irq_handled = false; 481 unsigned int i; 482 483 regidx_min = pbus->irq_min_sid / 4; 484 regidx_min += SPMI_SLV_3_0_EINT; 485 486 regidx_max = pbus->irq_max_sid / 4; 487 regidx_max += SPMI_SLV_3_0_EINT; 488 489 chained_irq_enter(chip, desc); 490 491 for (i = regidx_min; i <= regidx_max; i++) { 492 u32 val = mtk_spmi_readl(arb, pbus, i); 493 494 while (val) { 495 u8 bit = __ffs(val); 496 u8 bank = bit / 7; 497 u8 sid = ((i - SPMI_SLV_3_0_EINT) * 4) + bank; 498 499 val &= ~(PMIF_RCS_IRQ_MASK << (8 * bank)); 500 501 /* Check if IRQs for this SID are enabled */ 502 if (!(pbus->irq_en & BIT(sid))) 503 continue; 504 505 generic_handle_domain_irq_safe(pbus->dom, sid); 506 irq_handled = true; 507 } 508 } 509 510 if (!irq_handled) 511 handle_bad_irq(desc); 512 513 chained_irq_exit(chip, desc); 514 } 515 516 static void mtk_spmi_rcs_irq_eoi(struct irq_data *d) 517 { 518 struct pmif_bus *pbus = irq_data_get_irq_chip_data(d); 519 struct pmif *arb = to_mtk_pmif(pbus->ctrl); 520 irq_hw_number_t irq = irqd_to_hwirq(d); 521 unsigned int reg, shift; 522 523 /* There are four interrupts (8 bits each) per register */ 524 reg = SPMI_SLV_3_0_EINT + d->hwirq / 4; 525 shift = (irq % 4) * 8; 526 527 mtk_spmi_writel(arb, pbus, PMIF_RCS_IRQ_MASK << shift, reg); 528 } 529 530 static void mtk_spmi_rcs_irq_enable(struct irq_data *d) 531 { 532 struct pmif_bus *pbus = irq_data_get_irq_chip_data(d); 533 irq_hw_number_t irq = irqd_to_hwirq(d); 534 535 pbus->irq_en |= BIT(irq); 536 } 537 538 static void mtk_spmi_rcs_irq_disable(struct irq_data *d) 539 { 540 struct pmif_bus *pbus = irq_data_get_irq_chip_data(d); 541 irq_hw_number_t irq = irqd_to_hwirq(d); 542 543 pbus->irq_en &= ~BIT(irq); 544 } 545 546 static int mtk_spmi_rcs_irq_set_wake(struct irq_data *d, unsigned int on) 547 { 548 struct pmif_bus *pbus = irq_data_get_irq_chip_data(d); 549 550 return irq_set_irq_wake(pbus->irq, on); 551 } 552 553 static const struct irq_chip mtk_spmi_rcs_irq_chip = { 554 .name = "spmi_rcs", 555 .irq_eoi = mtk_spmi_rcs_irq_eoi, 556 .irq_enable = mtk_spmi_rcs_irq_enable, 557 .irq_disable = mtk_spmi_rcs_irq_disable, 558 .irq_set_wake = mtk_spmi_rcs_irq_set_wake, 559 }; 560 561 static int mtk_spmi_rcs_irq_translate(struct irq_domain *d, struct irq_fwspec *fwspec, 562 unsigned long *out_hwirq, unsigned int *out_type) 563 { 564 struct pmif_bus *pbus = d->host_data; 565 struct device *dev = &pbus->ctrl->dev; 566 u32 *intspec = fwspec->param; 567 568 if (intspec[0] > SPMI_MAX_SLAVE_ID) 569 return -EINVAL; 570 571 /* 572 * The IRQ number in intspec[1] is ignored on purpose here! 573 * 574 * The controller only has knowledge of which SID raised an interrupt 575 * and the type of irq, but doesn't know about any device irq number, 576 * hence that must be read from the SPMI device's registers. 577 */ 578 *out_hwirq = intspec[0]; 579 *out_type = intspec[2] & IRQ_TYPE_SENSE_MASK; 580 581 if (pbus->irq_min_sid > intspec[0]) 582 pbus->irq_min_sid = intspec[0]; 583 584 if (pbus->irq_max_sid < intspec[0]) 585 pbus->irq_max_sid = intspec[0]; 586 587 dev_dbg(dev, "Found SPMI IRQ %u (map: 0x%lx)\n", intspec[0], *out_hwirq); 588 589 return 0; 590 } 591 592 static struct lock_class_key mtk_spmi_rcs_irqlock_class, mtk_spmi_rcs_irqreq_class; 593 594 static int mtk_spmi_rcs_irq_alloc(struct irq_domain *d, unsigned int virq, 595 unsigned int nr_irqs, void *data) 596 { 597 struct pmif_bus *pbus = d->host_data; 598 struct device *dev = &pbus->ctrl->dev; 599 struct irq_fwspec *fwspec = data; 600 irq_hw_number_t hwirq; 601 unsigned int irqtype; 602 int i, ret; 603 604 ret = mtk_spmi_rcs_irq_translate(d, fwspec, &hwirq, &irqtype); 605 if (ret) 606 return ret; 607 608 for (i = 0; i < nr_irqs; i++) { 609 dev_dbg(dev, "Mapping IRQ%u (hwirq %lu) with type %u\n", 610 virq, hwirq, irqtype); 611 612 irq_set_lockdep_class(virq, &mtk_spmi_rcs_irqlock_class, 613 &mtk_spmi_rcs_irqreq_class); 614 irq_domain_set_info(d, virq, hwirq, &mtk_spmi_rcs_irq_chip, 615 pbus, handle_level_irq, NULL, NULL); 616 } 617 618 return 0; 619 } 620 621 static const struct irq_domain_ops mtk_spmi_rcs_irq_domain_ops = { 622 .alloc = mtk_spmi_rcs_irq_alloc, 623 .free = irq_domain_free_irqs_common, 624 .translate = mtk_spmi_rcs_irq_translate, 625 }; 626 627 static const struct pmif_data mt6873_pmif_arb = { 628 .regs = mt6873_regs, 629 .spmimst_regs = mt6873_spmi_regs, 630 .soc_chan = 2, 631 }; 632 633 static const struct pmif_data mt8195_pmif_arb = { 634 .regs = mt8195_regs, 635 .spmimst_regs = mt8195_spmi_regs, 636 .soc_chan = 2, 637 }; 638 639 static const struct pmif_data mt8196_pmif_arb = { 640 .regs = mt8195_regs, 641 .spmimst_regs = mt8195_spmi_regs, 642 .soc_chan = 2, 643 .spmi_ver = 2, 644 .num_spmi_buses = 2, 645 }; 646 647 static int mtk_spmi_irq_init(struct device_node *node, 648 const struct pmif_data *pdata, 649 struct pmif_bus *pbus) 650 { 651 struct pmif *arb = to_mtk_pmif(pbus->ctrl); 652 unsigned int i; 653 654 /* No interrupts required for SPMI 1.x controller */ 655 if (pdata->spmi_ver < 2) { 656 pbus->dom = NULL; 657 return 0; 658 } 659 660 pbus->irq = of_irq_get_byname(node, "rcs"); 661 if (pbus->irq <= 0) 662 return pbus->irq ? : -ENXIO; 663 664 pbus->dom = irq_domain_create_tree(of_fwnode_handle(node), 665 &mtk_spmi_rcs_irq_domain_ops, pbus); 666 if (!pbus->dom) 667 return -ENOMEM; 668 669 /* Clear possible unhandled interrupts coming from bootloader SPMI init */ 670 for (i = SPMI_SLV_3_0_EINT; i <= SPMI_SLV_F_C_EINT; i++) 671 mtk_spmi_writel(arb, pbus, GENMASK(31, 0), i); 672 673 return 0; 674 } 675 676 static void mtk_spmi_irq_remove(struct pmif_bus *pbus) 677 { 678 if (!pbus->dom) 679 return; 680 681 irq_set_chained_handler_and_data(pbus->irq, NULL, NULL); 682 irq_domain_remove(pbus->dom); 683 } 684 685 static int mtk_spmi_bus_probe(struct platform_device *pdev, 686 struct device_node *node, 687 const struct pmif_data *pdata, 688 struct pmif_bus *pbus) 689 { 690 struct spmi_controller *ctrl; 691 int err, idx, bus_id, i; 692 693 if (pdata->num_spmi_buses > 1) 694 bus_id = of_alias_get_id(node, "spmi"); 695 else 696 bus_id = 0; 697 698 if (bus_id < 0) 699 return dev_err_probe(&pdev->dev, bus_id, 700 "Cannot find SPMI Bus alias ID\n"); 701 702 ctrl = devm_spmi_controller_alloc(&pdev->dev, sizeof(*pbus)); 703 if (IS_ERR(ctrl)) 704 return PTR_ERR(ctrl); 705 706 pbus = spmi_controller_get_drvdata(ctrl); 707 pbus->ctrl = ctrl; 708 709 idx = of_property_match_string(node, "reg-names", "pmif"); 710 if (idx < 0) 711 return -EINVAL; 712 713 pbus->base = devm_of_iomap(&pdev->dev, node, idx, NULL); 714 if (IS_ERR(pbus->base)) 715 return PTR_ERR(pbus->base); 716 717 idx = of_property_match_string(node, "reg-names", "spmimst"); 718 if (idx < 0) 719 return -EINVAL; 720 721 pbus->spmimst_base = devm_of_iomap(&pdev->dev, node, idx, NULL); 722 if (IS_ERR(pbus->spmimst_base)) 723 return PTR_ERR(pbus->spmimst_base); 724 725 pbus->nclks = ARRAY_SIZE(pmif_clock_names); 726 for (i = 0; i < pbus->nclks; i++) { 727 pbus->clks[i].id = pmif_clock_names[i]; 728 pbus->clks[i].clk = of_clk_get_by_name(node, pbus->clks[i].id); 729 if (IS_ERR(pbus->clks[i].clk)) 730 return dev_err_probe(&pdev->dev, PTR_ERR(pbus->clks[i].clk), 731 "Failed to get clocks\n"); 732 } 733 734 err = clk_bulk_prepare_enable(pbus->nclks, pbus->clks); 735 if (err) { 736 dev_err_probe(&pdev->dev, err, "Failed to enable clocks\n"); 737 goto err_put_clks; 738 } 739 740 err = mtk_spmi_irq_init(node, pdata, pbus); 741 if (err) { 742 dev_err_probe(&pdev->dev, err, "Cannot initialize SPMI IRQs\n"); 743 goto err_disable_clks; 744 } 745 746 ctrl->cmd = pmif_arb_cmd; 747 ctrl->read_cmd = pmif_spmi_read_cmd; 748 ctrl->write_cmd = pmif_spmi_write_cmd; 749 ctrl->dev.of_node = node; 750 dev_set_name(&ctrl->dev, "spmi-%d", bus_id); 751 752 raw_spin_lock_init(&pbus->lock); 753 754 err = spmi_controller_add(ctrl); 755 if (err) 756 goto err_remove_irq; 757 758 if (pbus->dom) 759 irq_set_chained_handler_and_data(pbus->irq, mtk_spmi_handle_chained_irq, pbus); 760 761 return 0; 762 763 err_remove_irq: 764 mtk_spmi_irq_remove(pbus); 765 err_disable_clks: 766 clk_bulk_disable_unprepare(pbus->nclks, pbus->clks); 767 err_put_clks: 768 clk_bulk_put(pbus->nclks, pbus->clks); 769 return err; 770 } 771 772 static int mtk_spmi_probe(struct platform_device *pdev) 773 { 774 struct device_node *node = pdev->dev.of_node; 775 struct pmif *arb; 776 u32 chan_offset; 777 u8 cur_bus = 0; 778 int ret; 779 780 arb = devm_kzalloc(&pdev->dev, sizeof(*arb), GFP_KERNEL); 781 if (!arb) 782 return -ENOMEM; 783 784 arb->data = device_get_match_data(&pdev->dev); 785 if (!arb->data) { 786 dev_err(&pdev->dev, "Cannot get drv_data\n"); 787 return -EINVAL; 788 } 789 790 platform_set_drvdata(pdev, arb); 791 792 if (!arb->data->num_spmi_buses) { 793 ret = mtk_spmi_bus_probe(pdev, node, arb->data, &arb->bus[cur_bus]); 794 if (ret) 795 return ret; 796 } else { 797 for_each_available_child_of_node_scoped(node, child) { 798 if (!of_node_name_eq(child, "spmi")) 799 continue; 800 801 ret = mtk_spmi_bus_probe(pdev, child, arb->data, 802 &arb->bus[cur_bus]); 803 if (ret) 804 return ret; 805 cur_bus++; 806 } 807 } 808 809 chan_offset = PMIF_CHAN_OFFSET * arb->data->soc_chan; 810 arb->chan.ch_sta = PMIF_SWINF_0_STA + chan_offset; 811 arb->chan.wdata = PMIF_SWINF_0_WDATA_31_0 + chan_offset; 812 arb->chan.rdata = PMIF_SWINF_0_RDATA_31_0 + chan_offset; 813 arb->chan.ch_send = PMIF_SWINF_0_ACC + chan_offset; 814 arb->chan.ch_rdy = PMIF_SWINF_0_VLD_CLR + chan_offset; 815 816 return 0; 817 } 818 819 static void mtk_spmi_remove(struct platform_device *pdev) 820 { 821 struct pmif *arb = platform_get_drvdata(pdev); 822 int i; 823 824 for (i = 0; i < PMIF_MAX_BUSES; i++) { 825 struct pmif_bus *pbus = &arb->bus[i]; 826 827 if (!pbus->ctrl) 828 continue; 829 830 mtk_spmi_irq_remove(pbus); 831 spmi_controller_remove(pbus->ctrl); 832 clk_bulk_disable_unprepare(pbus->nclks, pbus->clks); 833 clk_bulk_put(pbus->nclks, pbus->clks); 834 } 835 } 836 837 static const struct of_device_id mtk_spmi_match_table[] = { 838 { 839 .compatible = "mediatek,mt6873-spmi", 840 .data = &mt6873_pmif_arb, 841 }, { 842 .compatible = "mediatek,mt8195-spmi", 843 .data = &mt8195_pmif_arb, 844 }, { 845 .compatible = "mediatek,mt8196-spmi", 846 .data = &mt8196_pmif_arb, 847 }, { 848 /* sentinel */ 849 }, 850 }; 851 MODULE_DEVICE_TABLE(of, mtk_spmi_match_table); 852 853 static struct platform_driver mtk_spmi_driver = { 854 .driver = { 855 .name = "spmi-mtk", 856 .of_match_table = mtk_spmi_match_table, 857 }, 858 .probe = mtk_spmi_probe, 859 .remove = mtk_spmi_remove, 860 }; 861 module_platform_driver(mtk_spmi_driver); 862 863 MODULE_AUTHOR("AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>"); 864 MODULE_AUTHOR("Hsin-Hsiung Wang <hsin-hsiung.wang@mediatek.com>"); 865 MODULE_DESCRIPTION("MediaTek SPMI Driver"); 866 MODULE_LICENSE("GPL"); 867