1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Xilinx Zynq UltraScale+ MPSoC Quad-SPI (QSPI) controller driver 4 * (master mode only) 5 * 6 * Copyright (C) 2009 - 2015 Xilinx, Inc. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/dma-mapping.h> 12 #include <linux/dmaengine.h> 13 #include <linux/firmware/xlnx-zynqmp.h> 14 #include <linux/interrupt.h> 15 #include <linux/io.h> 16 #include <linux/module.h> 17 #include <linux/of_irq.h> 18 #include <linux/of_address.h> 19 #include <linux/platform_device.h> 20 #include <linux/pm_runtime.h> 21 #include <linux/spi/spi.h> 22 #include <linux/spinlock.h> 23 #include <linux/workqueue.h> 24 #include <linux/spi/spi-mem.h> 25 26 /* Generic QSPI register offsets */ 27 #define GQSPI_CONFIG_OFST 0x00000100 28 #define GQSPI_ISR_OFST 0x00000104 29 #define GQSPI_IDR_OFST 0x0000010C 30 #define GQSPI_IER_OFST 0x00000108 31 #define GQSPI_IMASK_OFST 0x00000110 32 #define GQSPI_EN_OFST 0x00000114 33 #define GQSPI_TXD_OFST 0x0000011C 34 #define GQSPI_RXD_OFST 0x00000120 35 #define GQSPI_TX_THRESHOLD_OFST 0x00000128 36 #define GQSPI_RX_THRESHOLD_OFST 0x0000012C 37 #define GQSPI_LPBK_DLY_ADJ_OFST 0x00000138 38 #define GQSPI_GEN_FIFO_OFST 0x00000140 39 #define GQSPI_SEL_OFST 0x00000144 40 #define GQSPI_GF_THRESHOLD_OFST 0x00000150 41 #define GQSPI_FIFO_CTRL_OFST 0x0000014C 42 #define GQSPI_QSPIDMA_DST_CTRL_OFST 0x0000080C 43 #define GQSPI_QSPIDMA_DST_SIZE_OFST 0x00000804 44 #define GQSPI_QSPIDMA_DST_STS_OFST 0x00000808 45 #define GQSPI_QSPIDMA_DST_I_STS_OFST 0x00000814 46 #define GQSPI_QSPIDMA_DST_I_EN_OFST 0x00000818 47 #define GQSPI_QSPIDMA_DST_I_DIS_OFST 0x0000081C 48 #define GQSPI_QSPIDMA_DST_I_MASK_OFST 0x00000820 49 #define GQSPI_QSPIDMA_DST_ADDR_OFST 0x00000800 50 #define GQSPI_QSPIDMA_DST_ADDR_MSB_OFST 0x00000828 51 52 /* GQSPI register bit masks */ 53 #define GQSPI_SEL_MASK 0x00000001 54 #define GQSPI_EN_MASK 0x00000001 55 #define GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK 0x00000020 56 #define GQSPI_ISR_WR_TO_CLR_MASK 0x00000002 57 #define GQSPI_IDR_ALL_MASK 0x00000FBE 58 #define GQSPI_CFG_MODE_EN_MASK 0xC0000000 59 #define GQSPI_CFG_GEN_FIFO_START_MODE_MASK 0x20000000 60 #define GQSPI_CFG_ENDIAN_MASK 0x04000000 61 #define GQSPI_CFG_EN_POLL_TO_MASK 0x00100000 62 #define GQSPI_CFG_WP_HOLD_MASK 0x00080000 63 #define GQSPI_CFG_BAUD_RATE_DIV_MASK 0x00000038 64 #define GQSPI_CFG_CLK_PHA_MASK 0x00000004 65 #define GQSPI_CFG_CLK_POL_MASK 0x00000002 66 #define GQSPI_CFG_START_GEN_FIFO_MASK 0x10000000 67 #define GQSPI_GENFIFO_IMM_DATA_MASK 0x000000FF 68 #define GQSPI_GENFIFO_DATA_XFER 0x00000100 69 #define GQSPI_GENFIFO_EXP 0x00000200 70 #define GQSPI_GENFIFO_MODE_SPI 0x00000400 71 #define GQSPI_GENFIFO_MODE_DUALSPI 0x00000800 72 #define GQSPI_GENFIFO_MODE_QUADSPI 0x00000C00 73 #define GQSPI_GENFIFO_MODE_MASK 0x00000C00 74 #define GQSPI_GENFIFO_CS_LOWER 0x00001000 75 #define GQSPI_GENFIFO_CS_UPPER 0x00002000 76 #define GQSPI_GENFIFO_BUS_LOWER 0x00004000 77 #define GQSPI_GENFIFO_BUS_UPPER 0x00008000 78 #define GQSPI_GENFIFO_BUS_BOTH 0x0000C000 79 #define GQSPI_GENFIFO_BUS_MASK 0x0000C000 80 #define GQSPI_GENFIFO_TX 0x00010000 81 #define GQSPI_GENFIFO_RX 0x00020000 82 #define GQSPI_GENFIFO_STRIPE 0x00040000 83 #define GQSPI_GENFIFO_POLL 0x00080000 84 #define GQSPI_GENFIFO_EXP_START 0x00000100 85 #define GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK 0x00000004 86 #define GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK 0x00000002 87 #define GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK 0x00000001 88 #define GQSPI_ISR_RXEMPTY_MASK 0x00000800 89 #define GQSPI_ISR_GENFIFOFULL_MASK 0x00000400 90 #define GQSPI_ISR_GENFIFONOT_FULL_MASK 0x00000200 91 #define GQSPI_ISR_TXEMPTY_MASK 0x00000100 92 #define GQSPI_ISR_GENFIFOEMPTY_MASK 0x00000080 93 #define GQSPI_ISR_RXFULL_MASK 0x00000020 94 #define GQSPI_ISR_RXNEMPTY_MASK 0x00000010 95 #define GQSPI_ISR_TXFULL_MASK 0x00000008 96 #define GQSPI_ISR_TXNOT_FULL_MASK 0x00000004 97 #define GQSPI_ISR_POLL_TIME_EXPIRE_MASK 0x00000002 98 #define GQSPI_IER_TXNOT_FULL_MASK 0x00000004 99 #define GQSPI_IER_RXEMPTY_MASK 0x00000800 100 #define GQSPI_IER_POLL_TIME_EXPIRE_MASK 0x00000002 101 #define GQSPI_IER_RXNEMPTY_MASK 0x00000010 102 #define GQSPI_IER_GENFIFOEMPTY_MASK 0x00000080 103 #define GQSPI_IER_TXEMPTY_MASK 0x00000100 104 #define GQSPI_QSPIDMA_DST_INTR_ALL_MASK 0x000000FE 105 #define GQSPI_QSPIDMA_DST_STS_WTC 0x0000E000 106 #define GQSPI_CFG_MODE_EN_DMA_MASK 0x80000000 107 #define GQSPI_ISR_IDR_MASK 0x00000994 108 #define GQSPI_QSPIDMA_DST_I_EN_DONE_MASK 0x00000002 109 #define GQSPI_QSPIDMA_DST_I_STS_DONE_MASK 0x00000002 110 #define GQSPI_IRQ_MASK 0x00000980 111 112 #define GQSPI_CFG_BAUD_RATE_DIV_SHIFT 3 113 #define GQSPI_GENFIFO_CS_SETUP 0x4 114 #define GQSPI_GENFIFO_CS_HOLD 0x3 115 #define GQSPI_TXD_DEPTH 64 116 #define GQSPI_RX_FIFO_THRESHOLD 32 117 #define GQSPI_RX_FIFO_FILL (GQSPI_RX_FIFO_THRESHOLD * 4) 118 #define GQSPI_TX_FIFO_THRESHOLD_RESET_VAL 32 119 #define GQSPI_TX_FIFO_FILL (GQSPI_TXD_DEPTH -\ 120 GQSPI_TX_FIFO_THRESHOLD_RESET_VAL) 121 #define GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL 0X10 122 #define GQSPI_QSPIDMA_DST_CTRL_RESET_VAL 0x803FFA00 123 #define GQSPI_SELECT_FLASH_CS_LOWER 0x1 124 #define GQSPI_SELECT_FLASH_CS_UPPER 0x2 125 #define GQSPI_SELECT_FLASH_CS_BOTH 0x3 126 #define GQSPI_SELECT_FLASH_BUS_LOWER 0x1 127 #define GQSPI_SELECT_FLASH_BUS_UPPER 0x2 128 #define GQSPI_SELECT_FLASH_BUS_BOTH 0x3 129 #define GQSPI_BAUD_DIV_MAX 7 /* Baud rate divisor maximum */ 130 #define GQSPI_BAUD_DIV_SHIFT 2 /* Baud rate divisor shift */ 131 #define GQSPI_SELECT_MODE_SPI 0x1 132 #define GQSPI_SELECT_MODE_DUALSPI 0x2 133 #define GQSPI_SELECT_MODE_QUADSPI 0x4 134 #define GQSPI_DMA_UNALIGN 0x3 135 #define GQSPI_DEFAULT_NUM_CS 1 /* Default number of chip selects */ 136 137 #define SPI_AUTOSUSPEND_TIMEOUT 3000 138 enum mode_type {GQSPI_MODE_IO, GQSPI_MODE_DMA}; 139 140 /** 141 * struct zynqmp_qspi - Defines qspi driver instance 142 * @regs: Virtual address of the QSPI controller registers 143 * @refclk: Pointer to the peripheral clock 144 * @pclk: Pointer to the APB clock 145 * @irq: IRQ number 146 * @dev: Pointer to struct device 147 * @txbuf: Pointer to the TX buffer 148 * @rxbuf: Pointer to the RX buffer 149 * @bytes_to_transfer: Number of bytes left to transfer 150 * @bytes_to_receive: Number of bytes left to receive 151 * @genfifocs: Used for chip select 152 * @genfifobus: Used to select the upper or lower bus 153 * @dma_rx_bytes: Remaining bytes to receive by DMA mode 154 * @dma_addr: DMA address after mapping the kernel buffer 155 * @genfifoentry: Used for storing the genfifoentry instruction. 156 * @mode: Defines the mode in which QSPI is operating 157 * @data_completion: completion structure 158 */ 159 struct zynqmp_qspi { 160 struct spi_controller *ctlr; 161 void __iomem *regs; 162 struct clk *refclk; 163 struct clk *pclk; 164 int irq; 165 struct device *dev; 166 const void *txbuf; 167 void *rxbuf; 168 int bytes_to_transfer; 169 int bytes_to_receive; 170 u32 genfifocs; 171 u32 genfifobus; 172 u32 dma_rx_bytes; 173 dma_addr_t dma_addr; 174 u32 genfifoentry; 175 enum mode_type mode; 176 struct completion data_completion; 177 struct mutex op_lock; 178 }; 179 180 /** 181 * zynqmp_gqspi_read - For GQSPI controller read operation 182 * @xqspi: Pointer to the zynqmp_qspi structure 183 * @offset: Offset from where to read 184 * Return: Value at the offset 185 */ 186 static u32 zynqmp_gqspi_read(struct zynqmp_qspi *xqspi, u32 offset) 187 { 188 return readl_relaxed(xqspi->regs + offset); 189 } 190 191 /** 192 * zynqmp_gqspi_write - For GQSPI controller write operation 193 * @xqspi: Pointer to the zynqmp_qspi structure 194 * @offset: Offset where to write 195 * @val: Value to be written 196 */ 197 static inline void zynqmp_gqspi_write(struct zynqmp_qspi *xqspi, u32 offset, 198 u32 val) 199 { 200 writel_relaxed(val, (xqspi->regs + offset)); 201 } 202 203 /** 204 * zynqmp_gqspi_selectslave - For selection of slave device 205 * @instanceptr: Pointer to the zynqmp_qspi structure 206 * @slavecs: For chip select 207 * @slavebus: To check which bus is selected- upper or lower 208 */ 209 static void zynqmp_gqspi_selectslave(struct zynqmp_qspi *instanceptr, 210 u8 slavecs, u8 slavebus) 211 { 212 /* 213 * Bus and CS lines selected here will be updated in the instance and 214 * used for subsequent GENFIFO entries during transfer. 215 */ 216 217 /* Choose slave select line */ 218 switch (slavecs) { 219 case GQSPI_SELECT_FLASH_CS_BOTH: 220 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER | 221 GQSPI_GENFIFO_CS_UPPER; 222 break; 223 case GQSPI_SELECT_FLASH_CS_UPPER: 224 instanceptr->genfifocs = GQSPI_GENFIFO_CS_UPPER; 225 break; 226 case GQSPI_SELECT_FLASH_CS_LOWER: 227 instanceptr->genfifocs = GQSPI_GENFIFO_CS_LOWER; 228 break; 229 default: 230 dev_warn(instanceptr->dev, "Invalid slave select\n"); 231 } 232 233 /* Choose the bus */ 234 switch (slavebus) { 235 case GQSPI_SELECT_FLASH_BUS_BOTH: 236 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER | 237 GQSPI_GENFIFO_BUS_UPPER; 238 break; 239 case GQSPI_SELECT_FLASH_BUS_UPPER: 240 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_UPPER; 241 break; 242 case GQSPI_SELECT_FLASH_BUS_LOWER: 243 instanceptr->genfifobus = GQSPI_GENFIFO_BUS_LOWER; 244 break; 245 default: 246 dev_warn(instanceptr->dev, "Invalid slave bus\n"); 247 } 248 } 249 250 /** 251 * zynqmp_qspi_init_hw - Initialize the hardware 252 * @xqspi: Pointer to the zynqmp_qspi structure 253 * 254 * The default settings of the QSPI controller's configurable parameters on 255 * reset are 256 * - Master mode 257 * - TX threshold set to 1 258 * - RX threshold set to 1 259 * - Flash memory interface mode enabled 260 * This function performs the following actions 261 * - Disable and clear all the interrupts 262 * - Enable manual slave select 263 * - Enable manual start 264 * - Deselect all the chip select lines 265 * - Set the little endian mode of TX FIFO and 266 * - Enable the QSPI controller 267 */ 268 static void zynqmp_qspi_init_hw(struct zynqmp_qspi *xqspi) 269 { 270 u32 config_reg; 271 272 /* Select the GQSPI mode */ 273 zynqmp_gqspi_write(xqspi, GQSPI_SEL_OFST, GQSPI_SEL_MASK); 274 /* Clear and disable interrupts */ 275 zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST, 276 zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST) | 277 GQSPI_ISR_WR_TO_CLR_MASK); 278 /* Clear the DMA STS */ 279 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST, 280 zynqmp_gqspi_read(xqspi, 281 GQSPI_QSPIDMA_DST_I_STS_OFST)); 282 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_STS_OFST, 283 zynqmp_gqspi_read(xqspi, 284 GQSPI_QSPIDMA_DST_STS_OFST) | 285 GQSPI_QSPIDMA_DST_STS_WTC); 286 zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_IDR_ALL_MASK); 287 zynqmp_gqspi_write(xqspi, 288 GQSPI_QSPIDMA_DST_I_DIS_OFST, 289 GQSPI_QSPIDMA_DST_INTR_ALL_MASK); 290 /* Disable the GQSPI */ 291 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0); 292 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST); 293 config_reg &= ~GQSPI_CFG_MODE_EN_MASK; 294 /* Manual start */ 295 config_reg |= GQSPI_CFG_GEN_FIFO_START_MODE_MASK; 296 /* Little endian by default */ 297 config_reg &= ~GQSPI_CFG_ENDIAN_MASK; 298 /* Disable poll time out */ 299 config_reg &= ~GQSPI_CFG_EN_POLL_TO_MASK; 300 /* Set hold bit */ 301 config_reg |= GQSPI_CFG_WP_HOLD_MASK; 302 /* Clear pre-scalar by default */ 303 config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK; 304 /* CPHA 0 */ 305 config_reg &= ~GQSPI_CFG_CLK_PHA_MASK; 306 /* CPOL 0 */ 307 config_reg &= ~GQSPI_CFG_CLK_POL_MASK; 308 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg); 309 310 /* Clear the TX and RX FIFO */ 311 zynqmp_gqspi_write(xqspi, GQSPI_FIFO_CTRL_OFST, 312 GQSPI_FIFO_CTRL_RST_RX_FIFO_MASK | 313 GQSPI_FIFO_CTRL_RST_TX_FIFO_MASK | 314 GQSPI_FIFO_CTRL_RST_GEN_FIFO_MASK); 315 /* Set by default to allow for high frequencies */ 316 zynqmp_gqspi_write(xqspi, GQSPI_LPBK_DLY_ADJ_OFST, 317 zynqmp_gqspi_read(xqspi, GQSPI_LPBK_DLY_ADJ_OFST) | 318 GQSPI_LPBK_DLY_ADJ_USE_LPBK_MASK); 319 /* Reset thresholds */ 320 zynqmp_gqspi_write(xqspi, GQSPI_TX_THRESHOLD_OFST, 321 GQSPI_TX_FIFO_THRESHOLD_RESET_VAL); 322 zynqmp_gqspi_write(xqspi, GQSPI_RX_THRESHOLD_OFST, 323 GQSPI_RX_FIFO_THRESHOLD); 324 zynqmp_gqspi_write(xqspi, GQSPI_GF_THRESHOLD_OFST, 325 GQSPI_GEN_FIFO_THRESHOLD_RESET_VAL); 326 zynqmp_gqspi_selectslave(xqspi, 327 GQSPI_SELECT_FLASH_CS_LOWER, 328 GQSPI_SELECT_FLASH_BUS_LOWER); 329 /* Initialize DMA */ 330 zynqmp_gqspi_write(xqspi, 331 GQSPI_QSPIDMA_DST_CTRL_OFST, 332 GQSPI_QSPIDMA_DST_CTRL_RESET_VAL); 333 334 /* Enable the GQSPI */ 335 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK); 336 } 337 338 /** 339 * zynqmp_qspi_copy_read_data - Copy data to RX buffer 340 * @xqspi: Pointer to the zynqmp_qspi structure 341 * @data: The variable where data is stored 342 * @size: Number of bytes to be copied from data to RX buffer 343 */ 344 static void zynqmp_qspi_copy_read_data(struct zynqmp_qspi *xqspi, 345 ulong data, u8 size) 346 { 347 memcpy(xqspi->rxbuf, &data, size); 348 xqspi->rxbuf += size; 349 xqspi->bytes_to_receive -= size; 350 } 351 352 /** 353 * zynqmp_qspi_chipselect - Select or deselect the chip select line 354 * @qspi: Pointer to the spi_device structure 355 * @is_high: Select(0) or deselect (1) the chip select line 356 */ 357 static void zynqmp_qspi_chipselect(struct spi_device *qspi, bool is_high) 358 { 359 struct zynqmp_qspi *xqspi = spi_master_get_devdata(qspi->master); 360 ulong timeout; 361 u32 genfifoentry = 0, statusreg; 362 363 genfifoentry |= GQSPI_GENFIFO_MODE_SPI; 364 365 if (!is_high) { 366 xqspi->genfifobus = GQSPI_GENFIFO_BUS_LOWER; 367 xqspi->genfifocs = GQSPI_GENFIFO_CS_LOWER; 368 genfifoentry |= xqspi->genfifobus; 369 genfifoentry |= xqspi->genfifocs; 370 genfifoentry |= GQSPI_GENFIFO_CS_SETUP; 371 } else { 372 genfifoentry |= GQSPI_GENFIFO_CS_HOLD; 373 } 374 375 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry); 376 377 /* Manually start the generic FIFO command */ 378 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, 379 zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) | 380 GQSPI_CFG_START_GEN_FIFO_MASK); 381 382 timeout = jiffies + msecs_to_jiffies(1000); 383 384 /* Wait until the generic FIFO command is empty */ 385 do { 386 statusreg = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST); 387 388 if ((statusreg & GQSPI_ISR_GENFIFOEMPTY_MASK) && 389 (statusreg & GQSPI_ISR_TXEMPTY_MASK)) 390 break; 391 cpu_relax(); 392 } while (!time_after_eq(jiffies, timeout)); 393 394 if (time_after_eq(jiffies, timeout)) 395 dev_err(xqspi->dev, "Chip select timed out\n"); 396 } 397 398 /** 399 * zynqmp_qspi_selectspimode - Selects SPI mode - x1 or x2 or x4. 400 * @xqspi: xqspi is a pointer to the GQSPI instance 401 * @spimode: spimode - SPI or DUAL or QUAD. 402 * Return: Mask to set desired SPI mode in GENFIFO entry. 403 */ 404 static inline u32 zynqmp_qspi_selectspimode(struct zynqmp_qspi *xqspi, 405 u8 spimode) 406 { 407 u32 mask = 0; 408 409 switch (spimode) { 410 case GQSPI_SELECT_MODE_DUALSPI: 411 mask = GQSPI_GENFIFO_MODE_DUALSPI; 412 break; 413 case GQSPI_SELECT_MODE_QUADSPI: 414 mask = GQSPI_GENFIFO_MODE_QUADSPI; 415 break; 416 case GQSPI_SELECT_MODE_SPI: 417 mask = GQSPI_GENFIFO_MODE_SPI; 418 break; 419 default: 420 dev_warn(xqspi->dev, "Invalid SPI mode\n"); 421 } 422 423 return mask; 424 } 425 426 /** 427 * zynqmp_qspi_config_op - Configure QSPI controller for specified 428 * transfer 429 * @xqspi: Pointer to the zynqmp_qspi structure 430 * @qspi: Pointer to the spi_device structure 431 * 432 * Sets the operational mode of QSPI controller for the next QSPI transfer and 433 * sets the requested clock frequency. 434 * 435 * Return: Always 0 436 * 437 * Note: 438 * If the requested frequency is not an exact match with what can be 439 * obtained using the pre-scalar value, the driver sets the clock 440 * frequency which is lower than the requested frequency (maximum lower) 441 * for the transfer. 442 * 443 * If the requested frequency is higher or lower than that is supported 444 * by the QSPI controller the driver will set the highest or lowest 445 * frequency supported by controller. 446 */ 447 static int zynqmp_qspi_config_op(struct zynqmp_qspi *xqspi, 448 struct spi_device *qspi) 449 { 450 ulong clk_rate; 451 u32 config_reg, baud_rate_val = 0; 452 453 /* Set the clock frequency */ 454 /* If req_hz == 0, default to lowest speed */ 455 clk_rate = clk_get_rate(xqspi->refclk); 456 457 while ((baud_rate_val < GQSPI_BAUD_DIV_MAX) && 458 (clk_rate / 459 (GQSPI_BAUD_DIV_SHIFT << baud_rate_val)) > qspi->max_speed_hz) 460 baud_rate_val++; 461 462 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST); 463 464 /* Set the QSPI clock phase and clock polarity */ 465 config_reg &= (~GQSPI_CFG_CLK_PHA_MASK) & (~GQSPI_CFG_CLK_POL_MASK); 466 467 if (qspi->mode & SPI_CPHA) 468 config_reg |= GQSPI_CFG_CLK_PHA_MASK; 469 if (qspi->mode & SPI_CPOL) 470 config_reg |= GQSPI_CFG_CLK_POL_MASK; 471 472 config_reg &= ~GQSPI_CFG_BAUD_RATE_DIV_MASK; 473 config_reg |= (baud_rate_val << GQSPI_CFG_BAUD_RATE_DIV_SHIFT); 474 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg); 475 return 0; 476 } 477 478 /** 479 * zynqmp_qspi_setup_op - Configure the QSPI controller 480 * @qspi: Pointer to the spi_device structure 481 * 482 * Sets the operational mode of QSPI controller for the next QSPI transfer, 483 * baud rate and divisor value to setup the requested qspi clock. 484 * 485 * Return: 0 on success; error value otherwise. 486 */ 487 static int zynqmp_qspi_setup_op(struct spi_device *qspi) 488 { 489 struct spi_controller *ctlr = qspi->master; 490 struct zynqmp_qspi *xqspi = spi_controller_get_devdata(ctlr); 491 492 if (ctlr->busy) 493 return -EBUSY; 494 495 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK); 496 497 return 0; 498 } 499 500 /** 501 * zynqmp_qspi_filltxfifo - Fills the TX FIFO as long as there is room in 502 * the FIFO or the bytes required to be 503 * transmitted. 504 * @xqspi: Pointer to the zynqmp_qspi structure 505 * @size: Number of bytes to be copied from TX buffer to TX FIFO 506 */ 507 static void zynqmp_qspi_filltxfifo(struct zynqmp_qspi *xqspi, int size) 508 { 509 u32 count = 0, intermediate; 510 511 while ((xqspi->bytes_to_transfer > 0) && (count < size) && (xqspi->txbuf)) { 512 if (xqspi->bytes_to_transfer >= 4) { 513 memcpy(&intermediate, xqspi->txbuf, 4); 514 xqspi->txbuf += 4; 515 xqspi->bytes_to_transfer -= 4; 516 count += 4; 517 } else { 518 memcpy(&intermediate, xqspi->txbuf, 519 xqspi->bytes_to_transfer); 520 xqspi->txbuf += xqspi->bytes_to_transfer; 521 xqspi->bytes_to_transfer = 0; 522 count += xqspi->bytes_to_transfer; 523 } 524 zynqmp_gqspi_write(xqspi, GQSPI_TXD_OFST, intermediate); 525 } 526 } 527 528 /** 529 * zynqmp_qspi_readrxfifo - Fills the RX FIFO as long as there is room in 530 * the FIFO. 531 * @xqspi: Pointer to the zynqmp_qspi structure 532 * @size: Number of bytes to be copied from RX buffer to RX FIFO 533 */ 534 static void zynqmp_qspi_readrxfifo(struct zynqmp_qspi *xqspi, u32 size) 535 { 536 ulong data; 537 int count = 0; 538 539 while ((count < size) && (xqspi->bytes_to_receive > 0)) { 540 if (xqspi->bytes_to_receive >= 4) { 541 (*(u32 *)xqspi->rxbuf) = 542 zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST); 543 xqspi->rxbuf += 4; 544 xqspi->bytes_to_receive -= 4; 545 count += 4; 546 } else { 547 data = zynqmp_gqspi_read(xqspi, GQSPI_RXD_OFST); 548 count += xqspi->bytes_to_receive; 549 zynqmp_qspi_copy_read_data(xqspi, data, 550 xqspi->bytes_to_receive); 551 xqspi->bytes_to_receive = 0; 552 } 553 } 554 } 555 556 /** 557 * zynqmp_qspi_fillgenfifo - Fills the GENFIFO. 558 * @xqspi: Pointer to the zynqmp_qspi structure 559 * @nbits: Transfer/Receive buswidth. 560 * @genfifoentry: Variable in which GENFIFO mask is saved 561 */ 562 static void zynqmp_qspi_fillgenfifo(struct zynqmp_qspi *xqspi, u8 nbits, 563 u32 genfifoentry) 564 { 565 u32 transfer_len = 0; 566 567 if (xqspi->txbuf) { 568 genfifoentry &= ~GQSPI_GENFIFO_RX; 569 genfifoentry |= GQSPI_GENFIFO_DATA_XFER; 570 genfifoentry |= GQSPI_GENFIFO_TX; 571 transfer_len = xqspi->bytes_to_transfer; 572 } else if (xqspi->rxbuf) { 573 genfifoentry &= ~GQSPI_GENFIFO_TX; 574 genfifoentry |= GQSPI_GENFIFO_DATA_XFER; 575 genfifoentry |= GQSPI_GENFIFO_RX; 576 if (xqspi->mode == GQSPI_MODE_DMA) 577 transfer_len = xqspi->dma_rx_bytes; 578 else 579 transfer_len = xqspi->bytes_to_receive; 580 } else { 581 /* Sending dummy circles here */ 582 genfifoentry &= ~(GQSPI_GENFIFO_TX | GQSPI_GENFIFO_RX); 583 genfifoentry |= GQSPI_GENFIFO_DATA_XFER; 584 transfer_len = xqspi->bytes_to_transfer; 585 } 586 genfifoentry |= zynqmp_qspi_selectspimode(xqspi, nbits); 587 xqspi->genfifoentry = genfifoentry; 588 589 if ((transfer_len) < GQSPI_GENFIFO_IMM_DATA_MASK) { 590 genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK; 591 genfifoentry |= transfer_len; 592 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry); 593 } else { 594 int tempcount = transfer_len; 595 u32 exponent = 8; /* 2^8 = 256 */ 596 u8 imm_data = tempcount & 0xFF; 597 598 tempcount &= ~(tempcount & 0xFF); 599 /* Immediate entry */ 600 if (tempcount != 0) { 601 /* Exponent entries */ 602 genfifoentry |= GQSPI_GENFIFO_EXP; 603 while (tempcount != 0) { 604 if (tempcount & GQSPI_GENFIFO_EXP_START) { 605 genfifoentry &= 606 ~GQSPI_GENFIFO_IMM_DATA_MASK; 607 genfifoentry |= exponent; 608 zynqmp_gqspi_write(xqspi, 609 GQSPI_GEN_FIFO_OFST, 610 genfifoentry); 611 } 612 tempcount = tempcount >> 1; 613 exponent++; 614 } 615 } 616 if (imm_data != 0) { 617 genfifoentry &= ~GQSPI_GENFIFO_EXP; 618 genfifoentry &= ~GQSPI_GENFIFO_IMM_DATA_MASK; 619 genfifoentry |= (u8)(imm_data & 0xFF); 620 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 621 genfifoentry); 622 } 623 } 624 if (xqspi->mode == GQSPI_MODE_IO && xqspi->rxbuf) { 625 /* Dummy generic FIFO entry */ 626 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0); 627 } 628 } 629 630 /** 631 * zynqmp_process_dma_irq - Handler for DMA done interrupt of QSPI 632 * controller 633 * @xqspi: zynqmp_qspi instance pointer 634 * 635 * This function handles DMA interrupt only. 636 */ 637 static void zynqmp_process_dma_irq(struct zynqmp_qspi *xqspi) 638 { 639 u32 config_reg, genfifoentry; 640 641 dma_unmap_single(xqspi->dev, xqspi->dma_addr, 642 xqspi->dma_rx_bytes, DMA_FROM_DEVICE); 643 xqspi->rxbuf += xqspi->dma_rx_bytes; 644 xqspi->bytes_to_receive -= xqspi->dma_rx_bytes; 645 xqspi->dma_rx_bytes = 0; 646 647 /* Disabling the DMA interrupts */ 648 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_DIS_OFST, 649 GQSPI_QSPIDMA_DST_I_EN_DONE_MASK); 650 651 if (xqspi->bytes_to_receive > 0) { 652 /* Switch to IO mode,for remaining bytes to receive */ 653 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST); 654 config_reg &= ~GQSPI_CFG_MODE_EN_MASK; 655 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg); 656 657 /* Initiate the transfer of remaining bytes */ 658 genfifoentry = xqspi->genfifoentry; 659 genfifoentry |= xqspi->bytes_to_receive; 660 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, genfifoentry); 661 662 /* Dummy generic FIFO entry */ 663 zynqmp_gqspi_write(xqspi, GQSPI_GEN_FIFO_OFST, 0x0); 664 665 /* Manual start */ 666 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, 667 (zynqmp_gqspi_read(xqspi, 668 GQSPI_CONFIG_OFST) | 669 GQSPI_CFG_START_GEN_FIFO_MASK)); 670 671 /* Enable the RX interrupts for IO mode */ 672 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST, 673 GQSPI_IER_GENFIFOEMPTY_MASK | 674 GQSPI_IER_RXNEMPTY_MASK | 675 GQSPI_IER_RXEMPTY_MASK); 676 } 677 } 678 679 /** 680 * zynqmp_qspi_irq - Interrupt service routine of the QSPI controller 681 * @irq: IRQ number 682 * @dev_id: Pointer to the xqspi structure 683 * 684 * This function handles TX empty only. 685 * On TX empty interrupt this function reads the received data from RX FIFO 686 * and fills the TX FIFO if there is any data remaining to be transferred. 687 * 688 * Return: IRQ_HANDLED when interrupt is handled 689 * IRQ_NONE otherwise. 690 */ 691 static irqreturn_t zynqmp_qspi_irq(int irq, void *dev_id) 692 { 693 struct zynqmp_qspi *xqspi = (struct zynqmp_qspi *)dev_id; 694 irqreturn_t ret = IRQ_NONE; 695 u32 status, mask, dma_status = 0; 696 697 status = zynqmp_gqspi_read(xqspi, GQSPI_ISR_OFST); 698 zynqmp_gqspi_write(xqspi, GQSPI_ISR_OFST, status); 699 mask = (status & ~(zynqmp_gqspi_read(xqspi, GQSPI_IMASK_OFST))); 700 701 /* Read and clear DMA status */ 702 if (xqspi->mode == GQSPI_MODE_DMA) { 703 dma_status = 704 zynqmp_gqspi_read(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST); 705 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_I_STS_OFST, 706 dma_status); 707 } 708 709 if (mask & GQSPI_ISR_TXNOT_FULL_MASK) { 710 zynqmp_qspi_filltxfifo(xqspi, GQSPI_TX_FIFO_FILL); 711 ret = IRQ_HANDLED; 712 } 713 714 if (dma_status & GQSPI_QSPIDMA_DST_I_STS_DONE_MASK) { 715 zynqmp_process_dma_irq(xqspi); 716 ret = IRQ_HANDLED; 717 } else if (!(mask & GQSPI_IER_RXEMPTY_MASK) && 718 (mask & GQSPI_IER_GENFIFOEMPTY_MASK)) { 719 zynqmp_qspi_readrxfifo(xqspi, GQSPI_RX_FIFO_FILL); 720 ret = IRQ_HANDLED; 721 } 722 723 if (xqspi->bytes_to_receive == 0 && xqspi->bytes_to_transfer == 0 && 724 ((status & GQSPI_IRQ_MASK) == GQSPI_IRQ_MASK)) { 725 zynqmp_gqspi_write(xqspi, GQSPI_IDR_OFST, GQSPI_ISR_IDR_MASK); 726 complete(&xqspi->data_completion); 727 ret = IRQ_HANDLED; 728 } 729 return ret; 730 } 731 732 /** 733 * zynqmp_qspi_setuprxdma - This function sets up the RX DMA operation 734 * @xqspi: xqspi is a pointer to the GQSPI instance. 735 */ 736 static int zynqmp_qspi_setuprxdma(struct zynqmp_qspi *xqspi) 737 { 738 u32 rx_bytes, rx_rem, config_reg; 739 dma_addr_t addr; 740 u64 dma_align = (u64)(uintptr_t)xqspi->rxbuf; 741 742 if (xqspi->bytes_to_receive < 8 || 743 ((dma_align & GQSPI_DMA_UNALIGN) != 0x0)) { 744 /* Setting to IO mode */ 745 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST); 746 config_reg &= ~GQSPI_CFG_MODE_EN_MASK; 747 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg); 748 xqspi->mode = GQSPI_MODE_IO; 749 xqspi->dma_rx_bytes = 0; 750 return 0; 751 } 752 753 rx_rem = xqspi->bytes_to_receive % 4; 754 rx_bytes = (xqspi->bytes_to_receive - rx_rem); 755 756 addr = dma_map_single(xqspi->dev, (void *)xqspi->rxbuf, 757 rx_bytes, DMA_FROM_DEVICE); 758 if (dma_mapping_error(xqspi->dev, addr)) { 759 dev_err(xqspi->dev, "ERR:rxdma:memory not mapped\n"); 760 return -ENOMEM; 761 } 762 763 xqspi->dma_rx_bytes = rx_bytes; 764 xqspi->dma_addr = addr; 765 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_OFST, 766 (u32)(addr & 0xffffffff)); 767 addr = ((addr >> 16) >> 16); 768 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_ADDR_MSB_OFST, 769 ((u32)addr) & 0xfff); 770 771 /* Enabling the DMA mode */ 772 config_reg = zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST); 773 config_reg &= ~GQSPI_CFG_MODE_EN_MASK; 774 config_reg |= GQSPI_CFG_MODE_EN_DMA_MASK; 775 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, config_reg); 776 777 /* Switch to DMA mode */ 778 xqspi->mode = GQSPI_MODE_DMA; 779 780 /* Write the number of bytes to transfer */ 781 zynqmp_gqspi_write(xqspi, GQSPI_QSPIDMA_DST_SIZE_OFST, rx_bytes); 782 783 return 0; 784 } 785 786 /** 787 * zynqmp_qspi_write_op - This function sets up the GENFIFO entries, 788 * TX FIFO, and fills the TX FIFO with as many 789 * bytes as possible. 790 * @xqspi: Pointer to the GQSPI instance. 791 * @tx_nbits: Transfer buswidth. 792 * @genfifoentry: Variable in which GENFIFO mask is returned 793 * to calling function 794 */ 795 static void zynqmp_qspi_write_op(struct zynqmp_qspi *xqspi, u8 tx_nbits, 796 u32 genfifoentry) 797 { 798 u32 config_reg; 799 800 zynqmp_qspi_fillgenfifo(xqspi, tx_nbits, genfifoentry); 801 zynqmp_qspi_filltxfifo(xqspi, GQSPI_TXD_DEPTH); 802 if (xqspi->mode == GQSPI_MODE_DMA) { 803 config_reg = zynqmp_gqspi_read(xqspi, 804 GQSPI_CONFIG_OFST); 805 config_reg &= ~GQSPI_CFG_MODE_EN_MASK; 806 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, 807 config_reg); 808 xqspi->mode = GQSPI_MODE_IO; 809 } 810 } 811 812 /** 813 * zynqmp_qspi_read_op - This function sets up the GENFIFO entries and 814 * RX DMA operation. 815 * @xqspi: xqspi is a pointer to the GQSPI instance. 816 * @rx_nbits: Receive buswidth. 817 * @genfifoentry: genfifoentry is pointer to the variable in which 818 * GENFIFO mask is returned to calling function 819 */ 820 static int zynqmp_qspi_read_op(struct zynqmp_qspi *xqspi, u8 rx_nbits, 821 u32 genfifoentry) 822 { 823 int ret; 824 825 ret = zynqmp_qspi_setuprxdma(xqspi); 826 if (ret) 827 return ret; 828 zynqmp_qspi_fillgenfifo(xqspi, rx_nbits, genfifoentry); 829 830 return 0; 831 } 832 833 /** 834 * zynqmp_qspi_suspend - Suspend method for the QSPI driver 835 * @dev: Address of the platform_device structure 836 * 837 * This function stops the QSPI driver queue and disables the QSPI controller 838 * 839 * Return: Always 0 840 */ 841 static int __maybe_unused zynqmp_qspi_suspend(struct device *dev) 842 { 843 struct zynqmp_qspi *xqspi = dev_get_drvdata(dev); 844 struct spi_controller *ctlr = xqspi->ctlr; 845 int ret; 846 847 ret = spi_controller_suspend(ctlr); 848 if (ret) 849 return ret; 850 851 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0); 852 853 return 0; 854 } 855 856 /** 857 * zynqmp_qspi_resume - Resume method for the QSPI driver 858 * @dev: Address of the platform_device structure 859 * 860 * The function starts the QSPI driver queue and initializes the QSPI 861 * controller 862 * 863 * Return: 0 on success; error value otherwise 864 */ 865 static int __maybe_unused zynqmp_qspi_resume(struct device *dev) 866 { 867 struct zynqmp_qspi *xqspi = dev_get_drvdata(dev); 868 struct spi_controller *ctlr = xqspi->ctlr; 869 870 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, GQSPI_EN_MASK); 871 872 spi_controller_resume(ctlr); 873 874 return 0; 875 } 876 877 /** 878 * zynqmp_runtime_suspend - Runtime suspend method for the SPI driver 879 * @dev: Address of the platform_device structure 880 * 881 * This function disables the clocks 882 * 883 * Return: Always 0 884 */ 885 static int __maybe_unused zynqmp_runtime_suspend(struct device *dev) 886 { 887 struct zynqmp_qspi *xqspi = dev_get_drvdata(dev); 888 889 clk_disable_unprepare(xqspi->refclk); 890 clk_disable_unprepare(xqspi->pclk); 891 892 return 0; 893 } 894 895 /** 896 * zynqmp_runtime_resume - Runtime resume method for the SPI driver 897 * @dev: Address of the platform_device structure 898 * 899 * This function enables the clocks 900 * 901 * Return: 0 on success and error value on error 902 */ 903 static int __maybe_unused zynqmp_runtime_resume(struct device *dev) 904 { 905 struct zynqmp_qspi *xqspi = dev_get_drvdata(dev); 906 int ret; 907 908 ret = clk_prepare_enable(xqspi->pclk); 909 if (ret) { 910 dev_err(dev, "Cannot enable APB clock.\n"); 911 return ret; 912 } 913 914 ret = clk_prepare_enable(xqspi->refclk); 915 if (ret) { 916 dev_err(dev, "Cannot enable device clock.\n"); 917 clk_disable_unprepare(xqspi->pclk); 918 return ret; 919 } 920 921 return 0; 922 } 923 924 /** 925 * zynqmp_qspi_exec_op() - Initiates the QSPI transfer 926 * @mem: The SPI memory 927 * @op: The memory operation to execute 928 * 929 * Executes a memory operation. 930 * 931 * This function first selects the chip and starts the memory operation. 932 * 933 * Return: 0 in case of success, a negative error code otherwise. 934 */ 935 static int zynqmp_qspi_exec_op(struct spi_mem *mem, 936 const struct spi_mem_op *op) 937 { 938 struct zynqmp_qspi *xqspi = spi_controller_get_devdata 939 (mem->spi->master); 940 int err = 0, i; 941 u32 genfifoentry = 0; 942 u16 opcode = op->cmd.opcode; 943 u64 opaddr; 944 945 dev_dbg(xqspi->dev, "cmd:%#x mode:%d.%d.%d.%d\n", 946 op->cmd.opcode, op->cmd.buswidth, op->addr.buswidth, 947 op->dummy.buswidth, op->data.buswidth); 948 949 mutex_lock(&xqspi->op_lock); 950 zynqmp_qspi_config_op(xqspi, mem->spi); 951 zynqmp_qspi_chipselect(mem->spi, false); 952 genfifoentry |= xqspi->genfifocs; 953 genfifoentry |= xqspi->genfifobus; 954 955 if (op->cmd.opcode) { 956 reinit_completion(&xqspi->data_completion); 957 xqspi->txbuf = &opcode; 958 xqspi->rxbuf = NULL; 959 xqspi->bytes_to_transfer = op->cmd.nbytes; 960 xqspi->bytes_to_receive = 0; 961 zynqmp_qspi_write_op(xqspi, op->cmd.buswidth, genfifoentry); 962 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, 963 zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) | 964 GQSPI_CFG_START_GEN_FIFO_MASK); 965 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST, 966 GQSPI_IER_GENFIFOEMPTY_MASK | 967 GQSPI_IER_TXNOT_FULL_MASK); 968 if (!wait_for_completion_timeout 969 (&xqspi->data_completion, msecs_to_jiffies(1000))) { 970 err = -ETIMEDOUT; 971 goto return_err; 972 } 973 } 974 975 if (op->addr.nbytes) { 976 xqspi->txbuf = &opaddr; 977 for (i = 0; i < op->addr.nbytes; i++) { 978 *(((u8 *)xqspi->txbuf) + i) = op->addr.val >> 979 (8 * (op->addr.nbytes - i - 1)); 980 } 981 982 reinit_completion(&xqspi->data_completion); 983 xqspi->rxbuf = NULL; 984 xqspi->bytes_to_transfer = op->addr.nbytes; 985 xqspi->bytes_to_receive = 0; 986 zynqmp_qspi_write_op(xqspi, op->addr.buswidth, genfifoentry); 987 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, 988 zynqmp_gqspi_read(xqspi, 989 GQSPI_CONFIG_OFST) | 990 GQSPI_CFG_START_GEN_FIFO_MASK); 991 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST, 992 GQSPI_IER_TXEMPTY_MASK | 993 GQSPI_IER_GENFIFOEMPTY_MASK | 994 GQSPI_IER_TXNOT_FULL_MASK); 995 if (!wait_for_completion_timeout 996 (&xqspi->data_completion, msecs_to_jiffies(1000))) { 997 err = -ETIMEDOUT; 998 goto return_err; 999 } 1000 } 1001 1002 if (op->dummy.nbytes) { 1003 xqspi->txbuf = NULL; 1004 xqspi->rxbuf = NULL; 1005 /* 1006 * xqspi->bytes_to_transfer here represents the dummy circles 1007 * which need to be sent. 1008 */ 1009 xqspi->bytes_to_transfer = op->dummy.nbytes * 8 / op->dummy.buswidth; 1010 xqspi->bytes_to_receive = 0; 1011 /* 1012 * Using op->data.buswidth instead of op->dummy.buswidth here because 1013 * we need to use it to configure the correct SPI mode. 1014 */ 1015 zynqmp_qspi_write_op(xqspi, op->data.buswidth, 1016 genfifoentry); 1017 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, 1018 zynqmp_gqspi_read(xqspi, GQSPI_CONFIG_OFST) | 1019 GQSPI_CFG_START_GEN_FIFO_MASK); 1020 } 1021 1022 if (op->data.nbytes) { 1023 reinit_completion(&xqspi->data_completion); 1024 if (op->data.dir == SPI_MEM_DATA_OUT) { 1025 xqspi->txbuf = (u8 *)op->data.buf.out; 1026 xqspi->rxbuf = NULL; 1027 xqspi->bytes_to_transfer = op->data.nbytes; 1028 xqspi->bytes_to_receive = 0; 1029 zynqmp_qspi_write_op(xqspi, op->data.buswidth, 1030 genfifoentry); 1031 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, 1032 zynqmp_gqspi_read 1033 (xqspi, GQSPI_CONFIG_OFST) | 1034 GQSPI_CFG_START_GEN_FIFO_MASK); 1035 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST, 1036 GQSPI_IER_TXEMPTY_MASK | 1037 GQSPI_IER_GENFIFOEMPTY_MASK | 1038 GQSPI_IER_TXNOT_FULL_MASK); 1039 } else { 1040 xqspi->txbuf = NULL; 1041 xqspi->rxbuf = (u8 *)op->data.buf.in; 1042 xqspi->bytes_to_receive = op->data.nbytes; 1043 xqspi->bytes_to_transfer = 0; 1044 err = zynqmp_qspi_read_op(xqspi, op->data.buswidth, 1045 genfifoentry); 1046 if (err) 1047 goto return_err; 1048 1049 zynqmp_gqspi_write(xqspi, GQSPI_CONFIG_OFST, 1050 zynqmp_gqspi_read 1051 (xqspi, GQSPI_CONFIG_OFST) | 1052 GQSPI_CFG_START_GEN_FIFO_MASK); 1053 if (xqspi->mode == GQSPI_MODE_DMA) { 1054 zynqmp_gqspi_write 1055 (xqspi, GQSPI_QSPIDMA_DST_I_EN_OFST, 1056 GQSPI_QSPIDMA_DST_I_EN_DONE_MASK); 1057 } else { 1058 zynqmp_gqspi_write(xqspi, GQSPI_IER_OFST, 1059 GQSPI_IER_GENFIFOEMPTY_MASK | 1060 GQSPI_IER_RXNEMPTY_MASK | 1061 GQSPI_IER_RXEMPTY_MASK); 1062 } 1063 } 1064 if (!wait_for_completion_timeout 1065 (&xqspi->data_completion, msecs_to_jiffies(1000))) 1066 err = -ETIMEDOUT; 1067 } 1068 1069 return_err: 1070 1071 zynqmp_qspi_chipselect(mem->spi, true); 1072 mutex_unlock(&xqspi->op_lock); 1073 1074 return err; 1075 } 1076 1077 static const struct dev_pm_ops zynqmp_qspi_dev_pm_ops = { 1078 SET_RUNTIME_PM_OPS(zynqmp_runtime_suspend, 1079 zynqmp_runtime_resume, NULL) 1080 SET_SYSTEM_SLEEP_PM_OPS(zynqmp_qspi_suspend, zynqmp_qspi_resume) 1081 }; 1082 1083 static const struct spi_controller_mem_ops zynqmp_qspi_mem_ops = { 1084 .exec_op = zynqmp_qspi_exec_op, 1085 }; 1086 1087 /** 1088 * zynqmp_qspi_probe - Probe method for the QSPI driver 1089 * @pdev: Pointer to the platform_device structure 1090 * 1091 * This function initializes the driver data structures and the hardware. 1092 * 1093 * Return: 0 on success; error value otherwise 1094 */ 1095 static int zynqmp_qspi_probe(struct platform_device *pdev) 1096 { 1097 int ret = 0; 1098 struct spi_controller *ctlr; 1099 struct zynqmp_qspi *xqspi; 1100 struct device *dev = &pdev->dev; 1101 struct device_node *np = dev->of_node; 1102 1103 ctlr = spi_alloc_master(&pdev->dev, sizeof(*xqspi)); 1104 if (!ctlr) 1105 return -ENOMEM; 1106 1107 xqspi = spi_controller_get_devdata(ctlr); 1108 xqspi->dev = dev; 1109 xqspi->ctlr = ctlr; 1110 platform_set_drvdata(pdev, xqspi); 1111 1112 xqspi->regs = devm_platform_ioremap_resource(pdev, 0); 1113 if (IS_ERR(xqspi->regs)) { 1114 ret = PTR_ERR(xqspi->regs); 1115 goto remove_master; 1116 } 1117 1118 xqspi->pclk = devm_clk_get(&pdev->dev, "pclk"); 1119 if (IS_ERR(xqspi->pclk)) { 1120 dev_err(dev, "pclk clock not found.\n"); 1121 ret = PTR_ERR(xqspi->pclk); 1122 goto remove_master; 1123 } 1124 1125 xqspi->refclk = devm_clk_get(&pdev->dev, "ref_clk"); 1126 if (IS_ERR(xqspi->refclk)) { 1127 dev_err(dev, "ref_clk clock not found.\n"); 1128 ret = PTR_ERR(xqspi->refclk); 1129 goto remove_master; 1130 } 1131 1132 ret = clk_prepare_enable(xqspi->pclk); 1133 if (ret) { 1134 dev_err(dev, "Unable to enable APB clock.\n"); 1135 goto remove_master; 1136 } 1137 1138 ret = clk_prepare_enable(xqspi->refclk); 1139 if (ret) { 1140 dev_err(dev, "Unable to enable device clock.\n"); 1141 goto clk_dis_pclk; 1142 } 1143 1144 init_completion(&xqspi->data_completion); 1145 1146 mutex_init(&xqspi->op_lock); 1147 1148 pm_runtime_use_autosuspend(&pdev->dev); 1149 pm_runtime_set_autosuspend_delay(&pdev->dev, SPI_AUTOSUSPEND_TIMEOUT); 1150 pm_runtime_set_active(&pdev->dev); 1151 pm_runtime_enable(&pdev->dev); 1152 1153 ret = pm_runtime_get_sync(&pdev->dev); 1154 if (ret < 0) { 1155 dev_err(&pdev->dev, "Failed to pm_runtime_get_sync: %d\n", ret); 1156 goto clk_dis_all; 1157 } 1158 1159 /* QSPI controller initializations */ 1160 zynqmp_qspi_init_hw(xqspi); 1161 1162 xqspi->irq = platform_get_irq(pdev, 0); 1163 if (xqspi->irq <= 0) { 1164 ret = -ENXIO; 1165 goto clk_dis_all; 1166 } 1167 ret = devm_request_irq(&pdev->dev, xqspi->irq, zynqmp_qspi_irq, 1168 0, pdev->name, xqspi); 1169 if (ret != 0) { 1170 ret = -ENXIO; 1171 dev_err(dev, "request_irq failed\n"); 1172 goto clk_dis_all; 1173 } 1174 1175 dma_set_mask(&pdev->dev, DMA_BIT_MASK(44)); 1176 ctlr->bits_per_word_mask = SPI_BPW_MASK(8); 1177 ctlr->num_chipselect = GQSPI_DEFAULT_NUM_CS; 1178 ctlr->mem_ops = &zynqmp_qspi_mem_ops; 1179 ctlr->setup = zynqmp_qspi_setup_op; 1180 ctlr->max_speed_hz = clk_get_rate(xqspi->refclk) / 2; 1181 ctlr->bits_per_word_mask = SPI_BPW_MASK(8); 1182 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD | 1183 SPI_TX_DUAL | SPI_TX_QUAD; 1184 ctlr->dev.of_node = np; 1185 ctlr->auto_runtime_pm = true; 1186 1187 ret = devm_spi_register_controller(&pdev->dev, ctlr); 1188 if (ret) { 1189 dev_err(&pdev->dev, "spi_register_controller failed\n"); 1190 goto clk_dis_all; 1191 } 1192 1193 pm_runtime_mark_last_busy(&pdev->dev); 1194 pm_runtime_put_autosuspend(&pdev->dev); 1195 1196 return 0; 1197 1198 clk_dis_all: 1199 pm_runtime_put_sync(&pdev->dev); 1200 pm_runtime_set_suspended(&pdev->dev); 1201 pm_runtime_disable(&pdev->dev); 1202 clk_disable_unprepare(xqspi->refclk); 1203 clk_dis_pclk: 1204 clk_disable_unprepare(xqspi->pclk); 1205 remove_master: 1206 spi_controller_put(ctlr); 1207 1208 return ret; 1209 } 1210 1211 /** 1212 * zynqmp_qspi_remove - Remove method for the QSPI driver 1213 * @pdev: Pointer to the platform_device structure 1214 * 1215 * This function is called if a device is physically removed from the system or 1216 * if the driver module is being unloaded. It frees all resources allocated to 1217 * the device. 1218 * 1219 * Return: 0 Always 1220 */ 1221 static int zynqmp_qspi_remove(struct platform_device *pdev) 1222 { 1223 struct zynqmp_qspi *xqspi = platform_get_drvdata(pdev); 1224 1225 zynqmp_gqspi_write(xqspi, GQSPI_EN_OFST, 0x0); 1226 clk_disable_unprepare(xqspi->refclk); 1227 clk_disable_unprepare(xqspi->pclk); 1228 pm_runtime_set_suspended(&pdev->dev); 1229 pm_runtime_disable(&pdev->dev); 1230 1231 return 0; 1232 } 1233 1234 static const struct of_device_id zynqmp_qspi_of_match[] = { 1235 { .compatible = "xlnx,zynqmp-qspi-1.0", }, 1236 { /* End of table */ } 1237 }; 1238 1239 MODULE_DEVICE_TABLE(of, zynqmp_qspi_of_match); 1240 1241 static struct platform_driver zynqmp_qspi_driver = { 1242 .probe = zynqmp_qspi_probe, 1243 .remove = zynqmp_qspi_remove, 1244 .driver = { 1245 .name = "zynqmp-qspi", 1246 .of_match_table = zynqmp_qspi_of_match, 1247 .pm = &zynqmp_qspi_dev_pm_ops, 1248 }, 1249 }; 1250 1251 module_platform_driver(zynqmp_qspi_driver); 1252 1253 MODULE_AUTHOR("Xilinx, Inc."); 1254 MODULE_DESCRIPTION("Xilinx Zynqmp QSPI driver"); 1255 MODULE_LICENSE("GPL"); 1256