1 /* 2 * TI QSPI driver 3 * 4 * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com 5 * Author: Sourav Poddar <sourav.poddar@ti.com> 6 * 7 * This program is free software; you can redistribute it and/or 8 * modify it under the terms of the GPLv2. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/kernel.h> 17 #include <linux/init.h> 18 #include <linux/interrupt.h> 19 #include <linux/module.h> 20 #include <linux/device.h> 21 #include <linux/delay.h> 22 #include <linux/dma-mapping.h> 23 #include <linux/dmaengine.h> 24 #include <linux/omap-dma.h> 25 #include <linux/platform_device.h> 26 #include <linux/err.h> 27 #include <linux/clk.h> 28 #include <linux/io.h> 29 #include <linux/slab.h> 30 #include <linux/pm_runtime.h> 31 #include <linux/of.h> 32 #include <linux/of_device.h> 33 #include <linux/pinctrl/consumer.h> 34 #include <linux/mfd/syscon.h> 35 #include <linux/regmap.h> 36 37 #include <linux/spi/spi.h> 38 39 struct ti_qspi_regs { 40 u32 clkctrl; 41 }; 42 43 struct ti_qspi { 44 /* list synchronization */ 45 struct mutex list_lock; 46 47 struct spi_master *master; 48 void __iomem *base; 49 void __iomem *mmap_base; 50 struct regmap *ctrl_base; 51 unsigned int ctrl_reg; 52 struct clk *fclk; 53 struct device *dev; 54 55 struct ti_qspi_regs ctx_reg; 56 57 u32 spi_max_frequency; 58 u32 cmd; 59 u32 dc; 60 61 bool mmap_enabled; 62 }; 63 64 #define QSPI_PID (0x0) 65 #define QSPI_SYSCONFIG (0x10) 66 #define QSPI_SPI_CLOCK_CNTRL_REG (0x40) 67 #define QSPI_SPI_DC_REG (0x44) 68 #define QSPI_SPI_CMD_REG (0x48) 69 #define QSPI_SPI_STATUS_REG (0x4c) 70 #define QSPI_SPI_DATA_REG (0x50) 71 #define QSPI_SPI_SETUP_REG(n) ((0x54 + 4 * n)) 72 #define QSPI_SPI_SWITCH_REG (0x64) 73 #define QSPI_SPI_DATA_REG_1 (0x68) 74 #define QSPI_SPI_DATA_REG_2 (0x6c) 75 #define QSPI_SPI_DATA_REG_3 (0x70) 76 77 #define QSPI_COMPLETION_TIMEOUT msecs_to_jiffies(2000) 78 79 #define QSPI_FCLK 192000000 80 81 /* Clock Control */ 82 #define QSPI_CLK_EN (1 << 31) 83 #define QSPI_CLK_DIV_MAX 0xffff 84 85 /* Command */ 86 #define QSPI_EN_CS(n) (n << 28) 87 #define QSPI_WLEN(n) ((n - 1) << 19) 88 #define QSPI_3_PIN (1 << 18) 89 #define QSPI_RD_SNGL (1 << 16) 90 #define QSPI_WR_SNGL (2 << 16) 91 #define QSPI_RD_DUAL (3 << 16) 92 #define QSPI_RD_QUAD (7 << 16) 93 #define QSPI_INVAL (4 << 16) 94 #define QSPI_FLEN(n) ((n - 1) << 0) 95 #define QSPI_WLEN_MAX_BITS 128 96 #define QSPI_WLEN_MAX_BYTES 16 97 98 /* STATUS REGISTER */ 99 #define BUSY 0x01 100 #define WC 0x02 101 102 /* Device Control */ 103 #define QSPI_DD(m, n) (m << (3 + n * 8)) 104 #define QSPI_CKPHA(n) (1 << (2 + n * 8)) 105 #define QSPI_CSPOL(n) (1 << (1 + n * 8)) 106 #define QSPI_CKPOL(n) (1 << (n * 8)) 107 108 #define QSPI_FRAME 4096 109 110 #define QSPI_AUTOSUSPEND_TIMEOUT 2000 111 112 #define MEM_CS_EN(n) ((n + 1) << 8) 113 #define MEM_CS_MASK (7 << 8) 114 115 #define MM_SWITCH 0x1 116 117 #define QSPI_SETUP_RD_NORMAL (0x0 << 12) 118 #define QSPI_SETUP_RD_DUAL (0x1 << 12) 119 #define QSPI_SETUP_RD_QUAD (0x3 << 12) 120 #define QSPI_SETUP_ADDR_SHIFT 8 121 #define QSPI_SETUP_DUMMY_SHIFT 10 122 123 static inline unsigned long ti_qspi_read(struct ti_qspi *qspi, 124 unsigned long reg) 125 { 126 return readl(qspi->base + reg); 127 } 128 129 static inline void ti_qspi_write(struct ti_qspi *qspi, 130 unsigned long val, unsigned long reg) 131 { 132 writel(val, qspi->base + reg); 133 } 134 135 static int ti_qspi_setup(struct spi_device *spi) 136 { 137 struct ti_qspi *qspi = spi_master_get_devdata(spi->master); 138 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg; 139 int clk_div = 0, ret; 140 u32 clk_ctrl_reg, clk_rate, clk_mask; 141 142 if (spi->master->busy) { 143 dev_dbg(qspi->dev, "master busy doing other trasnfers\n"); 144 return -EBUSY; 145 } 146 147 if (!qspi->spi_max_frequency) { 148 dev_err(qspi->dev, "spi max frequency not defined\n"); 149 return -EINVAL; 150 } 151 152 clk_rate = clk_get_rate(qspi->fclk); 153 154 clk_div = DIV_ROUND_UP(clk_rate, qspi->spi_max_frequency) - 1; 155 156 if (clk_div < 0) { 157 dev_dbg(qspi->dev, "clock divider < 0, using /1 divider\n"); 158 return -EINVAL; 159 } 160 161 if (clk_div > QSPI_CLK_DIV_MAX) { 162 dev_dbg(qspi->dev, "clock divider >%d , using /%d divider\n", 163 QSPI_CLK_DIV_MAX, QSPI_CLK_DIV_MAX + 1); 164 return -EINVAL; 165 } 166 167 dev_dbg(qspi->dev, "hz: %d, clock divider %d\n", 168 qspi->spi_max_frequency, clk_div); 169 170 ret = pm_runtime_get_sync(qspi->dev); 171 if (ret < 0) { 172 dev_err(qspi->dev, "pm_runtime_get_sync() failed\n"); 173 return ret; 174 } 175 176 clk_ctrl_reg = ti_qspi_read(qspi, QSPI_SPI_CLOCK_CNTRL_REG); 177 178 clk_ctrl_reg &= ~QSPI_CLK_EN; 179 180 /* disable SCLK */ 181 ti_qspi_write(qspi, clk_ctrl_reg, QSPI_SPI_CLOCK_CNTRL_REG); 182 183 /* enable SCLK */ 184 clk_mask = QSPI_CLK_EN | clk_div; 185 ti_qspi_write(qspi, clk_mask, QSPI_SPI_CLOCK_CNTRL_REG); 186 ctx_reg->clkctrl = clk_mask; 187 188 pm_runtime_mark_last_busy(qspi->dev); 189 ret = pm_runtime_put_autosuspend(qspi->dev); 190 if (ret < 0) { 191 dev_err(qspi->dev, "pm_runtime_put_autosuspend() failed\n"); 192 return ret; 193 } 194 195 return 0; 196 } 197 198 static void ti_qspi_restore_ctx(struct ti_qspi *qspi) 199 { 200 struct ti_qspi_regs *ctx_reg = &qspi->ctx_reg; 201 202 ti_qspi_write(qspi, ctx_reg->clkctrl, QSPI_SPI_CLOCK_CNTRL_REG); 203 } 204 205 static inline u32 qspi_is_busy(struct ti_qspi *qspi) 206 { 207 u32 stat; 208 unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT; 209 210 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); 211 while ((stat & BUSY) && time_after(timeout, jiffies)) { 212 cpu_relax(); 213 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); 214 } 215 216 WARN(stat & BUSY, "qspi busy\n"); 217 return stat & BUSY; 218 } 219 220 static inline int ti_qspi_poll_wc(struct ti_qspi *qspi) 221 { 222 u32 stat; 223 unsigned long timeout = jiffies + QSPI_COMPLETION_TIMEOUT; 224 225 do { 226 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); 227 if (stat & WC) 228 return 0; 229 cpu_relax(); 230 } while (time_after(timeout, jiffies)); 231 232 stat = ti_qspi_read(qspi, QSPI_SPI_STATUS_REG); 233 if (stat & WC) 234 return 0; 235 return -ETIMEDOUT; 236 } 237 238 static int qspi_write_msg(struct ti_qspi *qspi, struct spi_transfer *t) 239 { 240 int wlen, count, xfer_len; 241 unsigned int cmd; 242 const u8 *txbuf; 243 u32 data; 244 245 txbuf = t->tx_buf; 246 cmd = qspi->cmd | QSPI_WR_SNGL; 247 count = t->len; 248 wlen = t->bits_per_word >> 3; /* in bytes */ 249 xfer_len = wlen; 250 251 while (count) { 252 if (qspi_is_busy(qspi)) 253 return -EBUSY; 254 255 switch (wlen) { 256 case 1: 257 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %02x\n", 258 cmd, qspi->dc, *txbuf); 259 if (count >= QSPI_WLEN_MAX_BYTES) { 260 u32 *txp = (u32 *)txbuf; 261 262 data = cpu_to_be32(*txp++); 263 writel(data, qspi->base + 264 QSPI_SPI_DATA_REG_3); 265 data = cpu_to_be32(*txp++); 266 writel(data, qspi->base + 267 QSPI_SPI_DATA_REG_2); 268 data = cpu_to_be32(*txp++); 269 writel(data, qspi->base + 270 QSPI_SPI_DATA_REG_1); 271 data = cpu_to_be32(*txp++); 272 writel(data, qspi->base + 273 QSPI_SPI_DATA_REG); 274 xfer_len = QSPI_WLEN_MAX_BYTES; 275 cmd |= QSPI_WLEN(QSPI_WLEN_MAX_BITS); 276 } else { 277 writeb(*txbuf, qspi->base + QSPI_SPI_DATA_REG); 278 cmd = qspi->cmd | QSPI_WR_SNGL; 279 xfer_len = wlen; 280 cmd |= QSPI_WLEN(wlen); 281 } 282 break; 283 case 2: 284 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %04x\n", 285 cmd, qspi->dc, *txbuf); 286 writew(*((u16 *)txbuf), qspi->base + QSPI_SPI_DATA_REG); 287 break; 288 case 4: 289 dev_dbg(qspi->dev, "tx cmd %08x dc %08x data %08x\n", 290 cmd, qspi->dc, *txbuf); 291 writel(*((u32 *)txbuf), qspi->base + QSPI_SPI_DATA_REG); 292 break; 293 } 294 295 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG); 296 if (ti_qspi_poll_wc(qspi)) { 297 dev_err(qspi->dev, "write timed out\n"); 298 return -ETIMEDOUT; 299 } 300 txbuf += xfer_len; 301 count -= xfer_len; 302 } 303 304 return 0; 305 } 306 307 static int qspi_read_msg(struct ti_qspi *qspi, struct spi_transfer *t) 308 { 309 int wlen, count; 310 unsigned int cmd; 311 u8 *rxbuf; 312 313 rxbuf = t->rx_buf; 314 cmd = qspi->cmd; 315 switch (t->rx_nbits) { 316 case SPI_NBITS_DUAL: 317 cmd |= QSPI_RD_DUAL; 318 break; 319 case SPI_NBITS_QUAD: 320 cmd |= QSPI_RD_QUAD; 321 break; 322 default: 323 cmd |= QSPI_RD_SNGL; 324 break; 325 } 326 count = t->len; 327 wlen = t->bits_per_word >> 3; /* in bytes */ 328 329 while (count) { 330 dev_dbg(qspi->dev, "rx cmd %08x dc %08x\n", cmd, qspi->dc); 331 if (qspi_is_busy(qspi)) 332 return -EBUSY; 333 334 ti_qspi_write(qspi, cmd, QSPI_SPI_CMD_REG); 335 if (ti_qspi_poll_wc(qspi)) { 336 dev_err(qspi->dev, "read timed out\n"); 337 return -ETIMEDOUT; 338 } 339 switch (wlen) { 340 case 1: 341 *rxbuf = readb(qspi->base + QSPI_SPI_DATA_REG); 342 break; 343 case 2: 344 *((u16 *)rxbuf) = readw(qspi->base + QSPI_SPI_DATA_REG); 345 break; 346 case 4: 347 *((u32 *)rxbuf) = readl(qspi->base + QSPI_SPI_DATA_REG); 348 break; 349 } 350 rxbuf += wlen; 351 count -= wlen; 352 } 353 354 return 0; 355 } 356 357 static int qspi_transfer_msg(struct ti_qspi *qspi, struct spi_transfer *t) 358 { 359 int ret; 360 361 if (t->tx_buf) { 362 ret = qspi_write_msg(qspi, t); 363 if (ret) { 364 dev_dbg(qspi->dev, "Error while writing\n"); 365 return ret; 366 } 367 } 368 369 if (t->rx_buf) { 370 ret = qspi_read_msg(qspi, t); 371 if (ret) { 372 dev_dbg(qspi->dev, "Error while reading\n"); 373 return ret; 374 } 375 } 376 377 return 0; 378 } 379 380 static void ti_qspi_enable_memory_map(struct spi_device *spi) 381 { 382 struct ti_qspi *qspi = spi_master_get_devdata(spi->master); 383 384 ti_qspi_write(qspi, MM_SWITCH, QSPI_SPI_SWITCH_REG); 385 if (qspi->ctrl_base) { 386 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg, 387 MEM_CS_EN(spi->chip_select), 388 MEM_CS_MASK); 389 } 390 qspi->mmap_enabled = true; 391 } 392 393 static void ti_qspi_disable_memory_map(struct spi_device *spi) 394 { 395 struct ti_qspi *qspi = spi_master_get_devdata(spi->master); 396 397 ti_qspi_write(qspi, 0, QSPI_SPI_SWITCH_REG); 398 if (qspi->ctrl_base) 399 regmap_update_bits(qspi->ctrl_base, qspi->ctrl_reg, 400 0, MEM_CS_MASK); 401 qspi->mmap_enabled = false; 402 } 403 404 static void ti_qspi_setup_mmap_read(struct spi_device *spi, 405 struct spi_flash_read_message *msg) 406 { 407 struct ti_qspi *qspi = spi_master_get_devdata(spi->master); 408 u32 memval = msg->read_opcode; 409 410 switch (msg->data_nbits) { 411 case SPI_NBITS_QUAD: 412 memval |= QSPI_SETUP_RD_QUAD; 413 break; 414 case SPI_NBITS_DUAL: 415 memval |= QSPI_SETUP_RD_DUAL; 416 break; 417 default: 418 memval |= QSPI_SETUP_RD_NORMAL; 419 break; 420 } 421 memval |= ((msg->addr_width - 1) << QSPI_SETUP_ADDR_SHIFT | 422 msg->dummy_bytes << QSPI_SETUP_DUMMY_SHIFT); 423 ti_qspi_write(qspi, memval, 424 QSPI_SPI_SETUP_REG(spi->chip_select)); 425 } 426 427 static int ti_qspi_spi_flash_read(struct spi_device *spi, 428 struct spi_flash_read_message *msg) 429 { 430 struct ti_qspi *qspi = spi_master_get_devdata(spi->master); 431 int ret = 0; 432 433 mutex_lock(&qspi->list_lock); 434 435 if (!qspi->mmap_enabled) 436 ti_qspi_enable_memory_map(spi); 437 ti_qspi_setup_mmap_read(spi, msg); 438 memcpy_fromio(msg->buf, qspi->mmap_base + msg->from, msg->len); 439 msg->retlen = msg->len; 440 441 mutex_unlock(&qspi->list_lock); 442 443 return ret; 444 } 445 446 static int ti_qspi_start_transfer_one(struct spi_master *master, 447 struct spi_message *m) 448 { 449 struct ti_qspi *qspi = spi_master_get_devdata(master); 450 struct spi_device *spi = m->spi; 451 struct spi_transfer *t; 452 int status = 0, ret; 453 int frame_length; 454 455 /* setup device control reg */ 456 qspi->dc = 0; 457 458 if (spi->mode & SPI_CPHA) 459 qspi->dc |= QSPI_CKPHA(spi->chip_select); 460 if (spi->mode & SPI_CPOL) 461 qspi->dc |= QSPI_CKPOL(spi->chip_select); 462 if (spi->mode & SPI_CS_HIGH) 463 qspi->dc |= QSPI_CSPOL(spi->chip_select); 464 465 frame_length = (m->frame_length << 3) / spi->bits_per_word; 466 467 frame_length = clamp(frame_length, 0, QSPI_FRAME); 468 469 /* setup command reg */ 470 qspi->cmd = 0; 471 qspi->cmd |= QSPI_EN_CS(spi->chip_select); 472 qspi->cmd |= QSPI_FLEN(frame_length); 473 474 ti_qspi_write(qspi, qspi->dc, QSPI_SPI_DC_REG); 475 476 mutex_lock(&qspi->list_lock); 477 478 if (qspi->mmap_enabled) 479 ti_qspi_disable_memory_map(spi); 480 481 list_for_each_entry(t, &m->transfers, transfer_list) { 482 qspi->cmd |= QSPI_WLEN(t->bits_per_word); 483 484 ret = qspi_transfer_msg(qspi, t); 485 if (ret) { 486 dev_dbg(qspi->dev, "transfer message failed\n"); 487 mutex_unlock(&qspi->list_lock); 488 return -EINVAL; 489 } 490 491 m->actual_length += t->len; 492 } 493 494 mutex_unlock(&qspi->list_lock); 495 496 ti_qspi_write(qspi, qspi->cmd | QSPI_INVAL, QSPI_SPI_CMD_REG); 497 m->status = status; 498 spi_finalize_current_message(master); 499 500 return status; 501 } 502 503 static int ti_qspi_runtime_resume(struct device *dev) 504 { 505 struct ti_qspi *qspi; 506 507 qspi = dev_get_drvdata(dev); 508 ti_qspi_restore_ctx(qspi); 509 510 return 0; 511 } 512 513 static const struct of_device_id ti_qspi_match[] = { 514 {.compatible = "ti,dra7xxx-qspi" }, 515 {.compatible = "ti,am4372-qspi" }, 516 {}, 517 }; 518 MODULE_DEVICE_TABLE(of, ti_qspi_match); 519 520 static int ti_qspi_probe(struct platform_device *pdev) 521 { 522 struct ti_qspi *qspi; 523 struct spi_master *master; 524 struct resource *r, *res_mmap; 525 struct device_node *np = pdev->dev.of_node; 526 u32 max_freq; 527 int ret = 0, num_cs, irq; 528 529 master = spi_alloc_master(&pdev->dev, sizeof(*qspi)); 530 if (!master) 531 return -ENOMEM; 532 533 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_RX_DUAL | SPI_RX_QUAD; 534 535 master->flags = SPI_MASTER_HALF_DUPLEX; 536 master->setup = ti_qspi_setup; 537 master->auto_runtime_pm = true; 538 master->transfer_one_message = ti_qspi_start_transfer_one; 539 master->dev.of_node = pdev->dev.of_node; 540 master->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | 541 SPI_BPW_MASK(8); 542 543 if (!of_property_read_u32(np, "num-cs", &num_cs)) 544 master->num_chipselect = num_cs; 545 546 qspi = spi_master_get_devdata(master); 547 qspi->master = master; 548 qspi->dev = &pdev->dev; 549 platform_set_drvdata(pdev, qspi); 550 551 r = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qspi_base"); 552 if (r == NULL) { 553 r = platform_get_resource(pdev, IORESOURCE_MEM, 0); 554 if (r == NULL) { 555 dev_err(&pdev->dev, "missing platform data\n"); 556 return -ENODEV; 557 } 558 } 559 560 res_mmap = platform_get_resource_byname(pdev, 561 IORESOURCE_MEM, "qspi_mmap"); 562 if (res_mmap == NULL) { 563 res_mmap = platform_get_resource(pdev, IORESOURCE_MEM, 1); 564 if (res_mmap == NULL) { 565 dev_err(&pdev->dev, 566 "memory mapped resource not required\n"); 567 } 568 } 569 570 irq = platform_get_irq(pdev, 0); 571 if (irq < 0) { 572 dev_err(&pdev->dev, "no irq resource?\n"); 573 return irq; 574 } 575 576 mutex_init(&qspi->list_lock); 577 578 qspi->base = devm_ioremap_resource(&pdev->dev, r); 579 if (IS_ERR(qspi->base)) { 580 ret = PTR_ERR(qspi->base); 581 goto free_master; 582 } 583 584 if (res_mmap) { 585 qspi->mmap_base = devm_ioremap_resource(&pdev->dev, 586 res_mmap); 587 master->spi_flash_read = ti_qspi_spi_flash_read; 588 if (IS_ERR(qspi->mmap_base)) { 589 dev_err(&pdev->dev, 590 "falling back to PIO mode\n"); 591 master->spi_flash_read = NULL; 592 } 593 } 594 qspi->mmap_enabled = false; 595 596 if (of_property_read_bool(np, "syscon-chipselects")) { 597 qspi->ctrl_base = 598 syscon_regmap_lookup_by_phandle(np, 599 "syscon-chipselects"); 600 if (IS_ERR(qspi->ctrl_base)) 601 return PTR_ERR(qspi->ctrl_base); 602 ret = of_property_read_u32_index(np, 603 "syscon-chipselects", 604 1, &qspi->ctrl_reg); 605 if (ret) { 606 dev_err(&pdev->dev, 607 "couldn't get ctrl_mod reg index\n"); 608 return ret; 609 } 610 } 611 612 qspi->fclk = devm_clk_get(&pdev->dev, "fck"); 613 if (IS_ERR(qspi->fclk)) { 614 ret = PTR_ERR(qspi->fclk); 615 dev_err(&pdev->dev, "could not get clk: %d\n", ret); 616 } 617 618 pm_runtime_use_autosuspend(&pdev->dev); 619 pm_runtime_set_autosuspend_delay(&pdev->dev, QSPI_AUTOSUSPEND_TIMEOUT); 620 pm_runtime_enable(&pdev->dev); 621 622 if (!of_property_read_u32(np, "spi-max-frequency", &max_freq)) 623 qspi->spi_max_frequency = max_freq; 624 625 ret = devm_spi_register_master(&pdev->dev, master); 626 if (ret) 627 goto free_master; 628 629 return 0; 630 631 free_master: 632 spi_master_put(master); 633 return ret; 634 } 635 636 static int ti_qspi_remove(struct platform_device *pdev) 637 { 638 pm_runtime_put_sync(&pdev->dev); 639 pm_runtime_disable(&pdev->dev); 640 641 return 0; 642 } 643 644 static const struct dev_pm_ops ti_qspi_pm_ops = { 645 .runtime_resume = ti_qspi_runtime_resume, 646 }; 647 648 static struct platform_driver ti_qspi_driver = { 649 .probe = ti_qspi_probe, 650 .remove = ti_qspi_remove, 651 .driver = { 652 .name = "ti-qspi", 653 .pm = &ti_qspi_pm_ops, 654 .of_match_table = ti_qspi_match, 655 } 656 }; 657 658 module_platform_driver(ti_qspi_driver); 659 660 MODULE_AUTHOR("Sourav Poddar <sourav.poddar@ti.com>"); 661 MODULE_LICENSE("GPL v2"); 662 MODULE_DESCRIPTION("TI QSPI controller driver"); 663 MODULE_ALIAS("platform:ti-qspi"); 664