1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * SPI driver for Nvidia's Tegra20/Tegra30 SLINK Controller. 4 * 5 * Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved. 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/completion.h> 10 #include <linux/delay.h> 11 #include <linux/dmaengine.h> 12 #include <linux/dma-mapping.h> 13 #include <linux/dmapool.h> 14 #include <linux/err.h> 15 #include <linux/interrupt.h> 16 #include <linux/io.h> 17 #include <linux/kernel.h> 18 #include <linux/kthread.h> 19 #include <linux/module.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_opp.h> 22 #include <linux/pm_runtime.h> 23 #include <linux/of.h> 24 #include <linux/reset.h> 25 #include <linux/spi/spi.h> 26 27 #include <soc/tegra/common.h> 28 29 #define SLINK_COMMAND 0x000 30 #define SLINK_BIT_LENGTH(x) (((x) & 0x1f) << 0) 31 #define SLINK_WORD_SIZE(x) (((x) & 0x1f) << 5) 32 #define SLINK_BOTH_EN (1 << 10) 33 #define SLINK_CS_SW (1 << 11) 34 #define SLINK_CS_VALUE (1 << 12) 35 #define SLINK_CS_POLARITY (1 << 13) 36 #define SLINK_IDLE_SDA_DRIVE_LOW (0 << 16) 37 #define SLINK_IDLE_SDA_DRIVE_HIGH (1 << 16) 38 #define SLINK_IDLE_SDA_PULL_LOW (2 << 16) 39 #define SLINK_IDLE_SDA_PULL_HIGH (3 << 16) 40 #define SLINK_IDLE_SDA_MASK (3 << 16) 41 #define SLINK_CS_POLARITY1 (1 << 20) 42 #define SLINK_CK_SDA (1 << 21) 43 #define SLINK_CS_POLARITY2 (1 << 22) 44 #define SLINK_CS_POLARITY3 (1 << 23) 45 #define SLINK_IDLE_SCLK_DRIVE_LOW (0 << 24) 46 #define SLINK_IDLE_SCLK_DRIVE_HIGH (1 << 24) 47 #define SLINK_IDLE_SCLK_PULL_LOW (2 << 24) 48 #define SLINK_IDLE_SCLK_PULL_HIGH (3 << 24) 49 #define SLINK_IDLE_SCLK_MASK (3 << 24) 50 #define SLINK_M_S (1 << 28) 51 #define SLINK_WAIT (1 << 29) 52 #define SLINK_GO (1 << 30) 53 #define SLINK_ENB (1 << 31) 54 55 #define SLINK_MODES (SLINK_IDLE_SCLK_MASK | SLINK_CK_SDA) 56 57 #define SLINK_COMMAND2 0x004 58 #define SLINK_LSBFE (1 << 0) 59 #define SLINK_SSOE (1 << 1) 60 #define SLINK_SPIE (1 << 4) 61 #define SLINK_BIDIROE (1 << 6) 62 #define SLINK_MODFEN (1 << 7) 63 #define SLINK_INT_SIZE(x) (((x) & 0x1f) << 8) 64 #define SLINK_CS_ACTIVE_BETWEEN (1 << 17) 65 #define SLINK_SS_EN_CS(x) (((x) & 0x3) << 18) 66 #define SLINK_SS_SETUP(x) (((x) & 0x3) << 20) 67 #define SLINK_FIFO_REFILLS_0 (0 << 22) 68 #define SLINK_FIFO_REFILLS_1 (1 << 22) 69 #define SLINK_FIFO_REFILLS_2 (2 << 22) 70 #define SLINK_FIFO_REFILLS_3 (3 << 22) 71 #define SLINK_FIFO_REFILLS_MASK (3 << 22) 72 #define SLINK_WAIT_PACK_INT(x) (((x) & 0x7) << 26) 73 #define SLINK_SPC0 (1 << 29) 74 #define SLINK_TXEN (1 << 30) 75 #define SLINK_RXEN (1 << 31) 76 77 #define SLINK_STATUS 0x008 78 #define SLINK_COUNT(val) (((val) >> 0) & 0x1f) 79 #define SLINK_WORD(val) (((val) >> 5) & 0x1f) 80 #define SLINK_BLK_CNT(val) (((val) >> 0) & 0xffff) 81 #define SLINK_MODF (1 << 16) 82 #define SLINK_RX_UNF (1 << 18) 83 #define SLINK_TX_OVF (1 << 19) 84 #define SLINK_TX_FULL (1 << 20) 85 #define SLINK_TX_EMPTY (1 << 21) 86 #define SLINK_RX_FULL (1 << 22) 87 #define SLINK_RX_EMPTY (1 << 23) 88 #define SLINK_TX_UNF (1 << 24) 89 #define SLINK_RX_OVF (1 << 25) 90 #define SLINK_TX_FLUSH (1 << 26) 91 #define SLINK_RX_FLUSH (1 << 27) 92 #define SLINK_SCLK (1 << 28) 93 #define SLINK_ERR (1 << 29) 94 #define SLINK_RDY (1 << 30) 95 #define SLINK_BSY (1 << 31) 96 #define SLINK_FIFO_ERROR (SLINK_TX_OVF | SLINK_RX_UNF | \ 97 SLINK_TX_UNF | SLINK_RX_OVF) 98 99 #define SLINK_FIFO_EMPTY (SLINK_TX_EMPTY | SLINK_RX_EMPTY) 100 101 #define SLINK_MAS_DATA 0x010 102 #define SLINK_SLAVE_DATA 0x014 103 104 #define SLINK_DMA_CTL 0x018 105 #define SLINK_DMA_BLOCK_SIZE(x) (((x) & 0xffff) << 0) 106 #define SLINK_TX_TRIG_1 (0 << 16) 107 #define SLINK_TX_TRIG_4 (1 << 16) 108 #define SLINK_TX_TRIG_8 (2 << 16) 109 #define SLINK_TX_TRIG_16 (3 << 16) 110 #define SLINK_TX_TRIG_MASK (3 << 16) 111 #define SLINK_RX_TRIG_1 (0 << 18) 112 #define SLINK_RX_TRIG_4 (1 << 18) 113 #define SLINK_RX_TRIG_8 (2 << 18) 114 #define SLINK_RX_TRIG_16 (3 << 18) 115 #define SLINK_RX_TRIG_MASK (3 << 18) 116 #define SLINK_PACKED (1 << 20) 117 #define SLINK_PACK_SIZE_4 (0 << 21) 118 #define SLINK_PACK_SIZE_8 (1 << 21) 119 #define SLINK_PACK_SIZE_16 (2 << 21) 120 #define SLINK_PACK_SIZE_32 (3 << 21) 121 #define SLINK_PACK_SIZE_MASK (3 << 21) 122 #define SLINK_IE_TXC (1 << 26) 123 #define SLINK_IE_RXC (1 << 27) 124 #define SLINK_DMA_EN (1 << 31) 125 126 #define SLINK_STATUS2 0x01c 127 #define SLINK_TX_FIFO_EMPTY_COUNT(val) (((val) & 0x3f) >> 0) 128 #define SLINK_RX_FIFO_FULL_COUNT(val) (((val) & 0x3f0000) >> 16) 129 #define SLINK_SS_HOLD_TIME(val) (((val) & 0xF) << 6) 130 131 #define SLINK_TX_FIFO 0x100 132 #define SLINK_RX_FIFO 0x180 133 134 #define DATA_DIR_TX (1 << 0) 135 #define DATA_DIR_RX (1 << 1) 136 137 #define SLINK_DMA_TIMEOUT (msecs_to_jiffies(1000)) 138 139 #define DEFAULT_SPI_DMA_BUF_LEN (16*1024) 140 #define TX_FIFO_EMPTY_COUNT_MAX SLINK_TX_FIFO_EMPTY_COUNT(0x20) 141 #define RX_FIFO_FULL_COUNT_ZERO SLINK_RX_FIFO_FULL_COUNT(0) 142 143 #define SLINK_STATUS2_RESET \ 144 (TX_FIFO_EMPTY_COUNT_MAX | RX_FIFO_FULL_COUNT_ZERO << 16) 145 146 #define MAX_CHIP_SELECT 4 147 #define SLINK_FIFO_DEPTH 32 148 149 struct tegra_slink_chip_data { 150 bool cs_hold_time; 151 }; 152 153 struct tegra_slink_data { 154 struct device *dev; 155 struct spi_master *master; 156 const struct tegra_slink_chip_data *chip_data; 157 spinlock_t lock; 158 159 struct clk *clk; 160 struct reset_control *rst; 161 void __iomem *base; 162 phys_addr_t phys; 163 unsigned irq; 164 u32 cur_speed; 165 166 struct spi_device *cur_spi; 167 unsigned cur_pos; 168 unsigned cur_len; 169 unsigned words_per_32bit; 170 unsigned bytes_per_word; 171 unsigned curr_dma_words; 172 unsigned cur_direction; 173 174 unsigned cur_rx_pos; 175 unsigned cur_tx_pos; 176 177 unsigned dma_buf_size; 178 unsigned max_buf_size; 179 bool is_curr_dma_xfer; 180 181 struct completion rx_dma_complete; 182 struct completion tx_dma_complete; 183 184 u32 tx_status; 185 u32 rx_status; 186 u32 status_reg; 187 bool is_packed; 188 u32 packed_size; 189 190 u32 command_reg; 191 u32 command2_reg; 192 u32 dma_control_reg; 193 u32 def_command_reg; 194 u32 def_command2_reg; 195 196 struct completion xfer_completion; 197 struct spi_transfer *curr_xfer; 198 struct dma_chan *rx_dma_chan; 199 u32 *rx_dma_buf; 200 dma_addr_t rx_dma_phys; 201 struct dma_async_tx_descriptor *rx_dma_desc; 202 203 struct dma_chan *tx_dma_chan; 204 u32 *tx_dma_buf; 205 dma_addr_t tx_dma_phys; 206 struct dma_async_tx_descriptor *tx_dma_desc; 207 }; 208 209 static inline u32 tegra_slink_readl(struct tegra_slink_data *tspi, 210 unsigned long reg) 211 { 212 return readl(tspi->base + reg); 213 } 214 215 static inline void tegra_slink_writel(struct tegra_slink_data *tspi, 216 u32 val, unsigned long reg) 217 { 218 writel(val, tspi->base + reg); 219 220 /* Read back register to make sure that register writes completed */ 221 if (reg != SLINK_TX_FIFO) 222 readl(tspi->base + SLINK_MAS_DATA); 223 } 224 225 static void tegra_slink_clear_status(struct tegra_slink_data *tspi) 226 { 227 u32 val_write; 228 229 tegra_slink_readl(tspi, SLINK_STATUS); 230 231 /* Write 1 to clear status register */ 232 val_write = SLINK_RDY | SLINK_FIFO_ERROR; 233 tegra_slink_writel(tspi, val_write, SLINK_STATUS); 234 } 235 236 static u32 tegra_slink_get_packed_size(struct tegra_slink_data *tspi, 237 struct spi_transfer *t) 238 { 239 switch (tspi->bytes_per_word) { 240 case 0: 241 return SLINK_PACK_SIZE_4; 242 case 1: 243 return SLINK_PACK_SIZE_8; 244 case 2: 245 return SLINK_PACK_SIZE_16; 246 case 4: 247 return SLINK_PACK_SIZE_32; 248 default: 249 return 0; 250 } 251 } 252 253 static unsigned tegra_slink_calculate_curr_xfer_param( 254 struct spi_device *spi, struct tegra_slink_data *tspi, 255 struct spi_transfer *t) 256 { 257 unsigned remain_len = t->len - tspi->cur_pos; 258 unsigned max_word; 259 unsigned bits_per_word; 260 unsigned max_len; 261 unsigned total_fifo_words; 262 263 bits_per_word = t->bits_per_word; 264 tspi->bytes_per_word = DIV_ROUND_UP(bits_per_word, 8); 265 266 if (bits_per_word == 8 || bits_per_word == 16) { 267 tspi->is_packed = true; 268 tspi->words_per_32bit = 32/bits_per_word; 269 } else { 270 tspi->is_packed = false; 271 tspi->words_per_32bit = 1; 272 } 273 tspi->packed_size = tegra_slink_get_packed_size(tspi, t); 274 275 if (tspi->is_packed) { 276 max_len = min(remain_len, tspi->max_buf_size); 277 tspi->curr_dma_words = max_len/tspi->bytes_per_word; 278 total_fifo_words = max_len/4; 279 } else { 280 max_word = (remain_len - 1) / tspi->bytes_per_word + 1; 281 max_word = min(max_word, tspi->max_buf_size/4); 282 tspi->curr_dma_words = max_word; 283 total_fifo_words = max_word; 284 } 285 return total_fifo_words; 286 } 287 288 static unsigned tegra_slink_fill_tx_fifo_from_client_txbuf( 289 struct tegra_slink_data *tspi, struct spi_transfer *t) 290 { 291 unsigned nbytes; 292 unsigned tx_empty_count; 293 u32 fifo_status; 294 unsigned max_n_32bit; 295 unsigned i, count; 296 unsigned int written_words; 297 unsigned fifo_words_left; 298 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos; 299 300 fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2); 301 tx_empty_count = SLINK_TX_FIFO_EMPTY_COUNT(fifo_status); 302 303 if (tspi->is_packed) { 304 fifo_words_left = tx_empty_count * tspi->words_per_32bit; 305 written_words = min(fifo_words_left, tspi->curr_dma_words); 306 nbytes = written_words * tspi->bytes_per_word; 307 max_n_32bit = DIV_ROUND_UP(nbytes, 4); 308 for (count = 0; count < max_n_32bit; count++) { 309 u32 x = 0; 310 for (i = 0; (i < 4) && nbytes; i++, nbytes--) 311 x |= (u32)(*tx_buf++) << (i * 8); 312 tegra_slink_writel(tspi, x, SLINK_TX_FIFO); 313 } 314 } else { 315 max_n_32bit = min(tspi->curr_dma_words, tx_empty_count); 316 written_words = max_n_32bit; 317 nbytes = written_words * tspi->bytes_per_word; 318 for (count = 0; count < max_n_32bit; count++) { 319 u32 x = 0; 320 for (i = 0; nbytes && (i < tspi->bytes_per_word); 321 i++, nbytes--) 322 x |= (u32)(*tx_buf++) << (i * 8); 323 tegra_slink_writel(tspi, x, SLINK_TX_FIFO); 324 } 325 } 326 tspi->cur_tx_pos += written_words * tspi->bytes_per_word; 327 return written_words; 328 } 329 330 static unsigned int tegra_slink_read_rx_fifo_to_client_rxbuf( 331 struct tegra_slink_data *tspi, struct spi_transfer *t) 332 { 333 unsigned rx_full_count; 334 u32 fifo_status; 335 unsigned i, count; 336 unsigned int read_words = 0; 337 unsigned len; 338 u8 *rx_buf = (u8 *)t->rx_buf + tspi->cur_rx_pos; 339 340 fifo_status = tegra_slink_readl(tspi, SLINK_STATUS2); 341 rx_full_count = SLINK_RX_FIFO_FULL_COUNT(fifo_status); 342 if (tspi->is_packed) { 343 len = tspi->curr_dma_words * tspi->bytes_per_word; 344 for (count = 0; count < rx_full_count; count++) { 345 u32 x = tegra_slink_readl(tspi, SLINK_RX_FIFO); 346 for (i = 0; len && (i < 4); i++, len--) 347 *rx_buf++ = (x >> i*8) & 0xFF; 348 } 349 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word; 350 read_words += tspi->curr_dma_words; 351 } else { 352 for (count = 0; count < rx_full_count; count++) { 353 u32 x = tegra_slink_readl(tspi, SLINK_RX_FIFO); 354 for (i = 0; (i < tspi->bytes_per_word); i++) 355 *rx_buf++ = (x >> (i*8)) & 0xFF; 356 } 357 tspi->cur_rx_pos += rx_full_count * tspi->bytes_per_word; 358 read_words += rx_full_count; 359 } 360 return read_words; 361 } 362 363 static void tegra_slink_copy_client_txbuf_to_spi_txbuf( 364 struct tegra_slink_data *tspi, struct spi_transfer *t) 365 { 366 /* Make the dma buffer to read by cpu */ 367 dma_sync_single_for_cpu(tspi->dev, tspi->tx_dma_phys, 368 tspi->dma_buf_size, DMA_TO_DEVICE); 369 370 if (tspi->is_packed) { 371 unsigned len = tspi->curr_dma_words * tspi->bytes_per_word; 372 memcpy(tspi->tx_dma_buf, t->tx_buf + tspi->cur_pos, len); 373 } else { 374 unsigned int i; 375 unsigned int count; 376 u8 *tx_buf = (u8 *)t->tx_buf + tspi->cur_tx_pos; 377 unsigned consume = tspi->curr_dma_words * tspi->bytes_per_word; 378 379 for (count = 0; count < tspi->curr_dma_words; count++) { 380 u32 x = 0; 381 for (i = 0; consume && (i < tspi->bytes_per_word); 382 i++, consume--) 383 x |= (u32)(*tx_buf++) << (i * 8); 384 tspi->tx_dma_buf[count] = x; 385 } 386 } 387 tspi->cur_tx_pos += tspi->curr_dma_words * tspi->bytes_per_word; 388 389 /* Make the dma buffer to read by dma */ 390 dma_sync_single_for_device(tspi->dev, tspi->tx_dma_phys, 391 tspi->dma_buf_size, DMA_TO_DEVICE); 392 } 393 394 static void tegra_slink_copy_spi_rxbuf_to_client_rxbuf( 395 struct tegra_slink_data *tspi, struct spi_transfer *t) 396 { 397 unsigned len; 398 399 /* Make the dma buffer to read by cpu */ 400 dma_sync_single_for_cpu(tspi->dev, tspi->rx_dma_phys, 401 tspi->dma_buf_size, DMA_FROM_DEVICE); 402 403 if (tspi->is_packed) { 404 len = tspi->curr_dma_words * tspi->bytes_per_word; 405 memcpy(t->rx_buf + tspi->cur_rx_pos, tspi->rx_dma_buf, len); 406 } else { 407 unsigned int i; 408 unsigned int count; 409 unsigned char *rx_buf = t->rx_buf + tspi->cur_rx_pos; 410 u32 rx_mask = ((u32)1 << t->bits_per_word) - 1; 411 412 for (count = 0; count < tspi->curr_dma_words; count++) { 413 u32 x = tspi->rx_dma_buf[count] & rx_mask; 414 for (i = 0; (i < tspi->bytes_per_word); i++) 415 *rx_buf++ = (x >> (i*8)) & 0xFF; 416 } 417 } 418 tspi->cur_rx_pos += tspi->curr_dma_words * tspi->bytes_per_word; 419 420 /* Make the dma buffer to read by dma */ 421 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys, 422 tspi->dma_buf_size, DMA_FROM_DEVICE); 423 } 424 425 static void tegra_slink_dma_complete(void *args) 426 { 427 struct completion *dma_complete = args; 428 429 complete(dma_complete); 430 } 431 432 static int tegra_slink_start_tx_dma(struct tegra_slink_data *tspi, int len) 433 { 434 reinit_completion(&tspi->tx_dma_complete); 435 tspi->tx_dma_desc = dmaengine_prep_slave_single(tspi->tx_dma_chan, 436 tspi->tx_dma_phys, len, DMA_MEM_TO_DEV, 437 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 438 if (!tspi->tx_dma_desc) { 439 dev_err(tspi->dev, "Not able to get desc for Tx\n"); 440 return -EIO; 441 } 442 443 tspi->tx_dma_desc->callback = tegra_slink_dma_complete; 444 tspi->tx_dma_desc->callback_param = &tspi->tx_dma_complete; 445 446 dmaengine_submit(tspi->tx_dma_desc); 447 dma_async_issue_pending(tspi->tx_dma_chan); 448 return 0; 449 } 450 451 static int tegra_slink_start_rx_dma(struct tegra_slink_data *tspi, int len) 452 { 453 reinit_completion(&tspi->rx_dma_complete); 454 tspi->rx_dma_desc = dmaengine_prep_slave_single(tspi->rx_dma_chan, 455 tspi->rx_dma_phys, len, DMA_DEV_TO_MEM, 456 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 457 if (!tspi->rx_dma_desc) { 458 dev_err(tspi->dev, "Not able to get desc for Rx\n"); 459 return -EIO; 460 } 461 462 tspi->rx_dma_desc->callback = tegra_slink_dma_complete; 463 tspi->rx_dma_desc->callback_param = &tspi->rx_dma_complete; 464 465 dmaengine_submit(tspi->rx_dma_desc); 466 dma_async_issue_pending(tspi->rx_dma_chan); 467 return 0; 468 } 469 470 static int tegra_slink_start_dma_based_transfer( 471 struct tegra_slink_data *tspi, struct spi_transfer *t) 472 { 473 u32 val; 474 unsigned int len; 475 int ret = 0; 476 u32 status; 477 478 /* Make sure that Rx and Tx fifo are empty */ 479 status = tegra_slink_readl(tspi, SLINK_STATUS); 480 if ((status & SLINK_FIFO_EMPTY) != SLINK_FIFO_EMPTY) { 481 dev_err(tspi->dev, "Rx/Tx fifo are not empty status 0x%08x\n", 482 (unsigned)status); 483 return -EIO; 484 } 485 486 val = SLINK_DMA_BLOCK_SIZE(tspi->curr_dma_words - 1); 487 val |= tspi->packed_size; 488 if (tspi->is_packed) 489 len = DIV_ROUND_UP(tspi->curr_dma_words * tspi->bytes_per_word, 490 4) * 4; 491 else 492 len = tspi->curr_dma_words * 4; 493 494 /* Set attention level based on length of transfer */ 495 if (len & 0xF) 496 val |= SLINK_TX_TRIG_1 | SLINK_RX_TRIG_1; 497 else if (((len) >> 4) & 0x1) 498 val |= SLINK_TX_TRIG_4 | SLINK_RX_TRIG_4; 499 else 500 val |= SLINK_TX_TRIG_8 | SLINK_RX_TRIG_8; 501 502 if (tspi->cur_direction & DATA_DIR_TX) 503 val |= SLINK_IE_TXC; 504 505 if (tspi->cur_direction & DATA_DIR_RX) 506 val |= SLINK_IE_RXC; 507 508 tegra_slink_writel(tspi, val, SLINK_DMA_CTL); 509 tspi->dma_control_reg = val; 510 511 if (tspi->cur_direction & DATA_DIR_TX) { 512 tegra_slink_copy_client_txbuf_to_spi_txbuf(tspi, t); 513 wmb(); 514 ret = tegra_slink_start_tx_dma(tspi, len); 515 if (ret < 0) { 516 dev_err(tspi->dev, 517 "Starting tx dma failed, err %d\n", ret); 518 return ret; 519 } 520 521 /* Wait for tx fifo to be fill before starting slink */ 522 status = tegra_slink_readl(tspi, SLINK_STATUS); 523 while (!(status & SLINK_TX_FULL)) 524 status = tegra_slink_readl(tspi, SLINK_STATUS); 525 } 526 527 if (tspi->cur_direction & DATA_DIR_RX) { 528 /* Make the dma buffer to read by dma */ 529 dma_sync_single_for_device(tspi->dev, tspi->rx_dma_phys, 530 tspi->dma_buf_size, DMA_FROM_DEVICE); 531 532 ret = tegra_slink_start_rx_dma(tspi, len); 533 if (ret < 0) { 534 dev_err(tspi->dev, 535 "Starting rx dma failed, err %d\n", ret); 536 if (tspi->cur_direction & DATA_DIR_TX) 537 dmaengine_terminate_all(tspi->tx_dma_chan); 538 return ret; 539 } 540 } 541 tspi->is_curr_dma_xfer = true; 542 if (tspi->is_packed) { 543 val |= SLINK_PACKED; 544 tegra_slink_writel(tspi, val, SLINK_DMA_CTL); 545 /* HW need small delay after settign Packed mode */ 546 udelay(1); 547 } 548 tspi->dma_control_reg = val; 549 550 val |= SLINK_DMA_EN; 551 tegra_slink_writel(tspi, val, SLINK_DMA_CTL); 552 return ret; 553 } 554 555 static int tegra_slink_start_cpu_based_transfer( 556 struct tegra_slink_data *tspi, struct spi_transfer *t) 557 { 558 u32 val; 559 unsigned cur_words; 560 561 val = tspi->packed_size; 562 if (tspi->cur_direction & DATA_DIR_TX) 563 val |= SLINK_IE_TXC; 564 565 if (tspi->cur_direction & DATA_DIR_RX) 566 val |= SLINK_IE_RXC; 567 568 tegra_slink_writel(tspi, val, SLINK_DMA_CTL); 569 tspi->dma_control_reg = val; 570 571 if (tspi->cur_direction & DATA_DIR_TX) 572 cur_words = tegra_slink_fill_tx_fifo_from_client_txbuf(tspi, t); 573 else 574 cur_words = tspi->curr_dma_words; 575 val |= SLINK_DMA_BLOCK_SIZE(cur_words - 1); 576 tegra_slink_writel(tspi, val, SLINK_DMA_CTL); 577 tspi->dma_control_reg = val; 578 579 tspi->is_curr_dma_xfer = false; 580 if (tspi->is_packed) { 581 val |= SLINK_PACKED; 582 tegra_slink_writel(tspi, val, SLINK_DMA_CTL); 583 udelay(1); 584 wmb(); 585 } 586 tspi->dma_control_reg = val; 587 val |= SLINK_DMA_EN; 588 tegra_slink_writel(tspi, val, SLINK_DMA_CTL); 589 return 0; 590 } 591 592 static int tegra_slink_init_dma_param(struct tegra_slink_data *tspi, 593 bool dma_to_memory) 594 { 595 struct dma_chan *dma_chan; 596 u32 *dma_buf; 597 dma_addr_t dma_phys; 598 int ret; 599 struct dma_slave_config dma_sconfig; 600 601 dma_chan = dma_request_chan(tspi->dev, dma_to_memory ? "rx" : "tx"); 602 if (IS_ERR(dma_chan)) 603 return dev_err_probe(tspi->dev, PTR_ERR(dma_chan), 604 "Dma channel is not available\n"); 605 606 dma_buf = dma_alloc_coherent(tspi->dev, tspi->dma_buf_size, 607 &dma_phys, GFP_KERNEL); 608 if (!dma_buf) { 609 dev_err(tspi->dev, " Not able to allocate the dma buffer\n"); 610 dma_release_channel(dma_chan); 611 return -ENOMEM; 612 } 613 614 if (dma_to_memory) { 615 dma_sconfig.src_addr = tspi->phys + SLINK_RX_FIFO; 616 dma_sconfig.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 617 dma_sconfig.src_maxburst = 0; 618 } else { 619 dma_sconfig.dst_addr = tspi->phys + SLINK_TX_FIFO; 620 dma_sconfig.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 621 dma_sconfig.dst_maxburst = 0; 622 } 623 624 ret = dmaengine_slave_config(dma_chan, &dma_sconfig); 625 if (ret) 626 goto scrub; 627 if (dma_to_memory) { 628 tspi->rx_dma_chan = dma_chan; 629 tspi->rx_dma_buf = dma_buf; 630 tspi->rx_dma_phys = dma_phys; 631 } else { 632 tspi->tx_dma_chan = dma_chan; 633 tspi->tx_dma_buf = dma_buf; 634 tspi->tx_dma_phys = dma_phys; 635 } 636 return 0; 637 638 scrub: 639 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys); 640 dma_release_channel(dma_chan); 641 return ret; 642 } 643 644 static void tegra_slink_deinit_dma_param(struct tegra_slink_data *tspi, 645 bool dma_to_memory) 646 { 647 u32 *dma_buf; 648 dma_addr_t dma_phys; 649 struct dma_chan *dma_chan; 650 651 if (dma_to_memory) { 652 dma_buf = tspi->rx_dma_buf; 653 dma_chan = tspi->rx_dma_chan; 654 dma_phys = tspi->rx_dma_phys; 655 tspi->rx_dma_chan = NULL; 656 tspi->rx_dma_buf = NULL; 657 } else { 658 dma_buf = tspi->tx_dma_buf; 659 dma_chan = tspi->tx_dma_chan; 660 dma_phys = tspi->tx_dma_phys; 661 tspi->tx_dma_buf = NULL; 662 tspi->tx_dma_chan = NULL; 663 } 664 if (!dma_chan) 665 return; 666 667 dma_free_coherent(tspi->dev, tspi->dma_buf_size, dma_buf, dma_phys); 668 dma_release_channel(dma_chan); 669 } 670 671 static int tegra_slink_start_transfer_one(struct spi_device *spi, 672 struct spi_transfer *t) 673 { 674 struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master); 675 u32 speed; 676 u8 bits_per_word; 677 unsigned total_fifo_words; 678 int ret; 679 u32 command; 680 u32 command2; 681 682 bits_per_word = t->bits_per_word; 683 speed = t->speed_hz; 684 if (speed != tspi->cur_speed) { 685 dev_pm_opp_set_rate(tspi->dev, speed * 4); 686 tspi->cur_speed = speed; 687 } 688 689 tspi->cur_spi = spi; 690 tspi->cur_pos = 0; 691 tspi->cur_rx_pos = 0; 692 tspi->cur_tx_pos = 0; 693 tspi->curr_xfer = t; 694 total_fifo_words = tegra_slink_calculate_curr_xfer_param(spi, tspi, t); 695 696 command = tspi->command_reg; 697 command &= ~SLINK_BIT_LENGTH(~0); 698 command |= SLINK_BIT_LENGTH(bits_per_word - 1); 699 700 command2 = tspi->command2_reg; 701 command2 &= ~(SLINK_RXEN | SLINK_TXEN); 702 703 tspi->cur_direction = 0; 704 if (t->rx_buf) { 705 command2 |= SLINK_RXEN; 706 tspi->cur_direction |= DATA_DIR_RX; 707 } 708 if (t->tx_buf) { 709 command2 |= SLINK_TXEN; 710 tspi->cur_direction |= DATA_DIR_TX; 711 } 712 713 /* 714 * Writing to the command2 register bevore the command register prevents 715 * a spike in chip_select line 0. This selects the chip_select line 716 * before changing the chip_select value. 717 */ 718 tegra_slink_writel(tspi, command2, SLINK_COMMAND2); 719 tspi->command2_reg = command2; 720 721 tegra_slink_writel(tspi, command, SLINK_COMMAND); 722 tspi->command_reg = command; 723 724 if (total_fifo_words > SLINK_FIFO_DEPTH) 725 ret = tegra_slink_start_dma_based_transfer(tspi, t); 726 else 727 ret = tegra_slink_start_cpu_based_transfer(tspi, t); 728 return ret; 729 } 730 731 static int tegra_slink_setup(struct spi_device *spi) 732 { 733 static const u32 cs_pol_bit[MAX_CHIP_SELECT] = { 734 SLINK_CS_POLARITY, 735 SLINK_CS_POLARITY1, 736 SLINK_CS_POLARITY2, 737 SLINK_CS_POLARITY3, 738 }; 739 740 struct tegra_slink_data *tspi = spi_master_get_devdata(spi->master); 741 u32 val; 742 unsigned long flags; 743 int ret; 744 745 dev_dbg(&spi->dev, "setup %d bpw, %scpol, %scpha, %dHz\n", 746 spi->bits_per_word, 747 spi->mode & SPI_CPOL ? "" : "~", 748 spi->mode & SPI_CPHA ? "" : "~", 749 spi->max_speed_hz); 750 751 ret = pm_runtime_resume_and_get(tspi->dev); 752 if (ret < 0) { 753 dev_err(tspi->dev, "pm runtime failed, e = %d\n", ret); 754 return ret; 755 } 756 757 spin_lock_irqsave(&tspi->lock, flags); 758 val = tspi->def_command_reg; 759 if (spi->mode & SPI_CS_HIGH) 760 val |= cs_pol_bit[spi_get_chipselect(spi, 0)]; 761 else 762 val &= ~cs_pol_bit[spi_get_chipselect(spi, 0)]; 763 tspi->def_command_reg = val; 764 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND); 765 spin_unlock_irqrestore(&tspi->lock, flags); 766 767 pm_runtime_put(tspi->dev); 768 return 0; 769 } 770 771 static int tegra_slink_prepare_message(struct spi_master *master, 772 struct spi_message *msg) 773 { 774 struct tegra_slink_data *tspi = spi_master_get_devdata(master); 775 struct spi_device *spi = msg->spi; 776 777 tegra_slink_clear_status(tspi); 778 779 tspi->command_reg = tspi->def_command_reg; 780 tspi->command_reg |= SLINK_CS_SW | SLINK_CS_VALUE; 781 782 tspi->command2_reg = tspi->def_command2_reg; 783 tspi->command2_reg |= SLINK_SS_EN_CS(spi_get_chipselect(spi, 0)); 784 785 tspi->command_reg &= ~SLINK_MODES; 786 if (spi->mode & SPI_CPHA) 787 tspi->command_reg |= SLINK_CK_SDA; 788 789 if (spi->mode & SPI_CPOL) 790 tspi->command_reg |= SLINK_IDLE_SCLK_DRIVE_HIGH; 791 else 792 tspi->command_reg |= SLINK_IDLE_SCLK_DRIVE_LOW; 793 794 return 0; 795 } 796 797 static int tegra_slink_transfer_one(struct spi_master *master, 798 struct spi_device *spi, 799 struct spi_transfer *xfer) 800 { 801 struct tegra_slink_data *tspi = spi_master_get_devdata(master); 802 int ret; 803 804 reinit_completion(&tspi->xfer_completion); 805 ret = tegra_slink_start_transfer_one(spi, xfer); 806 if (ret < 0) { 807 dev_err(tspi->dev, 808 "spi can not start transfer, err %d\n", ret); 809 return ret; 810 } 811 812 ret = wait_for_completion_timeout(&tspi->xfer_completion, 813 SLINK_DMA_TIMEOUT); 814 if (WARN_ON(ret == 0)) { 815 dev_err(tspi->dev, 816 "spi transfer timeout, err %d\n", ret); 817 return -EIO; 818 } 819 820 if (tspi->tx_status) 821 return tspi->tx_status; 822 if (tspi->rx_status) 823 return tspi->rx_status; 824 825 return 0; 826 } 827 828 static int tegra_slink_unprepare_message(struct spi_master *master, 829 struct spi_message *msg) 830 { 831 struct tegra_slink_data *tspi = spi_master_get_devdata(master); 832 833 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND); 834 tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2); 835 836 return 0; 837 } 838 839 static irqreturn_t handle_cpu_based_xfer(struct tegra_slink_data *tspi) 840 { 841 struct spi_transfer *t = tspi->curr_xfer; 842 unsigned long flags; 843 844 spin_lock_irqsave(&tspi->lock, flags); 845 if (tspi->tx_status || tspi->rx_status || 846 (tspi->status_reg & SLINK_BSY)) { 847 dev_err(tspi->dev, 848 "CpuXfer ERROR bit set 0x%x\n", tspi->status_reg); 849 dev_err(tspi->dev, 850 "CpuXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg, 851 tspi->command2_reg, tspi->dma_control_reg); 852 reset_control_assert(tspi->rst); 853 udelay(2); 854 reset_control_deassert(tspi->rst); 855 complete(&tspi->xfer_completion); 856 goto exit; 857 } 858 859 if (tspi->cur_direction & DATA_DIR_RX) 860 tegra_slink_read_rx_fifo_to_client_rxbuf(tspi, t); 861 862 if (tspi->cur_direction & DATA_DIR_TX) 863 tspi->cur_pos = tspi->cur_tx_pos; 864 else 865 tspi->cur_pos = tspi->cur_rx_pos; 866 867 if (tspi->cur_pos == t->len) { 868 complete(&tspi->xfer_completion); 869 goto exit; 870 } 871 872 tegra_slink_calculate_curr_xfer_param(tspi->cur_spi, tspi, t); 873 tegra_slink_start_cpu_based_transfer(tspi, t); 874 exit: 875 spin_unlock_irqrestore(&tspi->lock, flags); 876 return IRQ_HANDLED; 877 } 878 879 static irqreturn_t handle_dma_based_xfer(struct tegra_slink_data *tspi) 880 { 881 struct spi_transfer *t = tspi->curr_xfer; 882 long wait_status; 883 int err = 0; 884 unsigned total_fifo_words; 885 unsigned long flags; 886 887 /* Abort dmas if any error */ 888 if (tspi->cur_direction & DATA_DIR_TX) { 889 if (tspi->tx_status) { 890 dmaengine_terminate_all(tspi->tx_dma_chan); 891 err += 1; 892 } else { 893 wait_status = wait_for_completion_interruptible_timeout( 894 &tspi->tx_dma_complete, SLINK_DMA_TIMEOUT); 895 if (wait_status <= 0) { 896 dmaengine_terminate_all(tspi->tx_dma_chan); 897 dev_err(tspi->dev, "TxDma Xfer failed\n"); 898 err += 1; 899 } 900 } 901 } 902 903 if (tspi->cur_direction & DATA_DIR_RX) { 904 if (tspi->rx_status) { 905 dmaengine_terminate_all(tspi->rx_dma_chan); 906 err += 2; 907 } else { 908 wait_status = wait_for_completion_interruptible_timeout( 909 &tspi->rx_dma_complete, SLINK_DMA_TIMEOUT); 910 if (wait_status <= 0) { 911 dmaengine_terminate_all(tspi->rx_dma_chan); 912 dev_err(tspi->dev, "RxDma Xfer failed\n"); 913 err += 2; 914 } 915 } 916 } 917 918 spin_lock_irqsave(&tspi->lock, flags); 919 if (err) { 920 dev_err(tspi->dev, 921 "DmaXfer: ERROR bit set 0x%x\n", tspi->status_reg); 922 dev_err(tspi->dev, 923 "DmaXfer 0x%08x:0x%08x:0x%08x\n", tspi->command_reg, 924 tspi->command2_reg, tspi->dma_control_reg); 925 reset_control_assert(tspi->rst); 926 udelay(2); 927 reset_control_assert(tspi->rst); 928 complete(&tspi->xfer_completion); 929 spin_unlock_irqrestore(&tspi->lock, flags); 930 return IRQ_HANDLED; 931 } 932 933 if (tspi->cur_direction & DATA_DIR_RX) 934 tegra_slink_copy_spi_rxbuf_to_client_rxbuf(tspi, t); 935 936 if (tspi->cur_direction & DATA_DIR_TX) 937 tspi->cur_pos = tspi->cur_tx_pos; 938 else 939 tspi->cur_pos = tspi->cur_rx_pos; 940 941 if (tspi->cur_pos == t->len) { 942 complete(&tspi->xfer_completion); 943 goto exit; 944 } 945 946 /* Continue transfer in current message */ 947 total_fifo_words = tegra_slink_calculate_curr_xfer_param(tspi->cur_spi, 948 tspi, t); 949 if (total_fifo_words > SLINK_FIFO_DEPTH) 950 err = tegra_slink_start_dma_based_transfer(tspi, t); 951 else 952 err = tegra_slink_start_cpu_based_transfer(tspi, t); 953 954 exit: 955 spin_unlock_irqrestore(&tspi->lock, flags); 956 return IRQ_HANDLED; 957 } 958 959 static irqreturn_t tegra_slink_isr_thread(int irq, void *context_data) 960 { 961 struct tegra_slink_data *tspi = context_data; 962 963 if (!tspi->is_curr_dma_xfer) 964 return handle_cpu_based_xfer(tspi); 965 return handle_dma_based_xfer(tspi); 966 } 967 968 static irqreturn_t tegra_slink_isr(int irq, void *context_data) 969 { 970 struct tegra_slink_data *tspi = context_data; 971 972 tspi->status_reg = tegra_slink_readl(tspi, SLINK_STATUS); 973 if (tspi->cur_direction & DATA_DIR_TX) 974 tspi->tx_status = tspi->status_reg & 975 (SLINK_TX_OVF | SLINK_TX_UNF); 976 977 if (tspi->cur_direction & DATA_DIR_RX) 978 tspi->rx_status = tspi->status_reg & 979 (SLINK_RX_OVF | SLINK_RX_UNF); 980 tegra_slink_clear_status(tspi); 981 982 return IRQ_WAKE_THREAD; 983 } 984 985 static const struct tegra_slink_chip_data tegra30_spi_cdata = { 986 .cs_hold_time = true, 987 }; 988 989 static const struct tegra_slink_chip_data tegra20_spi_cdata = { 990 .cs_hold_time = false, 991 }; 992 993 static const struct of_device_id tegra_slink_of_match[] = { 994 { .compatible = "nvidia,tegra30-slink", .data = &tegra30_spi_cdata, }, 995 { .compatible = "nvidia,tegra20-slink", .data = &tegra20_spi_cdata, }, 996 {} 997 }; 998 MODULE_DEVICE_TABLE(of, tegra_slink_of_match); 999 1000 static int tegra_slink_probe(struct platform_device *pdev) 1001 { 1002 struct spi_master *master; 1003 struct tegra_slink_data *tspi; 1004 struct resource *r; 1005 int ret, spi_irq; 1006 const struct tegra_slink_chip_data *cdata = NULL; 1007 1008 cdata = of_device_get_match_data(&pdev->dev); 1009 1010 master = spi_alloc_master(&pdev->dev, sizeof(*tspi)); 1011 if (!master) { 1012 dev_err(&pdev->dev, "master allocation failed\n"); 1013 return -ENOMEM; 1014 } 1015 1016 /* the spi->mode bits understood by this driver: */ 1017 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1018 master->setup = tegra_slink_setup; 1019 master->prepare_message = tegra_slink_prepare_message; 1020 master->transfer_one = tegra_slink_transfer_one; 1021 master->unprepare_message = tegra_slink_unprepare_message; 1022 master->auto_runtime_pm = true; 1023 master->num_chipselect = MAX_CHIP_SELECT; 1024 1025 platform_set_drvdata(pdev, master); 1026 tspi = spi_master_get_devdata(master); 1027 tspi->master = master; 1028 tspi->dev = &pdev->dev; 1029 tspi->chip_data = cdata; 1030 spin_lock_init(&tspi->lock); 1031 1032 if (of_property_read_u32(tspi->dev->of_node, "spi-max-frequency", 1033 &master->max_speed_hz)) 1034 master->max_speed_hz = 25000000; /* 25MHz */ 1035 1036 tspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, &r); 1037 if (IS_ERR(tspi->base)) { 1038 ret = PTR_ERR(tspi->base); 1039 goto exit_free_master; 1040 } 1041 tspi->phys = r->start; 1042 1043 /* disabled clock may cause interrupt storm upon request */ 1044 tspi->clk = devm_clk_get(&pdev->dev, NULL); 1045 if (IS_ERR(tspi->clk)) { 1046 ret = PTR_ERR(tspi->clk); 1047 dev_err(&pdev->dev, "Can not get clock %d\n", ret); 1048 goto exit_free_master; 1049 } 1050 1051 tspi->rst = devm_reset_control_get_exclusive(&pdev->dev, "spi"); 1052 if (IS_ERR(tspi->rst)) { 1053 dev_err(&pdev->dev, "can not get reset\n"); 1054 ret = PTR_ERR(tspi->rst); 1055 goto exit_free_master; 1056 } 1057 1058 ret = devm_tegra_core_dev_init_opp_table_common(&pdev->dev); 1059 if (ret) 1060 goto exit_free_master; 1061 1062 tspi->max_buf_size = SLINK_FIFO_DEPTH << 2; 1063 tspi->dma_buf_size = DEFAULT_SPI_DMA_BUF_LEN; 1064 1065 ret = tegra_slink_init_dma_param(tspi, true); 1066 if (ret < 0) 1067 goto exit_free_master; 1068 ret = tegra_slink_init_dma_param(tspi, false); 1069 if (ret < 0) 1070 goto exit_rx_dma_free; 1071 tspi->max_buf_size = tspi->dma_buf_size; 1072 init_completion(&tspi->tx_dma_complete); 1073 init_completion(&tspi->rx_dma_complete); 1074 1075 init_completion(&tspi->xfer_completion); 1076 1077 pm_runtime_enable(&pdev->dev); 1078 ret = pm_runtime_resume_and_get(&pdev->dev); 1079 if (ret) { 1080 dev_err(&pdev->dev, "pm runtime get failed, e = %d\n", ret); 1081 goto exit_pm_disable; 1082 } 1083 1084 reset_control_assert(tspi->rst); 1085 udelay(2); 1086 reset_control_deassert(tspi->rst); 1087 1088 spi_irq = platform_get_irq(pdev, 0); 1089 tspi->irq = spi_irq; 1090 ret = request_threaded_irq(tspi->irq, tegra_slink_isr, 1091 tegra_slink_isr_thread, IRQF_ONESHOT, 1092 dev_name(&pdev->dev), tspi); 1093 if (ret < 0) { 1094 dev_err(&pdev->dev, "Failed to register ISR for IRQ %d\n", 1095 tspi->irq); 1096 goto exit_pm_put; 1097 } 1098 1099 tspi->def_command_reg = SLINK_M_S; 1100 tspi->def_command2_reg = SLINK_CS_ACTIVE_BETWEEN; 1101 tegra_slink_writel(tspi, tspi->def_command_reg, SLINK_COMMAND); 1102 tegra_slink_writel(tspi, tspi->def_command2_reg, SLINK_COMMAND2); 1103 1104 master->dev.of_node = pdev->dev.of_node; 1105 ret = spi_register_master(master); 1106 if (ret < 0) { 1107 dev_err(&pdev->dev, "can not register to master err %d\n", ret); 1108 goto exit_free_irq; 1109 } 1110 1111 pm_runtime_put(&pdev->dev); 1112 1113 return ret; 1114 1115 exit_free_irq: 1116 free_irq(spi_irq, tspi); 1117 exit_pm_put: 1118 pm_runtime_put(&pdev->dev); 1119 exit_pm_disable: 1120 pm_runtime_force_suspend(&pdev->dev); 1121 1122 tegra_slink_deinit_dma_param(tspi, false); 1123 exit_rx_dma_free: 1124 tegra_slink_deinit_dma_param(tspi, true); 1125 exit_free_master: 1126 spi_master_put(master); 1127 return ret; 1128 } 1129 1130 static void tegra_slink_remove(struct platform_device *pdev) 1131 { 1132 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); 1133 struct tegra_slink_data *tspi = spi_master_get_devdata(master); 1134 1135 spi_unregister_master(master); 1136 1137 free_irq(tspi->irq, tspi); 1138 1139 pm_runtime_force_suspend(&pdev->dev); 1140 1141 if (tspi->tx_dma_chan) 1142 tegra_slink_deinit_dma_param(tspi, false); 1143 1144 if (tspi->rx_dma_chan) 1145 tegra_slink_deinit_dma_param(tspi, true); 1146 1147 spi_master_put(master); 1148 } 1149 1150 #ifdef CONFIG_PM_SLEEP 1151 static int tegra_slink_suspend(struct device *dev) 1152 { 1153 struct spi_master *master = dev_get_drvdata(dev); 1154 1155 return spi_master_suspend(master); 1156 } 1157 1158 static int tegra_slink_resume(struct device *dev) 1159 { 1160 struct spi_master *master = dev_get_drvdata(dev); 1161 struct tegra_slink_data *tspi = spi_master_get_devdata(master); 1162 int ret; 1163 1164 ret = pm_runtime_resume_and_get(dev); 1165 if (ret < 0) { 1166 dev_err(dev, "pm runtime failed, e = %d\n", ret); 1167 return ret; 1168 } 1169 tegra_slink_writel(tspi, tspi->command_reg, SLINK_COMMAND); 1170 tegra_slink_writel(tspi, tspi->command2_reg, SLINK_COMMAND2); 1171 pm_runtime_put(dev); 1172 1173 return spi_master_resume(master); 1174 } 1175 #endif 1176 1177 static int __maybe_unused tegra_slink_runtime_suspend(struct device *dev) 1178 { 1179 struct spi_master *master = dev_get_drvdata(dev); 1180 struct tegra_slink_data *tspi = spi_master_get_devdata(master); 1181 1182 /* Flush all write which are in PPSB queue by reading back */ 1183 tegra_slink_readl(tspi, SLINK_MAS_DATA); 1184 1185 clk_disable_unprepare(tspi->clk); 1186 return 0; 1187 } 1188 1189 static int __maybe_unused tegra_slink_runtime_resume(struct device *dev) 1190 { 1191 struct spi_master *master = dev_get_drvdata(dev); 1192 struct tegra_slink_data *tspi = spi_master_get_devdata(master); 1193 int ret; 1194 1195 ret = clk_prepare_enable(tspi->clk); 1196 if (ret < 0) { 1197 dev_err(tspi->dev, "clk_prepare failed: %d\n", ret); 1198 return ret; 1199 } 1200 return 0; 1201 } 1202 1203 static const struct dev_pm_ops slink_pm_ops = { 1204 SET_RUNTIME_PM_OPS(tegra_slink_runtime_suspend, 1205 tegra_slink_runtime_resume, NULL) 1206 SET_SYSTEM_SLEEP_PM_OPS(tegra_slink_suspend, tegra_slink_resume) 1207 }; 1208 static struct platform_driver tegra_slink_driver = { 1209 .driver = { 1210 .name = "spi-tegra-slink", 1211 .pm = &slink_pm_ops, 1212 .of_match_table = tegra_slink_of_match, 1213 }, 1214 .probe = tegra_slink_probe, 1215 .remove_new = tegra_slink_remove, 1216 }; 1217 module_platform_driver(tegra_slink_driver); 1218 1219 MODULE_ALIAS("platform:spi-tegra-slink"); 1220 MODULE_DESCRIPTION("NVIDIA Tegra20/Tegra30 SLINK Controller Driver"); 1221 MODULE_AUTHOR("Laxman Dewangan <ldewangan@nvidia.com>"); 1222 MODULE_LICENSE("GPL v2"); 1223