1 /* 2 * Copyright (C) 2012 - 2014 Allwinner Tech 3 * Pan Nan <pannan@allwinnertech.com> 4 * 5 * Copyright (C) 2014 Maxime Ripard 6 * Maxime Ripard <maxime.ripard@free-electrons.com> 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 */ 13 14 #include <linux/clk.h> 15 #include <linux/delay.h> 16 #include <linux/device.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/module.h> 20 #include <linux/platform_device.h> 21 #include <linux/pm_runtime.h> 22 #include <linux/reset.h> 23 24 #include <linux/spi/spi.h> 25 26 #define SUN6I_FIFO_DEPTH 128 27 28 #define SUN6I_GBL_CTL_REG 0x04 29 #define SUN6I_GBL_CTL_BUS_ENABLE BIT(0) 30 #define SUN6I_GBL_CTL_MASTER BIT(1) 31 #define SUN6I_GBL_CTL_TP BIT(7) 32 #define SUN6I_GBL_CTL_RST BIT(31) 33 34 #define SUN6I_TFR_CTL_REG 0x08 35 #define SUN6I_TFR_CTL_CPHA BIT(0) 36 #define SUN6I_TFR_CTL_CPOL BIT(1) 37 #define SUN6I_TFR_CTL_SPOL BIT(2) 38 #define SUN6I_TFR_CTL_CS_MASK 0x30 39 #define SUN6I_TFR_CTL_CS(cs) (((cs) << 4) & SUN6I_TFR_CTL_CS_MASK) 40 #define SUN6I_TFR_CTL_CS_MANUAL BIT(6) 41 #define SUN6I_TFR_CTL_CS_LEVEL BIT(7) 42 #define SUN6I_TFR_CTL_DHB BIT(8) 43 #define SUN6I_TFR_CTL_FBS BIT(12) 44 #define SUN6I_TFR_CTL_XCH BIT(31) 45 46 #define SUN6I_INT_CTL_REG 0x10 47 #define SUN6I_INT_CTL_RF_OVF BIT(8) 48 #define SUN6I_INT_CTL_TC BIT(12) 49 50 #define SUN6I_INT_STA_REG 0x14 51 52 #define SUN6I_FIFO_CTL_REG 0x18 53 #define SUN6I_FIFO_CTL_RF_RST BIT(15) 54 #define SUN6I_FIFO_CTL_TF_RST BIT(31) 55 56 #define SUN6I_FIFO_STA_REG 0x1c 57 #define SUN6I_FIFO_STA_RF_CNT_MASK 0x7f 58 #define SUN6I_FIFO_STA_RF_CNT_BITS 0 59 #define SUN6I_FIFO_STA_TF_CNT_MASK 0x7f 60 #define SUN6I_FIFO_STA_TF_CNT_BITS 16 61 62 #define SUN6I_CLK_CTL_REG 0x24 63 #define SUN6I_CLK_CTL_CDR2_MASK 0xff 64 #define SUN6I_CLK_CTL_CDR2(div) (((div) & SUN6I_CLK_CTL_CDR2_MASK) << 0) 65 #define SUN6I_CLK_CTL_CDR1_MASK 0xf 66 #define SUN6I_CLK_CTL_CDR1(div) (((div) & SUN6I_CLK_CTL_CDR1_MASK) << 8) 67 #define SUN6I_CLK_CTL_DRS BIT(12) 68 69 #define SUN6I_BURST_CNT_REG 0x30 70 #define SUN6I_BURST_CNT(cnt) ((cnt) & 0xffffff) 71 72 #define SUN6I_XMIT_CNT_REG 0x34 73 #define SUN6I_XMIT_CNT(cnt) ((cnt) & 0xffffff) 74 75 #define SUN6I_BURST_CTL_CNT_REG 0x38 76 #define SUN6I_BURST_CTL_CNT_STC(cnt) ((cnt) & 0xffffff) 77 78 #define SUN6I_TXDATA_REG 0x200 79 #define SUN6I_RXDATA_REG 0x300 80 81 struct sun6i_spi { 82 struct spi_master *master; 83 void __iomem *base_addr; 84 struct clk *hclk; 85 struct clk *mclk; 86 struct reset_control *rstc; 87 88 struct completion done; 89 90 const u8 *tx_buf; 91 u8 *rx_buf; 92 int len; 93 }; 94 95 static inline u32 sun6i_spi_read(struct sun6i_spi *sspi, u32 reg) 96 { 97 return readl(sspi->base_addr + reg); 98 } 99 100 static inline void sun6i_spi_write(struct sun6i_spi *sspi, u32 reg, u32 value) 101 { 102 writel(value, sspi->base_addr + reg); 103 } 104 105 static inline void sun6i_spi_drain_fifo(struct sun6i_spi *sspi, int len) 106 { 107 u32 reg, cnt; 108 u8 byte; 109 110 /* See how much data is available */ 111 reg = sun6i_spi_read(sspi, SUN6I_FIFO_STA_REG); 112 reg &= SUN6I_FIFO_STA_RF_CNT_MASK; 113 cnt = reg >> SUN6I_FIFO_STA_RF_CNT_BITS; 114 115 if (len > cnt) 116 len = cnt; 117 118 while (len--) { 119 byte = readb(sspi->base_addr + SUN6I_RXDATA_REG); 120 if (sspi->rx_buf) 121 *sspi->rx_buf++ = byte; 122 } 123 } 124 125 static inline void sun6i_spi_fill_fifo(struct sun6i_spi *sspi, int len) 126 { 127 u8 byte; 128 129 if (len > sspi->len) 130 len = sspi->len; 131 132 while (len--) { 133 byte = sspi->tx_buf ? *sspi->tx_buf++ : 0; 134 writeb(byte, sspi->base_addr + SUN6I_TXDATA_REG); 135 sspi->len--; 136 } 137 } 138 139 static void sun6i_spi_set_cs(struct spi_device *spi, bool enable) 140 { 141 struct sun6i_spi *sspi = spi_master_get_devdata(spi->master); 142 u32 reg; 143 144 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); 145 reg &= ~SUN6I_TFR_CTL_CS_MASK; 146 reg |= SUN6I_TFR_CTL_CS(spi->chip_select); 147 148 if (enable) 149 reg |= SUN6I_TFR_CTL_CS_LEVEL; 150 else 151 reg &= ~SUN6I_TFR_CTL_CS_LEVEL; 152 153 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); 154 } 155 156 157 static int sun6i_spi_transfer_one(struct spi_master *master, 158 struct spi_device *spi, 159 struct spi_transfer *tfr) 160 { 161 struct sun6i_spi *sspi = spi_master_get_devdata(master); 162 unsigned int mclk_rate, div, timeout; 163 unsigned int tx_len = 0; 164 int ret = 0; 165 u32 reg; 166 167 /* We don't support transfer larger than the FIFO */ 168 if (tfr->len > SUN6I_FIFO_DEPTH) 169 return -EINVAL; 170 171 reinit_completion(&sspi->done); 172 sspi->tx_buf = tfr->tx_buf; 173 sspi->rx_buf = tfr->rx_buf; 174 sspi->len = tfr->len; 175 176 /* Clear pending interrupts */ 177 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, ~0); 178 179 /* Reset FIFO */ 180 sun6i_spi_write(sspi, SUN6I_FIFO_CTL_REG, 181 SUN6I_FIFO_CTL_RF_RST | SUN6I_FIFO_CTL_TF_RST); 182 183 /* 184 * Setup the transfer control register: Chip Select, 185 * polarities, etc. 186 */ 187 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); 188 189 if (spi->mode & SPI_CPOL) 190 reg |= SUN6I_TFR_CTL_CPOL; 191 else 192 reg &= ~SUN6I_TFR_CTL_CPOL; 193 194 if (spi->mode & SPI_CPHA) 195 reg |= SUN6I_TFR_CTL_CPHA; 196 else 197 reg &= ~SUN6I_TFR_CTL_CPHA; 198 199 if (spi->mode & SPI_LSB_FIRST) 200 reg |= SUN6I_TFR_CTL_FBS; 201 else 202 reg &= ~SUN6I_TFR_CTL_FBS; 203 204 /* 205 * If it's a TX only transfer, we don't want to fill the RX 206 * FIFO with bogus data 207 */ 208 if (sspi->rx_buf) 209 reg &= ~SUN6I_TFR_CTL_DHB; 210 else 211 reg |= SUN6I_TFR_CTL_DHB; 212 213 /* We want to control the chip select manually */ 214 reg |= SUN6I_TFR_CTL_CS_MANUAL; 215 216 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg); 217 218 /* Ensure that we have a parent clock fast enough */ 219 mclk_rate = clk_get_rate(sspi->mclk); 220 if (mclk_rate < (2 * spi->max_speed_hz)) { 221 clk_set_rate(sspi->mclk, 2 * spi->max_speed_hz); 222 mclk_rate = clk_get_rate(sspi->mclk); 223 } 224 225 /* 226 * Setup clock divider. 227 * 228 * We have two choices there. Either we can use the clock 229 * divide rate 1, which is calculated thanks to this formula: 230 * SPI_CLK = MOD_CLK / (2 ^ cdr) 231 * Or we can use CDR2, which is calculated with the formula: 232 * SPI_CLK = MOD_CLK / (2 * (cdr + 1)) 233 * Wether we use the former or the latter is set through the 234 * DRS bit. 235 * 236 * First try CDR2, and if we can't reach the expected 237 * frequency, fall back to CDR1. 238 */ 239 div = mclk_rate / (2 * spi->max_speed_hz); 240 if (div <= (SUN6I_CLK_CTL_CDR2_MASK + 1)) { 241 if (div > 0) 242 div--; 243 244 reg = SUN6I_CLK_CTL_CDR2(div) | SUN6I_CLK_CTL_DRS; 245 } else { 246 div = ilog2(mclk_rate) - ilog2(spi->max_speed_hz); 247 reg = SUN6I_CLK_CTL_CDR1(div); 248 } 249 250 sun6i_spi_write(sspi, SUN6I_CLK_CTL_REG, reg); 251 252 /* Setup the transfer now... */ 253 if (sspi->tx_buf) 254 tx_len = tfr->len; 255 256 /* Setup the counters */ 257 sun6i_spi_write(sspi, SUN6I_BURST_CNT_REG, SUN6I_BURST_CNT(tfr->len)); 258 sun6i_spi_write(sspi, SUN6I_XMIT_CNT_REG, SUN6I_XMIT_CNT(tx_len)); 259 sun6i_spi_write(sspi, SUN6I_BURST_CTL_CNT_REG, 260 SUN6I_BURST_CTL_CNT_STC(tx_len)); 261 262 /* Fill the TX FIFO */ 263 sun6i_spi_fill_fifo(sspi, SUN6I_FIFO_DEPTH); 264 265 /* Enable the interrupts */ 266 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, SUN6I_INT_CTL_TC); 267 268 /* Start the transfer */ 269 reg = sun6i_spi_read(sspi, SUN6I_TFR_CTL_REG); 270 sun6i_spi_write(sspi, SUN6I_TFR_CTL_REG, reg | SUN6I_TFR_CTL_XCH); 271 272 timeout = wait_for_completion_timeout(&sspi->done, 273 msecs_to_jiffies(1000)); 274 if (!timeout) { 275 ret = -ETIMEDOUT; 276 goto out; 277 } 278 279 sun6i_spi_drain_fifo(sspi, SUN6I_FIFO_DEPTH); 280 281 out: 282 sun6i_spi_write(sspi, SUN6I_INT_CTL_REG, 0); 283 284 return ret; 285 } 286 287 static irqreturn_t sun6i_spi_handler(int irq, void *dev_id) 288 { 289 struct sun6i_spi *sspi = dev_id; 290 u32 status = sun6i_spi_read(sspi, SUN6I_INT_STA_REG); 291 292 /* Transfer complete */ 293 if (status & SUN6I_INT_CTL_TC) { 294 sun6i_spi_write(sspi, SUN6I_INT_STA_REG, SUN6I_INT_CTL_TC); 295 complete(&sspi->done); 296 return IRQ_HANDLED; 297 } 298 299 return IRQ_NONE; 300 } 301 302 static int sun6i_spi_runtime_resume(struct device *dev) 303 { 304 struct spi_master *master = dev_get_drvdata(dev); 305 struct sun6i_spi *sspi = spi_master_get_devdata(master); 306 int ret; 307 308 ret = clk_prepare_enable(sspi->hclk); 309 if (ret) { 310 dev_err(dev, "Couldn't enable AHB clock\n"); 311 goto out; 312 } 313 314 ret = clk_prepare_enable(sspi->mclk); 315 if (ret) { 316 dev_err(dev, "Couldn't enable module clock\n"); 317 goto err; 318 } 319 320 ret = reset_control_deassert(sspi->rstc); 321 if (ret) { 322 dev_err(dev, "Couldn't deassert the device from reset\n"); 323 goto err2; 324 } 325 326 sun6i_spi_write(sspi, SUN6I_GBL_CTL_REG, 327 SUN6I_GBL_CTL_BUS_ENABLE | SUN6I_GBL_CTL_MASTER | SUN6I_GBL_CTL_TP); 328 329 return 0; 330 331 err2: 332 clk_disable_unprepare(sspi->mclk); 333 err: 334 clk_disable_unprepare(sspi->hclk); 335 out: 336 return ret; 337 } 338 339 static int sun6i_spi_runtime_suspend(struct device *dev) 340 { 341 struct spi_master *master = dev_get_drvdata(dev); 342 struct sun6i_spi *sspi = spi_master_get_devdata(master); 343 344 reset_control_assert(sspi->rstc); 345 clk_disable_unprepare(sspi->mclk); 346 clk_disable_unprepare(sspi->hclk); 347 348 return 0; 349 } 350 351 static int sun6i_spi_probe(struct platform_device *pdev) 352 { 353 struct spi_master *master; 354 struct sun6i_spi *sspi; 355 struct resource *res; 356 int ret = 0, irq; 357 358 master = spi_alloc_master(&pdev->dev, sizeof(struct sun6i_spi)); 359 if (!master) { 360 dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); 361 return -ENOMEM; 362 } 363 364 platform_set_drvdata(pdev, master); 365 sspi = spi_master_get_devdata(master); 366 367 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 368 sspi->base_addr = devm_ioremap_resource(&pdev->dev, res); 369 if (IS_ERR(sspi->base_addr)) { 370 ret = PTR_ERR(sspi->base_addr); 371 goto err_free_master; 372 } 373 374 irq = platform_get_irq(pdev, 0); 375 if (irq < 0) { 376 dev_err(&pdev->dev, "No spi IRQ specified\n"); 377 ret = -ENXIO; 378 goto err_free_master; 379 } 380 381 ret = devm_request_irq(&pdev->dev, irq, sun6i_spi_handler, 382 0, "sun6i-spi", sspi); 383 if (ret) { 384 dev_err(&pdev->dev, "Cannot request IRQ\n"); 385 goto err_free_master; 386 } 387 388 sspi->master = master; 389 master->set_cs = sun6i_spi_set_cs; 390 master->transfer_one = sun6i_spi_transfer_one; 391 master->num_chipselect = 4; 392 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LSB_FIRST; 393 master->bits_per_word_mask = SPI_BPW_MASK(8); 394 master->dev.of_node = pdev->dev.of_node; 395 master->auto_runtime_pm = true; 396 397 sspi->hclk = devm_clk_get(&pdev->dev, "ahb"); 398 if (IS_ERR(sspi->hclk)) { 399 dev_err(&pdev->dev, "Unable to acquire AHB clock\n"); 400 ret = PTR_ERR(sspi->hclk); 401 goto err_free_master; 402 } 403 404 sspi->mclk = devm_clk_get(&pdev->dev, "mod"); 405 if (IS_ERR(sspi->mclk)) { 406 dev_err(&pdev->dev, "Unable to acquire module clock\n"); 407 ret = PTR_ERR(sspi->mclk); 408 goto err_free_master; 409 } 410 411 init_completion(&sspi->done); 412 413 sspi->rstc = devm_reset_control_get(&pdev->dev, NULL); 414 if (IS_ERR(sspi->rstc)) { 415 dev_err(&pdev->dev, "Couldn't get reset controller\n"); 416 ret = PTR_ERR(sspi->rstc); 417 goto err_free_master; 418 } 419 420 /* 421 * This wake-up/shutdown pattern is to be able to have the 422 * device woken up, even if runtime_pm is disabled 423 */ 424 ret = sun6i_spi_runtime_resume(&pdev->dev); 425 if (ret) { 426 dev_err(&pdev->dev, "Couldn't resume the device\n"); 427 goto err_free_master; 428 } 429 430 pm_runtime_set_active(&pdev->dev); 431 pm_runtime_enable(&pdev->dev); 432 pm_runtime_idle(&pdev->dev); 433 434 ret = devm_spi_register_master(&pdev->dev, master); 435 if (ret) { 436 dev_err(&pdev->dev, "cannot register SPI master\n"); 437 goto err_pm_disable; 438 } 439 440 return 0; 441 442 err_pm_disable: 443 pm_runtime_disable(&pdev->dev); 444 sun6i_spi_runtime_suspend(&pdev->dev); 445 err_free_master: 446 spi_master_put(master); 447 return ret; 448 } 449 450 static int sun6i_spi_remove(struct platform_device *pdev) 451 { 452 pm_runtime_disable(&pdev->dev); 453 454 return 0; 455 } 456 457 static const struct of_device_id sun6i_spi_match[] = { 458 { .compatible = "allwinner,sun6i-a31-spi", }, 459 {} 460 }; 461 MODULE_DEVICE_TABLE(of, sun6i_spi_match); 462 463 static const struct dev_pm_ops sun6i_spi_pm_ops = { 464 .runtime_resume = sun6i_spi_runtime_resume, 465 .runtime_suspend = sun6i_spi_runtime_suspend, 466 }; 467 468 static struct platform_driver sun6i_spi_driver = { 469 .probe = sun6i_spi_probe, 470 .remove = sun6i_spi_remove, 471 .driver = { 472 .name = "sun6i-spi", 473 .of_match_table = sun6i_spi_match, 474 .pm = &sun6i_spi_pm_ops, 475 }, 476 }; 477 module_platform_driver(sun6i_spi_driver); 478 479 MODULE_AUTHOR("Pan Nan <pannan@allwinnertech.com>"); 480 MODULE_AUTHOR("Maxime Ripard <maxime.ripard@free-electrons.com>"); 481 MODULE_DESCRIPTION("Allwinner A31 SPI controller driver"); 482 MODULE_LICENSE("GPL"); 483