1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Socionext SPI flash controller F_OSPI driver 4 * Copyright (C) 2021 Socionext Inc. 5 */ 6 7 #include <linux/bitfield.h> 8 #include <linux/clk.h> 9 #include <linux/io.h> 10 #include <linux/iopoll.h> 11 #include <linux/module.h> 12 #include <linux/mutex.h> 13 #include <linux/of.h> 14 #include <linux/platform_device.h> 15 #include <linux/spi/spi.h> 16 #include <linux/spi/spi-mem.h> 17 18 /* Registers */ 19 #define OSPI_PROT_CTL_INDIR 0x00 20 #define OSPI_PROT_MODE_DATA_MASK GENMASK(31, 30) 21 #define OSPI_PROT_MODE_ALT_MASK GENMASK(29, 28) 22 #define OSPI_PROT_MODE_ADDR_MASK GENMASK(27, 26) 23 #define OSPI_PROT_MODE_CODE_MASK GENMASK(25, 24) 24 #define OSPI_PROT_MODE_SINGLE 0 25 #define OSPI_PROT_MODE_DUAL 1 26 #define OSPI_PROT_MODE_QUAD 2 27 #define OSPI_PROT_MODE_OCTAL 3 28 #define OSPI_PROT_DATA_RATE_DATA BIT(23) 29 #define OSPI_PROT_DATA_RATE_ALT BIT(22) 30 #define OSPI_PROT_DATA_RATE_ADDR BIT(21) 31 #define OSPI_PROT_DATA_RATE_CODE BIT(20) 32 #define OSPI_PROT_SDR 0 33 #define OSPI_PROT_DDR 1 34 #define OSPI_PROT_BIT_POS_DATA BIT(19) 35 #define OSPI_PROT_BIT_POS_ALT BIT(18) 36 #define OSPI_PROT_BIT_POS_ADDR BIT(17) 37 #define OSPI_PROT_BIT_POS_CODE BIT(16) 38 #define OSPI_PROT_SAMP_EDGE BIT(12) 39 #define OSPI_PROT_DATA_UNIT_MASK GENMASK(11, 10) 40 #define OSPI_PROT_DATA_UNIT_1B 0 41 #define OSPI_PROT_DATA_UNIT_2B 1 42 #define OSPI_PROT_DATA_UNIT_4B 3 43 #define OSPI_PROT_TRANS_DIR_WRITE BIT(9) 44 #define OSPI_PROT_DATA_EN BIT(8) 45 #define OSPI_PROT_ALT_SIZE_MASK GENMASK(7, 5) 46 #define OSPI_PROT_ADDR_SIZE_MASK GENMASK(4, 2) 47 #define OSPI_PROT_CODE_SIZE_MASK GENMASK(1, 0) 48 49 #define OSPI_CLK_CTL 0x10 50 #define OSPI_CLK_CTL_BOOT_INT_CLK_EN BIT(16) 51 #define OSPI_CLK_CTL_PHA BIT(12) 52 #define OSPI_CLK_CTL_PHA_180 0 53 #define OSPI_CLK_CTL_PHA_90 1 54 #define OSPI_CLK_CTL_DIV GENMASK(9, 8) 55 #define OSPI_CLK_CTL_DIV_1 0 56 #define OSPI_CLK_CTL_DIV_2 1 57 #define OSPI_CLK_CTL_DIV_4 2 58 #define OSPI_CLK_CTL_DIV_8 3 59 #define OSPI_CLK_CTL_INT_CLK_EN BIT(0) 60 61 #define OSPI_CS_CTL1 0x14 62 #define OSPI_CS_CTL2 0x18 63 #define OSPI_SSEL 0x20 64 #define OSPI_CMD_IDX_INDIR 0x40 65 #define OSPI_ADDR 0x50 66 #define OSPI_ALT_INDIR 0x60 67 #define OSPI_DMY_INDIR 0x70 68 #define OSPI_DAT 0x80 69 #define OSPI_DAT_SWP_INDIR 0x90 70 71 #define OSPI_DAT_SIZE_INDIR 0xA0 72 #define OSPI_DAT_SIZE_EN BIT(15) 73 #define OSPI_DAT_SIZE_MASK GENMASK(10, 0) 74 #define OSPI_DAT_SIZE_MAX (OSPI_DAT_SIZE_MASK + 1) 75 76 #define OSPI_TRANS_CTL 0xC0 77 #define OSPI_TRANS_CTL_STOP_REQ BIT(1) /* RW1AC */ 78 #define OSPI_TRANS_CTL_START_REQ BIT(0) /* RW1AC */ 79 80 #define OSPI_ACC_MODE 0xC4 81 #define OSPI_ACC_MODE_BOOT_DISABLE BIT(0) 82 83 #define OSPI_SWRST 0xD0 84 #define OSPI_SWRST_INDIR_WRITE_FIFO BIT(9) /* RW1AC */ 85 #define OSPI_SWRST_INDIR_READ_FIFO BIT(8) /* RW1AC */ 86 87 #define OSPI_STAT 0xE0 88 #define OSPI_STAT_IS_AXI_WRITING BIT(10) 89 #define OSPI_STAT_IS_AXI_READING BIT(9) 90 #define OSPI_STAT_IS_SPI_INT_CLK_STOP BIT(4) 91 #define OSPI_STAT_IS_SPI_IDLE BIT(3) 92 93 #define OSPI_IRQ 0xF0 94 #define OSPI_IRQ_CS_DEASSERT BIT(8) 95 #define OSPI_IRQ_WRITE_BUF_READY BIT(2) 96 #define OSPI_IRQ_READ_BUF_READY BIT(1) 97 #define OSPI_IRQ_CS_TRANS_COMP BIT(0) 98 #define OSPI_IRQ_ALL \ 99 (OSPI_IRQ_CS_DEASSERT | OSPI_IRQ_WRITE_BUF_READY \ 100 | OSPI_IRQ_READ_BUF_READY | OSPI_IRQ_CS_TRANS_COMP) 101 102 #define OSPI_IRQ_STAT_EN 0xF4 103 #define OSPI_IRQ_SIG_EN 0xF8 104 105 /* Parameters */ 106 #define OSPI_NUM_CS 4 107 #define OSPI_DUMMY_CYCLE_MAX 255 108 #define OSPI_WAIT_MAX_MSEC 100 109 110 struct f_ospi { 111 void __iomem *base; 112 struct device *dev; 113 struct clk *clk; 114 struct mutex mlock; 115 }; 116 117 static u32 f_ospi_get_dummy_cycle(const struct spi_mem_op *op) 118 { 119 if (!op->dummy.nbytes) 120 return 0; 121 122 return (op->dummy.nbytes * 8) / op->dummy.buswidth; 123 } 124 125 static void f_ospi_clear_irq(struct f_ospi *ospi) 126 { 127 writel(OSPI_IRQ_CS_DEASSERT | OSPI_IRQ_CS_TRANS_COMP, 128 ospi->base + OSPI_IRQ); 129 } 130 131 static void f_ospi_enable_irq_status(struct f_ospi *ospi, u32 irq_bits) 132 { 133 u32 val; 134 135 val = readl(ospi->base + OSPI_IRQ_STAT_EN); 136 val |= irq_bits; 137 writel(val, ospi->base + OSPI_IRQ_STAT_EN); 138 } 139 140 static void f_ospi_disable_irq_status(struct f_ospi *ospi, u32 irq_bits) 141 { 142 u32 val; 143 144 val = readl(ospi->base + OSPI_IRQ_STAT_EN); 145 val &= ~irq_bits; 146 writel(val, ospi->base + OSPI_IRQ_STAT_EN); 147 } 148 149 static void f_ospi_disable_irq_output(struct f_ospi *ospi, u32 irq_bits) 150 { 151 u32 val; 152 153 val = readl(ospi->base + OSPI_IRQ_SIG_EN); 154 val &= ~irq_bits; 155 writel(val, ospi->base + OSPI_IRQ_SIG_EN); 156 } 157 158 static int f_ospi_prepare_config(struct f_ospi *ospi) 159 { 160 u32 val, stat0, stat1; 161 162 /* G4: Disable internal clock */ 163 val = readl(ospi->base + OSPI_CLK_CTL); 164 val &= ~(OSPI_CLK_CTL_BOOT_INT_CLK_EN | OSPI_CLK_CTL_INT_CLK_EN); 165 writel(val, ospi->base + OSPI_CLK_CTL); 166 167 /* G5: Wait for stop */ 168 stat0 = OSPI_STAT_IS_AXI_WRITING | OSPI_STAT_IS_AXI_READING; 169 stat1 = OSPI_STAT_IS_SPI_IDLE | OSPI_STAT_IS_SPI_INT_CLK_STOP; 170 171 return readl_poll_timeout(ospi->base + OSPI_STAT, 172 val, (val & (stat0 | stat1)) == stat1, 173 0, OSPI_WAIT_MAX_MSEC); 174 } 175 176 static int f_ospi_unprepare_config(struct f_ospi *ospi) 177 { 178 u32 val; 179 180 /* G11: Enable internal clock */ 181 val = readl(ospi->base + OSPI_CLK_CTL); 182 val |= OSPI_CLK_CTL_BOOT_INT_CLK_EN | OSPI_CLK_CTL_INT_CLK_EN; 183 writel(val, ospi->base + OSPI_CLK_CTL); 184 185 /* G12: Wait for clock to start */ 186 return readl_poll_timeout(ospi->base + OSPI_STAT, 187 val, !(val & OSPI_STAT_IS_SPI_INT_CLK_STOP), 188 0, OSPI_WAIT_MAX_MSEC); 189 } 190 191 static void f_ospi_config_clk(struct f_ospi *ospi, u32 device_hz) 192 { 193 long rate_hz = clk_get_rate(ospi->clk); 194 u32 div = DIV_ROUND_UP(rate_hz, device_hz); 195 u32 div_reg; 196 u32 val; 197 198 if (rate_hz < device_hz) { 199 dev_warn(ospi->dev, "Device frequency too large: %d\n", 200 device_hz); 201 div_reg = OSPI_CLK_CTL_DIV_1; 202 } else { 203 if (div == 1) { 204 div_reg = OSPI_CLK_CTL_DIV_1; 205 } else if (div == 2) { 206 div_reg = OSPI_CLK_CTL_DIV_2; 207 } else if (div <= 4) { 208 div_reg = OSPI_CLK_CTL_DIV_4; 209 } else if (div <= 8) { 210 div_reg = OSPI_CLK_CTL_DIV_8; 211 } else { 212 dev_warn(ospi->dev, "Device frequency too small: %d\n", 213 device_hz); 214 div_reg = OSPI_CLK_CTL_DIV_8; 215 } 216 } 217 218 /* 219 * G7: Set clock mode 220 * clock phase is fixed at 180 degrees and configure edge direction 221 * instead. 222 */ 223 val = readl(ospi->base + OSPI_CLK_CTL); 224 225 val &= ~(OSPI_CLK_CTL_PHA | OSPI_CLK_CTL_DIV); 226 val |= FIELD_PREP(OSPI_CLK_CTL_PHA, OSPI_CLK_CTL_PHA_180) 227 | FIELD_PREP(OSPI_CLK_CTL_DIV, div_reg); 228 229 writel(val, ospi->base + OSPI_CLK_CTL); 230 } 231 232 static void f_ospi_config_dll(struct f_ospi *ospi) 233 { 234 /* G8: Configure DLL, nothing */ 235 } 236 237 static u8 f_ospi_get_mode(struct f_ospi *ospi, int width, int data_size) 238 { 239 u8 mode = OSPI_PROT_MODE_SINGLE; 240 241 switch (width) { 242 case 1: 243 mode = OSPI_PROT_MODE_SINGLE; 244 break; 245 case 2: 246 mode = OSPI_PROT_MODE_DUAL; 247 break; 248 case 4: 249 mode = OSPI_PROT_MODE_QUAD; 250 break; 251 case 8: 252 mode = OSPI_PROT_MODE_OCTAL; 253 break; 254 default: 255 if (data_size) 256 dev_err(ospi->dev, "Invalid buswidth: %d\n", width); 257 break; 258 } 259 260 return mode; 261 } 262 263 static void f_ospi_config_indir_protocol(struct f_ospi *ospi, 264 struct spi_mem *mem, 265 const struct spi_mem_op *op) 266 { 267 struct spi_device *spi = mem->spi; 268 u8 mode; 269 u32 prot = 0, val; 270 int unit; 271 272 /* Set one chip select */ 273 writel(BIT(spi_get_chipselect(spi, 0)), ospi->base + OSPI_SSEL); 274 275 mode = f_ospi_get_mode(ospi, op->cmd.buswidth, 1); 276 prot |= FIELD_PREP(OSPI_PROT_MODE_CODE_MASK, mode); 277 278 mode = f_ospi_get_mode(ospi, op->addr.buswidth, op->addr.nbytes); 279 prot |= FIELD_PREP(OSPI_PROT_MODE_ADDR_MASK, mode); 280 281 mode = f_ospi_get_mode(ospi, op->data.buswidth, op->data.nbytes); 282 prot |= FIELD_PREP(OSPI_PROT_MODE_DATA_MASK, mode); 283 284 prot |= FIELD_PREP(OSPI_PROT_DATA_RATE_DATA, OSPI_PROT_SDR); 285 prot |= FIELD_PREP(OSPI_PROT_DATA_RATE_ALT, OSPI_PROT_SDR); 286 prot |= FIELD_PREP(OSPI_PROT_DATA_RATE_ADDR, OSPI_PROT_SDR); 287 prot |= FIELD_PREP(OSPI_PROT_DATA_RATE_CODE, OSPI_PROT_SDR); 288 289 if (spi->mode & SPI_LSB_FIRST) 290 prot |= OSPI_PROT_BIT_POS_DATA | OSPI_PROT_BIT_POS_ALT 291 | OSPI_PROT_BIT_POS_ADDR | OSPI_PROT_BIT_POS_CODE; 292 293 if (spi->mode & SPI_CPHA) 294 prot |= OSPI_PROT_SAMP_EDGE; 295 296 /* Examine nbytes % 4 */ 297 switch (op->data.nbytes & 0x3) { 298 case 0: 299 unit = OSPI_PROT_DATA_UNIT_4B; 300 val = 0; 301 break; 302 case 2: 303 unit = OSPI_PROT_DATA_UNIT_2B; 304 val = OSPI_DAT_SIZE_EN | (op->data.nbytes - 1); 305 break; 306 default: 307 unit = OSPI_PROT_DATA_UNIT_1B; 308 val = OSPI_DAT_SIZE_EN | (op->data.nbytes - 1); 309 break; 310 } 311 prot |= FIELD_PREP(OSPI_PROT_DATA_UNIT_MASK, unit); 312 313 switch (op->data.dir) { 314 case SPI_MEM_DATA_IN: 315 prot |= OSPI_PROT_DATA_EN; 316 break; 317 318 case SPI_MEM_DATA_OUT: 319 prot |= OSPI_PROT_TRANS_DIR_WRITE | OSPI_PROT_DATA_EN; 320 break; 321 322 case SPI_MEM_NO_DATA: 323 prot |= OSPI_PROT_TRANS_DIR_WRITE; 324 break; 325 326 default: 327 dev_warn(ospi->dev, "Unsupported direction"); 328 break; 329 } 330 331 prot |= FIELD_PREP(OSPI_PROT_ADDR_SIZE_MASK, op->addr.nbytes); 332 prot |= FIELD_PREP(OSPI_PROT_CODE_SIZE_MASK, 1); /* 1byte */ 333 334 writel(prot, ospi->base + OSPI_PROT_CTL_INDIR); 335 writel(val, ospi->base + OSPI_DAT_SIZE_INDIR); 336 } 337 338 static int f_ospi_indir_prepare_op(struct f_ospi *ospi, struct spi_mem *mem, 339 const struct spi_mem_op *op) 340 { 341 u32 irq_stat_en; 342 int ret; 343 344 ret = f_ospi_prepare_config(ospi); 345 if (ret) 346 return ret; 347 348 f_ospi_config_clk(ospi, op->max_freq); 349 350 f_ospi_config_indir_protocol(ospi, mem, op); 351 352 writel(f_ospi_get_dummy_cycle(op), ospi->base + OSPI_DMY_INDIR); 353 writel(op->addr.val, ospi->base + OSPI_ADDR); 354 writel(op->cmd.opcode, ospi->base + OSPI_CMD_IDX_INDIR); 355 356 f_ospi_clear_irq(ospi); 357 358 switch (op->data.dir) { 359 case SPI_MEM_DATA_IN: 360 irq_stat_en = OSPI_IRQ_READ_BUF_READY | OSPI_IRQ_CS_TRANS_COMP; 361 break; 362 363 case SPI_MEM_DATA_OUT: 364 irq_stat_en = OSPI_IRQ_WRITE_BUF_READY | OSPI_IRQ_CS_TRANS_COMP; 365 break; 366 367 case SPI_MEM_NO_DATA: 368 irq_stat_en = OSPI_IRQ_CS_TRANS_COMP; 369 break; 370 371 default: 372 dev_warn(ospi->dev, "Unsupported direction"); 373 irq_stat_en = 0; 374 } 375 376 f_ospi_disable_irq_status(ospi, ~irq_stat_en); 377 f_ospi_enable_irq_status(ospi, irq_stat_en); 378 379 return f_ospi_unprepare_config(ospi); 380 } 381 382 static void f_ospi_indir_start_xfer(struct f_ospi *ospi) 383 { 384 /* Write only 1, auto cleared */ 385 writel(OSPI_TRANS_CTL_START_REQ, ospi->base + OSPI_TRANS_CTL); 386 } 387 388 static void f_ospi_indir_stop_xfer(struct f_ospi *ospi) 389 { 390 /* Write only 1, auto cleared */ 391 writel(OSPI_TRANS_CTL_STOP_REQ, ospi->base + OSPI_TRANS_CTL); 392 } 393 394 static int f_ospi_indir_wait_xfer_complete(struct f_ospi *ospi) 395 { 396 u32 val; 397 398 return readl_poll_timeout(ospi->base + OSPI_IRQ, val, 399 val & OSPI_IRQ_CS_TRANS_COMP, 400 0, OSPI_WAIT_MAX_MSEC); 401 } 402 403 static int f_ospi_indir_read(struct f_ospi *ospi, struct spi_mem *mem, 404 const struct spi_mem_op *op) 405 { 406 u8 *buf = op->data.buf.in; 407 u32 val; 408 int i, ret; 409 410 mutex_lock(&ospi->mlock); 411 412 /* E1-2: Prepare transfer operation */ 413 ret = f_ospi_indir_prepare_op(ospi, mem, op); 414 if (ret) 415 goto out; 416 417 f_ospi_indir_start_xfer(ospi); 418 419 /* E3-4: Wait for ready and read data */ 420 for (i = 0; i < op->data.nbytes; i++) { 421 ret = readl_poll_timeout(ospi->base + OSPI_IRQ, val, 422 val & OSPI_IRQ_READ_BUF_READY, 423 0, OSPI_WAIT_MAX_MSEC); 424 if (ret) 425 goto out; 426 427 buf[i] = readl(ospi->base + OSPI_DAT) & 0xFF; 428 } 429 430 /* E5-6: Stop transfer if data size is nothing */ 431 if (!(readl(ospi->base + OSPI_DAT_SIZE_INDIR) & OSPI_DAT_SIZE_EN)) 432 f_ospi_indir_stop_xfer(ospi); 433 434 /* E7-8: Wait for completion and clear */ 435 ret = f_ospi_indir_wait_xfer_complete(ospi); 436 if (ret) 437 goto out; 438 439 writel(OSPI_IRQ_CS_TRANS_COMP, ospi->base + OSPI_IRQ); 440 441 /* E9: Do nothing if data size is valid */ 442 if (readl(ospi->base + OSPI_DAT_SIZE_INDIR) & OSPI_DAT_SIZE_EN) 443 goto out; 444 445 /* E10-11: Reset and check read fifo */ 446 writel(OSPI_SWRST_INDIR_READ_FIFO, ospi->base + OSPI_SWRST); 447 448 ret = readl_poll_timeout(ospi->base + OSPI_SWRST, val, 449 !(val & OSPI_SWRST_INDIR_READ_FIFO), 450 0, OSPI_WAIT_MAX_MSEC); 451 out: 452 mutex_unlock(&ospi->mlock); 453 454 return ret; 455 } 456 457 static int f_ospi_indir_write(struct f_ospi *ospi, struct spi_mem *mem, 458 const struct spi_mem_op *op) 459 { 460 u8 *buf = (u8 *)op->data.buf.out; 461 u32 val; 462 int i, ret; 463 464 mutex_lock(&ospi->mlock); 465 466 /* F1-3: Prepare transfer operation */ 467 ret = f_ospi_indir_prepare_op(ospi, mem, op); 468 if (ret) 469 goto out; 470 471 f_ospi_indir_start_xfer(ospi); 472 473 if (!(readl(ospi->base + OSPI_PROT_CTL_INDIR) & OSPI_PROT_DATA_EN)) 474 goto nodata; 475 476 /* F4-5: Wait for buffer ready and write data */ 477 for (i = 0; i < op->data.nbytes; i++) { 478 ret = readl_poll_timeout(ospi->base + OSPI_IRQ, val, 479 val & OSPI_IRQ_WRITE_BUF_READY, 480 0, OSPI_WAIT_MAX_MSEC); 481 if (ret) 482 goto out; 483 484 writel(buf[i], ospi->base + OSPI_DAT); 485 } 486 487 /* F6-7: Stop transfer if data size is nothing */ 488 if (!(readl(ospi->base + OSPI_DAT_SIZE_INDIR) & OSPI_DAT_SIZE_EN)) 489 f_ospi_indir_stop_xfer(ospi); 490 491 nodata: 492 /* F8-9: Wait for completion and clear */ 493 ret = f_ospi_indir_wait_xfer_complete(ospi); 494 if (ret) 495 goto out; 496 497 writel(OSPI_IRQ_CS_TRANS_COMP, ospi->base + OSPI_IRQ); 498 out: 499 mutex_unlock(&ospi->mlock); 500 501 return ret; 502 } 503 504 static int f_ospi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) 505 { 506 struct f_ospi *ospi = spi_controller_get_devdata(mem->spi->controller); 507 int err = 0; 508 509 switch (op->data.dir) { 510 case SPI_MEM_DATA_IN: 511 err = f_ospi_indir_read(ospi, mem, op); 512 break; 513 514 case SPI_MEM_DATA_OUT: 515 fallthrough; 516 case SPI_MEM_NO_DATA: 517 err = f_ospi_indir_write(ospi, mem, op); 518 break; 519 520 default: 521 dev_warn(ospi->dev, "Unsupported direction"); 522 err = -EOPNOTSUPP; 523 } 524 525 return err; 526 } 527 528 static bool f_ospi_supports_op_width(struct spi_mem *mem, 529 const struct spi_mem_op *op) 530 { 531 static const u8 width_available[] = { 0, 1, 2, 4, 8 }; 532 u8 width_op[] = { op->cmd.buswidth, op->addr.buswidth, 533 op->dummy.buswidth, op->data.buswidth }; 534 bool is_match_found; 535 int i, j; 536 537 for (i = 0; i < ARRAY_SIZE(width_op); i++) { 538 is_match_found = false; 539 540 for (j = 0; j < ARRAY_SIZE(width_available); j++) { 541 if (width_op[i] == width_available[j]) { 542 is_match_found = true; 543 break; 544 } 545 } 546 547 if (!is_match_found) 548 return false; 549 } 550 551 return true; 552 } 553 554 static bool f_ospi_supports_op(struct spi_mem *mem, 555 const struct spi_mem_op *op) 556 { 557 if (f_ospi_get_dummy_cycle(op) > OSPI_DUMMY_CYCLE_MAX) 558 return false; 559 560 if (op->addr.nbytes > 4) 561 return false; 562 563 if (!f_ospi_supports_op_width(mem, op)) 564 return false; 565 566 return spi_mem_default_supports_op(mem, op); 567 } 568 569 static int f_ospi_adjust_op_size(struct spi_mem *mem, struct spi_mem_op *op) 570 { 571 op->data.nbytes = min_t(int, op->data.nbytes, OSPI_DAT_SIZE_MAX); 572 573 return 0; 574 } 575 576 static const struct spi_controller_mem_ops f_ospi_mem_ops = { 577 .adjust_op_size = f_ospi_adjust_op_size, 578 .supports_op = f_ospi_supports_op, 579 .exec_op = f_ospi_exec_op, 580 }; 581 582 static const struct spi_controller_mem_caps f_ospi_mem_caps = { 583 .per_op_freq = true, 584 }; 585 586 static int f_ospi_init(struct f_ospi *ospi) 587 { 588 int ret; 589 590 ret = f_ospi_prepare_config(ospi); 591 if (ret) 592 return ret; 593 594 /* Disable boot signal */ 595 writel(OSPI_ACC_MODE_BOOT_DISABLE, ospi->base + OSPI_ACC_MODE); 596 597 f_ospi_config_dll(ospi); 598 599 /* Disable IRQ */ 600 f_ospi_clear_irq(ospi); 601 f_ospi_disable_irq_status(ospi, OSPI_IRQ_ALL); 602 f_ospi_disable_irq_output(ospi, OSPI_IRQ_ALL); 603 604 return f_ospi_unprepare_config(ospi); 605 } 606 607 static int f_ospi_probe(struct platform_device *pdev) 608 { 609 struct spi_controller *ctlr; 610 struct device *dev = &pdev->dev; 611 struct f_ospi *ospi; 612 u32 num_cs = OSPI_NUM_CS; 613 int ret; 614 615 ctlr = spi_alloc_host(dev, sizeof(*ospi)); 616 if (!ctlr) 617 return -ENOMEM; 618 619 ctlr->mode_bits = SPI_TX_DUAL | SPI_TX_QUAD | SPI_TX_OCTAL 620 | SPI_RX_DUAL | SPI_RX_QUAD | SPI_RX_OCTAL 621 | SPI_MODE_0 | SPI_MODE_1 | SPI_LSB_FIRST; 622 ctlr->mem_ops = &f_ospi_mem_ops; 623 ctlr->mem_caps = &f_ospi_mem_caps; 624 ctlr->bus_num = -1; 625 of_property_read_u32(dev->of_node, "num-cs", &num_cs); 626 if (num_cs > OSPI_NUM_CS) { 627 dev_err(dev, "num-cs too large: %d\n", num_cs); 628 return -ENOMEM; 629 } 630 ctlr->num_chipselect = num_cs; 631 ctlr->dev.of_node = dev->of_node; 632 633 ospi = spi_controller_get_devdata(ctlr); 634 ospi->dev = dev; 635 636 platform_set_drvdata(pdev, ospi); 637 638 ospi->base = devm_platform_ioremap_resource(pdev, 0); 639 if (IS_ERR(ospi->base)) { 640 ret = PTR_ERR(ospi->base); 641 goto err_put_ctlr; 642 } 643 644 ospi->clk = devm_clk_get_enabled(dev, NULL); 645 if (IS_ERR(ospi->clk)) { 646 ret = PTR_ERR(ospi->clk); 647 goto err_put_ctlr; 648 } 649 650 mutex_init(&ospi->mlock); 651 652 ret = f_ospi_init(ospi); 653 if (ret) 654 goto err_destroy_mutex; 655 656 ret = devm_spi_register_controller(dev, ctlr); 657 if (ret) 658 goto err_destroy_mutex; 659 660 return 0; 661 662 err_destroy_mutex: 663 mutex_destroy(&ospi->mlock); 664 665 err_put_ctlr: 666 spi_controller_put(ctlr); 667 668 return ret; 669 } 670 671 static void f_ospi_remove(struct platform_device *pdev) 672 { 673 struct f_ospi *ospi = platform_get_drvdata(pdev); 674 675 mutex_destroy(&ospi->mlock); 676 } 677 678 static const struct of_device_id f_ospi_dt_ids[] = { 679 { .compatible = "socionext,f-ospi" }, 680 {} 681 }; 682 MODULE_DEVICE_TABLE(of, f_ospi_dt_ids); 683 684 static struct platform_driver f_ospi_driver = { 685 .driver = { 686 .name = "socionext,f-ospi", 687 .of_match_table = f_ospi_dt_ids, 688 }, 689 .probe = f_ospi_probe, 690 .remove = f_ospi_remove, 691 }; 692 module_platform_driver(f_ospi_driver); 693 694 MODULE_DESCRIPTION("Socionext F_OSPI controller driver"); 695 MODULE_AUTHOR("Socionext Inc."); 696 MODULE_AUTHOR("Kunihiko Hayashi <hayashi.kunihiko@socionext.com>"); 697 MODULE_LICENSE("GPL"); 698