1484a9a68SYash Shah // SPDX-License-Identifier: GPL-2.0
2484a9a68SYash Shah //
3484a9a68SYash Shah // Copyright 2018 SiFive, Inc.
4484a9a68SYash Shah //
5484a9a68SYash Shah // SiFive SPI controller driver (master mode only)
6484a9a68SYash Shah //
7484a9a68SYash Shah // Author: SiFive, Inc.
8484a9a68SYash Shah // sifive@sifive.com
9484a9a68SYash Shah
10484a9a68SYash Shah #include <linux/clk.h>
11484a9a68SYash Shah #include <linux/module.h>
12484a9a68SYash Shah #include <linux/interrupt.h>
13484a9a68SYash Shah #include <linux/of.h>
14484a9a68SYash Shah #include <linux/platform_device.h>
15484a9a68SYash Shah #include <linux/spi/spi.h>
16484a9a68SYash Shah #include <linux/io.h>
17484a9a68SYash Shah #include <linux/log2.h>
18484a9a68SYash Shah
19484a9a68SYash Shah #define SIFIVE_SPI_DRIVER_NAME "sifive_spi"
20484a9a68SYash Shah
21484a9a68SYash Shah #define SIFIVE_SPI_MAX_CS 32
22484a9a68SYash Shah #define SIFIVE_SPI_DEFAULT_DEPTH 8
23484a9a68SYash Shah #define SIFIVE_SPI_DEFAULT_MAX_BITS 8
24484a9a68SYash Shah
25484a9a68SYash Shah /* register offsets */
26484a9a68SYash Shah #define SIFIVE_SPI_REG_SCKDIV 0x00 /* Serial clock divisor */
27484a9a68SYash Shah #define SIFIVE_SPI_REG_SCKMODE 0x04 /* Serial clock mode */
28484a9a68SYash Shah #define SIFIVE_SPI_REG_CSID 0x10 /* Chip select ID */
29484a9a68SYash Shah #define SIFIVE_SPI_REG_CSDEF 0x14 /* Chip select default */
30484a9a68SYash Shah #define SIFIVE_SPI_REG_CSMODE 0x18 /* Chip select mode */
31484a9a68SYash Shah #define SIFIVE_SPI_REG_DELAY0 0x28 /* Delay control 0 */
32484a9a68SYash Shah #define SIFIVE_SPI_REG_DELAY1 0x2c /* Delay control 1 */
33484a9a68SYash Shah #define SIFIVE_SPI_REG_FMT 0x40 /* Frame format */
34484a9a68SYash Shah #define SIFIVE_SPI_REG_TXDATA 0x48 /* Tx FIFO data */
35484a9a68SYash Shah #define SIFIVE_SPI_REG_RXDATA 0x4c /* Rx FIFO data */
36484a9a68SYash Shah #define SIFIVE_SPI_REG_TXMARK 0x50 /* Tx FIFO watermark */
37484a9a68SYash Shah #define SIFIVE_SPI_REG_RXMARK 0x54 /* Rx FIFO watermark */
38484a9a68SYash Shah #define SIFIVE_SPI_REG_FCTRL 0x60 /* SPI flash interface control */
39484a9a68SYash Shah #define SIFIVE_SPI_REG_FFMT 0x64 /* SPI flash instruction format */
40484a9a68SYash Shah #define SIFIVE_SPI_REG_IE 0x70 /* Interrupt Enable Register */
41484a9a68SYash Shah #define SIFIVE_SPI_REG_IP 0x74 /* Interrupt Pendings Register */
42484a9a68SYash Shah
43484a9a68SYash Shah /* sckdiv bits */
44484a9a68SYash Shah #define SIFIVE_SPI_SCKDIV_DIV_MASK 0xfffU
45484a9a68SYash Shah
46484a9a68SYash Shah /* sckmode bits */
47484a9a68SYash Shah #define SIFIVE_SPI_SCKMODE_PHA BIT(0)
48484a9a68SYash Shah #define SIFIVE_SPI_SCKMODE_POL BIT(1)
49484a9a68SYash Shah #define SIFIVE_SPI_SCKMODE_MODE_MASK (SIFIVE_SPI_SCKMODE_PHA | \
50484a9a68SYash Shah SIFIVE_SPI_SCKMODE_POL)
51484a9a68SYash Shah
52484a9a68SYash Shah /* csmode bits */
53484a9a68SYash Shah #define SIFIVE_SPI_CSMODE_MODE_AUTO 0U
54484a9a68SYash Shah #define SIFIVE_SPI_CSMODE_MODE_HOLD 2U
55484a9a68SYash Shah #define SIFIVE_SPI_CSMODE_MODE_OFF 3U
56484a9a68SYash Shah
57484a9a68SYash Shah /* delay0 bits */
58484a9a68SYash Shah #define SIFIVE_SPI_DELAY0_CSSCK(x) ((u32)(x))
59484a9a68SYash Shah #define SIFIVE_SPI_DELAY0_CSSCK_MASK 0xffU
60484a9a68SYash Shah #define SIFIVE_SPI_DELAY0_SCKCS(x) ((u32)(x) << 16)
61484a9a68SYash Shah #define SIFIVE_SPI_DELAY0_SCKCS_MASK (0xffU << 16)
62484a9a68SYash Shah
63484a9a68SYash Shah /* delay1 bits */
64484a9a68SYash Shah #define SIFIVE_SPI_DELAY1_INTERCS(x) ((u32)(x))
65484a9a68SYash Shah #define SIFIVE_SPI_DELAY1_INTERCS_MASK 0xffU
66484a9a68SYash Shah #define SIFIVE_SPI_DELAY1_INTERXFR(x) ((u32)(x) << 16)
67484a9a68SYash Shah #define SIFIVE_SPI_DELAY1_INTERXFR_MASK (0xffU << 16)
68484a9a68SYash Shah
69484a9a68SYash Shah /* fmt bits */
70484a9a68SYash Shah #define SIFIVE_SPI_FMT_PROTO_SINGLE 0U
71484a9a68SYash Shah #define SIFIVE_SPI_FMT_PROTO_DUAL 1U
72484a9a68SYash Shah #define SIFIVE_SPI_FMT_PROTO_QUAD 2U
73484a9a68SYash Shah #define SIFIVE_SPI_FMT_PROTO_MASK 3U
74484a9a68SYash Shah #define SIFIVE_SPI_FMT_ENDIAN BIT(2)
75484a9a68SYash Shah #define SIFIVE_SPI_FMT_DIR BIT(3)
76484a9a68SYash Shah #define SIFIVE_SPI_FMT_LEN(x) ((u32)(x) << 16)
77484a9a68SYash Shah #define SIFIVE_SPI_FMT_LEN_MASK (0xfU << 16)
78484a9a68SYash Shah
79484a9a68SYash Shah /* txdata bits */
80484a9a68SYash Shah #define SIFIVE_SPI_TXDATA_DATA_MASK 0xffU
81484a9a68SYash Shah #define SIFIVE_SPI_TXDATA_FULL BIT(31)
82484a9a68SYash Shah
83484a9a68SYash Shah /* rxdata bits */
84484a9a68SYash Shah #define SIFIVE_SPI_RXDATA_DATA_MASK 0xffU
85484a9a68SYash Shah #define SIFIVE_SPI_RXDATA_EMPTY BIT(31)
86484a9a68SYash Shah
87484a9a68SYash Shah /* ie and ip bits */
88484a9a68SYash Shah #define SIFIVE_SPI_IP_TXWM BIT(0)
89484a9a68SYash Shah #define SIFIVE_SPI_IP_RXWM BIT(1)
90484a9a68SYash Shah
91484a9a68SYash Shah struct sifive_spi {
92484a9a68SYash Shah void __iomem *regs; /* virt. address of control registers */
93484a9a68SYash Shah struct clk *clk; /* bus clock */
94484a9a68SYash Shah unsigned int fifo_depth; /* fifo depth in words */
95484a9a68SYash Shah u32 cs_inactive; /* level of the CS pins when inactive */
96484a9a68SYash Shah struct completion done; /* wake-up from interrupt */
97484a9a68SYash Shah };
98484a9a68SYash Shah
sifive_spi_write(struct sifive_spi * spi,int offset,u32 value)99484a9a68SYash Shah static void sifive_spi_write(struct sifive_spi *spi, int offset, u32 value)
100484a9a68SYash Shah {
101484a9a68SYash Shah iowrite32(value, spi->regs + offset);
102484a9a68SYash Shah }
103484a9a68SYash Shah
sifive_spi_read(struct sifive_spi * spi,int offset)104484a9a68SYash Shah static u32 sifive_spi_read(struct sifive_spi *spi, int offset)
105484a9a68SYash Shah {
106484a9a68SYash Shah return ioread32(spi->regs + offset);
107484a9a68SYash Shah }
108484a9a68SYash Shah
sifive_spi_init(struct sifive_spi * spi)109484a9a68SYash Shah static void sifive_spi_init(struct sifive_spi *spi)
110484a9a68SYash Shah {
111484a9a68SYash Shah /* Watermark interrupts are disabled by default */
112484a9a68SYash Shah sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);
113484a9a68SYash Shah
114484a9a68SYash Shah /* Default watermark FIFO threshold values */
115484a9a68SYash Shah sifive_spi_write(spi, SIFIVE_SPI_REG_TXMARK, 1);
116484a9a68SYash Shah sifive_spi_write(spi, SIFIVE_SPI_REG_RXMARK, 0);
117484a9a68SYash Shah
118484a9a68SYash Shah /* Set CS/SCK Delays and Inactive Time to defaults */
119484a9a68SYash Shah sifive_spi_write(spi, SIFIVE_SPI_REG_DELAY0,
120484a9a68SYash Shah SIFIVE_SPI_DELAY0_CSSCK(1) |
121484a9a68SYash Shah SIFIVE_SPI_DELAY0_SCKCS(1));
122484a9a68SYash Shah sifive_spi_write(spi, SIFIVE_SPI_REG_DELAY1,
123484a9a68SYash Shah SIFIVE_SPI_DELAY1_INTERCS(1) |
124484a9a68SYash Shah SIFIVE_SPI_DELAY1_INTERXFR(0));
125484a9a68SYash Shah
126484a9a68SYash Shah /* Exit specialized memory-mapped SPI flash mode */
127484a9a68SYash Shah sifive_spi_write(spi, SIFIVE_SPI_REG_FCTRL, 0);
128484a9a68SYash Shah }
129484a9a68SYash Shah
130484a9a68SYash Shah static int
sifive_spi_prepare_message(struct spi_controller * host,struct spi_message * msg)131*8d9ae783SYang Yingliang sifive_spi_prepare_message(struct spi_controller *host, struct spi_message *msg)
132484a9a68SYash Shah {
133*8d9ae783SYang Yingliang struct sifive_spi *spi = spi_controller_get_devdata(host);
134484a9a68SYash Shah struct spi_device *device = msg->spi;
135484a9a68SYash Shah
136484a9a68SYash Shah /* Update the chip select polarity */
137484a9a68SYash Shah if (device->mode & SPI_CS_HIGH)
1389e264f3fSAmit Kumar Mahapatra via Alsa-devel spi->cs_inactive &= ~BIT(spi_get_chipselect(device, 0));
139484a9a68SYash Shah else
1409e264f3fSAmit Kumar Mahapatra via Alsa-devel spi->cs_inactive |= BIT(spi_get_chipselect(device, 0));
141484a9a68SYash Shah sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, spi->cs_inactive);
142484a9a68SYash Shah
143484a9a68SYash Shah /* Select the correct device */
1449e264f3fSAmit Kumar Mahapatra via Alsa-devel sifive_spi_write(spi, SIFIVE_SPI_REG_CSID, spi_get_chipselect(device, 0));
145484a9a68SYash Shah
146484a9a68SYash Shah /* Set clock mode */
147484a9a68SYash Shah sifive_spi_write(spi, SIFIVE_SPI_REG_SCKMODE,
148484a9a68SYash Shah device->mode & SIFIVE_SPI_SCKMODE_MODE_MASK);
149484a9a68SYash Shah
150484a9a68SYash Shah return 0;
151484a9a68SYash Shah }
152484a9a68SYash Shah
sifive_spi_set_cs(struct spi_device * device,bool is_high)153484a9a68SYash Shah static void sifive_spi_set_cs(struct spi_device *device, bool is_high)
154484a9a68SYash Shah {
155*8d9ae783SYang Yingliang struct sifive_spi *spi = spi_controller_get_devdata(device->controller);
156484a9a68SYash Shah
157484a9a68SYash Shah /* Reverse polarity is handled by SCMR/CPOL. Not inverted CS. */
158484a9a68SYash Shah if (device->mode & SPI_CS_HIGH)
159484a9a68SYash Shah is_high = !is_high;
160484a9a68SYash Shah
161484a9a68SYash Shah sifive_spi_write(spi, SIFIVE_SPI_REG_CSMODE, is_high ?
162484a9a68SYash Shah SIFIVE_SPI_CSMODE_MODE_AUTO :
163484a9a68SYash Shah SIFIVE_SPI_CSMODE_MODE_HOLD);
164484a9a68SYash Shah }
165484a9a68SYash Shah
166484a9a68SYash Shah static int
sifive_spi_prep_transfer(struct sifive_spi * spi,struct spi_device * device,struct spi_transfer * t)167484a9a68SYash Shah sifive_spi_prep_transfer(struct sifive_spi *spi, struct spi_device *device,
168484a9a68SYash Shah struct spi_transfer *t)
169484a9a68SYash Shah {
170484a9a68SYash Shah u32 cr;
171484a9a68SYash Shah unsigned int mode;
172484a9a68SYash Shah
173484a9a68SYash Shah /* Calculate and program the clock rate */
174484a9a68SYash Shah cr = DIV_ROUND_UP(clk_get_rate(spi->clk) >> 1, t->speed_hz) - 1;
175484a9a68SYash Shah cr &= SIFIVE_SPI_SCKDIV_DIV_MASK;
176484a9a68SYash Shah sifive_spi_write(spi, SIFIVE_SPI_REG_SCKDIV, cr);
177484a9a68SYash Shah
178484a9a68SYash Shah mode = max_t(unsigned int, t->rx_nbits, t->tx_nbits);
179484a9a68SYash Shah
180484a9a68SYash Shah /* Set frame format */
181484a9a68SYash Shah cr = SIFIVE_SPI_FMT_LEN(t->bits_per_word);
182484a9a68SYash Shah switch (mode) {
183484a9a68SYash Shah case SPI_NBITS_QUAD:
184484a9a68SYash Shah cr |= SIFIVE_SPI_FMT_PROTO_QUAD;
185484a9a68SYash Shah break;
186484a9a68SYash Shah case SPI_NBITS_DUAL:
187484a9a68SYash Shah cr |= SIFIVE_SPI_FMT_PROTO_DUAL;
188484a9a68SYash Shah break;
189484a9a68SYash Shah default:
190484a9a68SYash Shah cr |= SIFIVE_SPI_FMT_PROTO_SINGLE;
191484a9a68SYash Shah break;
192484a9a68SYash Shah }
193484a9a68SYash Shah if (device->mode & SPI_LSB_FIRST)
194484a9a68SYash Shah cr |= SIFIVE_SPI_FMT_ENDIAN;
195484a9a68SYash Shah if (!t->rx_buf)
196484a9a68SYash Shah cr |= SIFIVE_SPI_FMT_DIR;
197484a9a68SYash Shah sifive_spi_write(spi, SIFIVE_SPI_REG_FMT, cr);
198484a9a68SYash Shah
199484a9a68SYash Shah /* We will want to poll if the time we need to wait is
200484a9a68SYash Shah * less than the context switching time.
201484a9a68SYash Shah * Let's call that threshold 5us. The operation will take:
202484a9a68SYash Shah * (8/mode) * fifo_depth / hz <= 5 * 10^-6
203484a9a68SYash Shah * 1600000 * fifo_depth <= hz * mode
204484a9a68SYash Shah */
205484a9a68SYash Shah return 1600000 * spi->fifo_depth <= t->speed_hz * mode;
206484a9a68SYash Shah }
207484a9a68SYash Shah
sifive_spi_irq(int irq,void * dev_id)208484a9a68SYash Shah static irqreturn_t sifive_spi_irq(int irq, void *dev_id)
209484a9a68SYash Shah {
210484a9a68SYash Shah struct sifive_spi *spi = dev_id;
211484a9a68SYash Shah u32 ip = sifive_spi_read(spi, SIFIVE_SPI_REG_IP);
212484a9a68SYash Shah
213484a9a68SYash Shah if (ip & (SIFIVE_SPI_IP_TXWM | SIFIVE_SPI_IP_RXWM)) {
214484a9a68SYash Shah /* Disable interrupts until next transfer */
215484a9a68SYash Shah sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);
216484a9a68SYash Shah complete(&spi->done);
217484a9a68SYash Shah return IRQ_HANDLED;
218484a9a68SYash Shah }
219484a9a68SYash Shah
220484a9a68SYash Shah return IRQ_NONE;
221484a9a68SYash Shah }
222484a9a68SYash Shah
sifive_spi_wait(struct sifive_spi * spi,u32 bit,int poll)223484a9a68SYash Shah static void sifive_spi_wait(struct sifive_spi *spi, u32 bit, int poll)
224484a9a68SYash Shah {
225484a9a68SYash Shah if (poll) {
226484a9a68SYash Shah u32 cr;
227484a9a68SYash Shah
228484a9a68SYash Shah do {
229484a9a68SYash Shah cr = sifive_spi_read(spi, SIFIVE_SPI_REG_IP);
230484a9a68SYash Shah } while (!(cr & bit));
231484a9a68SYash Shah } else {
232484a9a68SYash Shah reinit_completion(&spi->done);
233484a9a68SYash Shah sifive_spi_write(spi, SIFIVE_SPI_REG_IE, bit);
234484a9a68SYash Shah wait_for_completion(&spi->done);
235484a9a68SYash Shah }
236484a9a68SYash Shah }
237484a9a68SYash Shah
sifive_spi_tx(struct sifive_spi * spi,const u8 * tx_ptr)238484a9a68SYash Shah static void sifive_spi_tx(struct sifive_spi *spi, const u8 *tx_ptr)
239484a9a68SYash Shah {
240484a9a68SYash Shah WARN_ON_ONCE((sifive_spi_read(spi, SIFIVE_SPI_REG_TXDATA)
241484a9a68SYash Shah & SIFIVE_SPI_TXDATA_FULL) != 0);
242484a9a68SYash Shah sifive_spi_write(spi, SIFIVE_SPI_REG_TXDATA,
243484a9a68SYash Shah *tx_ptr & SIFIVE_SPI_TXDATA_DATA_MASK);
244484a9a68SYash Shah }
245484a9a68SYash Shah
sifive_spi_rx(struct sifive_spi * spi,u8 * rx_ptr)246484a9a68SYash Shah static void sifive_spi_rx(struct sifive_spi *spi, u8 *rx_ptr)
247484a9a68SYash Shah {
248484a9a68SYash Shah u32 data = sifive_spi_read(spi, SIFIVE_SPI_REG_RXDATA);
249484a9a68SYash Shah
250484a9a68SYash Shah WARN_ON_ONCE((data & SIFIVE_SPI_RXDATA_EMPTY) != 0);
251484a9a68SYash Shah *rx_ptr = data & SIFIVE_SPI_RXDATA_DATA_MASK;
252484a9a68SYash Shah }
253484a9a68SYash Shah
254484a9a68SYash Shah static int
sifive_spi_transfer_one(struct spi_controller * host,struct spi_device * device,struct spi_transfer * t)255*8d9ae783SYang Yingliang sifive_spi_transfer_one(struct spi_controller *host, struct spi_device *device,
256484a9a68SYash Shah struct spi_transfer *t)
257484a9a68SYash Shah {
258*8d9ae783SYang Yingliang struct sifive_spi *spi = spi_controller_get_devdata(host);
259484a9a68SYash Shah int poll = sifive_spi_prep_transfer(spi, device, t);
260484a9a68SYash Shah const u8 *tx_ptr = t->tx_buf;
261484a9a68SYash Shah u8 *rx_ptr = t->rx_buf;
262484a9a68SYash Shah unsigned int remaining_words = t->len;
263484a9a68SYash Shah
264484a9a68SYash Shah while (remaining_words) {
265484a9a68SYash Shah unsigned int n_words = min(remaining_words, spi->fifo_depth);
266484a9a68SYash Shah unsigned int i;
267484a9a68SYash Shah
268484a9a68SYash Shah /* Enqueue n_words for transmission */
269484a9a68SYash Shah for (i = 0; i < n_words; i++)
270484a9a68SYash Shah sifive_spi_tx(spi, tx_ptr++);
271484a9a68SYash Shah
272484a9a68SYash Shah if (rx_ptr) {
273484a9a68SYash Shah /* Wait for transmission + reception to complete */
274484a9a68SYash Shah sifive_spi_write(spi, SIFIVE_SPI_REG_RXMARK,
275484a9a68SYash Shah n_words - 1);
276484a9a68SYash Shah sifive_spi_wait(spi, SIFIVE_SPI_IP_RXWM, poll);
277484a9a68SYash Shah
278484a9a68SYash Shah /* Read out all the data from the RX FIFO */
279484a9a68SYash Shah for (i = 0; i < n_words; i++)
280484a9a68SYash Shah sifive_spi_rx(spi, rx_ptr++);
281484a9a68SYash Shah } else {
282484a9a68SYash Shah /* Wait for transmission to complete */
283484a9a68SYash Shah sifive_spi_wait(spi, SIFIVE_SPI_IP_TXWM, poll);
284484a9a68SYash Shah }
285484a9a68SYash Shah
286484a9a68SYash Shah remaining_words -= n_words;
287484a9a68SYash Shah }
288484a9a68SYash Shah
289484a9a68SYash Shah return 0;
290484a9a68SYash Shah }
291484a9a68SYash Shah
sifive_spi_probe(struct platform_device * pdev)292484a9a68SYash Shah static int sifive_spi_probe(struct platform_device *pdev)
293484a9a68SYash Shah {
294484a9a68SYash Shah struct sifive_spi *spi;
295484a9a68SYash Shah int ret, irq, num_cs;
296484a9a68SYash Shah u32 cs_bits, max_bits_per_word;
297*8d9ae783SYang Yingliang struct spi_controller *host;
298484a9a68SYash Shah
299*8d9ae783SYang Yingliang host = spi_alloc_host(&pdev->dev, sizeof(struct sifive_spi));
300*8d9ae783SYang Yingliang if (!host) {
301484a9a68SYash Shah dev_err(&pdev->dev, "out of memory\n");
302484a9a68SYash Shah return -ENOMEM;
303484a9a68SYash Shah }
304484a9a68SYash Shah
305*8d9ae783SYang Yingliang spi = spi_controller_get_devdata(host);
306484a9a68SYash Shah init_completion(&spi->done);
307*8d9ae783SYang Yingliang platform_set_drvdata(pdev, host);
308484a9a68SYash Shah
309fa79f200SYueHaibing spi->regs = devm_platform_ioremap_resource(pdev, 0);
310484a9a68SYash Shah if (IS_ERR(spi->regs)) {
311484a9a68SYash Shah ret = PTR_ERR(spi->regs);
312*8d9ae783SYang Yingliang goto put_host;
313484a9a68SYash Shah }
314484a9a68SYash Shah
315484a9a68SYash Shah spi->clk = devm_clk_get(&pdev->dev, NULL);
316484a9a68SYash Shah if (IS_ERR(spi->clk)) {
317484a9a68SYash Shah dev_err(&pdev->dev, "Unable to find bus clock\n");
318484a9a68SYash Shah ret = PTR_ERR(spi->clk);
319*8d9ae783SYang Yingliang goto put_host;
320484a9a68SYash Shah }
321484a9a68SYash Shah
322484a9a68SYash Shah irq = platform_get_irq(pdev, 0);
323484a9a68SYash Shah if (irq < 0) {
324484a9a68SYash Shah ret = irq;
325*8d9ae783SYang Yingliang goto put_host;
326484a9a68SYash Shah }
327484a9a68SYash Shah
328484a9a68SYash Shah /* Optional parameters */
329484a9a68SYash Shah ret =
330484a9a68SYash Shah of_property_read_u32(pdev->dev.of_node, "sifive,fifo-depth",
331484a9a68SYash Shah &spi->fifo_depth);
332484a9a68SYash Shah if (ret < 0)
333484a9a68SYash Shah spi->fifo_depth = SIFIVE_SPI_DEFAULT_DEPTH;
334484a9a68SYash Shah
335484a9a68SYash Shah ret =
336484a9a68SYash Shah of_property_read_u32(pdev->dev.of_node, "sifive,max-bits-per-word",
337484a9a68SYash Shah &max_bits_per_word);
338484a9a68SYash Shah
339484a9a68SYash Shah if (!ret && max_bits_per_word < 8) {
340484a9a68SYash Shah dev_err(&pdev->dev, "Only 8bit SPI words supported by the driver\n");
341484a9a68SYash Shah ret = -EINVAL;
342*8d9ae783SYang Yingliang goto put_host;
343484a9a68SYash Shah }
344484a9a68SYash Shah
345484a9a68SYash Shah /* Spin up the bus clock before hitting registers */
346484a9a68SYash Shah ret = clk_prepare_enable(spi->clk);
347484a9a68SYash Shah if (ret) {
348484a9a68SYash Shah dev_err(&pdev->dev, "Unable to enable bus clock\n");
349*8d9ae783SYang Yingliang goto put_host;
350484a9a68SYash Shah }
351484a9a68SYash Shah
352484a9a68SYash Shah /* probe the number of CS lines */
353484a9a68SYash Shah spi->cs_inactive = sifive_spi_read(spi, SIFIVE_SPI_REG_CSDEF);
354484a9a68SYash Shah sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, 0xffffffffU);
355484a9a68SYash Shah cs_bits = sifive_spi_read(spi, SIFIVE_SPI_REG_CSDEF);
356484a9a68SYash Shah sifive_spi_write(spi, SIFIVE_SPI_REG_CSDEF, spi->cs_inactive);
357484a9a68SYash Shah if (!cs_bits) {
358484a9a68SYash Shah dev_err(&pdev->dev, "Could not auto probe CS lines\n");
359484a9a68SYash Shah ret = -EINVAL;
360a725272bSChuhong Yuan goto disable_clk;
361484a9a68SYash Shah }
362484a9a68SYash Shah
363484a9a68SYash Shah num_cs = ilog2(cs_bits) + 1;
364484a9a68SYash Shah if (num_cs > SIFIVE_SPI_MAX_CS) {
365*8d9ae783SYang Yingliang dev_err(&pdev->dev, "Invalid number of spi targets\n");
366484a9a68SYash Shah ret = -EINVAL;
367a725272bSChuhong Yuan goto disable_clk;
368484a9a68SYash Shah }
369484a9a68SYash Shah
370*8d9ae783SYang Yingliang /* Define our host */
371*8d9ae783SYang Yingliang host->dev.of_node = pdev->dev.of_node;
372*8d9ae783SYang Yingliang host->bus_num = pdev->id;
373*8d9ae783SYang Yingliang host->num_chipselect = num_cs;
374*8d9ae783SYang Yingliang host->mode_bits = SPI_CPHA | SPI_CPOL
375484a9a68SYash Shah | SPI_CS_HIGH | SPI_LSB_FIRST
376484a9a68SYash Shah | SPI_TX_DUAL | SPI_TX_QUAD
377484a9a68SYash Shah | SPI_RX_DUAL | SPI_RX_QUAD;
378484a9a68SYash Shah /* TODO: add driver support for bits_per_word < 8
379484a9a68SYash Shah * we need to "left-align" the bits (unless SPI_LSB_FIRST)
380484a9a68SYash Shah */
381*8d9ae783SYang Yingliang host->bits_per_word_mask = SPI_BPW_MASK(8);
382*8d9ae783SYang Yingliang host->flags = SPI_CONTROLLER_MUST_TX | SPI_CONTROLLER_GPIO_SS;
383*8d9ae783SYang Yingliang host->prepare_message = sifive_spi_prepare_message;
384*8d9ae783SYang Yingliang host->set_cs = sifive_spi_set_cs;
385*8d9ae783SYang Yingliang host->transfer_one = sifive_spi_transfer_one;
386484a9a68SYash Shah
387484a9a68SYash Shah pdev->dev.dma_mask = NULL;
388*8d9ae783SYang Yingliang /* Configure the SPI host hardware */
389484a9a68SYash Shah sifive_spi_init(spi);
390484a9a68SYash Shah
391484a9a68SYash Shah /* Register for SPI Interrupt */
392484a9a68SYash Shah ret = devm_request_irq(&pdev->dev, irq, sifive_spi_irq, 0,
393484a9a68SYash Shah dev_name(&pdev->dev), spi);
394484a9a68SYash Shah if (ret) {
395484a9a68SYash Shah dev_err(&pdev->dev, "Unable to bind to interrupt\n");
396a725272bSChuhong Yuan goto disable_clk;
397484a9a68SYash Shah }
398484a9a68SYash Shah
399484a9a68SYash Shah dev_info(&pdev->dev, "mapped; irq=%d, cs=%d\n",
400*8d9ae783SYang Yingliang irq, host->num_chipselect);
401484a9a68SYash Shah
402*8d9ae783SYang Yingliang ret = devm_spi_register_controller(&pdev->dev, host);
403484a9a68SYash Shah if (ret < 0) {
404*8d9ae783SYang Yingliang dev_err(&pdev->dev, "spi_register_host failed\n");
405a725272bSChuhong Yuan goto disable_clk;
406484a9a68SYash Shah }
407484a9a68SYash Shah
408484a9a68SYash Shah return 0;
409484a9a68SYash Shah
410a725272bSChuhong Yuan disable_clk:
411a725272bSChuhong Yuan clk_disable_unprepare(spi->clk);
412*8d9ae783SYang Yingliang put_host:
413*8d9ae783SYang Yingliang spi_controller_put(host);
414484a9a68SYash Shah
415484a9a68SYash Shah return ret;
416484a9a68SYash Shah }
417484a9a68SYash Shah
sifive_spi_remove(struct platform_device * pdev)418fd8998c4SUwe Kleine-König static void sifive_spi_remove(struct platform_device *pdev)
419484a9a68SYash Shah {
420*8d9ae783SYang Yingliang struct spi_controller *host = platform_get_drvdata(pdev);
421*8d9ae783SYang Yingliang struct sifive_spi *spi = spi_controller_get_devdata(host);
422484a9a68SYash Shah
423484a9a68SYash Shah /* Disable all the interrupts just in case */
424484a9a68SYash Shah sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);
425a725272bSChuhong Yuan clk_disable_unprepare(spi->clk);
426484a9a68SYash Shah }
427484a9a68SYash Shah
sifive_spi_suspend(struct device * dev)428a1f0161eSAndy Chiu static int sifive_spi_suspend(struct device *dev)
429a1f0161eSAndy Chiu {
430*8d9ae783SYang Yingliang struct spi_controller *host = dev_get_drvdata(dev);
431*8d9ae783SYang Yingliang struct sifive_spi *spi = spi_controller_get_devdata(host);
432a1f0161eSAndy Chiu int ret;
433a1f0161eSAndy Chiu
434*8d9ae783SYang Yingliang ret = spi_controller_suspend(host);
435a1f0161eSAndy Chiu if (ret)
436a1f0161eSAndy Chiu return ret;
437a1f0161eSAndy Chiu
438a1f0161eSAndy Chiu /* Disable all the interrupts just in case */
439a1f0161eSAndy Chiu sifive_spi_write(spi, SIFIVE_SPI_REG_IE, 0);
440a1f0161eSAndy Chiu
441a1f0161eSAndy Chiu clk_disable_unprepare(spi->clk);
442a1f0161eSAndy Chiu
443a1f0161eSAndy Chiu return ret;
444a1f0161eSAndy Chiu }
445a1f0161eSAndy Chiu
sifive_spi_resume(struct device * dev)446a1f0161eSAndy Chiu static int sifive_spi_resume(struct device *dev)
447a1f0161eSAndy Chiu {
448*8d9ae783SYang Yingliang struct spi_controller *host = dev_get_drvdata(dev);
449*8d9ae783SYang Yingliang struct sifive_spi *spi = spi_controller_get_devdata(host);
450a1f0161eSAndy Chiu int ret;
451a1f0161eSAndy Chiu
452a1f0161eSAndy Chiu ret = clk_prepare_enable(spi->clk);
453a1f0161eSAndy Chiu if (ret)
454a1f0161eSAndy Chiu return ret;
455*8d9ae783SYang Yingliang ret = spi_controller_resume(host);
456a1f0161eSAndy Chiu if (ret)
457a1f0161eSAndy Chiu clk_disable_unprepare(spi->clk);
458a1f0161eSAndy Chiu
459a1f0161eSAndy Chiu return ret;
460a1f0161eSAndy Chiu }
461a1f0161eSAndy Chiu
462a1f0161eSAndy Chiu static DEFINE_SIMPLE_DEV_PM_OPS(sifive_spi_pm_ops,
463a1f0161eSAndy Chiu sifive_spi_suspend, sifive_spi_resume);
464a1f0161eSAndy Chiu
465a1f0161eSAndy Chiu
466484a9a68SYash Shah static const struct of_device_id sifive_spi_of_match[] = {
467484a9a68SYash Shah { .compatible = "sifive,spi0", },
468484a9a68SYash Shah {}
469484a9a68SYash Shah };
470484a9a68SYash Shah MODULE_DEVICE_TABLE(of, sifive_spi_of_match);
471484a9a68SYash Shah
472484a9a68SYash Shah static struct platform_driver sifive_spi_driver = {
473484a9a68SYash Shah .probe = sifive_spi_probe,
474fd8998c4SUwe Kleine-König .remove_new = sifive_spi_remove,
475484a9a68SYash Shah .driver = {
476484a9a68SYash Shah .name = SIFIVE_SPI_DRIVER_NAME,
477a1f0161eSAndy Chiu .pm = &sifive_spi_pm_ops,
478484a9a68SYash Shah .of_match_table = sifive_spi_of_match,
479484a9a68SYash Shah },
480484a9a68SYash Shah };
481484a9a68SYash Shah module_platform_driver(sifive_spi_driver);
482484a9a68SYash Shah
483484a9a68SYash Shah MODULE_AUTHOR("SiFive, Inc. <sifive@sifive.com>");
484484a9a68SYash Shah MODULE_DESCRIPTION("SiFive SPI driver");
485484a9a68SYash Shah MODULE_LICENSE("GPL");
486