1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * SuperH MSIOF SPI Controller Interface 4 * 5 * Copyright (c) 2009 Magnus Damm 6 * Copyright (C) 2014 Renesas Electronics Corporation 7 * Copyright (C) 2014-2017 Glider bvba 8 */ 9 10 #include <linux/bitmap.h> 11 #include <linux/clk.h> 12 #include <linux/completion.h> 13 #include <linux/delay.h> 14 #include <linux/dma-mapping.h> 15 #include <linux/dmaengine.h> 16 #include <linux/err.h> 17 #include <linux/interrupt.h> 18 #include <linux/io.h> 19 #include <linux/iopoll.h> 20 #include <linux/kernel.h> 21 #include <linux/module.h> 22 #include <linux/of.h> 23 #include <linux/platform_device.h> 24 #include <linux/pm_runtime.h> 25 #include <linux/sh_dma.h> 26 27 #include <linux/spi/sh_msiof.h> 28 #include <linux/spi/spi.h> 29 30 #include <asm/unaligned.h> 31 32 struct sh_msiof_chipdata { 33 u32 bits_per_word_mask; 34 u16 tx_fifo_size; 35 u16 rx_fifo_size; 36 u16 ctlr_flags; 37 u16 min_div_pow; 38 }; 39 40 struct sh_msiof_spi_priv { 41 struct spi_controller *ctlr; 42 void __iomem *mapbase; 43 struct clk *clk; 44 struct platform_device *pdev; 45 struct sh_msiof_spi_info *info; 46 struct completion done; 47 struct completion done_txdma; 48 unsigned int tx_fifo_size; 49 unsigned int rx_fifo_size; 50 unsigned int min_div_pow; 51 void *tx_dma_page; 52 void *rx_dma_page; 53 dma_addr_t tx_dma_addr; 54 dma_addr_t rx_dma_addr; 55 bool native_cs_inited; 56 bool native_cs_high; 57 bool target_aborted; 58 }; 59 60 #define MAX_SS 3 /* Maximum number of native chip selects */ 61 62 #define SITMDR1 0x00 /* Transmit Mode Register 1 */ 63 #define SITMDR2 0x04 /* Transmit Mode Register 2 */ 64 #define SITMDR3 0x08 /* Transmit Mode Register 3 */ 65 #define SIRMDR1 0x10 /* Receive Mode Register 1 */ 66 #define SIRMDR2 0x14 /* Receive Mode Register 2 */ 67 #define SIRMDR3 0x18 /* Receive Mode Register 3 */ 68 #define SITSCR 0x20 /* Transmit Clock Select Register */ 69 #define SIRSCR 0x22 /* Receive Clock Select Register (SH, A1, APE6) */ 70 #define SICTR 0x28 /* Control Register */ 71 #define SIFCTR 0x30 /* FIFO Control Register */ 72 #define SISTR 0x40 /* Status Register */ 73 #define SIIER 0x44 /* Interrupt Enable Register */ 74 #define SITDR1 0x48 /* Transmit Control Data Register 1 (SH, A1) */ 75 #define SITDR2 0x4c /* Transmit Control Data Register 2 (SH, A1) */ 76 #define SITFDR 0x50 /* Transmit FIFO Data Register */ 77 #define SIRDR1 0x58 /* Receive Control Data Register 1 (SH, A1) */ 78 #define SIRDR2 0x5c /* Receive Control Data Register 2 (SH, A1) */ 79 #define SIRFDR 0x60 /* Receive FIFO Data Register */ 80 81 /* SITMDR1 and SIRMDR1 */ 82 #define SIMDR1_TRMD BIT(31) /* Transfer Mode (1 = Master mode) */ 83 #define SIMDR1_SYNCMD_MASK GENMASK(29, 28) /* SYNC Mode */ 84 #define SIMDR1_SYNCMD_SPI (2 << 28) /* Level mode/SPI */ 85 #define SIMDR1_SYNCMD_LR (3 << 28) /* L/R mode */ 86 #define SIMDR1_SYNCAC_SHIFT 25 /* Sync Polarity (1 = Active-low) */ 87 #define SIMDR1_BITLSB_SHIFT 24 /* MSB/LSB First (1 = LSB first) */ 88 #define SIMDR1_DTDL_SHIFT 20 /* Data Pin Bit Delay for MSIOF_SYNC */ 89 #define SIMDR1_SYNCDL_SHIFT 16 /* Frame Sync Signal Timing Delay */ 90 #define SIMDR1_FLD_MASK GENMASK(3, 2) /* Frame Sync Signal Interval (0-3) */ 91 #define SIMDR1_FLD_SHIFT 2 92 #define SIMDR1_XXSTP BIT(0) /* Transmission/Reception Stop on FIFO */ 93 /* SITMDR1 */ 94 #define SITMDR1_PCON BIT(30) /* Transfer Signal Connection */ 95 #define SITMDR1_SYNCCH_MASK GENMASK(27, 26) /* Sync Signal Channel Select */ 96 #define SITMDR1_SYNCCH_SHIFT 26 /* 0=MSIOF_SYNC, 1=MSIOF_SS1, 2=MSIOF_SS2 */ 97 98 /* SITMDR2 and SIRMDR2 */ 99 #define SIMDR2_BITLEN1(i) (((i) - 1) << 24) /* Data Size (8-32 bits) */ 100 #define SIMDR2_WDLEN1(i) (((i) - 1) << 16) /* Word Count (1-64/256 (SH, A1))) */ 101 #define SIMDR2_GRPMASK1 BIT(0) /* Group Output Mask 1 (SH, A1) */ 102 103 /* SITSCR and SIRSCR */ 104 #define SISCR_BRPS_MASK GENMASK(12, 8) /* Prescaler Setting (1-32) */ 105 #define SISCR_BRPS(i) (((i) - 1) << 8) 106 #define SISCR_BRDV_MASK GENMASK(2, 0) /* Baud Rate Generator's Division Ratio */ 107 #define SISCR_BRDV_DIV_2 0 108 #define SISCR_BRDV_DIV_4 1 109 #define SISCR_BRDV_DIV_8 2 110 #define SISCR_BRDV_DIV_16 3 111 #define SISCR_BRDV_DIV_32 4 112 #define SISCR_BRDV_DIV_1 7 113 114 /* SICTR */ 115 #define SICTR_TSCKIZ_MASK GENMASK(31, 30) /* Transmit Clock I/O Polarity Select */ 116 #define SICTR_TSCKIZ_SCK BIT(31) /* Disable SCK when TX disabled */ 117 #define SICTR_TSCKIZ_POL_SHIFT 30 /* Transmit Clock Polarity */ 118 #define SICTR_RSCKIZ_MASK GENMASK(29, 28) /* Receive Clock Polarity Select */ 119 #define SICTR_RSCKIZ_SCK BIT(29) /* Must match CTR_TSCKIZ_SCK */ 120 #define SICTR_RSCKIZ_POL_SHIFT 28 /* Receive Clock Polarity */ 121 #define SICTR_TEDG_SHIFT 27 /* Transmit Timing (1 = falling edge) */ 122 #define SICTR_REDG_SHIFT 26 /* Receive Timing (1 = falling edge) */ 123 #define SICTR_TXDIZ_MASK GENMASK(23, 22) /* Pin Output When TX is Disabled */ 124 #define SICTR_TXDIZ_LOW (0 << 22) /* 0 */ 125 #define SICTR_TXDIZ_HIGH (1 << 22) /* 1 */ 126 #define SICTR_TXDIZ_HIZ (2 << 22) /* High-impedance */ 127 #define SICTR_TSCKE BIT(15) /* Transmit Serial Clock Output Enable */ 128 #define SICTR_TFSE BIT(14) /* Transmit Frame Sync Signal Output Enable */ 129 #define SICTR_TXE BIT(9) /* Transmit Enable */ 130 #define SICTR_RXE BIT(8) /* Receive Enable */ 131 #define SICTR_TXRST BIT(1) /* Transmit Reset */ 132 #define SICTR_RXRST BIT(0) /* Receive Reset */ 133 134 /* SIFCTR */ 135 #define SIFCTR_TFWM_MASK GENMASK(31, 29) /* Transmit FIFO Watermark */ 136 #define SIFCTR_TFWM_64 (0 << 29) /* Transfer Request when 64 empty stages */ 137 #define SIFCTR_TFWM_32 (1 << 29) /* Transfer Request when 32 empty stages */ 138 #define SIFCTR_TFWM_24 (2 << 29) /* Transfer Request when 24 empty stages */ 139 #define SIFCTR_TFWM_16 (3 << 29) /* Transfer Request when 16 empty stages */ 140 #define SIFCTR_TFWM_12 (4 << 29) /* Transfer Request when 12 empty stages */ 141 #define SIFCTR_TFWM_8 (5 << 29) /* Transfer Request when 8 empty stages */ 142 #define SIFCTR_TFWM_4 (6 << 29) /* Transfer Request when 4 empty stages */ 143 #define SIFCTR_TFWM_1 (7 << 29) /* Transfer Request when 1 empty stage */ 144 #define SIFCTR_TFUA_MASK GENMASK(26, 20) /* Transmit FIFO Usable Area */ 145 #define SIFCTR_TFUA_SHIFT 20 146 #define SIFCTR_TFUA(i) ((i) << SIFCTR_TFUA_SHIFT) 147 #define SIFCTR_RFWM_MASK GENMASK(15, 13) /* Receive FIFO Watermark */ 148 #define SIFCTR_RFWM_1 (0 << 13) /* Transfer Request when 1 valid stages */ 149 #define SIFCTR_RFWM_4 (1 << 13) /* Transfer Request when 4 valid stages */ 150 #define SIFCTR_RFWM_8 (2 << 13) /* Transfer Request when 8 valid stages */ 151 #define SIFCTR_RFWM_16 (3 << 13) /* Transfer Request when 16 valid stages */ 152 #define SIFCTR_RFWM_32 (4 << 13) /* Transfer Request when 32 valid stages */ 153 #define SIFCTR_RFWM_64 (5 << 13) /* Transfer Request when 64 valid stages */ 154 #define SIFCTR_RFWM_128 (6 << 13) /* Transfer Request when 128 valid stages */ 155 #define SIFCTR_RFWM_256 (7 << 13) /* Transfer Request when 256 valid stages */ 156 #define SIFCTR_RFUA_MASK GENMASK(12, 4) /* Receive FIFO Usable Area (0x40 = full) */ 157 #define SIFCTR_RFUA_SHIFT 4 158 #define SIFCTR_RFUA(i) ((i) << SIFCTR_RFUA_SHIFT) 159 160 /* SISTR */ 161 #define SISTR_TFEMP BIT(29) /* Transmit FIFO Empty */ 162 #define SISTR_TDREQ BIT(28) /* Transmit Data Transfer Request */ 163 #define SISTR_TEOF BIT(23) /* Frame Transmission End */ 164 #define SISTR_TFSERR BIT(21) /* Transmit Frame Synchronization Error */ 165 #define SISTR_TFOVF BIT(20) /* Transmit FIFO Overflow */ 166 #define SISTR_TFUDF BIT(19) /* Transmit FIFO Underflow */ 167 #define SISTR_RFFUL BIT(13) /* Receive FIFO Full */ 168 #define SISTR_RDREQ BIT(12) /* Receive Data Transfer Request */ 169 #define SISTR_REOF BIT(7) /* Frame Reception End */ 170 #define SISTR_RFSERR BIT(5) /* Receive Frame Synchronization Error */ 171 #define SISTR_RFUDF BIT(4) /* Receive FIFO Underflow */ 172 #define SISTR_RFOVF BIT(3) /* Receive FIFO Overflow */ 173 174 /* SIIER */ 175 #define SIIER_TDMAE BIT(31) /* Transmit Data DMA Transfer Req. Enable */ 176 #define SIIER_TFEMPE BIT(29) /* Transmit FIFO Empty Enable */ 177 #define SIIER_TDREQE BIT(28) /* Transmit Data Transfer Request Enable */ 178 #define SIIER_TEOFE BIT(23) /* Frame Transmission End Enable */ 179 #define SIIER_TFSERRE BIT(21) /* Transmit Frame Sync Error Enable */ 180 #define SIIER_TFOVFE BIT(20) /* Transmit FIFO Overflow Enable */ 181 #define SIIER_TFUDFE BIT(19) /* Transmit FIFO Underflow Enable */ 182 #define SIIER_RDMAE BIT(15) /* Receive Data DMA Transfer Req. Enable */ 183 #define SIIER_RFFULE BIT(13) /* Receive FIFO Full Enable */ 184 #define SIIER_RDREQE BIT(12) /* Receive Data Transfer Request Enable */ 185 #define SIIER_REOFE BIT(7) /* Frame Reception End Enable */ 186 #define SIIER_RFSERRE BIT(5) /* Receive Frame Sync Error Enable */ 187 #define SIIER_RFUDFE BIT(4) /* Receive FIFO Underflow Enable */ 188 #define SIIER_RFOVFE BIT(3) /* Receive FIFO Overflow Enable */ 189 190 191 static u32 sh_msiof_read(struct sh_msiof_spi_priv *p, int reg_offs) 192 { 193 switch (reg_offs) { 194 case SITSCR: 195 case SIRSCR: 196 return ioread16(p->mapbase + reg_offs); 197 default: 198 return ioread32(p->mapbase + reg_offs); 199 } 200 } 201 202 static void sh_msiof_write(struct sh_msiof_spi_priv *p, int reg_offs, 203 u32 value) 204 { 205 switch (reg_offs) { 206 case SITSCR: 207 case SIRSCR: 208 iowrite16(value, p->mapbase + reg_offs); 209 break; 210 default: 211 iowrite32(value, p->mapbase + reg_offs); 212 break; 213 } 214 } 215 216 static int sh_msiof_modify_ctr_wait(struct sh_msiof_spi_priv *p, 217 u32 clr, u32 set) 218 { 219 u32 mask = clr | set; 220 u32 data; 221 222 data = sh_msiof_read(p, SICTR); 223 data &= ~clr; 224 data |= set; 225 sh_msiof_write(p, SICTR, data); 226 227 return readl_poll_timeout_atomic(p->mapbase + SICTR, data, 228 (data & mask) == set, 1, 100); 229 } 230 231 static irqreturn_t sh_msiof_spi_irq(int irq, void *data) 232 { 233 struct sh_msiof_spi_priv *p = data; 234 235 /* just disable the interrupt and wake up */ 236 sh_msiof_write(p, SIIER, 0); 237 complete(&p->done); 238 239 return IRQ_HANDLED; 240 } 241 242 static void sh_msiof_spi_reset_regs(struct sh_msiof_spi_priv *p) 243 { 244 u32 mask = SICTR_TXRST | SICTR_RXRST; 245 u32 data; 246 247 data = sh_msiof_read(p, SICTR); 248 data |= mask; 249 sh_msiof_write(p, SICTR, data); 250 251 readl_poll_timeout_atomic(p->mapbase + SICTR, data, !(data & mask), 1, 252 100); 253 } 254 255 static const u32 sh_msiof_spi_div_array[] = { 256 SISCR_BRDV_DIV_1, SISCR_BRDV_DIV_2, SISCR_BRDV_DIV_4, 257 SISCR_BRDV_DIV_8, SISCR_BRDV_DIV_16, SISCR_BRDV_DIV_32, 258 }; 259 260 static void sh_msiof_spi_set_clk_regs(struct sh_msiof_spi_priv *p, 261 struct spi_transfer *t) 262 { 263 unsigned long parent_rate = clk_get_rate(p->clk); 264 unsigned int div_pow = p->min_div_pow; 265 u32 spi_hz = t->speed_hz; 266 unsigned long div; 267 u32 brps, scr; 268 269 if (!spi_hz || !parent_rate) { 270 WARN(1, "Invalid clock rate parameters %lu and %u\n", 271 parent_rate, spi_hz); 272 return; 273 } 274 275 div = DIV_ROUND_UP(parent_rate, spi_hz); 276 if (div <= 1024) { 277 /* SISCR_BRDV_DIV_1 is valid only if BRPS is x 1/1 or x 1/2 */ 278 if (!div_pow && div <= 32 && div > 2) 279 div_pow = 1; 280 281 if (div_pow) 282 brps = (div + 1) >> div_pow; 283 else 284 brps = div; 285 286 for (; brps > 32; div_pow++) 287 brps = (brps + 1) >> 1; 288 } else { 289 /* Set transfer rate composite divisor to 2^5 * 32 = 1024 */ 290 dev_err(&p->pdev->dev, 291 "Requested SPI transfer rate %d is too low\n", spi_hz); 292 div_pow = 5; 293 brps = 32; 294 } 295 296 t->effective_speed_hz = parent_rate / (brps << div_pow); 297 298 scr = sh_msiof_spi_div_array[div_pow] | SISCR_BRPS(brps); 299 sh_msiof_write(p, SITSCR, scr); 300 if (!(p->ctlr->flags & SPI_CONTROLLER_MUST_TX)) 301 sh_msiof_write(p, SIRSCR, scr); 302 } 303 304 static u32 sh_msiof_get_delay_bit(u32 dtdl_or_syncdl) 305 { 306 /* 307 * DTDL/SYNCDL bit : p->info->dtdl or p->info->syncdl 308 * b'000 : 0 309 * b'001 : 100 310 * b'010 : 200 311 * b'011 (SYNCDL only) : 300 312 * b'101 : 50 313 * b'110 : 150 314 */ 315 if (dtdl_or_syncdl % 100) 316 return dtdl_or_syncdl / 100 + 5; 317 else 318 return dtdl_or_syncdl / 100; 319 } 320 321 static u32 sh_msiof_spi_get_dtdl_and_syncdl(struct sh_msiof_spi_priv *p) 322 { 323 u32 val; 324 325 if (!p->info) 326 return 0; 327 328 /* check if DTDL and SYNCDL is allowed value */ 329 if (p->info->dtdl > 200 || p->info->syncdl > 300) { 330 dev_warn(&p->pdev->dev, "DTDL or SYNCDL is too large\n"); 331 return 0; 332 } 333 334 /* check if the sum of DTDL and SYNCDL becomes an integer value */ 335 if ((p->info->dtdl + p->info->syncdl) % 100) { 336 dev_warn(&p->pdev->dev, "the sum of DTDL/SYNCDL is not good\n"); 337 return 0; 338 } 339 340 val = sh_msiof_get_delay_bit(p->info->dtdl) << SIMDR1_DTDL_SHIFT; 341 val |= sh_msiof_get_delay_bit(p->info->syncdl) << SIMDR1_SYNCDL_SHIFT; 342 343 return val; 344 } 345 346 static void sh_msiof_spi_set_pin_regs(struct sh_msiof_spi_priv *p, u32 ss, 347 u32 cpol, u32 cpha, 348 u32 tx_hi_z, u32 lsb_first, u32 cs_high) 349 { 350 u32 tmp; 351 int edge; 352 353 /* 354 * CPOL CPHA TSCKIZ RSCKIZ TEDG REDG 355 * 0 0 10 10 1 1 356 * 0 1 10 10 0 0 357 * 1 0 11 11 0 0 358 * 1 1 11 11 1 1 359 */ 360 tmp = SIMDR1_SYNCMD_SPI | 1 << SIMDR1_FLD_SHIFT | SIMDR1_XXSTP; 361 tmp |= !cs_high << SIMDR1_SYNCAC_SHIFT; 362 tmp |= lsb_first << SIMDR1_BITLSB_SHIFT; 363 tmp |= sh_msiof_spi_get_dtdl_and_syncdl(p); 364 if (spi_controller_is_target(p->ctlr)) { 365 sh_msiof_write(p, SITMDR1, tmp | SITMDR1_PCON); 366 } else { 367 sh_msiof_write(p, SITMDR1, 368 tmp | SIMDR1_TRMD | SITMDR1_PCON | 369 (ss < MAX_SS ? ss : 0) << SITMDR1_SYNCCH_SHIFT); 370 } 371 if (p->ctlr->flags & SPI_CONTROLLER_MUST_TX) { 372 /* These bits are reserved if RX needs TX */ 373 tmp &= ~0x0000ffff; 374 } 375 sh_msiof_write(p, SIRMDR1, tmp); 376 377 tmp = 0; 378 tmp |= SICTR_TSCKIZ_SCK | cpol << SICTR_TSCKIZ_POL_SHIFT; 379 tmp |= SICTR_RSCKIZ_SCK | cpol << SICTR_RSCKIZ_POL_SHIFT; 380 381 edge = cpol ^ !cpha; 382 383 tmp |= edge << SICTR_TEDG_SHIFT; 384 tmp |= edge << SICTR_REDG_SHIFT; 385 tmp |= tx_hi_z ? SICTR_TXDIZ_HIZ : SICTR_TXDIZ_LOW; 386 sh_msiof_write(p, SICTR, tmp); 387 } 388 389 static void sh_msiof_spi_set_mode_regs(struct sh_msiof_spi_priv *p, 390 const void *tx_buf, void *rx_buf, 391 u32 bits, u32 words) 392 { 393 u32 dr2 = SIMDR2_BITLEN1(bits) | SIMDR2_WDLEN1(words); 394 395 if (tx_buf || (p->ctlr->flags & SPI_CONTROLLER_MUST_TX)) 396 sh_msiof_write(p, SITMDR2, dr2); 397 else 398 sh_msiof_write(p, SITMDR2, dr2 | SIMDR2_GRPMASK1); 399 400 if (rx_buf) 401 sh_msiof_write(p, SIRMDR2, dr2); 402 } 403 404 static void sh_msiof_reset_str(struct sh_msiof_spi_priv *p) 405 { 406 sh_msiof_write(p, SISTR, 407 sh_msiof_read(p, SISTR) & ~(SISTR_TDREQ | SISTR_RDREQ)); 408 } 409 410 static void sh_msiof_spi_write_fifo_8(struct sh_msiof_spi_priv *p, 411 const void *tx_buf, int words, int fs) 412 { 413 const u8 *buf_8 = tx_buf; 414 int k; 415 416 for (k = 0; k < words; k++) 417 sh_msiof_write(p, SITFDR, buf_8[k] << fs); 418 } 419 420 static void sh_msiof_spi_write_fifo_16(struct sh_msiof_spi_priv *p, 421 const void *tx_buf, int words, int fs) 422 { 423 const u16 *buf_16 = tx_buf; 424 int k; 425 426 for (k = 0; k < words; k++) 427 sh_msiof_write(p, SITFDR, buf_16[k] << fs); 428 } 429 430 static void sh_msiof_spi_write_fifo_16u(struct sh_msiof_spi_priv *p, 431 const void *tx_buf, int words, int fs) 432 { 433 const u16 *buf_16 = tx_buf; 434 int k; 435 436 for (k = 0; k < words; k++) 437 sh_msiof_write(p, SITFDR, get_unaligned(&buf_16[k]) << fs); 438 } 439 440 static void sh_msiof_spi_write_fifo_32(struct sh_msiof_spi_priv *p, 441 const void *tx_buf, int words, int fs) 442 { 443 const u32 *buf_32 = tx_buf; 444 int k; 445 446 for (k = 0; k < words; k++) 447 sh_msiof_write(p, SITFDR, buf_32[k] << fs); 448 } 449 450 static void sh_msiof_spi_write_fifo_32u(struct sh_msiof_spi_priv *p, 451 const void *tx_buf, int words, int fs) 452 { 453 const u32 *buf_32 = tx_buf; 454 int k; 455 456 for (k = 0; k < words; k++) 457 sh_msiof_write(p, SITFDR, get_unaligned(&buf_32[k]) << fs); 458 } 459 460 static void sh_msiof_spi_write_fifo_s32(struct sh_msiof_spi_priv *p, 461 const void *tx_buf, int words, int fs) 462 { 463 const u32 *buf_32 = tx_buf; 464 int k; 465 466 for (k = 0; k < words; k++) 467 sh_msiof_write(p, SITFDR, swab32(buf_32[k] << fs)); 468 } 469 470 static void sh_msiof_spi_write_fifo_s32u(struct sh_msiof_spi_priv *p, 471 const void *tx_buf, int words, int fs) 472 { 473 const u32 *buf_32 = tx_buf; 474 int k; 475 476 for (k = 0; k < words; k++) 477 sh_msiof_write(p, SITFDR, swab32(get_unaligned(&buf_32[k]) << fs)); 478 } 479 480 static void sh_msiof_spi_read_fifo_8(struct sh_msiof_spi_priv *p, 481 void *rx_buf, int words, int fs) 482 { 483 u8 *buf_8 = rx_buf; 484 int k; 485 486 for (k = 0; k < words; k++) 487 buf_8[k] = sh_msiof_read(p, SIRFDR) >> fs; 488 } 489 490 static void sh_msiof_spi_read_fifo_16(struct sh_msiof_spi_priv *p, 491 void *rx_buf, int words, int fs) 492 { 493 u16 *buf_16 = rx_buf; 494 int k; 495 496 for (k = 0; k < words; k++) 497 buf_16[k] = sh_msiof_read(p, SIRFDR) >> fs; 498 } 499 500 static void sh_msiof_spi_read_fifo_16u(struct sh_msiof_spi_priv *p, 501 void *rx_buf, int words, int fs) 502 { 503 u16 *buf_16 = rx_buf; 504 int k; 505 506 for (k = 0; k < words; k++) 507 put_unaligned(sh_msiof_read(p, SIRFDR) >> fs, &buf_16[k]); 508 } 509 510 static void sh_msiof_spi_read_fifo_32(struct sh_msiof_spi_priv *p, 511 void *rx_buf, int words, int fs) 512 { 513 u32 *buf_32 = rx_buf; 514 int k; 515 516 for (k = 0; k < words; k++) 517 buf_32[k] = sh_msiof_read(p, SIRFDR) >> fs; 518 } 519 520 static void sh_msiof_spi_read_fifo_32u(struct sh_msiof_spi_priv *p, 521 void *rx_buf, int words, int fs) 522 { 523 u32 *buf_32 = rx_buf; 524 int k; 525 526 for (k = 0; k < words; k++) 527 put_unaligned(sh_msiof_read(p, SIRFDR) >> fs, &buf_32[k]); 528 } 529 530 static void sh_msiof_spi_read_fifo_s32(struct sh_msiof_spi_priv *p, 531 void *rx_buf, int words, int fs) 532 { 533 u32 *buf_32 = rx_buf; 534 int k; 535 536 for (k = 0; k < words; k++) 537 buf_32[k] = swab32(sh_msiof_read(p, SIRFDR) >> fs); 538 } 539 540 static void sh_msiof_spi_read_fifo_s32u(struct sh_msiof_spi_priv *p, 541 void *rx_buf, int words, int fs) 542 { 543 u32 *buf_32 = rx_buf; 544 int k; 545 546 for (k = 0; k < words; k++) 547 put_unaligned(swab32(sh_msiof_read(p, SIRFDR) >> fs), &buf_32[k]); 548 } 549 550 static int sh_msiof_spi_setup(struct spi_device *spi) 551 { 552 struct sh_msiof_spi_priv *p = 553 spi_controller_get_devdata(spi->controller); 554 u32 clr, set, tmp; 555 556 if (spi_get_csgpiod(spi, 0) || spi_controller_is_target(p->ctlr)) 557 return 0; 558 559 if (p->native_cs_inited && 560 (p->native_cs_high == !!(spi->mode & SPI_CS_HIGH))) 561 return 0; 562 563 /* Configure native chip select mode/polarity early */ 564 clr = SIMDR1_SYNCMD_MASK; 565 set = SIMDR1_SYNCMD_SPI; 566 if (spi->mode & SPI_CS_HIGH) 567 clr |= BIT(SIMDR1_SYNCAC_SHIFT); 568 else 569 set |= BIT(SIMDR1_SYNCAC_SHIFT); 570 pm_runtime_get_sync(&p->pdev->dev); 571 tmp = sh_msiof_read(p, SITMDR1) & ~clr; 572 sh_msiof_write(p, SITMDR1, tmp | set | SIMDR1_TRMD | SITMDR1_PCON); 573 tmp = sh_msiof_read(p, SIRMDR1) & ~clr; 574 sh_msiof_write(p, SIRMDR1, tmp | set); 575 pm_runtime_put(&p->pdev->dev); 576 p->native_cs_high = spi->mode & SPI_CS_HIGH; 577 p->native_cs_inited = true; 578 return 0; 579 } 580 581 static int sh_msiof_prepare_message(struct spi_controller *ctlr, 582 struct spi_message *msg) 583 { 584 struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr); 585 const struct spi_device *spi = msg->spi; 586 u32 ss, cs_high; 587 588 /* Configure pins before asserting CS */ 589 if (spi_get_csgpiod(spi, 0)) { 590 ss = ctlr->unused_native_cs; 591 cs_high = p->native_cs_high; 592 } else { 593 ss = spi_get_chipselect(spi, 0); 594 cs_high = !!(spi->mode & SPI_CS_HIGH); 595 } 596 sh_msiof_spi_set_pin_regs(p, ss, !!(spi->mode & SPI_CPOL), 597 !!(spi->mode & SPI_CPHA), 598 !!(spi->mode & SPI_3WIRE), 599 !!(spi->mode & SPI_LSB_FIRST), cs_high); 600 return 0; 601 } 602 603 static int sh_msiof_spi_start(struct sh_msiof_spi_priv *p, void *rx_buf) 604 { 605 bool target = spi_controller_is_target(p->ctlr); 606 int ret = 0; 607 608 /* setup clock and rx/tx signals */ 609 if (!target) 610 ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_TSCKE); 611 if (rx_buf && !ret) 612 ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_RXE); 613 if (!ret) 614 ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_TXE); 615 616 /* start by setting frame bit */ 617 if (!ret && !target) 618 ret = sh_msiof_modify_ctr_wait(p, 0, SICTR_TFSE); 619 620 return ret; 621 } 622 623 static int sh_msiof_spi_stop(struct sh_msiof_spi_priv *p, void *rx_buf) 624 { 625 bool target = spi_controller_is_target(p->ctlr); 626 int ret = 0; 627 628 /* shut down frame, rx/tx and clock signals */ 629 if (!target) 630 ret = sh_msiof_modify_ctr_wait(p, SICTR_TFSE, 0); 631 if (!ret) 632 ret = sh_msiof_modify_ctr_wait(p, SICTR_TXE, 0); 633 if (rx_buf && !ret) 634 ret = sh_msiof_modify_ctr_wait(p, SICTR_RXE, 0); 635 if (!ret && !target) 636 ret = sh_msiof_modify_ctr_wait(p, SICTR_TSCKE, 0); 637 638 return ret; 639 } 640 641 static int sh_msiof_target_abort(struct spi_controller *ctlr) 642 { 643 struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr); 644 645 p->target_aborted = true; 646 complete(&p->done); 647 complete(&p->done_txdma); 648 return 0; 649 } 650 651 static int sh_msiof_wait_for_completion(struct sh_msiof_spi_priv *p, 652 struct completion *x) 653 { 654 if (spi_controller_is_target(p->ctlr)) { 655 if (wait_for_completion_interruptible(x) || 656 p->target_aborted) { 657 dev_dbg(&p->pdev->dev, "interrupted\n"); 658 return -EINTR; 659 } 660 } else { 661 if (!wait_for_completion_timeout(x, HZ)) { 662 dev_err(&p->pdev->dev, "timeout\n"); 663 return -ETIMEDOUT; 664 } 665 } 666 667 return 0; 668 } 669 670 static int sh_msiof_spi_txrx_once(struct sh_msiof_spi_priv *p, 671 void (*tx_fifo)(struct sh_msiof_spi_priv *, 672 const void *, int, int), 673 void (*rx_fifo)(struct sh_msiof_spi_priv *, 674 void *, int, int), 675 const void *tx_buf, void *rx_buf, 676 int words, int bits) 677 { 678 int fifo_shift; 679 int ret; 680 681 /* limit maximum word transfer to rx/tx fifo size */ 682 if (tx_buf) 683 words = min_t(int, words, p->tx_fifo_size); 684 if (rx_buf) 685 words = min_t(int, words, p->rx_fifo_size); 686 687 /* the fifo contents need shifting */ 688 fifo_shift = 32 - bits; 689 690 /* default FIFO watermarks for PIO */ 691 sh_msiof_write(p, SIFCTR, 0); 692 693 /* setup msiof transfer mode registers */ 694 sh_msiof_spi_set_mode_regs(p, tx_buf, rx_buf, bits, words); 695 sh_msiof_write(p, SIIER, SIIER_TEOFE | SIIER_REOFE); 696 697 /* write tx fifo */ 698 if (tx_buf) 699 tx_fifo(p, tx_buf, words, fifo_shift); 700 701 reinit_completion(&p->done); 702 p->target_aborted = false; 703 704 ret = sh_msiof_spi_start(p, rx_buf); 705 if (ret) { 706 dev_err(&p->pdev->dev, "failed to start hardware\n"); 707 goto stop_ier; 708 } 709 710 /* wait for tx fifo to be emptied / rx fifo to be filled */ 711 ret = sh_msiof_wait_for_completion(p, &p->done); 712 if (ret) 713 goto stop_reset; 714 715 /* read rx fifo */ 716 if (rx_buf) 717 rx_fifo(p, rx_buf, words, fifo_shift); 718 719 /* clear status bits */ 720 sh_msiof_reset_str(p); 721 722 ret = sh_msiof_spi_stop(p, rx_buf); 723 if (ret) { 724 dev_err(&p->pdev->dev, "failed to shut down hardware\n"); 725 return ret; 726 } 727 728 return words; 729 730 stop_reset: 731 sh_msiof_reset_str(p); 732 sh_msiof_spi_stop(p, rx_buf); 733 stop_ier: 734 sh_msiof_write(p, SIIER, 0); 735 return ret; 736 } 737 738 static void sh_msiof_dma_complete(void *arg) 739 { 740 complete(arg); 741 } 742 743 static int sh_msiof_dma_once(struct sh_msiof_spi_priv *p, const void *tx, 744 void *rx, unsigned int len) 745 { 746 u32 ier_bits = 0; 747 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL; 748 dma_cookie_t cookie; 749 int ret; 750 751 /* First prepare and submit the DMA request(s), as this may fail */ 752 if (rx) { 753 ier_bits |= SIIER_RDREQE | SIIER_RDMAE; 754 desc_rx = dmaengine_prep_slave_single(p->ctlr->dma_rx, 755 p->rx_dma_addr, len, DMA_DEV_TO_MEM, 756 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 757 if (!desc_rx) 758 return -EAGAIN; 759 760 desc_rx->callback = sh_msiof_dma_complete; 761 desc_rx->callback_param = &p->done; 762 cookie = dmaengine_submit(desc_rx); 763 if (dma_submit_error(cookie)) 764 return cookie; 765 } 766 767 if (tx) { 768 ier_bits |= SIIER_TDREQE | SIIER_TDMAE; 769 dma_sync_single_for_device(p->ctlr->dma_tx->device->dev, 770 p->tx_dma_addr, len, DMA_TO_DEVICE); 771 desc_tx = dmaengine_prep_slave_single(p->ctlr->dma_tx, 772 p->tx_dma_addr, len, DMA_MEM_TO_DEV, 773 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 774 if (!desc_tx) { 775 ret = -EAGAIN; 776 goto no_dma_tx; 777 } 778 779 desc_tx->callback = sh_msiof_dma_complete; 780 desc_tx->callback_param = &p->done_txdma; 781 cookie = dmaengine_submit(desc_tx); 782 if (dma_submit_error(cookie)) { 783 ret = cookie; 784 goto no_dma_tx; 785 } 786 } 787 788 /* 1 stage FIFO watermarks for DMA */ 789 sh_msiof_write(p, SIFCTR, SIFCTR_TFWM_1 | SIFCTR_RFWM_1); 790 791 /* setup msiof transfer mode registers (32-bit words) */ 792 sh_msiof_spi_set_mode_regs(p, tx, rx, 32, len / 4); 793 794 sh_msiof_write(p, SIIER, ier_bits); 795 796 reinit_completion(&p->done); 797 if (tx) 798 reinit_completion(&p->done_txdma); 799 p->target_aborted = false; 800 801 /* Now start DMA */ 802 if (rx) 803 dma_async_issue_pending(p->ctlr->dma_rx); 804 if (tx) 805 dma_async_issue_pending(p->ctlr->dma_tx); 806 807 ret = sh_msiof_spi_start(p, rx); 808 if (ret) { 809 dev_err(&p->pdev->dev, "failed to start hardware\n"); 810 goto stop_dma; 811 } 812 813 if (tx) { 814 /* wait for tx DMA completion */ 815 ret = sh_msiof_wait_for_completion(p, &p->done_txdma); 816 if (ret) 817 goto stop_reset; 818 } 819 820 if (rx) { 821 /* wait for rx DMA completion */ 822 ret = sh_msiof_wait_for_completion(p, &p->done); 823 if (ret) 824 goto stop_reset; 825 826 sh_msiof_write(p, SIIER, 0); 827 } else { 828 /* wait for tx fifo to be emptied */ 829 sh_msiof_write(p, SIIER, SIIER_TEOFE); 830 ret = sh_msiof_wait_for_completion(p, &p->done); 831 if (ret) 832 goto stop_reset; 833 } 834 835 /* clear status bits */ 836 sh_msiof_reset_str(p); 837 838 ret = sh_msiof_spi_stop(p, rx); 839 if (ret) { 840 dev_err(&p->pdev->dev, "failed to shut down hardware\n"); 841 return ret; 842 } 843 844 if (rx) 845 dma_sync_single_for_cpu(p->ctlr->dma_rx->device->dev, 846 p->rx_dma_addr, len, DMA_FROM_DEVICE); 847 848 return 0; 849 850 stop_reset: 851 sh_msiof_reset_str(p); 852 sh_msiof_spi_stop(p, rx); 853 stop_dma: 854 if (tx) 855 dmaengine_terminate_sync(p->ctlr->dma_tx); 856 no_dma_tx: 857 if (rx) 858 dmaengine_terminate_sync(p->ctlr->dma_rx); 859 sh_msiof_write(p, SIIER, 0); 860 return ret; 861 } 862 863 static void copy_bswap32(u32 *dst, const u32 *src, unsigned int words) 864 { 865 /* src or dst can be unaligned, but not both */ 866 if ((unsigned long)src & 3) { 867 while (words--) { 868 *dst++ = swab32(get_unaligned(src)); 869 src++; 870 } 871 } else if ((unsigned long)dst & 3) { 872 while (words--) { 873 put_unaligned(swab32(*src++), dst); 874 dst++; 875 } 876 } else { 877 while (words--) 878 *dst++ = swab32(*src++); 879 } 880 } 881 882 static void copy_wswap32(u32 *dst, const u32 *src, unsigned int words) 883 { 884 /* src or dst can be unaligned, but not both */ 885 if ((unsigned long)src & 3) { 886 while (words--) { 887 *dst++ = swahw32(get_unaligned(src)); 888 src++; 889 } 890 } else if ((unsigned long)dst & 3) { 891 while (words--) { 892 put_unaligned(swahw32(*src++), dst); 893 dst++; 894 } 895 } else { 896 while (words--) 897 *dst++ = swahw32(*src++); 898 } 899 } 900 901 static void copy_plain32(u32 *dst, const u32 *src, unsigned int words) 902 { 903 memcpy(dst, src, words * 4); 904 } 905 906 static int sh_msiof_transfer_one(struct spi_controller *ctlr, 907 struct spi_device *spi, 908 struct spi_transfer *t) 909 { 910 struct sh_msiof_spi_priv *p = spi_controller_get_devdata(ctlr); 911 void (*copy32)(u32 *, const u32 *, unsigned int); 912 void (*tx_fifo)(struct sh_msiof_spi_priv *, const void *, int, int); 913 void (*rx_fifo)(struct sh_msiof_spi_priv *, void *, int, int); 914 const void *tx_buf = t->tx_buf; 915 void *rx_buf = t->rx_buf; 916 unsigned int len = t->len; 917 unsigned int bits = t->bits_per_word; 918 unsigned int bytes_per_word; 919 unsigned int words; 920 int n; 921 bool swab; 922 int ret; 923 924 /* reset registers */ 925 sh_msiof_spi_reset_regs(p); 926 927 /* setup clocks (clock already enabled in chipselect()) */ 928 if (!spi_controller_is_target(p->ctlr)) 929 sh_msiof_spi_set_clk_regs(p, t); 930 931 while (ctlr->dma_tx && len > 15) { 932 /* 933 * DMA supports 32-bit words only, hence pack 8-bit and 16-bit 934 * words, with byte resp. word swapping. 935 */ 936 unsigned int l = 0; 937 938 if (tx_buf) 939 l = min(round_down(len, 4), p->tx_fifo_size * 4); 940 if (rx_buf) 941 l = min(round_down(len, 4), p->rx_fifo_size * 4); 942 943 if (bits <= 8) { 944 copy32 = copy_bswap32; 945 } else if (bits <= 16) { 946 copy32 = copy_wswap32; 947 } else { 948 copy32 = copy_plain32; 949 } 950 951 if (tx_buf) 952 copy32(p->tx_dma_page, tx_buf, l / 4); 953 954 ret = sh_msiof_dma_once(p, tx_buf, rx_buf, l); 955 if (ret == -EAGAIN) { 956 dev_warn_once(&p->pdev->dev, 957 "DMA not available, falling back to PIO\n"); 958 break; 959 } 960 if (ret) 961 return ret; 962 963 if (rx_buf) { 964 copy32(rx_buf, p->rx_dma_page, l / 4); 965 rx_buf += l; 966 } 967 if (tx_buf) 968 tx_buf += l; 969 970 len -= l; 971 if (!len) 972 return 0; 973 } 974 975 if (bits <= 8 && len > 15) { 976 bits = 32; 977 swab = true; 978 } else { 979 swab = false; 980 } 981 982 /* setup bytes per word and fifo read/write functions */ 983 if (bits <= 8) { 984 bytes_per_word = 1; 985 tx_fifo = sh_msiof_spi_write_fifo_8; 986 rx_fifo = sh_msiof_spi_read_fifo_8; 987 } else if (bits <= 16) { 988 bytes_per_word = 2; 989 if ((unsigned long)tx_buf & 0x01) 990 tx_fifo = sh_msiof_spi_write_fifo_16u; 991 else 992 tx_fifo = sh_msiof_spi_write_fifo_16; 993 994 if ((unsigned long)rx_buf & 0x01) 995 rx_fifo = sh_msiof_spi_read_fifo_16u; 996 else 997 rx_fifo = sh_msiof_spi_read_fifo_16; 998 } else if (swab) { 999 bytes_per_word = 4; 1000 if ((unsigned long)tx_buf & 0x03) 1001 tx_fifo = sh_msiof_spi_write_fifo_s32u; 1002 else 1003 tx_fifo = sh_msiof_spi_write_fifo_s32; 1004 1005 if ((unsigned long)rx_buf & 0x03) 1006 rx_fifo = sh_msiof_spi_read_fifo_s32u; 1007 else 1008 rx_fifo = sh_msiof_spi_read_fifo_s32; 1009 } else { 1010 bytes_per_word = 4; 1011 if ((unsigned long)tx_buf & 0x03) 1012 tx_fifo = sh_msiof_spi_write_fifo_32u; 1013 else 1014 tx_fifo = sh_msiof_spi_write_fifo_32; 1015 1016 if ((unsigned long)rx_buf & 0x03) 1017 rx_fifo = sh_msiof_spi_read_fifo_32u; 1018 else 1019 rx_fifo = sh_msiof_spi_read_fifo_32; 1020 } 1021 1022 /* transfer in fifo sized chunks */ 1023 words = len / bytes_per_word; 1024 1025 while (words > 0) { 1026 n = sh_msiof_spi_txrx_once(p, tx_fifo, rx_fifo, tx_buf, rx_buf, 1027 words, bits); 1028 if (n < 0) 1029 return n; 1030 1031 if (tx_buf) 1032 tx_buf += n * bytes_per_word; 1033 if (rx_buf) 1034 rx_buf += n * bytes_per_word; 1035 words -= n; 1036 1037 if (words == 0 && (len % bytes_per_word)) { 1038 words = len % bytes_per_word; 1039 bits = t->bits_per_word; 1040 bytes_per_word = 1; 1041 tx_fifo = sh_msiof_spi_write_fifo_8; 1042 rx_fifo = sh_msiof_spi_read_fifo_8; 1043 } 1044 } 1045 1046 return 0; 1047 } 1048 1049 static const struct sh_msiof_chipdata sh_data = { 1050 .bits_per_word_mask = SPI_BPW_RANGE_MASK(8, 32), 1051 .tx_fifo_size = 64, 1052 .rx_fifo_size = 64, 1053 .ctlr_flags = 0, 1054 .min_div_pow = 0, 1055 }; 1056 1057 static const struct sh_msiof_chipdata rcar_gen2_data = { 1058 .bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) | 1059 SPI_BPW_MASK(24) | SPI_BPW_MASK(32), 1060 .tx_fifo_size = 64, 1061 .rx_fifo_size = 64, 1062 .ctlr_flags = SPI_CONTROLLER_MUST_TX, 1063 .min_div_pow = 0, 1064 }; 1065 1066 static const struct sh_msiof_chipdata rcar_gen3_data = { 1067 .bits_per_word_mask = SPI_BPW_MASK(8) | SPI_BPW_MASK(16) | 1068 SPI_BPW_MASK(24) | SPI_BPW_MASK(32), 1069 .tx_fifo_size = 64, 1070 .rx_fifo_size = 64, 1071 .ctlr_flags = SPI_CONTROLLER_MUST_TX, 1072 .min_div_pow = 1, 1073 }; 1074 1075 static const struct of_device_id sh_msiof_match[] __maybe_unused = { 1076 { .compatible = "renesas,sh-mobile-msiof", .data = &sh_data }, 1077 { .compatible = "renesas,msiof-r8a7743", .data = &rcar_gen2_data }, 1078 { .compatible = "renesas,msiof-r8a7745", .data = &rcar_gen2_data }, 1079 { .compatible = "renesas,msiof-r8a7790", .data = &rcar_gen2_data }, 1080 { .compatible = "renesas,msiof-r8a7791", .data = &rcar_gen2_data }, 1081 { .compatible = "renesas,msiof-r8a7792", .data = &rcar_gen2_data }, 1082 { .compatible = "renesas,msiof-r8a7793", .data = &rcar_gen2_data }, 1083 { .compatible = "renesas,msiof-r8a7794", .data = &rcar_gen2_data }, 1084 { .compatible = "renesas,rcar-gen2-msiof", .data = &rcar_gen2_data }, 1085 { .compatible = "renesas,msiof-r8a7796", .data = &rcar_gen3_data }, 1086 { .compatible = "renesas,rcar-gen3-msiof", .data = &rcar_gen3_data }, 1087 { .compatible = "renesas,rcar-gen4-msiof", .data = &rcar_gen3_data }, 1088 { .compatible = "renesas,sh-msiof", .data = &sh_data }, /* Deprecated */ 1089 {}, 1090 }; 1091 MODULE_DEVICE_TABLE(of, sh_msiof_match); 1092 1093 #ifdef CONFIG_OF 1094 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) 1095 { 1096 struct sh_msiof_spi_info *info; 1097 struct device_node *np = dev->of_node; 1098 u32 num_cs = 1; 1099 1100 info = devm_kzalloc(dev, sizeof(struct sh_msiof_spi_info), GFP_KERNEL); 1101 if (!info) 1102 return NULL; 1103 1104 info->mode = of_property_read_bool(np, "spi-slave") ? MSIOF_SPI_TARGET 1105 : MSIOF_SPI_HOST; 1106 1107 /* Parse the MSIOF properties */ 1108 if (info->mode == MSIOF_SPI_HOST) 1109 of_property_read_u32(np, "num-cs", &num_cs); 1110 of_property_read_u32(np, "renesas,tx-fifo-size", 1111 &info->tx_fifo_override); 1112 of_property_read_u32(np, "renesas,rx-fifo-size", 1113 &info->rx_fifo_override); 1114 of_property_read_u32(np, "renesas,dtdl", &info->dtdl); 1115 of_property_read_u32(np, "renesas,syncdl", &info->syncdl); 1116 1117 info->num_chipselect = num_cs; 1118 1119 return info; 1120 } 1121 #else 1122 static struct sh_msiof_spi_info *sh_msiof_spi_parse_dt(struct device *dev) 1123 { 1124 return NULL; 1125 } 1126 #endif 1127 1128 static struct dma_chan *sh_msiof_request_dma_chan(struct device *dev, 1129 enum dma_transfer_direction dir, unsigned int id, dma_addr_t port_addr) 1130 { 1131 dma_cap_mask_t mask; 1132 struct dma_chan *chan; 1133 struct dma_slave_config cfg; 1134 int ret; 1135 1136 dma_cap_zero(mask); 1137 dma_cap_set(DMA_SLAVE, mask); 1138 1139 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter, 1140 (void *)(unsigned long)id, dev, 1141 dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 1142 if (!chan) { 1143 dev_warn(dev, "dma_request_slave_channel_compat failed\n"); 1144 return NULL; 1145 } 1146 1147 memset(&cfg, 0, sizeof(cfg)); 1148 cfg.direction = dir; 1149 if (dir == DMA_MEM_TO_DEV) { 1150 cfg.dst_addr = port_addr; 1151 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1152 } else { 1153 cfg.src_addr = port_addr; 1154 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 1155 } 1156 1157 ret = dmaengine_slave_config(chan, &cfg); 1158 if (ret) { 1159 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret); 1160 dma_release_channel(chan); 1161 return NULL; 1162 } 1163 1164 return chan; 1165 } 1166 1167 static int sh_msiof_request_dma(struct sh_msiof_spi_priv *p) 1168 { 1169 struct platform_device *pdev = p->pdev; 1170 struct device *dev = &pdev->dev; 1171 const struct sh_msiof_spi_info *info = p->info; 1172 unsigned int dma_tx_id, dma_rx_id; 1173 const struct resource *res; 1174 struct spi_controller *ctlr; 1175 struct device *tx_dev, *rx_dev; 1176 1177 if (dev->of_node) { 1178 /* In the OF case we will get the slave IDs from the DT */ 1179 dma_tx_id = 0; 1180 dma_rx_id = 0; 1181 } else if (info && info->dma_tx_id && info->dma_rx_id) { 1182 dma_tx_id = info->dma_tx_id; 1183 dma_rx_id = info->dma_rx_id; 1184 } else { 1185 /* The driver assumes no error */ 1186 return 0; 1187 } 1188 1189 /* The DMA engine uses the second register set, if present */ 1190 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 1191 if (!res) 1192 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1193 1194 ctlr = p->ctlr; 1195 ctlr->dma_tx = sh_msiof_request_dma_chan(dev, DMA_MEM_TO_DEV, 1196 dma_tx_id, res->start + SITFDR); 1197 if (!ctlr->dma_tx) 1198 return -ENODEV; 1199 1200 ctlr->dma_rx = sh_msiof_request_dma_chan(dev, DMA_DEV_TO_MEM, 1201 dma_rx_id, res->start + SIRFDR); 1202 if (!ctlr->dma_rx) 1203 goto free_tx_chan; 1204 1205 p->tx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA); 1206 if (!p->tx_dma_page) 1207 goto free_rx_chan; 1208 1209 p->rx_dma_page = (void *)__get_free_page(GFP_KERNEL | GFP_DMA); 1210 if (!p->rx_dma_page) 1211 goto free_tx_page; 1212 1213 tx_dev = ctlr->dma_tx->device->dev; 1214 p->tx_dma_addr = dma_map_single(tx_dev, p->tx_dma_page, PAGE_SIZE, 1215 DMA_TO_DEVICE); 1216 if (dma_mapping_error(tx_dev, p->tx_dma_addr)) 1217 goto free_rx_page; 1218 1219 rx_dev = ctlr->dma_rx->device->dev; 1220 p->rx_dma_addr = dma_map_single(rx_dev, p->rx_dma_page, PAGE_SIZE, 1221 DMA_FROM_DEVICE); 1222 if (dma_mapping_error(rx_dev, p->rx_dma_addr)) 1223 goto unmap_tx_page; 1224 1225 dev_info(dev, "DMA available"); 1226 return 0; 1227 1228 unmap_tx_page: 1229 dma_unmap_single(tx_dev, p->tx_dma_addr, PAGE_SIZE, DMA_TO_DEVICE); 1230 free_rx_page: 1231 free_page((unsigned long)p->rx_dma_page); 1232 free_tx_page: 1233 free_page((unsigned long)p->tx_dma_page); 1234 free_rx_chan: 1235 dma_release_channel(ctlr->dma_rx); 1236 free_tx_chan: 1237 dma_release_channel(ctlr->dma_tx); 1238 ctlr->dma_tx = NULL; 1239 return -ENODEV; 1240 } 1241 1242 static void sh_msiof_release_dma(struct sh_msiof_spi_priv *p) 1243 { 1244 struct spi_controller *ctlr = p->ctlr; 1245 1246 if (!ctlr->dma_tx) 1247 return; 1248 1249 dma_unmap_single(ctlr->dma_rx->device->dev, p->rx_dma_addr, PAGE_SIZE, 1250 DMA_FROM_DEVICE); 1251 dma_unmap_single(ctlr->dma_tx->device->dev, p->tx_dma_addr, PAGE_SIZE, 1252 DMA_TO_DEVICE); 1253 free_page((unsigned long)p->rx_dma_page); 1254 free_page((unsigned long)p->tx_dma_page); 1255 dma_release_channel(ctlr->dma_rx); 1256 dma_release_channel(ctlr->dma_tx); 1257 } 1258 1259 static int sh_msiof_spi_probe(struct platform_device *pdev) 1260 { 1261 struct spi_controller *ctlr; 1262 const struct sh_msiof_chipdata *chipdata; 1263 struct sh_msiof_spi_info *info; 1264 struct sh_msiof_spi_priv *p; 1265 unsigned long clksrc; 1266 int i; 1267 int ret; 1268 1269 chipdata = of_device_get_match_data(&pdev->dev); 1270 if (chipdata) { 1271 info = sh_msiof_spi_parse_dt(&pdev->dev); 1272 } else { 1273 chipdata = (const void *)pdev->id_entry->driver_data; 1274 info = dev_get_platdata(&pdev->dev); 1275 } 1276 1277 if (!info) { 1278 dev_err(&pdev->dev, "failed to obtain device info\n"); 1279 return -ENXIO; 1280 } 1281 1282 if (info->mode == MSIOF_SPI_TARGET) 1283 ctlr = spi_alloc_target(&pdev->dev, 1284 sizeof(struct sh_msiof_spi_priv)); 1285 else 1286 ctlr = spi_alloc_host(&pdev->dev, 1287 sizeof(struct sh_msiof_spi_priv)); 1288 if (ctlr == NULL) 1289 return -ENOMEM; 1290 1291 p = spi_controller_get_devdata(ctlr); 1292 1293 platform_set_drvdata(pdev, p); 1294 p->ctlr = ctlr; 1295 p->info = info; 1296 p->min_div_pow = chipdata->min_div_pow; 1297 1298 init_completion(&p->done); 1299 init_completion(&p->done_txdma); 1300 1301 p->clk = devm_clk_get(&pdev->dev, NULL); 1302 if (IS_ERR(p->clk)) { 1303 dev_err(&pdev->dev, "cannot get clock\n"); 1304 ret = PTR_ERR(p->clk); 1305 goto err1; 1306 } 1307 1308 i = platform_get_irq(pdev, 0); 1309 if (i < 0) { 1310 ret = i; 1311 goto err1; 1312 } 1313 1314 p->mapbase = devm_platform_ioremap_resource(pdev, 0); 1315 if (IS_ERR(p->mapbase)) { 1316 ret = PTR_ERR(p->mapbase); 1317 goto err1; 1318 } 1319 1320 ret = devm_request_irq(&pdev->dev, i, sh_msiof_spi_irq, 0, 1321 dev_name(&pdev->dev), p); 1322 if (ret) { 1323 dev_err(&pdev->dev, "unable to request irq\n"); 1324 goto err1; 1325 } 1326 1327 p->pdev = pdev; 1328 pm_runtime_enable(&pdev->dev); 1329 1330 /* Platform data may override FIFO sizes */ 1331 p->tx_fifo_size = chipdata->tx_fifo_size; 1332 p->rx_fifo_size = chipdata->rx_fifo_size; 1333 if (p->info->tx_fifo_override) 1334 p->tx_fifo_size = p->info->tx_fifo_override; 1335 if (p->info->rx_fifo_override) 1336 p->rx_fifo_size = p->info->rx_fifo_override; 1337 1338 /* init controller code */ 1339 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1340 ctlr->mode_bits |= SPI_LSB_FIRST | SPI_3WIRE; 1341 clksrc = clk_get_rate(p->clk); 1342 ctlr->min_speed_hz = DIV_ROUND_UP(clksrc, 1024); 1343 ctlr->max_speed_hz = DIV_ROUND_UP(clksrc, 1 << p->min_div_pow); 1344 ctlr->flags = chipdata->ctlr_flags; 1345 ctlr->bus_num = pdev->id; 1346 ctlr->num_chipselect = p->info->num_chipselect; 1347 ctlr->dev.of_node = pdev->dev.of_node; 1348 ctlr->setup = sh_msiof_spi_setup; 1349 ctlr->prepare_message = sh_msiof_prepare_message; 1350 ctlr->target_abort = sh_msiof_target_abort; 1351 ctlr->bits_per_word_mask = chipdata->bits_per_word_mask; 1352 ctlr->auto_runtime_pm = true; 1353 ctlr->transfer_one = sh_msiof_transfer_one; 1354 ctlr->use_gpio_descriptors = true; 1355 ctlr->max_native_cs = MAX_SS; 1356 1357 ret = sh_msiof_request_dma(p); 1358 if (ret < 0) 1359 dev_warn(&pdev->dev, "DMA not available, using PIO\n"); 1360 1361 ret = devm_spi_register_controller(&pdev->dev, ctlr); 1362 if (ret < 0) { 1363 dev_err(&pdev->dev, "devm_spi_register_controller error.\n"); 1364 goto err2; 1365 } 1366 1367 return 0; 1368 1369 err2: 1370 sh_msiof_release_dma(p); 1371 pm_runtime_disable(&pdev->dev); 1372 err1: 1373 spi_controller_put(ctlr); 1374 return ret; 1375 } 1376 1377 static void sh_msiof_spi_remove(struct platform_device *pdev) 1378 { 1379 struct sh_msiof_spi_priv *p = platform_get_drvdata(pdev); 1380 1381 sh_msiof_release_dma(p); 1382 pm_runtime_disable(&pdev->dev); 1383 } 1384 1385 static const struct platform_device_id spi_driver_ids[] = { 1386 { "spi_sh_msiof", (kernel_ulong_t)&sh_data }, 1387 {}, 1388 }; 1389 MODULE_DEVICE_TABLE(platform, spi_driver_ids); 1390 1391 #ifdef CONFIG_PM_SLEEP 1392 static int sh_msiof_spi_suspend(struct device *dev) 1393 { 1394 struct sh_msiof_spi_priv *p = dev_get_drvdata(dev); 1395 1396 return spi_controller_suspend(p->ctlr); 1397 } 1398 1399 static int sh_msiof_spi_resume(struct device *dev) 1400 { 1401 struct sh_msiof_spi_priv *p = dev_get_drvdata(dev); 1402 1403 return spi_controller_resume(p->ctlr); 1404 } 1405 1406 static SIMPLE_DEV_PM_OPS(sh_msiof_spi_pm_ops, sh_msiof_spi_suspend, 1407 sh_msiof_spi_resume); 1408 #define DEV_PM_OPS (&sh_msiof_spi_pm_ops) 1409 #else 1410 #define DEV_PM_OPS NULL 1411 #endif /* CONFIG_PM_SLEEP */ 1412 1413 static struct platform_driver sh_msiof_spi_drv = { 1414 .probe = sh_msiof_spi_probe, 1415 .remove_new = sh_msiof_spi_remove, 1416 .id_table = spi_driver_ids, 1417 .driver = { 1418 .name = "spi_sh_msiof", 1419 .pm = DEV_PM_OPS, 1420 .of_match_table = of_match_ptr(sh_msiof_match), 1421 }, 1422 }; 1423 module_platform_driver(sh_msiof_spi_drv); 1424 1425 MODULE_DESCRIPTION("SuperH MSIOF SPI Controller Interface Driver"); 1426 MODULE_AUTHOR("Magnus Damm"); 1427 MODULE_LICENSE("GPL v2"); 1428