1 /* 2 * Copyright (C) 2009 Samsung Electronics Ltd. 3 * Jaswinder Singh <jassi.brar@samsung.com> 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. 18 */ 19 20 #include <linux/init.h> 21 #include <linux/module.h> 22 #include <linux/workqueue.h> 23 #include <linux/delay.h> 24 #include <linux/clk.h> 25 #include <linux/dma-mapping.h> 26 #include <linux/platform_device.h> 27 #include <linux/spi/spi.h> 28 29 #include <mach/dma.h> 30 #include <plat/s3c64xx-spi.h> 31 32 /* Registers and bit-fields */ 33 34 #define S3C64XX_SPI_CH_CFG 0x00 35 #define S3C64XX_SPI_CLK_CFG 0x04 36 #define S3C64XX_SPI_MODE_CFG 0x08 37 #define S3C64XX_SPI_SLAVE_SEL 0x0C 38 #define S3C64XX_SPI_INT_EN 0x10 39 #define S3C64XX_SPI_STATUS 0x14 40 #define S3C64XX_SPI_TX_DATA 0x18 41 #define S3C64XX_SPI_RX_DATA 0x1C 42 #define S3C64XX_SPI_PACKET_CNT 0x20 43 #define S3C64XX_SPI_PENDING_CLR 0x24 44 #define S3C64XX_SPI_SWAP_CFG 0x28 45 #define S3C64XX_SPI_FB_CLK 0x2C 46 47 #define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */ 48 #define S3C64XX_SPI_CH_SW_RST (1<<5) 49 #define S3C64XX_SPI_CH_SLAVE (1<<4) 50 #define S3C64XX_SPI_CPOL_L (1<<3) 51 #define S3C64XX_SPI_CPHA_B (1<<2) 52 #define S3C64XX_SPI_CH_RXCH_ON (1<<1) 53 #define S3C64XX_SPI_CH_TXCH_ON (1<<0) 54 55 #define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9) 56 #define S3C64XX_SPI_CLKSEL_SRCSHFT 9 57 #define S3C64XX_SPI_ENCLK_ENABLE (1<<8) 58 #define S3C64XX_SPI_PSR_MASK 0xff 59 60 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29) 61 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29) 62 #define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29) 63 #define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29) 64 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17) 65 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17) 66 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17) 67 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17) 68 #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2) 69 #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1) 70 #define S3C64XX_SPI_MODE_4BURST (1<<0) 71 72 #define S3C64XX_SPI_SLAVE_AUTO (1<<1) 73 #define S3C64XX_SPI_SLAVE_SIG_INACT (1<<0) 74 75 #define S3C64XX_SPI_ACT(c) writel(0, (c)->regs + S3C64XX_SPI_SLAVE_SEL) 76 77 #define S3C64XX_SPI_DEACT(c) writel(S3C64XX_SPI_SLAVE_SIG_INACT, \ 78 (c)->regs + S3C64XX_SPI_SLAVE_SEL) 79 80 #define S3C64XX_SPI_INT_TRAILING_EN (1<<6) 81 #define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5) 82 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4) 83 #define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3) 84 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2) 85 #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1) 86 #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0) 87 88 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5) 89 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4) 90 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3) 91 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2) 92 #define S3C64XX_SPI_ST_RX_FIFORDY (1<<1) 93 #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0) 94 95 #define S3C64XX_SPI_PACKET_CNT_EN (1<<16) 96 97 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4) 98 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3) 99 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2) 100 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1) 101 #define S3C64XX_SPI_PND_TRAILING_CLR (1<<0) 102 103 #define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7) 104 #define S3C64XX_SPI_SWAP_RX_BYTE (1<<6) 105 #define S3C64XX_SPI_SWAP_RX_BIT (1<<5) 106 #define S3C64XX_SPI_SWAP_RX_EN (1<<4) 107 #define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3) 108 #define S3C64XX_SPI_SWAP_TX_BYTE (1<<2) 109 #define S3C64XX_SPI_SWAP_TX_BIT (1<<1) 110 #define S3C64XX_SPI_SWAP_TX_EN (1<<0) 111 112 #define S3C64XX_SPI_FBCLK_MSK (3<<0) 113 114 #define S3C64XX_SPI_ST_TRLCNTZ(v, i) ((((v) >> (i)->rx_lvl_offset) & \ 115 (((i)->fifo_lvl_mask + 1))) \ 116 ? 1 : 0) 117 118 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & (1 << (i)->tx_st_done)) ? 1 : 0) 119 #define TX_FIFO_LVL(v, i) (((v) >> 6) & (i)->fifo_lvl_mask) 120 #define RX_FIFO_LVL(v, i) (((v) >> (i)->rx_lvl_offset) & (i)->fifo_lvl_mask) 121 122 #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff 123 #define S3C64XX_SPI_TRAILCNT_OFF 19 124 125 #define S3C64XX_SPI_TRAILCNT S3C64XX_SPI_MAX_TRAILCNT 126 127 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) 128 129 #define SUSPND (1<<0) 130 #define SPIBUSY (1<<1) 131 #define RXBUSY (1<<2) 132 #define TXBUSY (1<<3) 133 134 struct s3c64xx_spi_dma_data { 135 unsigned ch; 136 enum dma_data_direction direction; 137 enum dma_ch dmach; 138 }; 139 140 /** 141 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver. 142 * @clk: Pointer to the spi clock. 143 * @src_clk: Pointer to the clock used to generate SPI signals. 144 * @master: Pointer to the SPI Protocol master. 145 * @workqueue: Work queue for the SPI xfer requests. 146 * @cntrlr_info: Platform specific data for the controller this driver manages. 147 * @tgl_spi: Pointer to the last CS left untoggled by the cs_change hint. 148 * @work: Work 149 * @queue: To log SPI xfer requests. 150 * @lock: Controller specific lock. 151 * @state: Set of FLAGS to indicate status. 152 * @rx_dmach: Controller's DMA channel for Rx. 153 * @tx_dmach: Controller's DMA channel for Tx. 154 * @sfr_start: BUS address of SPI controller regs. 155 * @regs: Pointer to ioremap'ed controller registers. 156 * @xfer_completion: To indicate completion of xfer task. 157 * @cur_mode: Stores the active configuration of the controller. 158 * @cur_bpw: Stores the active bits per word settings. 159 * @cur_speed: Stores the active xfer clock speed. 160 */ 161 struct s3c64xx_spi_driver_data { 162 void __iomem *regs; 163 struct clk *clk; 164 struct clk *src_clk; 165 struct platform_device *pdev; 166 struct spi_master *master; 167 struct workqueue_struct *workqueue; 168 struct s3c64xx_spi_info *cntrlr_info; 169 struct spi_device *tgl_spi; 170 struct work_struct work; 171 struct list_head queue; 172 spinlock_t lock; 173 unsigned long sfr_start; 174 struct completion xfer_completion; 175 unsigned state; 176 unsigned cur_mode, cur_bpw; 177 unsigned cur_speed; 178 struct s3c64xx_spi_dma_data rx_dma; 179 struct s3c64xx_spi_dma_data tx_dma; 180 struct samsung_dma_ops *ops; 181 }; 182 183 static struct s3c2410_dma_client s3c64xx_spi_dma_client = { 184 .name = "samsung-spi-dma", 185 }; 186 187 static void flush_fifo(struct s3c64xx_spi_driver_data *sdd) 188 { 189 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 190 void __iomem *regs = sdd->regs; 191 unsigned long loops; 192 u32 val; 193 194 writel(0, regs + S3C64XX_SPI_PACKET_CNT); 195 196 val = readl(regs + S3C64XX_SPI_CH_CFG); 197 val |= S3C64XX_SPI_CH_SW_RST; 198 val &= ~S3C64XX_SPI_CH_HS_EN; 199 writel(val, regs + S3C64XX_SPI_CH_CFG); 200 201 /* Flush TxFIFO*/ 202 loops = msecs_to_loops(1); 203 do { 204 val = readl(regs + S3C64XX_SPI_STATUS); 205 } while (TX_FIFO_LVL(val, sci) && loops--); 206 207 if (loops == 0) 208 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); 209 210 /* Flush RxFIFO*/ 211 loops = msecs_to_loops(1); 212 do { 213 val = readl(regs + S3C64XX_SPI_STATUS); 214 if (RX_FIFO_LVL(val, sci)) 215 readl(regs + S3C64XX_SPI_RX_DATA); 216 else 217 break; 218 } while (loops--); 219 220 if (loops == 0) 221 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n"); 222 223 val = readl(regs + S3C64XX_SPI_CH_CFG); 224 val &= ~S3C64XX_SPI_CH_SW_RST; 225 writel(val, regs + S3C64XX_SPI_CH_CFG); 226 227 val = readl(regs + S3C64XX_SPI_MODE_CFG); 228 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); 229 writel(val, regs + S3C64XX_SPI_MODE_CFG); 230 231 val = readl(regs + S3C64XX_SPI_CH_CFG); 232 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON); 233 writel(val, regs + S3C64XX_SPI_CH_CFG); 234 } 235 236 static void s3c64xx_spi_dmacb(void *data) 237 { 238 struct s3c64xx_spi_driver_data *sdd; 239 struct s3c64xx_spi_dma_data *dma = data; 240 unsigned long flags; 241 242 if (dma->direction == DMA_FROM_DEVICE) 243 sdd = container_of(data, 244 struct s3c64xx_spi_driver_data, rx_dma); 245 else 246 sdd = container_of(data, 247 struct s3c64xx_spi_driver_data, tx_dma); 248 249 spin_lock_irqsave(&sdd->lock, flags); 250 251 if (dma->direction == DMA_FROM_DEVICE) { 252 sdd->state &= ~RXBUSY; 253 if (!(sdd->state & TXBUSY)) 254 complete(&sdd->xfer_completion); 255 } else { 256 sdd->state &= ~TXBUSY; 257 if (!(sdd->state & RXBUSY)) 258 complete(&sdd->xfer_completion); 259 } 260 261 spin_unlock_irqrestore(&sdd->lock, flags); 262 } 263 264 static void prepare_dma(struct s3c64xx_spi_dma_data *dma, 265 unsigned len, dma_addr_t buf) 266 { 267 struct s3c64xx_spi_driver_data *sdd; 268 struct samsung_dma_prep_info info; 269 270 if (dma->direction == DMA_FROM_DEVICE) 271 sdd = container_of((void *)dma, 272 struct s3c64xx_spi_driver_data, rx_dma); 273 else 274 sdd = container_of((void *)dma, 275 struct s3c64xx_spi_driver_data, tx_dma); 276 277 info.cap = DMA_SLAVE; 278 info.len = len; 279 info.fp = s3c64xx_spi_dmacb; 280 info.fp_param = dma; 281 info.direction = dma->direction; 282 info.buf = buf; 283 284 sdd->ops->prepare(dma->ch, &info); 285 sdd->ops->trigger(dma->ch); 286 } 287 288 static int acquire_dma(struct s3c64xx_spi_driver_data *sdd) 289 { 290 struct samsung_dma_info info; 291 292 sdd->ops = samsung_dma_get_ops(); 293 294 info.cap = DMA_SLAVE; 295 info.client = &s3c64xx_spi_dma_client; 296 info.width = sdd->cur_bpw / 8; 297 298 info.direction = sdd->rx_dma.direction; 299 info.fifo = sdd->sfr_start + S3C64XX_SPI_RX_DATA; 300 sdd->rx_dma.ch = sdd->ops->request(sdd->rx_dma.dmach, &info); 301 info.direction = sdd->tx_dma.direction; 302 info.fifo = sdd->sfr_start + S3C64XX_SPI_TX_DATA; 303 sdd->tx_dma.ch = sdd->ops->request(sdd->tx_dma.dmach, &info); 304 305 return 1; 306 } 307 308 static void enable_datapath(struct s3c64xx_spi_driver_data *sdd, 309 struct spi_device *spi, 310 struct spi_transfer *xfer, int dma_mode) 311 { 312 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 313 void __iomem *regs = sdd->regs; 314 u32 modecfg, chcfg; 315 316 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG); 317 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); 318 319 chcfg = readl(regs + S3C64XX_SPI_CH_CFG); 320 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON; 321 322 if (dma_mode) { 323 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON; 324 } else { 325 /* Always shift in data in FIFO, even if xfer is Tx only, 326 * this helps setting PCKT_CNT value for generating clocks 327 * as exactly needed. 328 */ 329 chcfg |= S3C64XX_SPI_CH_RXCH_ON; 330 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) 331 | S3C64XX_SPI_PACKET_CNT_EN, 332 regs + S3C64XX_SPI_PACKET_CNT); 333 } 334 335 if (xfer->tx_buf != NULL) { 336 sdd->state |= TXBUSY; 337 chcfg |= S3C64XX_SPI_CH_TXCH_ON; 338 if (dma_mode) { 339 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON; 340 prepare_dma(&sdd->tx_dma, xfer->len, xfer->tx_dma); 341 } else { 342 switch (sdd->cur_bpw) { 343 case 32: 344 iowrite32_rep(regs + S3C64XX_SPI_TX_DATA, 345 xfer->tx_buf, xfer->len / 4); 346 break; 347 case 16: 348 iowrite16_rep(regs + S3C64XX_SPI_TX_DATA, 349 xfer->tx_buf, xfer->len / 2); 350 break; 351 default: 352 iowrite8_rep(regs + S3C64XX_SPI_TX_DATA, 353 xfer->tx_buf, xfer->len); 354 break; 355 } 356 } 357 } 358 359 if (xfer->rx_buf != NULL) { 360 sdd->state |= RXBUSY; 361 362 if (sci->high_speed && sdd->cur_speed >= 30000000UL 363 && !(sdd->cur_mode & SPI_CPHA)) 364 chcfg |= S3C64XX_SPI_CH_HS_EN; 365 366 if (dma_mode) { 367 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON; 368 chcfg |= S3C64XX_SPI_CH_RXCH_ON; 369 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) 370 | S3C64XX_SPI_PACKET_CNT_EN, 371 regs + S3C64XX_SPI_PACKET_CNT); 372 prepare_dma(&sdd->rx_dma, xfer->len, xfer->rx_dma); 373 } 374 } 375 376 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG); 377 writel(chcfg, regs + S3C64XX_SPI_CH_CFG); 378 } 379 380 static inline void enable_cs(struct s3c64xx_spi_driver_data *sdd, 381 struct spi_device *spi) 382 { 383 struct s3c64xx_spi_csinfo *cs; 384 385 if (sdd->tgl_spi != NULL) { /* If last device toggled after mssg */ 386 if (sdd->tgl_spi != spi) { /* if last mssg on diff device */ 387 /* Deselect the last toggled device */ 388 cs = sdd->tgl_spi->controller_data; 389 cs->set_level(cs->line, 390 spi->mode & SPI_CS_HIGH ? 0 : 1); 391 } 392 sdd->tgl_spi = NULL; 393 } 394 395 cs = spi->controller_data; 396 cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 1 : 0); 397 } 398 399 static int wait_for_xfer(struct s3c64xx_spi_driver_data *sdd, 400 struct spi_transfer *xfer, int dma_mode) 401 { 402 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 403 void __iomem *regs = sdd->regs; 404 unsigned long val; 405 int ms; 406 407 /* millisecs to xfer 'len' bytes @ 'cur_speed' */ 408 ms = xfer->len * 8 * 1000 / sdd->cur_speed; 409 ms += 10; /* some tolerance */ 410 411 if (dma_mode) { 412 val = msecs_to_jiffies(ms) + 10; 413 val = wait_for_completion_timeout(&sdd->xfer_completion, val); 414 } else { 415 u32 status; 416 val = msecs_to_loops(ms); 417 do { 418 status = readl(regs + S3C64XX_SPI_STATUS); 419 } while (RX_FIFO_LVL(status, sci) < xfer->len && --val); 420 } 421 422 if (!val) 423 return -EIO; 424 425 if (dma_mode) { 426 u32 status; 427 428 /* 429 * DmaTx returns after simply writing data in the FIFO, 430 * w/o waiting for real transmission on the bus to finish. 431 * DmaRx returns only after Dma read data from FIFO which 432 * needs bus transmission to finish, so we don't worry if 433 * Xfer involved Rx(with or without Tx). 434 */ 435 if (xfer->rx_buf == NULL) { 436 val = msecs_to_loops(10); 437 status = readl(regs + S3C64XX_SPI_STATUS); 438 while ((TX_FIFO_LVL(status, sci) 439 || !S3C64XX_SPI_ST_TX_DONE(status, sci)) 440 && --val) { 441 cpu_relax(); 442 status = readl(regs + S3C64XX_SPI_STATUS); 443 } 444 445 if (!val) 446 return -EIO; 447 } 448 } else { 449 /* If it was only Tx */ 450 if (xfer->rx_buf == NULL) { 451 sdd->state &= ~TXBUSY; 452 return 0; 453 } 454 455 switch (sdd->cur_bpw) { 456 case 32: 457 ioread32_rep(regs + S3C64XX_SPI_RX_DATA, 458 xfer->rx_buf, xfer->len / 4); 459 break; 460 case 16: 461 ioread16_rep(regs + S3C64XX_SPI_RX_DATA, 462 xfer->rx_buf, xfer->len / 2); 463 break; 464 default: 465 ioread8_rep(regs + S3C64XX_SPI_RX_DATA, 466 xfer->rx_buf, xfer->len); 467 break; 468 } 469 sdd->state &= ~RXBUSY; 470 } 471 472 return 0; 473 } 474 475 static inline void disable_cs(struct s3c64xx_spi_driver_data *sdd, 476 struct spi_device *spi) 477 { 478 struct s3c64xx_spi_csinfo *cs = spi->controller_data; 479 480 if (sdd->tgl_spi == spi) 481 sdd->tgl_spi = NULL; 482 483 cs->set_level(cs->line, spi->mode & SPI_CS_HIGH ? 0 : 1); 484 } 485 486 static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) 487 { 488 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 489 void __iomem *regs = sdd->regs; 490 u32 val; 491 492 /* Disable Clock */ 493 if (sci->clk_from_cmu) { 494 clk_disable(sdd->src_clk); 495 } else { 496 val = readl(regs + S3C64XX_SPI_CLK_CFG); 497 val &= ~S3C64XX_SPI_ENCLK_ENABLE; 498 writel(val, regs + S3C64XX_SPI_CLK_CFG); 499 } 500 501 /* Set Polarity and Phase */ 502 val = readl(regs + S3C64XX_SPI_CH_CFG); 503 val &= ~(S3C64XX_SPI_CH_SLAVE | 504 S3C64XX_SPI_CPOL_L | 505 S3C64XX_SPI_CPHA_B); 506 507 if (sdd->cur_mode & SPI_CPOL) 508 val |= S3C64XX_SPI_CPOL_L; 509 510 if (sdd->cur_mode & SPI_CPHA) 511 val |= S3C64XX_SPI_CPHA_B; 512 513 writel(val, regs + S3C64XX_SPI_CH_CFG); 514 515 /* Set Channel & DMA Mode */ 516 val = readl(regs + S3C64XX_SPI_MODE_CFG); 517 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK 518 | S3C64XX_SPI_MODE_CH_TSZ_MASK); 519 520 switch (sdd->cur_bpw) { 521 case 32: 522 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD; 523 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD; 524 break; 525 case 16: 526 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD; 527 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD; 528 break; 529 default: 530 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE; 531 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE; 532 break; 533 } 534 535 writel(val, regs + S3C64XX_SPI_MODE_CFG); 536 537 if (sci->clk_from_cmu) { 538 /* Configure Clock */ 539 /* There is half-multiplier before the SPI */ 540 clk_set_rate(sdd->src_clk, sdd->cur_speed * 2); 541 /* Enable Clock */ 542 clk_enable(sdd->src_clk); 543 } else { 544 /* Configure Clock */ 545 val = readl(regs + S3C64XX_SPI_CLK_CFG); 546 val &= ~S3C64XX_SPI_PSR_MASK; 547 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / 2 - 1) 548 & S3C64XX_SPI_PSR_MASK); 549 writel(val, regs + S3C64XX_SPI_CLK_CFG); 550 551 /* Enable Clock */ 552 val = readl(regs + S3C64XX_SPI_CLK_CFG); 553 val |= S3C64XX_SPI_ENCLK_ENABLE; 554 writel(val, regs + S3C64XX_SPI_CLK_CFG); 555 } 556 } 557 558 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32) 559 560 static int s3c64xx_spi_map_mssg(struct s3c64xx_spi_driver_data *sdd, 561 struct spi_message *msg) 562 { 563 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 564 struct device *dev = &sdd->pdev->dev; 565 struct spi_transfer *xfer; 566 567 if (msg->is_dma_mapped) 568 return 0; 569 570 /* First mark all xfer unmapped */ 571 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 572 xfer->rx_dma = XFER_DMAADDR_INVALID; 573 xfer->tx_dma = XFER_DMAADDR_INVALID; 574 } 575 576 /* Map until end or first fail */ 577 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 578 579 if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1)) 580 continue; 581 582 if (xfer->tx_buf != NULL) { 583 xfer->tx_dma = dma_map_single(dev, 584 (void *)xfer->tx_buf, xfer->len, 585 DMA_TO_DEVICE); 586 if (dma_mapping_error(dev, xfer->tx_dma)) { 587 dev_err(dev, "dma_map_single Tx failed\n"); 588 xfer->tx_dma = XFER_DMAADDR_INVALID; 589 return -ENOMEM; 590 } 591 } 592 593 if (xfer->rx_buf != NULL) { 594 xfer->rx_dma = dma_map_single(dev, xfer->rx_buf, 595 xfer->len, DMA_FROM_DEVICE); 596 if (dma_mapping_error(dev, xfer->rx_dma)) { 597 dev_err(dev, "dma_map_single Rx failed\n"); 598 dma_unmap_single(dev, xfer->tx_dma, 599 xfer->len, DMA_TO_DEVICE); 600 xfer->tx_dma = XFER_DMAADDR_INVALID; 601 xfer->rx_dma = XFER_DMAADDR_INVALID; 602 return -ENOMEM; 603 } 604 } 605 } 606 607 return 0; 608 } 609 610 static void s3c64xx_spi_unmap_mssg(struct s3c64xx_spi_driver_data *sdd, 611 struct spi_message *msg) 612 { 613 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 614 struct device *dev = &sdd->pdev->dev; 615 struct spi_transfer *xfer; 616 617 if (msg->is_dma_mapped) 618 return; 619 620 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 621 622 if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1)) 623 continue; 624 625 if (xfer->rx_buf != NULL 626 && xfer->rx_dma != XFER_DMAADDR_INVALID) 627 dma_unmap_single(dev, xfer->rx_dma, 628 xfer->len, DMA_FROM_DEVICE); 629 630 if (xfer->tx_buf != NULL 631 && xfer->tx_dma != XFER_DMAADDR_INVALID) 632 dma_unmap_single(dev, xfer->tx_dma, 633 xfer->len, DMA_TO_DEVICE); 634 } 635 } 636 637 static void handle_msg(struct s3c64xx_spi_driver_data *sdd, 638 struct spi_message *msg) 639 { 640 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 641 struct spi_device *spi = msg->spi; 642 struct s3c64xx_spi_csinfo *cs = spi->controller_data; 643 struct spi_transfer *xfer; 644 int status = 0, cs_toggle = 0; 645 u32 speed; 646 u8 bpw; 647 648 /* If Master's(controller) state differs from that needed by Slave */ 649 if (sdd->cur_speed != spi->max_speed_hz 650 || sdd->cur_mode != spi->mode 651 || sdd->cur_bpw != spi->bits_per_word) { 652 sdd->cur_bpw = spi->bits_per_word; 653 sdd->cur_speed = spi->max_speed_hz; 654 sdd->cur_mode = spi->mode; 655 s3c64xx_spi_config(sdd); 656 } 657 658 /* Map all the transfers if needed */ 659 if (s3c64xx_spi_map_mssg(sdd, msg)) { 660 dev_err(&spi->dev, 661 "Xfer: Unable to map message buffers!\n"); 662 status = -ENOMEM; 663 goto out; 664 } 665 666 /* Configure feedback delay */ 667 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK); 668 669 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 670 671 unsigned long flags; 672 int use_dma; 673 674 INIT_COMPLETION(sdd->xfer_completion); 675 676 /* Only BPW and Speed may change across transfers */ 677 bpw = xfer->bits_per_word ? : spi->bits_per_word; 678 speed = xfer->speed_hz ? : spi->max_speed_hz; 679 680 if (xfer->len % (bpw / 8)) { 681 dev_err(&spi->dev, 682 "Xfer length(%u) not a multiple of word size(%u)\n", 683 xfer->len, bpw / 8); 684 status = -EIO; 685 goto out; 686 } 687 688 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) { 689 sdd->cur_bpw = bpw; 690 sdd->cur_speed = speed; 691 s3c64xx_spi_config(sdd); 692 } 693 694 /* Polling method for xfers not bigger than FIFO capacity */ 695 if (xfer->len <= ((sci->fifo_lvl_mask >> 1) + 1)) 696 use_dma = 0; 697 else 698 use_dma = 1; 699 700 spin_lock_irqsave(&sdd->lock, flags); 701 702 /* Pending only which is to be done */ 703 sdd->state &= ~RXBUSY; 704 sdd->state &= ~TXBUSY; 705 706 enable_datapath(sdd, spi, xfer, use_dma); 707 708 /* Slave Select */ 709 enable_cs(sdd, spi); 710 711 /* Start the signals */ 712 S3C64XX_SPI_ACT(sdd); 713 714 spin_unlock_irqrestore(&sdd->lock, flags); 715 716 status = wait_for_xfer(sdd, xfer, use_dma); 717 718 /* Quiese the signals */ 719 S3C64XX_SPI_DEACT(sdd); 720 721 if (status) { 722 dev_err(&spi->dev, "I/O Error: " 723 "rx-%d tx-%d res:rx-%c tx-%c len-%d\n", 724 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0, 725 (sdd->state & RXBUSY) ? 'f' : 'p', 726 (sdd->state & TXBUSY) ? 'f' : 'p', 727 xfer->len); 728 729 if (use_dma) { 730 if (xfer->tx_buf != NULL 731 && (sdd->state & TXBUSY)) 732 sdd->ops->stop(sdd->tx_dma.ch); 733 if (xfer->rx_buf != NULL 734 && (sdd->state & RXBUSY)) 735 sdd->ops->stop(sdd->rx_dma.ch); 736 } 737 738 goto out; 739 } 740 741 if (xfer->delay_usecs) 742 udelay(xfer->delay_usecs); 743 744 if (xfer->cs_change) { 745 /* Hint that the next mssg is gonna be 746 for the same device */ 747 if (list_is_last(&xfer->transfer_list, 748 &msg->transfers)) 749 cs_toggle = 1; 750 else 751 disable_cs(sdd, spi); 752 } 753 754 msg->actual_length += xfer->len; 755 756 flush_fifo(sdd); 757 } 758 759 out: 760 if (!cs_toggle || status) 761 disable_cs(sdd, spi); 762 else 763 sdd->tgl_spi = spi; 764 765 s3c64xx_spi_unmap_mssg(sdd, msg); 766 767 msg->status = status; 768 769 if (msg->complete) 770 msg->complete(msg->context); 771 } 772 773 static void s3c64xx_spi_work(struct work_struct *work) 774 { 775 struct s3c64xx_spi_driver_data *sdd = container_of(work, 776 struct s3c64xx_spi_driver_data, work); 777 unsigned long flags; 778 779 /* Acquire DMA channels */ 780 while (!acquire_dma(sdd)) 781 msleep(10); 782 783 spin_lock_irqsave(&sdd->lock, flags); 784 785 while (!list_empty(&sdd->queue) 786 && !(sdd->state & SUSPND)) { 787 788 struct spi_message *msg; 789 790 msg = container_of(sdd->queue.next, struct spi_message, queue); 791 792 list_del_init(&msg->queue); 793 794 /* Set Xfer busy flag */ 795 sdd->state |= SPIBUSY; 796 797 spin_unlock_irqrestore(&sdd->lock, flags); 798 799 handle_msg(sdd, msg); 800 801 spin_lock_irqsave(&sdd->lock, flags); 802 803 sdd->state &= ~SPIBUSY; 804 } 805 806 spin_unlock_irqrestore(&sdd->lock, flags); 807 808 /* Free DMA channels */ 809 sdd->ops->release(sdd->rx_dma.ch, &s3c64xx_spi_dma_client); 810 sdd->ops->release(sdd->tx_dma.ch, &s3c64xx_spi_dma_client); 811 } 812 813 static int s3c64xx_spi_transfer(struct spi_device *spi, 814 struct spi_message *msg) 815 { 816 struct s3c64xx_spi_driver_data *sdd; 817 unsigned long flags; 818 819 sdd = spi_master_get_devdata(spi->master); 820 821 spin_lock_irqsave(&sdd->lock, flags); 822 823 if (sdd->state & SUSPND) { 824 spin_unlock_irqrestore(&sdd->lock, flags); 825 return -ESHUTDOWN; 826 } 827 828 msg->status = -EINPROGRESS; 829 msg->actual_length = 0; 830 831 list_add_tail(&msg->queue, &sdd->queue); 832 833 queue_work(sdd->workqueue, &sdd->work); 834 835 spin_unlock_irqrestore(&sdd->lock, flags); 836 837 return 0; 838 } 839 840 /* 841 * Here we only check the validity of requested configuration 842 * and save the configuration in a local data-structure. 843 * The controller is actually configured only just before we 844 * get a message to transfer. 845 */ 846 static int s3c64xx_spi_setup(struct spi_device *spi) 847 { 848 struct s3c64xx_spi_csinfo *cs = spi->controller_data; 849 struct s3c64xx_spi_driver_data *sdd; 850 struct s3c64xx_spi_info *sci; 851 struct spi_message *msg; 852 unsigned long flags; 853 int err = 0; 854 855 if (cs == NULL || cs->set_level == NULL) { 856 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi->chip_select); 857 return -ENODEV; 858 } 859 860 sdd = spi_master_get_devdata(spi->master); 861 sci = sdd->cntrlr_info; 862 863 spin_lock_irqsave(&sdd->lock, flags); 864 865 list_for_each_entry(msg, &sdd->queue, queue) { 866 /* Is some mssg is already queued for this device */ 867 if (msg->spi == spi) { 868 dev_err(&spi->dev, 869 "setup: attempt while mssg in queue!\n"); 870 spin_unlock_irqrestore(&sdd->lock, flags); 871 return -EBUSY; 872 } 873 } 874 875 if (sdd->state & SUSPND) { 876 spin_unlock_irqrestore(&sdd->lock, flags); 877 dev_err(&spi->dev, 878 "setup: SPI-%d not active!\n", spi->master->bus_num); 879 return -ESHUTDOWN; 880 } 881 882 spin_unlock_irqrestore(&sdd->lock, flags); 883 884 if (spi->bits_per_word != 8 885 && spi->bits_per_word != 16 886 && spi->bits_per_word != 32) { 887 dev_err(&spi->dev, "setup: %dbits/wrd not supported!\n", 888 spi->bits_per_word); 889 err = -EINVAL; 890 goto setup_exit; 891 } 892 893 /* Check if we can provide the requested rate */ 894 if (!sci->clk_from_cmu) { 895 u32 psr, speed; 896 897 /* Max possible */ 898 speed = clk_get_rate(sdd->src_clk) / 2 / (0 + 1); 899 900 if (spi->max_speed_hz > speed) 901 spi->max_speed_hz = speed; 902 903 psr = clk_get_rate(sdd->src_clk) / 2 / spi->max_speed_hz - 1; 904 psr &= S3C64XX_SPI_PSR_MASK; 905 if (psr == S3C64XX_SPI_PSR_MASK) 906 psr--; 907 908 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); 909 if (spi->max_speed_hz < speed) { 910 if (psr+1 < S3C64XX_SPI_PSR_MASK) { 911 psr++; 912 } else { 913 err = -EINVAL; 914 goto setup_exit; 915 } 916 } 917 918 speed = clk_get_rate(sdd->src_clk) / 2 / (psr + 1); 919 if (spi->max_speed_hz >= speed) 920 spi->max_speed_hz = speed; 921 else 922 err = -EINVAL; 923 } 924 925 setup_exit: 926 927 /* setup() returns with device de-selected */ 928 disable_cs(sdd, spi); 929 930 return err; 931 } 932 933 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd, int channel) 934 { 935 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 936 void __iomem *regs = sdd->regs; 937 unsigned int val; 938 939 sdd->cur_speed = 0; 940 941 S3C64XX_SPI_DEACT(sdd); 942 943 /* Disable Interrupts - we use Polling if not DMA mode */ 944 writel(0, regs + S3C64XX_SPI_INT_EN); 945 946 if (!sci->clk_from_cmu) 947 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT, 948 regs + S3C64XX_SPI_CLK_CFG); 949 writel(0, regs + S3C64XX_SPI_MODE_CFG); 950 writel(0, regs + S3C64XX_SPI_PACKET_CNT); 951 952 /* Clear any irq pending bits */ 953 writel(readl(regs + S3C64XX_SPI_PENDING_CLR), 954 regs + S3C64XX_SPI_PENDING_CLR); 955 956 writel(0, regs + S3C64XX_SPI_SWAP_CFG); 957 958 val = readl(regs + S3C64XX_SPI_MODE_CFG); 959 val &= ~S3C64XX_SPI_MODE_4BURST; 960 val &= ~(S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); 961 val |= (S3C64XX_SPI_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); 962 writel(val, regs + S3C64XX_SPI_MODE_CFG); 963 964 flush_fifo(sdd); 965 } 966 967 static int __init s3c64xx_spi_probe(struct platform_device *pdev) 968 { 969 struct resource *mem_res, *dmatx_res, *dmarx_res; 970 struct s3c64xx_spi_driver_data *sdd; 971 struct s3c64xx_spi_info *sci; 972 struct spi_master *master; 973 int ret; 974 char clk_name[16]; 975 976 if (pdev->id < 0) { 977 dev_err(&pdev->dev, 978 "Invalid platform device id-%d\n", pdev->id); 979 return -ENODEV; 980 } 981 982 if (pdev->dev.platform_data == NULL) { 983 dev_err(&pdev->dev, "platform_data missing!\n"); 984 return -ENODEV; 985 } 986 987 sci = pdev->dev.platform_data; 988 989 /* Check for availability of necessary resource */ 990 991 dmatx_res = platform_get_resource(pdev, IORESOURCE_DMA, 0); 992 if (dmatx_res == NULL) { 993 dev_err(&pdev->dev, "Unable to get SPI-Tx dma resource\n"); 994 return -ENXIO; 995 } 996 997 dmarx_res = platform_get_resource(pdev, IORESOURCE_DMA, 1); 998 if (dmarx_res == NULL) { 999 dev_err(&pdev->dev, "Unable to get SPI-Rx dma resource\n"); 1000 return -ENXIO; 1001 } 1002 1003 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1004 if (mem_res == NULL) { 1005 dev_err(&pdev->dev, "Unable to get SPI MEM resource\n"); 1006 return -ENXIO; 1007 } 1008 1009 master = spi_alloc_master(&pdev->dev, 1010 sizeof(struct s3c64xx_spi_driver_data)); 1011 if (master == NULL) { 1012 dev_err(&pdev->dev, "Unable to allocate SPI Master\n"); 1013 return -ENOMEM; 1014 } 1015 1016 platform_set_drvdata(pdev, master); 1017 1018 sdd = spi_master_get_devdata(master); 1019 sdd->master = master; 1020 sdd->cntrlr_info = sci; 1021 sdd->pdev = pdev; 1022 sdd->sfr_start = mem_res->start; 1023 sdd->tx_dma.dmach = dmatx_res->start; 1024 sdd->tx_dma.direction = DMA_TO_DEVICE; 1025 sdd->rx_dma.dmach = dmarx_res->start; 1026 sdd->rx_dma.direction = DMA_FROM_DEVICE; 1027 1028 sdd->cur_bpw = 8; 1029 1030 master->bus_num = pdev->id; 1031 master->setup = s3c64xx_spi_setup; 1032 master->transfer = s3c64xx_spi_transfer; 1033 master->num_chipselect = sci->num_cs; 1034 master->dma_alignment = 8; 1035 /* the spi->mode bits understood by this driver: */ 1036 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1037 1038 if (request_mem_region(mem_res->start, 1039 resource_size(mem_res), pdev->name) == NULL) { 1040 dev_err(&pdev->dev, "Req mem region failed\n"); 1041 ret = -ENXIO; 1042 goto err0; 1043 } 1044 1045 sdd->regs = ioremap(mem_res->start, resource_size(mem_res)); 1046 if (sdd->regs == NULL) { 1047 dev_err(&pdev->dev, "Unable to remap IO\n"); 1048 ret = -ENXIO; 1049 goto err1; 1050 } 1051 1052 if (sci->cfg_gpio == NULL || sci->cfg_gpio(pdev)) { 1053 dev_err(&pdev->dev, "Unable to config gpio\n"); 1054 ret = -EBUSY; 1055 goto err2; 1056 } 1057 1058 /* Setup clocks */ 1059 sdd->clk = clk_get(&pdev->dev, "spi"); 1060 if (IS_ERR(sdd->clk)) { 1061 dev_err(&pdev->dev, "Unable to acquire clock 'spi'\n"); 1062 ret = PTR_ERR(sdd->clk); 1063 goto err3; 1064 } 1065 1066 if (clk_enable(sdd->clk)) { 1067 dev_err(&pdev->dev, "Couldn't enable clock 'spi'\n"); 1068 ret = -EBUSY; 1069 goto err4; 1070 } 1071 1072 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr); 1073 sdd->src_clk = clk_get(&pdev->dev, clk_name); 1074 if (IS_ERR(sdd->src_clk)) { 1075 dev_err(&pdev->dev, 1076 "Unable to acquire clock '%s'\n", clk_name); 1077 ret = PTR_ERR(sdd->src_clk); 1078 goto err5; 1079 } 1080 1081 if (clk_enable(sdd->src_clk)) { 1082 dev_err(&pdev->dev, "Couldn't enable clock '%s'\n", clk_name); 1083 ret = -EBUSY; 1084 goto err6; 1085 } 1086 1087 sdd->workqueue = create_singlethread_workqueue( 1088 dev_name(master->dev.parent)); 1089 if (sdd->workqueue == NULL) { 1090 dev_err(&pdev->dev, "Unable to create workqueue\n"); 1091 ret = -ENOMEM; 1092 goto err7; 1093 } 1094 1095 /* Setup Deufult Mode */ 1096 s3c64xx_spi_hwinit(sdd, pdev->id); 1097 1098 spin_lock_init(&sdd->lock); 1099 init_completion(&sdd->xfer_completion); 1100 INIT_WORK(&sdd->work, s3c64xx_spi_work); 1101 INIT_LIST_HEAD(&sdd->queue); 1102 1103 if (spi_register_master(master)) { 1104 dev_err(&pdev->dev, "cannot register SPI master\n"); 1105 ret = -EBUSY; 1106 goto err8; 1107 } 1108 1109 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d " 1110 "with %d Slaves attached\n", 1111 pdev->id, master->num_chipselect); 1112 dev_dbg(&pdev->dev, "\tIOmem=[0x%x-0x%x]\tDMA=[Rx-%d, Tx-%d]\n", 1113 mem_res->end, mem_res->start, 1114 sdd->rx_dma.dmach, sdd->tx_dma.dmach); 1115 1116 return 0; 1117 1118 err8: 1119 destroy_workqueue(sdd->workqueue); 1120 err7: 1121 clk_disable(sdd->src_clk); 1122 err6: 1123 clk_put(sdd->src_clk); 1124 err5: 1125 clk_disable(sdd->clk); 1126 err4: 1127 clk_put(sdd->clk); 1128 err3: 1129 err2: 1130 iounmap((void *) sdd->regs); 1131 err1: 1132 release_mem_region(mem_res->start, resource_size(mem_res)); 1133 err0: 1134 platform_set_drvdata(pdev, NULL); 1135 spi_master_put(master); 1136 1137 return ret; 1138 } 1139 1140 static int s3c64xx_spi_remove(struct platform_device *pdev) 1141 { 1142 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); 1143 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1144 struct resource *mem_res; 1145 unsigned long flags; 1146 1147 spin_lock_irqsave(&sdd->lock, flags); 1148 sdd->state |= SUSPND; 1149 spin_unlock_irqrestore(&sdd->lock, flags); 1150 1151 while (sdd->state & SPIBUSY) 1152 msleep(10); 1153 1154 spi_unregister_master(master); 1155 1156 destroy_workqueue(sdd->workqueue); 1157 1158 clk_disable(sdd->src_clk); 1159 clk_put(sdd->src_clk); 1160 1161 clk_disable(sdd->clk); 1162 clk_put(sdd->clk); 1163 1164 iounmap((void *) sdd->regs); 1165 1166 mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1167 if (mem_res != NULL) 1168 release_mem_region(mem_res->start, resource_size(mem_res)); 1169 1170 platform_set_drvdata(pdev, NULL); 1171 spi_master_put(master); 1172 1173 return 0; 1174 } 1175 1176 #ifdef CONFIG_PM 1177 static int s3c64xx_spi_suspend(struct platform_device *pdev, pm_message_t state) 1178 { 1179 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); 1180 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1181 unsigned long flags; 1182 1183 spin_lock_irqsave(&sdd->lock, flags); 1184 sdd->state |= SUSPND; 1185 spin_unlock_irqrestore(&sdd->lock, flags); 1186 1187 while (sdd->state & SPIBUSY) 1188 msleep(10); 1189 1190 /* Disable the clock */ 1191 clk_disable(sdd->src_clk); 1192 clk_disable(sdd->clk); 1193 1194 sdd->cur_speed = 0; /* Output Clock is stopped */ 1195 1196 return 0; 1197 } 1198 1199 static int s3c64xx_spi_resume(struct platform_device *pdev) 1200 { 1201 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); 1202 struct s3c64xx_spi_driver_data *sdd = spi_master_get_devdata(master); 1203 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 1204 unsigned long flags; 1205 1206 sci->cfg_gpio(pdev); 1207 1208 /* Enable the clock */ 1209 clk_enable(sdd->src_clk); 1210 clk_enable(sdd->clk); 1211 1212 s3c64xx_spi_hwinit(sdd, pdev->id); 1213 1214 spin_lock_irqsave(&sdd->lock, flags); 1215 sdd->state &= ~SUSPND; 1216 spin_unlock_irqrestore(&sdd->lock, flags); 1217 1218 return 0; 1219 } 1220 #else 1221 #define s3c64xx_spi_suspend NULL 1222 #define s3c64xx_spi_resume NULL 1223 #endif /* CONFIG_PM */ 1224 1225 static struct platform_driver s3c64xx_spi_driver = { 1226 .driver = { 1227 .name = "s3c64xx-spi", 1228 .owner = THIS_MODULE, 1229 }, 1230 .remove = s3c64xx_spi_remove, 1231 .suspend = s3c64xx_spi_suspend, 1232 .resume = s3c64xx_spi_resume, 1233 }; 1234 MODULE_ALIAS("platform:s3c64xx-spi"); 1235 1236 static int __init s3c64xx_spi_init(void) 1237 { 1238 return platform_driver_probe(&s3c64xx_spi_driver, s3c64xx_spi_probe); 1239 } 1240 subsys_initcall(s3c64xx_spi_init); 1241 1242 static void __exit s3c64xx_spi_exit(void) 1243 { 1244 platform_driver_unregister(&s3c64xx_spi_driver); 1245 } 1246 module_exit(s3c64xx_spi_exit); 1247 1248 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>"); 1249 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver"); 1250 MODULE_LICENSE("GPL"); 1251