1 // SPDX-License-Identifier: GPL-2.0+ 2 // 3 // Copyright (c) 2009 Samsung Electronics Co., Ltd. 4 // Jaswinder Singh <jassi.brar@samsung.com> 5 6 #include <linux/bitops.h> 7 #include <linux/bits.h> 8 #include <linux/clk.h> 9 #include <linux/delay.h> 10 #include <linux/dma-mapping.h> 11 #include <linux/dmaengine.h> 12 #include <linux/init.h> 13 #include <linux/interrupt.h> 14 #include <linux/io.h> 15 #include <linux/module.h> 16 #include <linux/of.h> 17 #include <linux/platform_data/spi-s3c64xx.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/spi/spi.h> 21 #include <linux/types.h> 22 23 #define MAX_SPI_PORTS 12 24 #define S3C64XX_SPI_QUIRK_CS_AUTO (1 << 1) 25 #define AUTOSUSPEND_TIMEOUT 2000 26 27 /* Registers and bit-fields */ 28 29 #define S3C64XX_SPI_CH_CFG 0x00 30 #define S3C64XX_SPI_CLK_CFG 0x04 31 #define S3C64XX_SPI_MODE_CFG 0x08 32 #define S3C64XX_SPI_CS_REG 0x0C 33 #define S3C64XX_SPI_INT_EN 0x10 34 #define S3C64XX_SPI_STATUS 0x14 35 #define S3C64XX_SPI_TX_DATA 0x18 36 #define S3C64XX_SPI_RX_DATA 0x1C 37 #define S3C64XX_SPI_PACKET_CNT 0x20 38 #define S3C64XX_SPI_PENDING_CLR 0x24 39 #define S3C64XX_SPI_SWAP_CFG 0x28 40 #define S3C64XX_SPI_FB_CLK 0x2C 41 42 #define S3C64XX_SPI_CH_HS_EN (1<<6) /* High Speed Enable */ 43 #define S3C64XX_SPI_CH_SW_RST (1<<5) 44 #define S3C64XX_SPI_CH_SLAVE (1<<4) 45 #define S3C64XX_SPI_CPOL_L (1<<3) 46 #define S3C64XX_SPI_CPHA_B (1<<2) 47 #define S3C64XX_SPI_CH_RXCH_ON (1<<1) 48 #define S3C64XX_SPI_CH_TXCH_ON (1<<0) 49 50 #define S3C64XX_SPI_CLKSEL_SRCMSK (3<<9) 51 #define S3C64XX_SPI_CLKSEL_SRCSHFT 9 52 #define S3C64XX_SPI_ENCLK_ENABLE (1<<8) 53 #define S3C64XX_SPI_PSR_MASK 0xff 54 55 #define S3C64XX_SPI_MODE_CH_TSZ_BYTE (0<<29) 56 #define S3C64XX_SPI_MODE_CH_TSZ_HALFWORD (1<<29) 57 #define S3C64XX_SPI_MODE_CH_TSZ_WORD (2<<29) 58 #define S3C64XX_SPI_MODE_CH_TSZ_MASK (3<<29) 59 #define S3C64XX_SPI_MODE_BUS_TSZ_BYTE (0<<17) 60 #define S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD (1<<17) 61 #define S3C64XX_SPI_MODE_BUS_TSZ_WORD (2<<17) 62 #define S3C64XX_SPI_MODE_BUS_TSZ_MASK (3<<17) 63 #define S3C64XX_SPI_MODE_RX_RDY_LVL GENMASK(16, 11) 64 #define S3C64XX_SPI_MODE_RX_RDY_LVL_SHIFT 11 65 #define S3C64XX_SPI_MODE_SELF_LOOPBACK (1<<3) 66 #define S3C64XX_SPI_MODE_RXDMA_ON (1<<2) 67 #define S3C64XX_SPI_MODE_TXDMA_ON (1<<1) 68 #define S3C64XX_SPI_MODE_4BURST (1<<0) 69 70 #define S3C64XX_SPI_CS_NSC_CNT_2 (2<<4) 71 #define S3C64XX_SPI_CS_AUTO (1<<1) 72 #define S3C64XX_SPI_CS_SIG_INACT (1<<0) 73 74 #define S3C64XX_SPI_INT_TRAILING_EN (1<<6) 75 #define S3C64XX_SPI_INT_RX_OVERRUN_EN (1<<5) 76 #define S3C64XX_SPI_INT_RX_UNDERRUN_EN (1<<4) 77 #define S3C64XX_SPI_INT_TX_OVERRUN_EN (1<<3) 78 #define S3C64XX_SPI_INT_TX_UNDERRUN_EN (1<<2) 79 #define S3C64XX_SPI_INT_RX_FIFORDY_EN (1<<1) 80 #define S3C64XX_SPI_INT_TX_FIFORDY_EN (1<<0) 81 82 #define S3C64XX_SPI_ST_RX_FIFO_RDY_V2 GENMASK(23, 15) 83 #define S3C64XX_SPI_ST_TX_FIFO_RDY_V2 GENMASK(14, 6) 84 #define S3C64XX_SPI_ST_TX_FIFO_LVL_SHIFT 6 85 #define S3C64XX_SPI_ST_RX_OVERRUN_ERR (1<<5) 86 #define S3C64XX_SPI_ST_RX_UNDERRUN_ERR (1<<4) 87 #define S3C64XX_SPI_ST_TX_OVERRUN_ERR (1<<3) 88 #define S3C64XX_SPI_ST_TX_UNDERRUN_ERR (1<<2) 89 #define S3C64XX_SPI_ST_RX_FIFORDY (1<<1) 90 #define S3C64XX_SPI_ST_TX_FIFORDY (1<<0) 91 92 #define S3C64XX_SPI_PACKET_CNT_EN (1<<16) 93 #define S3C64XX_SPI_PACKET_CNT_MASK GENMASK(15, 0) 94 95 #define S3C64XX_SPI_PND_TX_UNDERRUN_CLR (1<<4) 96 #define S3C64XX_SPI_PND_TX_OVERRUN_CLR (1<<3) 97 #define S3C64XX_SPI_PND_RX_UNDERRUN_CLR (1<<2) 98 #define S3C64XX_SPI_PND_RX_OVERRUN_CLR (1<<1) 99 #define S3C64XX_SPI_PND_TRAILING_CLR (1<<0) 100 101 #define S3C64XX_SPI_SWAP_RX_HALF_WORD (1<<7) 102 #define S3C64XX_SPI_SWAP_RX_BYTE (1<<6) 103 #define S3C64XX_SPI_SWAP_RX_BIT (1<<5) 104 #define S3C64XX_SPI_SWAP_RX_EN (1<<4) 105 #define S3C64XX_SPI_SWAP_TX_HALF_WORD (1<<3) 106 #define S3C64XX_SPI_SWAP_TX_BYTE (1<<2) 107 #define S3C64XX_SPI_SWAP_TX_BIT (1<<1) 108 #define S3C64XX_SPI_SWAP_TX_EN (1<<0) 109 110 #define S3C64XX_SPI_FBCLK_MSK (3<<0) 111 112 #define FIFO_LVL_MASK(i) ((i)->port_conf->fifo_lvl_mask[i->port_id]) 113 #define S3C64XX_SPI_ST_TX_DONE(v, i) (((v) & \ 114 (1 << (i)->port_conf->tx_st_done)) ? 1 : 0) 115 #define TX_FIFO_LVL(v, sdd) (((v) & (sdd)->tx_fifomask) >> \ 116 __ffs((sdd)->tx_fifomask)) 117 #define RX_FIFO_LVL(v, sdd) (((v) & (sdd)->rx_fifomask) >> \ 118 __ffs((sdd)->rx_fifomask)) 119 #define FIFO_DEPTH(i) ((FIFO_LVL_MASK(i) >> 1) + 1) 120 121 #define S3C64XX_SPI_MAX_TRAILCNT 0x3ff 122 #define S3C64XX_SPI_TRAILCNT_OFF 19 123 124 #define S3C64XX_SPI_POLLING_SIZE 32 125 126 #define msecs_to_loops(t) (loops_per_jiffy / 1000 * HZ * t) 127 #define is_polling(x) (x->cntrlr_info->polling) 128 129 #define RXBUSY (1<<2) 130 #define TXBUSY (1<<3) 131 132 struct s3c64xx_spi_dma_data { 133 struct dma_chan *ch; 134 dma_cookie_t cookie; 135 enum dma_transfer_direction direction; 136 }; 137 138 /** 139 * struct s3c64xx_spi_port_config - SPI Controller hardware info 140 * @fifo_lvl_mask: [DEPRECATED] use @{rx, tx}_fifomask instead. 141 * @rx_lvl_offset: [DEPRECATED] use @{rx,tx}_fifomask instead. 142 * @fifo_depth: depth of the FIFO. 143 * @rx_fifomask: SPI_STATUS.RX_FIFO_LVL mask. Shifted mask defining the field's 144 * length and position. 145 * @tx_fifomask: SPI_STATUS.TX_FIFO_LVL mask. Shifted mask defining the field's 146 * length and position. 147 * @tx_st_done: Bit offset of TX_DONE bit in SPI_STATUS regiter. 148 * @clk_div: Internal clock divider 149 * @quirks: Bitmask of known quirks 150 * @high_speed: True, if the controller supports HIGH_SPEED_EN bit. 151 * @clk_from_cmu: True, if the controller does not include a clock mux and 152 * prescaler unit. 153 * @clk_ioclk: True if clock is present on this device 154 * @has_loopback: True if loopback mode can be supported 155 * @use_32bit_io: True if the SoC allows only 32-bit register accesses. 156 * 157 * The Samsung s3c64xx SPI controller are used on various Samsung SoC's but 158 * differ in some aspects such as the size of the fifo and spi bus clock 159 * setup. Such differences are specified to the driver using this structure 160 * which is provided as driver data to the driver. 161 */ 162 struct s3c64xx_spi_port_config { 163 int fifo_lvl_mask[MAX_SPI_PORTS]; 164 int rx_lvl_offset; 165 unsigned int fifo_depth; 166 u32 rx_fifomask; 167 u32 tx_fifomask; 168 int tx_st_done; 169 int quirks; 170 int clk_div; 171 bool high_speed; 172 bool clk_from_cmu; 173 bool clk_ioclk; 174 bool has_loopback; 175 bool use_32bit_io; 176 }; 177 178 /** 179 * struct s3c64xx_spi_driver_data - Runtime info holder for SPI driver. 180 * @clk: Pointer to the spi clock. 181 * @src_clk: Pointer to the clock used to generate SPI signals. 182 * @ioclk: Pointer to the i/o clock between host and target 183 * @pdev: Pointer to device's platform device data 184 * @host: Pointer to the SPI Protocol host. 185 * @cntrlr_info: Platform specific data for the controller this driver manages. 186 * @lock: Controller specific lock. 187 * @state: Set of FLAGS to indicate status. 188 * @sfr_start: BUS address of SPI controller regs. 189 * @regs: Pointer to ioremap'ed controller registers. 190 * @xfer_completion: To indicate completion of xfer task. 191 * @cur_mode: Stores the active configuration of the controller. 192 * @cur_bpw: Stores the active bits per word settings. 193 * @cur_speed: Current clock speed 194 * @rx_dma: Local receive DMA data (e.g. chan and direction) 195 * @tx_dma: Local transmit DMA data (e.g. chan and direction) 196 * @port_conf: Local SPI port configuration data 197 * @port_id: [DEPRECATED] use @{rx,tx}_fifomask instead. 198 * @fifo_depth: depth of the FIFO. 199 * @rx_fifomask: SPI_STATUS.RX_FIFO_LVL mask. Shifted mask defining the field's 200 * length and position. 201 * @tx_fifomask: SPI_STATUS.TX_FIFO_LVL mask. Shifted mask defining the field's 202 * length and position. 203 */ 204 struct s3c64xx_spi_driver_data { 205 void __iomem *regs; 206 struct clk *clk; 207 struct clk *src_clk; 208 struct clk *ioclk; 209 struct platform_device *pdev; 210 struct spi_controller *host; 211 struct s3c64xx_spi_info *cntrlr_info; 212 spinlock_t lock; 213 unsigned long sfr_start; 214 struct completion xfer_completion; 215 unsigned state; 216 unsigned cur_mode, cur_bpw; 217 unsigned cur_speed; 218 struct s3c64xx_spi_dma_data rx_dma; 219 struct s3c64xx_spi_dma_data tx_dma; 220 const struct s3c64xx_spi_port_config *port_conf; 221 unsigned int port_id; 222 unsigned int fifo_depth; 223 u32 rx_fifomask; 224 u32 tx_fifomask; 225 }; 226 227 static void s3c64xx_flush_fifo(struct s3c64xx_spi_driver_data *sdd) 228 { 229 void __iomem *regs = sdd->regs; 230 unsigned long loops; 231 u32 val; 232 233 writel(0, regs + S3C64XX_SPI_PACKET_CNT); 234 235 val = readl(regs + S3C64XX_SPI_CH_CFG); 236 val &= ~(S3C64XX_SPI_CH_RXCH_ON | S3C64XX_SPI_CH_TXCH_ON); 237 writel(val, regs + S3C64XX_SPI_CH_CFG); 238 239 val = readl(regs + S3C64XX_SPI_CH_CFG); 240 val |= S3C64XX_SPI_CH_SW_RST; 241 val &= ~S3C64XX_SPI_CH_HS_EN; 242 writel(val, regs + S3C64XX_SPI_CH_CFG); 243 244 /* Flush TxFIFO*/ 245 loops = msecs_to_loops(1); 246 do { 247 val = readl(regs + S3C64XX_SPI_STATUS); 248 } while (TX_FIFO_LVL(val, sdd) && loops--); 249 250 if (loops == 0) 251 dev_warn(&sdd->pdev->dev, "Timed out flushing TX FIFO\n"); 252 253 /* Flush RxFIFO*/ 254 loops = msecs_to_loops(1); 255 do { 256 val = readl(regs + S3C64XX_SPI_STATUS); 257 if (RX_FIFO_LVL(val, sdd)) 258 readl(regs + S3C64XX_SPI_RX_DATA); 259 else 260 break; 261 } while (loops--); 262 263 if (loops == 0) 264 dev_warn(&sdd->pdev->dev, "Timed out flushing RX FIFO\n"); 265 266 val = readl(regs + S3C64XX_SPI_CH_CFG); 267 val &= ~S3C64XX_SPI_CH_SW_RST; 268 writel(val, regs + S3C64XX_SPI_CH_CFG); 269 270 val = readl(regs + S3C64XX_SPI_MODE_CFG); 271 val &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); 272 writel(val, regs + S3C64XX_SPI_MODE_CFG); 273 } 274 275 static void s3c64xx_spi_dmacb(void *data) 276 { 277 struct s3c64xx_spi_driver_data *sdd; 278 struct s3c64xx_spi_dma_data *dma = data; 279 unsigned long flags; 280 281 if (dma->direction == DMA_DEV_TO_MEM) 282 sdd = container_of(data, 283 struct s3c64xx_spi_driver_data, rx_dma); 284 else 285 sdd = container_of(data, 286 struct s3c64xx_spi_driver_data, tx_dma); 287 288 spin_lock_irqsave(&sdd->lock, flags); 289 290 if (dma->direction == DMA_DEV_TO_MEM) { 291 sdd->state &= ~RXBUSY; 292 if (!(sdd->state & TXBUSY)) 293 complete(&sdd->xfer_completion); 294 } else { 295 sdd->state &= ~TXBUSY; 296 if (!(sdd->state & RXBUSY)) 297 complete(&sdd->xfer_completion); 298 } 299 300 spin_unlock_irqrestore(&sdd->lock, flags); 301 } 302 303 static int s3c64xx_prepare_dma(struct s3c64xx_spi_dma_data *dma, 304 struct sg_table *sgt) 305 { 306 struct s3c64xx_spi_driver_data *sdd; 307 struct dma_slave_config config; 308 struct dma_async_tx_descriptor *desc; 309 int ret; 310 311 memset(&config, 0, sizeof(config)); 312 313 if (dma->direction == DMA_DEV_TO_MEM) { 314 sdd = container_of((void *)dma, 315 struct s3c64xx_spi_driver_data, rx_dma); 316 config.src_addr = sdd->sfr_start + S3C64XX_SPI_RX_DATA; 317 config.src_addr_width = sdd->cur_bpw / 8; 318 config.src_maxburst = 1; 319 } else { 320 sdd = container_of((void *)dma, 321 struct s3c64xx_spi_driver_data, tx_dma); 322 config.dst_addr = sdd->sfr_start + S3C64XX_SPI_TX_DATA; 323 config.dst_addr_width = sdd->cur_bpw / 8; 324 config.dst_maxburst = 1; 325 } 326 config.direction = dma->direction; 327 ret = dmaengine_slave_config(dma->ch, &config); 328 if (ret) 329 return ret; 330 331 desc = dmaengine_prep_slave_sg(dma->ch, sgt->sgl, sgt->nents, 332 dma->direction, DMA_PREP_INTERRUPT); 333 if (!desc) { 334 dev_err(&sdd->pdev->dev, "unable to prepare %s scatterlist", 335 dma->direction == DMA_DEV_TO_MEM ? "rx" : "tx"); 336 return -ENOMEM; 337 } 338 339 desc->callback = s3c64xx_spi_dmacb; 340 desc->callback_param = dma; 341 342 dma->cookie = dmaengine_submit(desc); 343 ret = dma_submit_error(dma->cookie); 344 if (ret) { 345 dev_err(&sdd->pdev->dev, "DMA submission failed"); 346 return ret; 347 } 348 349 dma_async_issue_pending(dma->ch); 350 return 0; 351 } 352 353 static void s3c64xx_spi_set_cs(struct spi_device *spi, bool enable) 354 { 355 struct s3c64xx_spi_driver_data *sdd = 356 spi_controller_get_devdata(spi->controller); 357 358 if (sdd->cntrlr_info->no_cs) 359 return; 360 361 if (enable) { 362 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) { 363 writel(0, sdd->regs + S3C64XX_SPI_CS_REG); 364 } else { 365 u32 ssel = readl(sdd->regs + S3C64XX_SPI_CS_REG); 366 367 ssel |= (S3C64XX_SPI_CS_AUTO | 368 S3C64XX_SPI_CS_NSC_CNT_2); 369 writel(ssel, sdd->regs + S3C64XX_SPI_CS_REG); 370 } 371 } else { 372 if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) 373 writel(S3C64XX_SPI_CS_SIG_INACT, 374 sdd->regs + S3C64XX_SPI_CS_REG); 375 } 376 } 377 378 static int s3c64xx_spi_prepare_transfer(struct spi_controller *spi) 379 { 380 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(spi); 381 382 if (is_polling(sdd)) 383 return 0; 384 385 /* Requests DMA channels */ 386 sdd->rx_dma.ch = dma_request_chan(&sdd->pdev->dev, "rx"); 387 if (IS_ERR(sdd->rx_dma.ch)) { 388 dev_err(&sdd->pdev->dev, "Failed to get RX DMA channel\n"); 389 sdd->rx_dma.ch = NULL; 390 return 0; 391 } 392 393 sdd->tx_dma.ch = dma_request_chan(&sdd->pdev->dev, "tx"); 394 if (IS_ERR(sdd->tx_dma.ch)) { 395 dev_err(&sdd->pdev->dev, "Failed to get TX DMA channel\n"); 396 dma_release_channel(sdd->rx_dma.ch); 397 sdd->tx_dma.ch = NULL; 398 sdd->rx_dma.ch = NULL; 399 return 0; 400 } 401 402 spi->dma_rx = sdd->rx_dma.ch; 403 spi->dma_tx = sdd->tx_dma.ch; 404 405 return 0; 406 } 407 408 static int s3c64xx_spi_unprepare_transfer(struct spi_controller *spi) 409 { 410 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(spi); 411 412 if (is_polling(sdd)) 413 return 0; 414 415 /* Releases DMA channels if they are allocated */ 416 if (sdd->rx_dma.ch && sdd->tx_dma.ch) { 417 dma_release_channel(sdd->rx_dma.ch); 418 dma_release_channel(sdd->tx_dma.ch); 419 sdd->rx_dma.ch = NULL; 420 sdd->tx_dma.ch = NULL; 421 } 422 423 return 0; 424 } 425 426 static bool s3c64xx_spi_can_dma(struct spi_controller *host, 427 struct spi_device *spi, 428 struct spi_transfer *xfer) 429 { 430 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); 431 432 if (sdd->rx_dma.ch && sdd->tx_dma.ch) 433 return xfer->len > sdd->fifo_depth; 434 435 return false; 436 } 437 438 static void s3c64xx_iowrite8_32_rep(volatile void __iomem *addr, 439 const void *buffer, unsigned int count) 440 { 441 if (count) { 442 const u8 *buf = buffer; 443 444 do { 445 __raw_writel(*buf++, addr); 446 } while (--count); 447 } 448 } 449 450 static void s3c64xx_iowrite16_32_rep(volatile void __iomem *addr, 451 const void *buffer, unsigned int count) 452 { 453 if (count) { 454 const u16 *buf = buffer; 455 456 do { 457 __raw_writel(*buf++, addr); 458 } while (--count); 459 } 460 } 461 462 static void s3c64xx_iowrite_rep(const struct s3c64xx_spi_driver_data *sdd, 463 struct spi_transfer *xfer) 464 { 465 void __iomem *addr = sdd->regs + S3C64XX_SPI_TX_DATA; 466 const void *buf = xfer->tx_buf; 467 unsigned int len = xfer->len; 468 469 switch (sdd->cur_bpw) { 470 case 32: 471 iowrite32_rep(addr, buf, len / 4); 472 break; 473 case 16: 474 if (sdd->port_conf->use_32bit_io) 475 s3c64xx_iowrite16_32_rep(addr, buf, len / 2); 476 else 477 iowrite16_rep(addr, buf, len / 2); 478 break; 479 default: 480 if (sdd->port_conf->use_32bit_io) 481 s3c64xx_iowrite8_32_rep(addr, buf, len); 482 else 483 iowrite8_rep(addr, buf, len); 484 break; 485 } 486 } 487 488 static int s3c64xx_enable_datapath(struct s3c64xx_spi_driver_data *sdd, 489 struct spi_transfer *xfer, int dma_mode) 490 { 491 void __iomem *regs = sdd->regs; 492 u32 modecfg, chcfg; 493 int ret = 0; 494 495 modecfg = readl(regs + S3C64XX_SPI_MODE_CFG); 496 modecfg &= ~(S3C64XX_SPI_MODE_TXDMA_ON | S3C64XX_SPI_MODE_RXDMA_ON); 497 498 chcfg = readl(regs + S3C64XX_SPI_CH_CFG); 499 chcfg &= ~S3C64XX_SPI_CH_TXCH_ON; 500 501 if (dma_mode) { 502 chcfg &= ~S3C64XX_SPI_CH_RXCH_ON; 503 } else { 504 /* Always shift in data in FIFO, even if xfer is Tx only, 505 * this helps setting PCKT_CNT value for generating clocks 506 * as exactly needed. 507 */ 508 chcfg |= S3C64XX_SPI_CH_RXCH_ON; 509 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) 510 | S3C64XX_SPI_PACKET_CNT_EN, 511 regs + S3C64XX_SPI_PACKET_CNT); 512 } 513 514 if (xfer->tx_buf != NULL) { 515 sdd->state |= TXBUSY; 516 chcfg |= S3C64XX_SPI_CH_TXCH_ON; 517 if (dma_mode) { 518 modecfg |= S3C64XX_SPI_MODE_TXDMA_ON; 519 ret = s3c64xx_prepare_dma(&sdd->tx_dma, &xfer->tx_sg); 520 } else { 521 s3c64xx_iowrite_rep(sdd, xfer); 522 } 523 } 524 525 if (xfer->rx_buf != NULL) { 526 sdd->state |= RXBUSY; 527 528 if (sdd->port_conf->high_speed && sdd->cur_speed >= 30000000UL 529 && !(sdd->cur_mode & SPI_CPHA)) 530 chcfg |= S3C64XX_SPI_CH_HS_EN; 531 532 if (dma_mode) { 533 modecfg |= S3C64XX_SPI_MODE_RXDMA_ON; 534 chcfg |= S3C64XX_SPI_CH_RXCH_ON; 535 writel(((xfer->len * 8 / sdd->cur_bpw) & 0xffff) 536 | S3C64XX_SPI_PACKET_CNT_EN, 537 regs + S3C64XX_SPI_PACKET_CNT); 538 ret = s3c64xx_prepare_dma(&sdd->rx_dma, &xfer->rx_sg); 539 } 540 } 541 542 if (ret) 543 return ret; 544 545 writel(modecfg, regs + S3C64XX_SPI_MODE_CFG); 546 writel(chcfg, regs + S3C64XX_SPI_CH_CFG); 547 548 return 0; 549 } 550 551 static u32 s3c64xx_spi_wait_for_timeout(struct s3c64xx_spi_driver_data *sdd, 552 int timeout_ms) 553 { 554 void __iomem *regs = sdd->regs; 555 unsigned long val = 1; 556 u32 status; 557 u32 max_fifo = sdd->fifo_depth; 558 559 if (timeout_ms) 560 val = msecs_to_loops(timeout_ms); 561 562 do { 563 status = readl(regs + S3C64XX_SPI_STATUS); 564 } while (RX_FIFO_LVL(status, sdd) < max_fifo && --val); 565 566 /* return the actual received data length */ 567 return RX_FIFO_LVL(status, sdd); 568 } 569 570 static int s3c64xx_wait_for_dma(struct s3c64xx_spi_driver_data *sdd, 571 struct spi_transfer *xfer) 572 { 573 void __iomem *regs = sdd->regs; 574 unsigned long val; 575 u32 status; 576 int ms; 577 578 /* millisecs to xfer 'len' bytes @ 'cur_speed' */ 579 ms = xfer->len * 8 * 1000 / sdd->cur_speed; 580 ms += 30; /* some tolerance */ 581 ms = max(ms, 100); /* minimum timeout */ 582 583 val = msecs_to_jiffies(ms) + 10; 584 val = wait_for_completion_timeout(&sdd->xfer_completion, val); 585 586 /* 587 * If the previous xfer was completed within timeout, then 588 * proceed further else return -ETIMEDOUT. 589 * DmaTx returns after simply writing data in the FIFO, 590 * w/o waiting for real transmission on the bus to finish. 591 * DmaRx returns only after Dma read data from FIFO which 592 * needs bus transmission to finish, so we don't worry if 593 * Xfer involved Rx(with or without Tx). 594 */ 595 if (val && !xfer->rx_buf) { 596 val = msecs_to_loops(10); 597 status = readl(regs + S3C64XX_SPI_STATUS); 598 while ((TX_FIFO_LVL(status, sdd) 599 || !S3C64XX_SPI_ST_TX_DONE(status, sdd)) 600 && --val) { 601 cpu_relax(); 602 status = readl(regs + S3C64XX_SPI_STATUS); 603 } 604 605 } 606 607 /* If timed out while checking rx/tx status return error */ 608 if (!val) 609 return -ETIMEDOUT; 610 611 return 0; 612 } 613 614 static int s3c64xx_wait_for_pio(struct s3c64xx_spi_driver_data *sdd, 615 struct spi_transfer *xfer, bool use_irq) 616 { 617 void __iomem *regs = sdd->regs; 618 unsigned long val; 619 u32 status; 620 int loops; 621 u32 cpy_len; 622 u8 *buf; 623 int ms; 624 unsigned long time_us; 625 626 /* microsecs to xfer 'len' bytes @ 'cur_speed' */ 627 time_us = (xfer->len * 8 * 1000 * 1000) / sdd->cur_speed; 628 ms = (time_us / 1000); 629 ms += 10; /* some tolerance */ 630 631 /* sleep during signal transfer time */ 632 status = readl(regs + S3C64XX_SPI_STATUS); 633 if (RX_FIFO_LVL(status, sdd) < xfer->len) 634 usleep_range(time_us / 2, time_us); 635 636 if (use_irq) { 637 val = msecs_to_jiffies(ms); 638 if (!wait_for_completion_timeout(&sdd->xfer_completion, val)) 639 return -ETIMEDOUT; 640 } 641 642 val = msecs_to_loops(ms); 643 do { 644 status = readl(regs + S3C64XX_SPI_STATUS); 645 } while (RX_FIFO_LVL(status, sdd) < xfer->len && --val); 646 647 if (!val) 648 return -EIO; 649 650 /* If it was only Tx */ 651 if (!xfer->rx_buf) { 652 sdd->state &= ~TXBUSY; 653 return 0; 654 } 655 656 /* 657 * If the receive length is bigger than the controller fifo 658 * size, calculate the loops and read the fifo as many times. 659 * loops = length / max fifo size (calculated by using the 660 * fifo mask). 661 * For any size less than the fifo size the below code is 662 * executed atleast once. 663 */ 664 loops = xfer->len / sdd->fifo_depth; 665 buf = xfer->rx_buf; 666 do { 667 /* wait for data to be received in the fifo */ 668 cpy_len = s3c64xx_spi_wait_for_timeout(sdd, 669 (loops ? ms : 0)); 670 671 switch (sdd->cur_bpw) { 672 case 32: 673 ioread32_rep(regs + S3C64XX_SPI_RX_DATA, 674 buf, cpy_len / 4); 675 break; 676 case 16: 677 ioread16_rep(regs + S3C64XX_SPI_RX_DATA, 678 buf, cpy_len / 2); 679 break; 680 default: 681 ioread8_rep(regs + S3C64XX_SPI_RX_DATA, 682 buf, cpy_len); 683 break; 684 } 685 686 buf = buf + cpy_len; 687 } while (loops--); 688 sdd->state &= ~RXBUSY; 689 690 return 0; 691 } 692 693 static int s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd) 694 { 695 void __iomem *regs = sdd->regs; 696 int ret; 697 u32 val; 698 int div = sdd->port_conf->clk_div; 699 700 /* Disable Clock */ 701 if (!sdd->port_conf->clk_from_cmu) { 702 val = readl(regs + S3C64XX_SPI_CLK_CFG); 703 val &= ~S3C64XX_SPI_ENCLK_ENABLE; 704 writel(val, regs + S3C64XX_SPI_CLK_CFG); 705 } 706 707 /* Set Polarity and Phase */ 708 val = readl(regs + S3C64XX_SPI_CH_CFG); 709 val &= ~(S3C64XX_SPI_CH_SLAVE | 710 S3C64XX_SPI_CPOL_L | 711 S3C64XX_SPI_CPHA_B); 712 713 if (sdd->cur_mode & SPI_CPOL) 714 val |= S3C64XX_SPI_CPOL_L; 715 716 if (sdd->cur_mode & SPI_CPHA) 717 val |= S3C64XX_SPI_CPHA_B; 718 719 writel(val, regs + S3C64XX_SPI_CH_CFG); 720 721 /* Set Channel & DMA Mode */ 722 val = readl(regs + S3C64XX_SPI_MODE_CFG); 723 val &= ~(S3C64XX_SPI_MODE_BUS_TSZ_MASK 724 | S3C64XX_SPI_MODE_CH_TSZ_MASK); 725 726 switch (sdd->cur_bpw) { 727 case 32: 728 val |= S3C64XX_SPI_MODE_BUS_TSZ_WORD; 729 val |= S3C64XX_SPI_MODE_CH_TSZ_WORD; 730 break; 731 case 16: 732 val |= S3C64XX_SPI_MODE_BUS_TSZ_HALFWORD; 733 val |= S3C64XX_SPI_MODE_CH_TSZ_HALFWORD; 734 break; 735 default: 736 val |= S3C64XX_SPI_MODE_BUS_TSZ_BYTE; 737 val |= S3C64XX_SPI_MODE_CH_TSZ_BYTE; 738 break; 739 } 740 741 if ((sdd->cur_mode & SPI_LOOP) && sdd->port_conf->has_loopback) 742 val |= S3C64XX_SPI_MODE_SELF_LOOPBACK; 743 else 744 val &= ~S3C64XX_SPI_MODE_SELF_LOOPBACK; 745 746 writel(val, regs + S3C64XX_SPI_MODE_CFG); 747 748 if (sdd->port_conf->clk_from_cmu) { 749 ret = clk_set_rate(sdd->src_clk, sdd->cur_speed * div); 750 if (ret) 751 return ret; 752 sdd->cur_speed = clk_get_rate(sdd->src_clk) / div; 753 } else { 754 /* Configure Clock */ 755 val = readl(regs + S3C64XX_SPI_CLK_CFG); 756 val &= ~S3C64XX_SPI_PSR_MASK; 757 val |= ((clk_get_rate(sdd->src_clk) / sdd->cur_speed / div - 1) 758 & S3C64XX_SPI_PSR_MASK); 759 writel(val, regs + S3C64XX_SPI_CLK_CFG); 760 761 /* Enable Clock */ 762 val = readl(regs + S3C64XX_SPI_CLK_CFG); 763 val |= S3C64XX_SPI_ENCLK_ENABLE; 764 writel(val, regs + S3C64XX_SPI_CLK_CFG); 765 } 766 767 return 0; 768 } 769 770 #define XFER_DMAADDR_INVALID DMA_BIT_MASK(32) 771 772 static int s3c64xx_spi_prepare_message(struct spi_controller *host, 773 struct spi_message *msg) 774 { 775 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); 776 struct spi_device *spi = msg->spi; 777 struct s3c64xx_spi_csinfo *cs = spi->controller_data; 778 779 /* Configure feedback delay */ 780 if (!cs) 781 /* No delay if not defined */ 782 writel(0, sdd->regs + S3C64XX_SPI_FB_CLK); 783 else 784 writel(cs->fb_delay & 0x3, sdd->regs + S3C64XX_SPI_FB_CLK); 785 786 return 0; 787 } 788 789 static size_t s3c64xx_spi_max_transfer_size(struct spi_device *spi) 790 { 791 struct spi_controller *ctlr = spi->controller; 792 793 return ctlr->can_dma ? S3C64XX_SPI_PACKET_CNT_MASK : SIZE_MAX; 794 } 795 796 static int s3c64xx_spi_transfer_one(struct spi_controller *host, 797 struct spi_device *spi, 798 struct spi_transfer *xfer) 799 { 800 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); 801 const unsigned int fifo_len = sdd->fifo_depth; 802 const void *tx_buf = NULL; 803 void *rx_buf = NULL; 804 int target_len = 0, origin_len = 0; 805 int use_dma = 0; 806 bool use_irq = false; 807 int status; 808 u32 speed; 809 u8 bpw; 810 unsigned long flags; 811 u32 rdy_lv; 812 u32 val; 813 814 reinit_completion(&sdd->xfer_completion); 815 816 /* Only BPW and Speed may change across transfers */ 817 bpw = xfer->bits_per_word; 818 speed = xfer->speed_hz; 819 820 if (bpw != sdd->cur_bpw || speed != sdd->cur_speed) { 821 sdd->cur_bpw = bpw; 822 sdd->cur_speed = speed; 823 sdd->cur_mode = spi->mode; 824 status = s3c64xx_spi_config(sdd); 825 if (status) 826 return status; 827 } 828 829 if (!is_polling(sdd) && (xfer->len > fifo_len) && 830 sdd->rx_dma.ch && sdd->tx_dma.ch) { 831 use_dma = 1; 832 833 } else if (xfer->len >= fifo_len) { 834 tx_buf = xfer->tx_buf; 835 rx_buf = xfer->rx_buf; 836 origin_len = xfer->len; 837 target_len = xfer->len; 838 xfer->len = fifo_len - 1; 839 } 840 841 do { 842 /* transfer size is greater than 32, change to IRQ mode */ 843 if (!use_dma && xfer->len > S3C64XX_SPI_POLLING_SIZE) 844 use_irq = true; 845 846 if (use_irq) { 847 reinit_completion(&sdd->xfer_completion); 848 849 rdy_lv = xfer->len; 850 /* Setup RDY_FIFO trigger Level 851 * RDY_LVL = 852 * fifo_lvl up to 64 byte -> N bytes 853 * 128 byte -> RDY_LVL * 2 bytes 854 * 256 byte -> RDY_LVL * 4 bytes 855 */ 856 if (fifo_len == 128) 857 rdy_lv /= 2; 858 else if (fifo_len == 256) 859 rdy_lv /= 4; 860 861 val = readl(sdd->regs + S3C64XX_SPI_MODE_CFG); 862 val &= ~S3C64XX_SPI_MODE_RX_RDY_LVL; 863 val |= (rdy_lv << S3C64XX_SPI_MODE_RX_RDY_LVL_SHIFT); 864 writel(val, sdd->regs + S3C64XX_SPI_MODE_CFG); 865 866 /* Enable FIFO_RDY_EN IRQ */ 867 val = readl(sdd->regs + S3C64XX_SPI_INT_EN); 868 writel((val | S3C64XX_SPI_INT_RX_FIFORDY_EN), 869 sdd->regs + S3C64XX_SPI_INT_EN); 870 871 } 872 873 spin_lock_irqsave(&sdd->lock, flags); 874 875 /* Pending only which is to be done */ 876 sdd->state &= ~RXBUSY; 877 sdd->state &= ~TXBUSY; 878 879 /* Start the signals */ 880 s3c64xx_spi_set_cs(spi, true); 881 882 status = s3c64xx_enable_datapath(sdd, xfer, use_dma); 883 884 spin_unlock_irqrestore(&sdd->lock, flags); 885 886 if (status) { 887 dev_err(&spi->dev, "failed to enable data path for transfer: %d\n", status); 888 break; 889 } 890 891 if (use_dma) 892 status = s3c64xx_wait_for_dma(sdd, xfer); 893 else 894 status = s3c64xx_wait_for_pio(sdd, xfer, use_irq); 895 896 if (status) { 897 dev_err(&spi->dev, 898 "I/O Error: rx-%d tx-%d rx-%c tx-%c len-%d dma-%d res-(%d)\n", 899 xfer->rx_buf ? 1 : 0, xfer->tx_buf ? 1 : 0, 900 (sdd->state & RXBUSY) ? 'f' : 'p', 901 (sdd->state & TXBUSY) ? 'f' : 'p', 902 xfer->len, use_dma ? 1 : 0, status); 903 904 if (use_dma) { 905 struct dma_tx_state s; 906 907 if (xfer->tx_buf && (sdd->state & TXBUSY)) { 908 dmaengine_pause(sdd->tx_dma.ch); 909 dmaengine_tx_status(sdd->tx_dma.ch, sdd->tx_dma.cookie, &s); 910 dmaengine_terminate_all(sdd->tx_dma.ch); 911 dev_err(&spi->dev, "TX residue: %d\n", s.residue); 912 913 } 914 if (xfer->rx_buf && (sdd->state & RXBUSY)) { 915 dmaengine_pause(sdd->rx_dma.ch); 916 dmaengine_tx_status(sdd->rx_dma.ch, sdd->rx_dma.cookie, &s); 917 dmaengine_terminate_all(sdd->rx_dma.ch); 918 dev_err(&spi->dev, "RX residue: %d\n", s.residue); 919 } 920 } 921 } else { 922 s3c64xx_flush_fifo(sdd); 923 } 924 if (target_len > 0) { 925 target_len -= xfer->len; 926 927 if (xfer->tx_buf) 928 xfer->tx_buf += xfer->len; 929 930 if (xfer->rx_buf) 931 xfer->rx_buf += xfer->len; 932 933 if (target_len >= fifo_len) 934 xfer->len = fifo_len - 1; 935 else 936 xfer->len = target_len; 937 } 938 } while (target_len > 0); 939 940 if (origin_len) { 941 /* Restore original xfer buffers and length */ 942 xfer->tx_buf = tx_buf; 943 xfer->rx_buf = rx_buf; 944 xfer->len = origin_len; 945 } 946 947 return status; 948 } 949 950 static struct s3c64xx_spi_csinfo *s3c64xx_get_target_ctrldata( 951 struct spi_device *spi) 952 { 953 struct s3c64xx_spi_csinfo *cs; 954 struct device_node *target_np, *data_np = NULL; 955 u32 fb_delay = 0; 956 957 target_np = spi->dev.of_node; 958 if (!target_np) { 959 dev_err(&spi->dev, "device node not found\n"); 960 return ERR_PTR(-EINVAL); 961 } 962 963 cs = kzalloc(sizeof(*cs), GFP_KERNEL); 964 if (!cs) 965 return ERR_PTR(-ENOMEM); 966 967 data_np = of_get_child_by_name(target_np, "controller-data"); 968 if (!data_np) { 969 dev_info(&spi->dev, "feedback delay set to default (0)\n"); 970 return cs; 971 } 972 973 of_property_read_u32(data_np, "samsung,spi-feedback-delay", &fb_delay); 974 cs->fb_delay = fb_delay; 975 of_node_put(data_np); 976 return cs; 977 } 978 979 /* 980 * Here we only check the validity of requested configuration 981 * and save the configuration in a local data-structure. 982 * The controller is actually configured only just before we 983 * get a message to transfer. 984 */ 985 static int s3c64xx_spi_setup(struct spi_device *spi) 986 { 987 struct s3c64xx_spi_csinfo *cs = spi->controller_data; 988 struct s3c64xx_spi_driver_data *sdd; 989 int err; 990 int div; 991 992 sdd = spi_controller_get_devdata(spi->controller); 993 if (spi->dev.of_node) { 994 cs = s3c64xx_get_target_ctrldata(spi); 995 spi->controller_data = cs; 996 } 997 998 /* NULL is fine, we just avoid using the FB delay (=0) */ 999 if (IS_ERR(cs)) { 1000 dev_err(&spi->dev, "No CS for SPI(%d)\n", spi_get_chipselect(spi, 0)); 1001 return -ENODEV; 1002 } 1003 1004 if (!spi_get_ctldata(spi)) 1005 spi_set_ctldata(spi, cs); 1006 1007 pm_runtime_get_sync(&sdd->pdev->dev); 1008 1009 div = sdd->port_conf->clk_div; 1010 1011 /* Check if we can provide the requested rate */ 1012 if (!sdd->port_conf->clk_from_cmu) { 1013 u32 psr, speed; 1014 1015 /* Max possible */ 1016 speed = clk_get_rate(sdd->src_clk) / div / (0 + 1); 1017 1018 if (spi->max_speed_hz > speed) 1019 spi->max_speed_hz = speed; 1020 1021 psr = clk_get_rate(sdd->src_clk) / div / spi->max_speed_hz - 1; 1022 psr &= S3C64XX_SPI_PSR_MASK; 1023 if (psr == S3C64XX_SPI_PSR_MASK) 1024 psr--; 1025 1026 speed = clk_get_rate(sdd->src_clk) / div / (psr + 1); 1027 if (spi->max_speed_hz < speed) { 1028 if (psr+1 < S3C64XX_SPI_PSR_MASK) { 1029 psr++; 1030 } else { 1031 err = -EINVAL; 1032 goto setup_exit; 1033 } 1034 } 1035 1036 speed = clk_get_rate(sdd->src_clk) / div / (psr + 1); 1037 if (spi->max_speed_hz >= speed) { 1038 spi->max_speed_hz = speed; 1039 } else { 1040 dev_err(&spi->dev, "Can't set %dHz transfer speed\n", 1041 spi->max_speed_hz); 1042 err = -EINVAL; 1043 goto setup_exit; 1044 } 1045 } 1046 1047 pm_runtime_mark_last_busy(&sdd->pdev->dev); 1048 pm_runtime_put_autosuspend(&sdd->pdev->dev); 1049 s3c64xx_spi_set_cs(spi, false); 1050 1051 return 0; 1052 1053 setup_exit: 1054 pm_runtime_mark_last_busy(&sdd->pdev->dev); 1055 pm_runtime_put_autosuspend(&sdd->pdev->dev); 1056 /* setup() returns with device de-selected */ 1057 s3c64xx_spi_set_cs(spi, false); 1058 1059 spi_set_ctldata(spi, NULL); 1060 1061 /* This was dynamically allocated on the DT path */ 1062 if (spi->dev.of_node) 1063 kfree(cs); 1064 1065 return err; 1066 } 1067 1068 static void s3c64xx_spi_cleanup(struct spi_device *spi) 1069 { 1070 struct s3c64xx_spi_csinfo *cs = spi_get_ctldata(spi); 1071 1072 /* This was dynamically allocated on the DT path */ 1073 if (spi->dev.of_node) 1074 kfree(cs); 1075 1076 spi_set_ctldata(spi, NULL); 1077 } 1078 1079 static irqreturn_t s3c64xx_spi_irq(int irq, void *data) 1080 { 1081 struct s3c64xx_spi_driver_data *sdd = data; 1082 struct spi_controller *spi = sdd->host; 1083 unsigned int val, clr = 0; 1084 1085 val = readl(sdd->regs + S3C64XX_SPI_STATUS); 1086 1087 if (val & S3C64XX_SPI_ST_RX_OVERRUN_ERR) { 1088 clr = S3C64XX_SPI_PND_RX_OVERRUN_CLR; 1089 dev_err(&spi->dev, "RX overrun\n"); 1090 } 1091 if (val & S3C64XX_SPI_ST_RX_UNDERRUN_ERR) { 1092 clr |= S3C64XX_SPI_PND_RX_UNDERRUN_CLR; 1093 dev_err(&spi->dev, "RX underrun\n"); 1094 } 1095 if (val & S3C64XX_SPI_ST_TX_OVERRUN_ERR) { 1096 clr |= S3C64XX_SPI_PND_TX_OVERRUN_CLR; 1097 dev_err(&spi->dev, "TX overrun\n"); 1098 } 1099 if (val & S3C64XX_SPI_ST_TX_UNDERRUN_ERR) { 1100 clr |= S3C64XX_SPI_PND_TX_UNDERRUN_CLR; 1101 dev_err(&spi->dev, "TX underrun\n"); 1102 } 1103 1104 if (val & S3C64XX_SPI_ST_RX_FIFORDY) { 1105 complete(&sdd->xfer_completion); 1106 /* No pending clear irq, turn-off INT_EN_RX_FIFO_RDY */ 1107 val = readl(sdd->regs + S3C64XX_SPI_INT_EN); 1108 writel((val & ~S3C64XX_SPI_INT_RX_FIFORDY_EN), 1109 sdd->regs + S3C64XX_SPI_INT_EN); 1110 } 1111 1112 /* Clear the pending irq by setting and then clearing it */ 1113 writel(clr, sdd->regs + S3C64XX_SPI_PENDING_CLR); 1114 writel(0, sdd->regs + S3C64XX_SPI_PENDING_CLR); 1115 1116 return IRQ_HANDLED; 1117 } 1118 1119 static void s3c64xx_spi_hwinit(struct s3c64xx_spi_driver_data *sdd) 1120 { 1121 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 1122 void __iomem *regs = sdd->regs; 1123 unsigned int val; 1124 1125 sdd->cur_speed = 0; 1126 1127 if (sci->no_cs) 1128 writel(0, sdd->regs + S3C64XX_SPI_CS_REG); 1129 else if (!(sdd->port_conf->quirks & S3C64XX_SPI_QUIRK_CS_AUTO)) 1130 writel(S3C64XX_SPI_CS_SIG_INACT, sdd->regs + S3C64XX_SPI_CS_REG); 1131 1132 /* Disable Interrupts - we use Polling if not DMA mode */ 1133 writel(0, regs + S3C64XX_SPI_INT_EN); 1134 1135 if (!sdd->port_conf->clk_from_cmu) 1136 writel(sci->src_clk_nr << S3C64XX_SPI_CLKSEL_SRCSHFT, 1137 regs + S3C64XX_SPI_CLK_CFG); 1138 writel(0, regs + S3C64XX_SPI_MODE_CFG); 1139 writel(0, regs + S3C64XX_SPI_PACKET_CNT); 1140 1141 /* Clear any irq pending bits, should set and clear the bits */ 1142 val = S3C64XX_SPI_PND_RX_OVERRUN_CLR | 1143 S3C64XX_SPI_PND_RX_UNDERRUN_CLR | 1144 S3C64XX_SPI_PND_TX_OVERRUN_CLR | 1145 S3C64XX_SPI_PND_TX_UNDERRUN_CLR; 1146 writel(val, regs + S3C64XX_SPI_PENDING_CLR); 1147 writel(0, regs + S3C64XX_SPI_PENDING_CLR); 1148 1149 writel(0, regs + S3C64XX_SPI_SWAP_CFG); 1150 1151 val = readl(regs + S3C64XX_SPI_MODE_CFG); 1152 val &= ~S3C64XX_SPI_MODE_4BURST; 1153 val |= (S3C64XX_SPI_MAX_TRAILCNT << S3C64XX_SPI_TRAILCNT_OFF); 1154 writel(val, regs + S3C64XX_SPI_MODE_CFG); 1155 1156 s3c64xx_flush_fifo(sdd); 1157 } 1158 1159 #ifdef CONFIG_OF 1160 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) 1161 { 1162 struct s3c64xx_spi_info *sci; 1163 u32 temp; 1164 1165 sci = devm_kzalloc(dev, sizeof(*sci), GFP_KERNEL); 1166 if (!sci) 1167 return ERR_PTR(-ENOMEM); 1168 1169 if (of_property_read_u32(dev->of_node, "samsung,spi-src-clk", &temp)) { 1170 dev_dbg(dev, "spi bus clock parent not specified, using clock at index 0 as parent\n"); 1171 sci->src_clk_nr = 0; 1172 } else { 1173 sci->src_clk_nr = temp; 1174 } 1175 1176 if (of_property_read_u32(dev->of_node, "num-cs", &temp)) { 1177 dev_dbg(dev, "number of chip select lines not specified, assuming 1 chip select line\n"); 1178 sci->num_cs = 1; 1179 } else { 1180 sci->num_cs = temp; 1181 } 1182 1183 sci->no_cs = of_property_read_bool(dev->of_node, "no-cs-readback"); 1184 sci->polling = !of_property_present(dev->of_node, "dmas"); 1185 1186 return sci; 1187 } 1188 #else 1189 static struct s3c64xx_spi_info *s3c64xx_spi_parse_dt(struct device *dev) 1190 { 1191 return dev_get_platdata(dev); 1192 } 1193 #endif 1194 1195 static inline const struct s3c64xx_spi_port_config *s3c64xx_spi_get_port_config( 1196 struct platform_device *pdev) 1197 { 1198 #ifdef CONFIG_OF 1199 if (pdev->dev.of_node) 1200 return of_device_get_match_data(&pdev->dev); 1201 #endif 1202 return (const struct s3c64xx_spi_port_config *)platform_get_device_id(pdev)->driver_data; 1203 } 1204 1205 static int s3c64xx_spi_set_port_id(struct platform_device *pdev, 1206 struct s3c64xx_spi_driver_data *sdd) 1207 { 1208 const struct s3c64xx_spi_port_config *port_conf = sdd->port_conf; 1209 int ret; 1210 1211 if (port_conf->rx_fifomask && port_conf->tx_fifomask) 1212 return 0; 1213 1214 if (pdev->dev.of_node) { 1215 ret = of_alias_get_id(pdev->dev.of_node, "spi"); 1216 if (ret < 0) 1217 return dev_err_probe(&pdev->dev, ret, 1218 "Failed to get alias id\n"); 1219 sdd->port_id = ret; 1220 } else { 1221 if (pdev->id < 0) 1222 return dev_err_probe(&pdev->dev, -EINVAL, 1223 "Negative platform ID is not allowed\n"); 1224 sdd->port_id = pdev->id; 1225 } 1226 1227 return 0; 1228 } 1229 1230 static void s3c64xx_spi_set_fifomask(struct s3c64xx_spi_driver_data *sdd) 1231 { 1232 const struct s3c64xx_spi_port_config *port_conf = sdd->port_conf; 1233 1234 if (port_conf->rx_fifomask) 1235 sdd->rx_fifomask = port_conf->rx_fifomask; 1236 else 1237 sdd->rx_fifomask = FIFO_LVL_MASK(sdd) << 1238 port_conf->rx_lvl_offset; 1239 1240 if (port_conf->tx_fifomask) 1241 sdd->tx_fifomask = port_conf->tx_fifomask; 1242 else 1243 sdd->tx_fifomask = FIFO_LVL_MASK(sdd) << 1244 S3C64XX_SPI_ST_TX_FIFO_LVL_SHIFT; 1245 } 1246 1247 static int s3c64xx_spi_probe(struct platform_device *pdev) 1248 { 1249 struct resource *mem_res; 1250 struct s3c64xx_spi_driver_data *sdd; 1251 struct s3c64xx_spi_info *sci = dev_get_platdata(&pdev->dev); 1252 struct spi_controller *host; 1253 int ret, irq; 1254 char clk_name[16]; 1255 1256 if (!sci && pdev->dev.of_node) { 1257 sci = s3c64xx_spi_parse_dt(&pdev->dev); 1258 if (IS_ERR(sci)) 1259 return PTR_ERR(sci); 1260 } 1261 1262 if (!sci) 1263 return dev_err_probe(&pdev->dev, -ENODEV, 1264 "Platform_data missing!\n"); 1265 1266 irq = platform_get_irq(pdev, 0); 1267 if (irq < 0) 1268 return irq; 1269 1270 host = devm_spi_alloc_host(&pdev->dev, sizeof(*sdd)); 1271 if (!host) 1272 return dev_err_probe(&pdev->dev, -ENOMEM, 1273 "Unable to allocate SPI Host\n"); 1274 1275 platform_set_drvdata(pdev, host); 1276 1277 sdd = spi_controller_get_devdata(host); 1278 sdd->port_conf = s3c64xx_spi_get_port_config(pdev); 1279 sdd->host = host; 1280 sdd->cntrlr_info = sci; 1281 sdd->pdev = pdev; 1282 1283 ret = s3c64xx_spi_set_port_id(pdev, sdd); 1284 if (ret) 1285 return ret; 1286 1287 if (sdd->port_conf->fifo_depth) 1288 sdd->fifo_depth = sdd->port_conf->fifo_depth; 1289 else if (of_property_read_u32(pdev->dev.of_node, "fifo-depth", 1290 &sdd->fifo_depth)) 1291 sdd->fifo_depth = FIFO_DEPTH(sdd); 1292 1293 s3c64xx_spi_set_fifomask(sdd); 1294 1295 sdd->cur_bpw = 8; 1296 1297 sdd->tx_dma.direction = DMA_MEM_TO_DEV; 1298 sdd->rx_dma.direction = DMA_DEV_TO_MEM; 1299 1300 host->dev.of_node = pdev->dev.of_node; 1301 host->bus_num = -1; 1302 host->setup = s3c64xx_spi_setup; 1303 host->cleanup = s3c64xx_spi_cleanup; 1304 host->prepare_transfer_hardware = s3c64xx_spi_prepare_transfer; 1305 host->unprepare_transfer_hardware = s3c64xx_spi_unprepare_transfer; 1306 host->prepare_message = s3c64xx_spi_prepare_message; 1307 host->transfer_one = s3c64xx_spi_transfer_one; 1308 host->max_transfer_size = s3c64xx_spi_max_transfer_size; 1309 host->num_chipselect = sci->num_cs; 1310 host->use_gpio_descriptors = true; 1311 host->dma_alignment = 8; 1312 host->bits_per_word_mask = SPI_BPW_MASK(32) | SPI_BPW_MASK(16) | 1313 SPI_BPW_MASK(8); 1314 /* the spi->mode bits understood by this driver: */ 1315 host->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH; 1316 if (sdd->port_conf->has_loopback) 1317 host->mode_bits |= SPI_LOOP; 1318 host->auto_runtime_pm = true; 1319 if (!is_polling(sdd)) 1320 host->can_dma = s3c64xx_spi_can_dma; 1321 1322 sdd->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem_res); 1323 if (IS_ERR(sdd->regs)) 1324 return PTR_ERR(sdd->regs); 1325 sdd->sfr_start = mem_res->start; 1326 1327 if (sci->cfg_gpio && sci->cfg_gpio()) 1328 return dev_err_probe(&pdev->dev, -EBUSY, 1329 "Unable to config gpio\n"); 1330 1331 /* Setup clocks */ 1332 sdd->clk = devm_clk_get_enabled(&pdev->dev, "spi"); 1333 if (IS_ERR(sdd->clk)) 1334 return dev_err_probe(&pdev->dev, PTR_ERR(sdd->clk), 1335 "Unable to acquire clock 'spi'\n"); 1336 1337 sprintf(clk_name, "spi_busclk%d", sci->src_clk_nr); 1338 sdd->src_clk = devm_clk_get_enabled(&pdev->dev, clk_name); 1339 if (IS_ERR(sdd->src_clk)) 1340 return dev_err_probe(&pdev->dev, PTR_ERR(sdd->src_clk), 1341 "Unable to acquire clock '%s'\n", 1342 clk_name); 1343 1344 if (sdd->port_conf->clk_ioclk) { 1345 sdd->ioclk = devm_clk_get_enabled(&pdev->dev, "spi_ioclk"); 1346 if (IS_ERR(sdd->ioclk)) 1347 return dev_err_probe(&pdev->dev, PTR_ERR(sdd->ioclk), 1348 "Unable to acquire 'ioclk'\n"); 1349 } 1350 1351 pm_runtime_set_autosuspend_delay(&pdev->dev, AUTOSUSPEND_TIMEOUT); 1352 pm_runtime_use_autosuspend(&pdev->dev); 1353 pm_runtime_set_active(&pdev->dev); 1354 pm_runtime_enable(&pdev->dev); 1355 pm_runtime_get_sync(&pdev->dev); 1356 1357 /* Setup Deufult Mode */ 1358 s3c64xx_spi_hwinit(sdd); 1359 1360 spin_lock_init(&sdd->lock); 1361 init_completion(&sdd->xfer_completion); 1362 1363 ret = devm_request_irq(&pdev->dev, irq, s3c64xx_spi_irq, 0, 1364 "spi-s3c64xx", sdd); 1365 if (ret != 0) { 1366 dev_err(&pdev->dev, "Failed to request IRQ %d: %d\n", 1367 irq, ret); 1368 goto err_pm_put; 1369 } 1370 1371 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN | 1372 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN, 1373 sdd->regs + S3C64XX_SPI_INT_EN); 1374 1375 ret = devm_spi_register_controller(&pdev->dev, host); 1376 if (ret != 0) { 1377 dev_err(&pdev->dev, "cannot register SPI host: %d\n", ret); 1378 goto err_pm_put; 1379 } 1380 1381 dev_dbg(&pdev->dev, "Samsung SoC SPI Driver loaded for Bus SPI-%d with %d Targets attached\n", 1382 host->bus_num, host->num_chipselect); 1383 dev_dbg(&pdev->dev, "\tIOmem=[%pR]\tFIFO %dbytes\n", 1384 mem_res, sdd->fifo_depth); 1385 1386 pm_runtime_mark_last_busy(&pdev->dev); 1387 pm_runtime_put_autosuspend(&pdev->dev); 1388 1389 return 0; 1390 1391 err_pm_put: 1392 pm_runtime_put_noidle(&pdev->dev); 1393 pm_runtime_disable(&pdev->dev); 1394 pm_runtime_set_suspended(&pdev->dev); 1395 1396 return ret; 1397 } 1398 1399 static void s3c64xx_spi_remove(struct platform_device *pdev) 1400 { 1401 struct spi_controller *host = platform_get_drvdata(pdev); 1402 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); 1403 1404 pm_runtime_get_sync(&pdev->dev); 1405 1406 writel(0, sdd->regs + S3C64XX_SPI_INT_EN); 1407 1408 if (!is_polling(sdd)) { 1409 dma_release_channel(sdd->rx_dma.ch); 1410 dma_release_channel(sdd->tx_dma.ch); 1411 } 1412 1413 pm_runtime_put_noidle(&pdev->dev); 1414 pm_runtime_disable(&pdev->dev); 1415 pm_runtime_set_suspended(&pdev->dev); 1416 } 1417 1418 #ifdef CONFIG_PM_SLEEP 1419 static int s3c64xx_spi_suspend(struct device *dev) 1420 { 1421 struct spi_controller *host = dev_get_drvdata(dev); 1422 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); 1423 int ret; 1424 1425 ret = spi_controller_suspend(host); 1426 if (ret) 1427 return ret; 1428 1429 ret = pm_runtime_force_suspend(dev); 1430 if (ret < 0) 1431 return ret; 1432 1433 sdd->cur_speed = 0; /* Output Clock is stopped */ 1434 1435 return 0; 1436 } 1437 1438 static int s3c64xx_spi_resume(struct device *dev) 1439 { 1440 struct spi_controller *host = dev_get_drvdata(dev); 1441 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); 1442 struct s3c64xx_spi_info *sci = sdd->cntrlr_info; 1443 int ret; 1444 1445 if (sci->cfg_gpio) 1446 sci->cfg_gpio(); 1447 1448 ret = pm_runtime_force_resume(dev); 1449 if (ret < 0) 1450 return ret; 1451 1452 return spi_controller_resume(host); 1453 } 1454 #endif /* CONFIG_PM_SLEEP */ 1455 1456 #ifdef CONFIG_PM 1457 static int s3c64xx_spi_runtime_suspend(struct device *dev) 1458 { 1459 struct spi_controller *host = dev_get_drvdata(dev); 1460 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); 1461 1462 clk_disable_unprepare(sdd->clk); 1463 clk_disable_unprepare(sdd->src_clk); 1464 clk_disable_unprepare(sdd->ioclk); 1465 1466 return 0; 1467 } 1468 1469 static int s3c64xx_spi_runtime_resume(struct device *dev) 1470 { 1471 struct spi_controller *host = dev_get_drvdata(dev); 1472 struct s3c64xx_spi_driver_data *sdd = spi_controller_get_devdata(host); 1473 int ret; 1474 1475 if (sdd->port_conf->clk_ioclk) { 1476 ret = clk_prepare_enable(sdd->ioclk); 1477 if (ret != 0) 1478 return ret; 1479 } 1480 1481 ret = clk_prepare_enable(sdd->src_clk); 1482 if (ret != 0) 1483 goto err_disable_ioclk; 1484 1485 ret = clk_prepare_enable(sdd->clk); 1486 if (ret != 0) 1487 goto err_disable_src_clk; 1488 1489 s3c64xx_spi_hwinit(sdd); 1490 1491 writel(S3C64XX_SPI_INT_RX_OVERRUN_EN | S3C64XX_SPI_INT_RX_UNDERRUN_EN | 1492 S3C64XX_SPI_INT_TX_OVERRUN_EN | S3C64XX_SPI_INT_TX_UNDERRUN_EN, 1493 sdd->regs + S3C64XX_SPI_INT_EN); 1494 1495 return 0; 1496 1497 err_disable_src_clk: 1498 clk_disable_unprepare(sdd->src_clk); 1499 err_disable_ioclk: 1500 clk_disable_unprepare(sdd->ioclk); 1501 1502 return ret; 1503 } 1504 #endif /* CONFIG_PM */ 1505 1506 static const struct dev_pm_ops s3c64xx_spi_pm = { 1507 SET_SYSTEM_SLEEP_PM_OPS(s3c64xx_spi_suspend, s3c64xx_spi_resume) 1508 SET_RUNTIME_PM_OPS(s3c64xx_spi_runtime_suspend, 1509 s3c64xx_spi_runtime_resume, NULL) 1510 }; 1511 1512 static const struct s3c64xx_spi_port_config s3c2443_spi_port_config = { 1513 /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ 1514 .fifo_lvl_mask = { 0x7f }, 1515 /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ 1516 .rx_lvl_offset = 13, 1517 .tx_st_done = 21, 1518 .clk_div = 2, 1519 .high_speed = true, 1520 }; 1521 1522 static const struct s3c64xx_spi_port_config s3c6410_spi_port_config = { 1523 /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ 1524 .fifo_lvl_mask = { 0x7f, 0x7F }, 1525 /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ 1526 .rx_lvl_offset = 13, 1527 .tx_st_done = 21, 1528 .clk_div = 2, 1529 }; 1530 1531 static const struct s3c64xx_spi_port_config s5pv210_spi_port_config = { 1532 /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ 1533 .fifo_lvl_mask = { 0x1ff, 0x7F }, 1534 /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ 1535 .rx_lvl_offset = 15, 1536 .tx_st_done = 25, 1537 .clk_div = 2, 1538 .high_speed = true, 1539 }; 1540 1541 static const struct s3c64xx_spi_port_config exynos4_spi_port_config = { 1542 /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ 1543 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F }, 1544 /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ 1545 .rx_lvl_offset = 15, 1546 .tx_st_done = 25, 1547 .clk_div = 2, 1548 .high_speed = true, 1549 .clk_from_cmu = true, 1550 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, 1551 }; 1552 1553 static const struct s3c64xx_spi_port_config exynos7_spi_port_config = { 1554 /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ 1555 .fifo_lvl_mask = { 0x1ff, 0x7F, 0x7F, 0x7F, 0x7F, 0x1ff}, 1556 /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ 1557 .rx_lvl_offset = 15, 1558 .tx_st_done = 25, 1559 .clk_div = 2, 1560 .high_speed = true, 1561 .clk_from_cmu = true, 1562 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, 1563 }; 1564 1565 static const struct s3c64xx_spi_port_config exynos5433_spi_port_config = { 1566 /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ 1567 .fifo_lvl_mask = { 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff}, 1568 /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ 1569 .rx_lvl_offset = 15, 1570 .tx_st_done = 25, 1571 .clk_div = 2, 1572 .high_speed = true, 1573 .clk_from_cmu = true, 1574 .clk_ioclk = true, 1575 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, 1576 }; 1577 1578 static const struct s3c64xx_spi_port_config exynos850_spi_port_config = { 1579 .fifo_depth = 64, 1580 .rx_fifomask = S3C64XX_SPI_ST_RX_FIFO_RDY_V2, 1581 .tx_fifomask = S3C64XX_SPI_ST_TX_FIFO_RDY_V2, 1582 .tx_st_done = 25, 1583 .clk_div = 4, 1584 .high_speed = true, 1585 .clk_from_cmu = true, 1586 .has_loopback = true, 1587 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, 1588 }; 1589 1590 static const struct s3c64xx_spi_port_config exynosautov9_spi_port_config = { 1591 /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ 1592 .fifo_lvl_mask = { 0x1ff, 0x1ff, 0x7f, 0x7f, 0x7f, 0x7f, 0x1ff, 0x7f, 1593 0x7f, 0x7f, 0x7f, 0x7f}, 1594 /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ 1595 .rx_lvl_offset = 15, 1596 .tx_st_done = 25, 1597 .clk_div = 4, 1598 .high_speed = true, 1599 .clk_from_cmu = true, 1600 .clk_ioclk = true, 1601 .has_loopback = true, 1602 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, 1603 }; 1604 1605 static const struct s3c64xx_spi_port_config fsd_spi_port_config = { 1606 /* fifo_lvl_mask is deprecated. Use {rx, tx}_fifomask instead. */ 1607 .fifo_lvl_mask = { 0x7f, 0x7f, 0x7f, 0x7f, 0x7f}, 1608 /* rx_lvl_offset is deprecated. Use {rx, tx}_fifomask instead. */ 1609 .rx_lvl_offset = 15, 1610 .tx_st_done = 25, 1611 .clk_div = 2, 1612 .high_speed = true, 1613 .clk_from_cmu = true, 1614 .clk_ioclk = false, 1615 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, 1616 }; 1617 1618 static const struct s3c64xx_spi_port_config gs101_spi_port_config = { 1619 .fifo_depth = 64, 1620 .rx_fifomask = S3C64XX_SPI_ST_RX_FIFO_RDY_V2, 1621 .tx_fifomask = S3C64XX_SPI_ST_TX_FIFO_RDY_V2, 1622 .tx_st_done = 25, 1623 .clk_div = 4, 1624 .high_speed = true, 1625 .clk_from_cmu = true, 1626 .has_loopback = true, 1627 .use_32bit_io = true, 1628 .quirks = S3C64XX_SPI_QUIRK_CS_AUTO, 1629 }; 1630 1631 static const struct platform_device_id s3c64xx_spi_driver_ids[] = { 1632 { 1633 .name = "s3c2443-spi", 1634 .driver_data = (kernel_ulong_t)&s3c2443_spi_port_config, 1635 }, { 1636 .name = "s3c6410-spi", 1637 .driver_data = (kernel_ulong_t)&s3c6410_spi_port_config, 1638 }, 1639 { }, 1640 }; 1641 1642 static const struct of_device_id s3c64xx_spi_dt_match[] = { 1643 { .compatible = "google,gs101-spi", 1644 .data = &gs101_spi_port_config, 1645 }, 1646 { .compatible = "samsung,s3c2443-spi", 1647 .data = &s3c2443_spi_port_config, 1648 }, 1649 { .compatible = "samsung,s3c6410-spi", 1650 .data = &s3c6410_spi_port_config, 1651 }, 1652 { .compatible = "samsung,s5pv210-spi", 1653 .data = &s5pv210_spi_port_config, 1654 }, 1655 { .compatible = "samsung,exynos4210-spi", 1656 .data = &exynos4_spi_port_config, 1657 }, 1658 { .compatible = "samsung,exynos7-spi", 1659 .data = &exynos7_spi_port_config, 1660 }, 1661 { .compatible = "samsung,exynos5433-spi", 1662 .data = &exynos5433_spi_port_config, 1663 }, 1664 { .compatible = "samsung,exynos850-spi", 1665 .data = &exynos850_spi_port_config, 1666 }, 1667 { .compatible = "samsung,exynosautov9-spi", 1668 .data = &exynosautov9_spi_port_config, 1669 }, 1670 { .compatible = "tesla,fsd-spi", 1671 .data = &fsd_spi_port_config, 1672 }, 1673 { }, 1674 }; 1675 MODULE_DEVICE_TABLE(of, s3c64xx_spi_dt_match); 1676 1677 static struct platform_driver s3c64xx_spi_driver = { 1678 .driver = { 1679 .name = "s3c64xx-spi", 1680 .pm = &s3c64xx_spi_pm, 1681 .of_match_table = of_match_ptr(s3c64xx_spi_dt_match), 1682 }, 1683 .probe = s3c64xx_spi_probe, 1684 .remove_new = s3c64xx_spi_remove, 1685 .id_table = s3c64xx_spi_driver_ids, 1686 }; 1687 MODULE_ALIAS("platform:s3c64xx-spi"); 1688 1689 module_platform_driver(s3c64xx_spi_driver); 1690 1691 MODULE_AUTHOR("Jaswinder Singh <jassi.brar@samsung.com>"); 1692 MODULE_DESCRIPTION("S3C64XX SPI Controller Driver"); 1693 MODULE_LICENSE("GPL"); 1694