xref: /linux/drivers/spi/spi-rzv2h-rspi.c (revision 260f6f4fda93c8485c8037865c941b42b9cba5d2) 
1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Renesas RZ/V2H Renesas Serial Peripheral Interface (RSPI)
4  *
5  * Copyright (C) 2025 Renesas Electronics Corporation
6  */
7 
8 #include <linux/bitfield.h>
9 #include <linux/bitops.h>
10 #include <linux/bits.h>
11 #include <linux/clk.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/limits.h>
15 #include <linux/log2.h>
16 #include <linux/math.h>
17 #include <linux/of.h>
18 #include <linux/platform_device.h>
19 #include <linux/property.h>
20 #include <linux/reset.h>
21 #include <linux/spi/spi.h>
22 #include <linux/wait.h>
23 
24 /* Registers */
25 #define RSPI_SPDR		0x00
26 #define RSPI_SPCR		0x08
27 #define RSPI_SSLP		0x10
28 #define RSPI_SPBR		0x11
29 #define RSPI_SPSCR		0x13
30 #define RSPI_SPCMD		0x14
31 #define RSPI_SPDCR2		0x44
32 #define RSPI_SPSR		0x52
33 #define RSPI_SPSRC		0x6a
34 #define RSPI_SPFCR		0x6c
35 
36 /* Register SPCR */
37 #define RSPI_SPCR_MSTR		BIT(30)
38 #define RSPI_SPCR_SPRIE		BIT(17)
39 #define RSPI_SPCR_SCKASE	BIT(12)
40 #define RSPI_SPCR_SPE		BIT(0)
41 
42 /* Register SPBR */
43 #define RSPI_SPBR_SPR_MIN	0
44 #define RSPI_SPBR_SPR_MAX	255
45 
46 /* Register SPCMD */
47 #define RSPI_SPCMD_SSLA		GENMASK(25, 24)
48 #define RSPI_SPCMD_SPB		GENMASK(20, 16)
49 #define RSPI_SPCMD_LSBF		BIT(12)
50 #define RSPI_SPCMD_SSLKP	BIT(7)
51 #define RSPI_SPCMD_BRDV		GENMASK(3, 2)
52 #define RSPI_SPCMD_CPOL		BIT(1)
53 #define RSPI_SPCMD_CPHA		BIT(0)
54 
55 #define RSPI_SPCMD_BRDV_MIN	0
56 #define RSPI_SPCMD_BRDV_MAX	3
57 
58 /* Register SPDCR2 */
59 #define RSPI_SPDCR2_TTRG	GENMASK(11, 8)
60 #define RSPI_SPDCR2_RTRG	GENMASK(3, 0)
61 #define RSPI_FIFO_SIZE		16
62 
63 /* Register SPSR */
64 #define RSPI_SPSR_SPRF		BIT(15)
65 
66 /* Register RSPI_SPSRC */
67 #define RSPI_SPSRC_CLEAR	0xfd80
68 
69 #define RSPI_RESET_NUM		2
70 #define RSPI_CLK_NUM		3
71 
72 struct rzv2h_rspi_priv {
73 	struct reset_control_bulk_data resets[RSPI_RESET_NUM];
74 	struct spi_controller *controller;
75 	void __iomem *base;
76 	struct clk *tclk;
77 	wait_queue_head_t wait;
78 	unsigned int bytes_per_word;
79 	u32 freq;
80 	u16 status;
81 };
82 
83 #define RZV2H_RSPI_TX(func, type)					\
84 static inline void rzv2h_rspi_tx_##type(struct rzv2h_rspi_priv *rspi,	\
85 					const void *txbuf,		\
86 					unsigned int index) {		\
87 	type buf = 0;							\
88 									\
89 	if (txbuf)							\
90 		buf = ((type *)txbuf)[index];				\
91 									\
92 	func(buf, rspi->base + RSPI_SPDR);				\
93 }
94 
95 #define RZV2H_RSPI_RX(func, type)					\
96 static inline void rzv2h_rspi_rx_##type(struct rzv2h_rspi_priv *rspi,	\
97 					void *rxbuf,			\
98 					unsigned int index) {		\
99 	type buf = func(rspi->base + RSPI_SPDR);			\
100 									\
101 	if (rxbuf)							\
102 		((type *)rxbuf)[index] = buf;				\
103 }
104 
105 RZV2H_RSPI_TX(writel, u32)
106 RZV2H_RSPI_TX(writew, u16)
107 RZV2H_RSPI_TX(writeb, u8)
108 RZV2H_RSPI_RX(readl, u32)
109 RZV2H_RSPI_RX(readw, u16)
110 RZV2H_RSPI_RX(readl, u8)
111 
112 static void rzv2h_rspi_reg_rmw(const struct rzv2h_rspi_priv *rspi,
113 				int reg_offs, u32 bit_mask, u32 value)
114 {
115 	u32 tmp;
116 
117 	value <<= __ffs(bit_mask);
118 	tmp = (readl(rspi->base + reg_offs) & ~bit_mask) | value;
119 	writel(tmp, rspi->base + reg_offs);
120 }
121 
122 static inline void rzv2h_rspi_spe_disable(const struct rzv2h_rspi_priv *rspi)
123 {
124 	rzv2h_rspi_reg_rmw(rspi, RSPI_SPCR, RSPI_SPCR_SPE, 0);
125 }
126 
127 static inline void rzv2h_rspi_spe_enable(const struct rzv2h_rspi_priv *rspi)
128 {
129 	rzv2h_rspi_reg_rmw(rspi, RSPI_SPCR, RSPI_SPCR_SPE, 1);
130 }
131 
132 static inline void rzv2h_rspi_clear_fifos(const struct rzv2h_rspi_priv *rspi)
133 {
134 	writeb(1, rspi->base + RSPI_SPFCR);
135 }
136 
137 static inline void rzv2h_rspi_clear_all_irqs(struct rzv2h_rspi_priv *rspi)
138 {
139 	writew(RSPI_SPSRC_CLEAR, rspi->base + RSPI_SPSRC);
140 	rspi->status = 0;
141 }
142 
143 static irqreturn_t rzv2h_rx_irq_handler(int irq, void *data)
144 {
145 	struct rzv2h_rspi_priv *rspi = data;
146 
147 	rspi->status = readw(rspi->base + RSPI_SPSR);
148 	wake_up(&rspi->wait);
149 
150 	return IRQ_HANDLED;
151 }
152 
153 static inline int rzv2h_rspi_wait_for_interrupt(struct rzv2h_rspi_priv *rspi,
154 						u32 wait_mask)
155 {
156 	return wait_event_timeout(rspi->wait, (rspi->status & wait_mask),
157 				  HZ) == 0 ? -ETIMEDOUT : 0;
158 }
159 
160 static void rzv2h_rspi_send(struct rzv2h_rspi_priv *rspi, const void *txbuf,
161 			    unsigned int index)
162 {
163 	switch (rspi->bytes_per_word) {
164 	case 4:
165 		rzv2h_rspi_tx_u32(rspi, txbuf, index);
166 		break;
167 	case 2:
168 		rzv2h_rspi_tx_u16(rspi, txbuf, index);
169 		break;
170 	default:
171 		rzv2h_rspi_tx_u8(rspi, txbuf, index);
172 	}
173 }
174 
175 static int rzv2h_rspi_receive(struct rzv2h_rspi_priv *rspi, void *rxbuf,
176 			      unsigned int index)
177 {
178 	int ret;
179 
180 	ret = rzv2h_rspi_wait_for_interrupt(rspi, RSPI_SPSR_SPRF);
181 	if (ret)
182 		return ret;
183 
184 	switch (rspi->bytes_per_word) {
185 	case 4:
186 		rzv2h_rspi_rx_u32(rspi, rxbuf, index);
187 		break;
188 	case 2:
189 		rzv2h_rspi_rx_u16(rspi, rxbuf, index);
190 		break;
191 	default:
192 		rzv2h_rspi_rx_u8(rspi, rxbuf, index);
193 	}
194 
195 	return 0;
196 }
197 
198 static int rzv2h_rspi_transfer_one(struct spi_controller *controller,
199 				  struct spi_device *spi,
200 				  struct spi_transfer *transfer)
201 {
202 	struct rzv2h_rspi_priv *rspi = spi_controller_get_devdata(controller);
203 	unsigned int words_to_transfer, i;
204 	int ret = 0;
205 
206 	transfer->effective_speed_hz = rspi->freq;
207 	words_to_transfer = transfer->len / rspi->bytes_per_word;
208 
209 	for (i = 0; i < words_to_transfer; i++) {
210 		rzv2h_rspi_clear_all_irqs(rspi);
211 
212 		rzv2h_rspi_send(rspi, transfer->tx_buf, i);
213 
214 		ret = rzv2h_rspi_receive(rspi, transfer->rx_buf, i);
215 		if (ret)
216 			break;
217 	}
218 
219 	rzv2h_rspi_clear_all_irqs(rspi);
220 
221 	if (ret)
222 		transfer->error = SPI_TRANS_FAIL_IO;
223 
224 	spi_finalize_current_transfer(controller);
225 
226 	return ret;
227 }
228 
229 static inline u32 rzv2h_rspi_calc_bitrate(unsigned long tclk_rate, u8 spr,
230 					  u8 brdv)
231 {
232 	return DIV_ROUND_UP(tclk_rate, (2 * (spr + 1) * (1 << brdv)));
233 }
234 
235 static u32 rzv2h_rspi_setup_clock(struct rzv2h_rspi_priv *rspi, u32 hz)
236 {
237 	unsigned long tclk_rate;
238 	int spr;
239 	u8 brdv;
240 
241 	/*
242 	 * From the manual:
243 	 * Bit rate = f(RSPI_n_TCLK)/(2*(n+1)*2^(N))
244 	 *
245 	 * Where:
246 	 * * RSPI_n_TCLK is fixed to 200MHz on V2H
247 	 * * n = SPR - is RSPI_SPBR.SPR (from 0 to 255)
248 	 * * N = BRDV - is RSPI_SPCMD.BRDV (from 0 to 3)
249 	 */
250 	tclk_rate = clk_get_rate(rspi->tclk);
251 	for (brdv = RSPI_SPCMD_BRDV_MIN; brdv <= RSPI_SPCMD_BRDV_MAX; brdv++) {
252 		spr = DIV_ROUND_UP(tclk_rate, hz * (1 << (brdv + 1)));
253 		spr--;
254 		if (spr >= RSPI_SPBR_SPR_MIN && spr <= RSPI_SPBR_SPR_MAX)
255 			goto clock_found;
256 	}
257 
258 	return 0;
259 
260 clock_found:
261 	rzv2h_rspi_reg_rmw(rspi, RSPI_SPCMD, RSPI_SPCMD_BRDV, brdv);
262 	writeb(spr, rspi->base + RSPI_SPBR);
263 
264 	return rzv2h_rspi_calc_bitrate(tclk_rate, spr, brdv);
265 }
266 
267 static int rzv2h_rspi_prepare_message(struct spi_controller *ctlr,
268 				      struct spi_message *message)
269 {
270 	struct rzv2h_rspi_priv *rspi = spi_controller_get_devdata(ctlr);
271 	const struct spi_device *spi = message->spi;
272 	struct spi_transfer *xfer;
273 	u32 speed_hz = U32_MAX;
274 	u8 bits_per_word;
275 	u32 conf32;
276 	u16 conf16;
277 
278 	/* Make sure SPCR.SPE is 0 before amending the configuration */
279 	rzv2h_rspi_spe_disable(rspi);
280 
281 	/* Configure the device to work in "host" mode */
282 	conf32 = RSPI_SPCR_MSTR;
283 
284 	/* Auto-stop function */
285 	conf32 |= RSPI_SPCR_SCKASE;
286 
287 	/* SPI receive buffer full interrupt enable */
288 	conf32 |= RSPI_SPCR_SPRIE;
289 
290 	writel(conf32, rspi->base + RSPI_SPCR);
291 
292 	/* Use SPCMD0 only */
293 	writeb(0x0, rspi->base + RSPI_SPSCR);
294 
295 	/* Setup mode */
296 	conf32 = FIELD_PREP(RSPI_SPCMD_CPOL, !!(spi->mode & SPI_CPOL));
297 	conf32 |= FIELD_PREP(RSPI_SPCMD_CPHA, !!(spi->mode & SPI_CPHA));
298 	conf32 |= FIELD_PREP(RSPI_SPCMD_LSBF, !!(spi->mode & SPI_LSB_FIRST));
299 	conf32 |= FIELD_PREP(RSPI_SPCMD_SSLKP, 1);
300 	conf32 |= FIELD_PREP(RSPI_SPCMD_SSLA, spi_get_chipselect(spi, 0));
301 	writel(conf32, rspi->base + RSPI_SPCMD);
302 	if (spi->mode & SPI_CS_HIGH)
303 		writeb(BIT(spi_get_chipselect(spi, 0)), rspi->base + RSPI_SSLP);
304 	else
305 		writeb(0, rspi->base + RSPI_SSLP);
306 
307 	/* Setup FIFO thresholds */
308 	conf16 = FIELD_PREP(RSPI_SPDCR2_TTRG, RSPI_FIFO_SIZE - 1);
309 	conf16 |= FIELD_PREP(RSPI_SPDCR2_RTRG, 0);
310 	writew(conf16, rspi->base + RSPI_SPDCR2);
311 
312 	rzv2h_rspi_clear_fifos(rspi);
313 
314 	list_for_each_entry(xfer, &message->transfers, transfer_list) {
315 		if (!xfer->speed_hz)
316 			continue;
317 
318 		speed_hz = min(xfer->speed_hz, speed_hz);
319 		bits_per_word = xfer->bits_per_word;
320 	}
321 
322 	if (speed_hz == U32_MAX)
323 		return -EINVAL;
324 
325 	rspi->bytes_per_word = roundup_pow_of_two(BITS_TO_BYTES(bits_per_word));
326 	rzv2h_rspi_reg_rmw(rspi, RSPI_SPCMD, RSPI_SPCMD_SPB, bits_per_word - 1);
327 
328 	rspi->freq = rzv2h_rspi_setup_clock(rspi, speed_hz);
329 	if (!rspi->freq)
330 		return -EINVAL;
331 
332 	rzv2h_rspi_spe_enable(rspi);
333 
334 	return 0;
335 }
336 
337 static int rzv2h_rspi_unprepare_message(struct spi_controller *ctlr,
338 					struct spi_message *message)
339 {
340 	struct rzv2h_rspi_priv *rspi = spi_controller_get_devdata(ctlr);
341 
342 	rzv2h_rspi_spe_disable(rspi);
343 
344 	return 0;
345 }
346 
347 static int rzv2h_rspi_probe(struct platform_device *pdev)
348 {
349 	struct spi_controller *controller;
350 	struct device *dev = &pdev->dev;
351 	struct rzv2h_rspi_priv *rspi;
352 	struct clk_bulk_data *clks;
353 	unsigned long tclk_rate;
354 	int irq_rx, ret, i;
355 
356 	controller = devm_spi_alloc_host(dev, sizeof(*rspi));
357 	if (!controller)
358 		return -ENOMEM;
359 
360 	rspi = spi_controller_get_devdata(controller);
361 	platform_set_drvdata(pdev, rspi);
362 
363 	rspi->controller = controller;
364 
365 	rspi->base = devm_platform_ioremap_resource(pdev, 0);
366 	if (IS_ERR(rspi->base))
367 		return PTR_ERR(rspi->base);
368 
369 	ret = devm_clk_bulk_get_all_enabled(dev, &clks);
370 	if (ret != RSPI_CLK_NUM)
371 		return dev_err_probe(dev, ret >= 0 ? -EINVAL : ret,
372 				     "cannot get clocks\n");
373 	for (i = 0; i < RSPI_CLK_NUM; i++) {
374 		if (!strcmp(clks[i].id, "tclk")) {
375 			rspi->tclk = clks[i].clk;
376 			break;
377 		}
378 	}
379 
380 	if (!rspi->tclk)
381 		return dev_err_probe(dev, -EINVAL, "Failed to get tclk\n");
382 
383 	tclk_rate = clk_get_rate(rspi->tclk);
384 
385 	rspi->resets[0].id = "presetn";
386 	rspi->resets[1].id = "tresetn";
387 	ret = devm_reset_control_bulk_get_exclusive(dev, RSPI_RESET_NUM,
388 						    rspi->resets);
389 	if (ret)
390 		return dev_err_probe(dev, ret, "cannot get resets\n");
391 
392 	irq_rx = platform_get_irq_byname(pdev, "rx");
393 	if (irq_rx < 0)
394 		return dev_err_probe(dev, irq_rx, "cannot get IRQ 'rx'\n");
395 
396 	ret = reset_control_bulk_deassert(RSPI_RESET_NUM, rspi->resets);
397 	if (ret)
398 		return dev_err_probe(dev, ret, "failed to deassert resets\n");
399 
400 	init_waitqueue_head(&rspi->wait);
401 
402 	ret = devm_request_irq(dev, irq_rx, rzv2h_rx_irq_handler, 0,
403 			       dev_name(dev), rspi);
404 	if (ret) {
405 		dev_err(dev, "cannot request `rx` IRQ\n");
406 		goto quit_resets;
407 	}
408 
409 	controller->mode_bits = SPI_CPHA | SPI_CPOL | SPI_CS_HIGH |
410 				SPI_LSB_FIRST;
411 	controller->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32);
412 	controller->prepare_message = rzv2h_rspi_prepare_message;
413 	controller->unprepare_message = rzv2h_rspi_unprepare_message;
414 	controller->num_chipselect = 4;
415 	controller->transfer_one = rzv2h_rspi_transfer_one;
416 	controller->min_speed_hz = rzv2h_rspi_calc_bitrate(tclk_rate,
417 							   RSPI_SPBR_SPR_MAX,
418 							   RSPI_SPCMD_BRDV_MAX);
419 	controller->max_speed_hz = rzv2h_rspi_calc_bitrate(tclk_rate,
420 							   RSPI_SPBR_SPR_MIN,
421 							   RSPI_SPCMD_BRDV_MIN);
422 
423 	device_set_node(&controller->dev, dev_fwnode(dev));
424 
425 	ret = spi_register_controller(controller);
426 	if (ret) {
427 		dev_err(dev, "register controller failed\n");
428 		goto quit_resets;
429 	}
430 
431 	return 0;
432 
433 quit_resets:
434 	reset_control_bulk_assert(RSPI_RESET_NUM, rspi->resets);
435 
436 	return ret;
437 }
438 
439 static void rzv2h_rspi_remove(struct platform_device *pdev)
440 {
441 	struct rzv2h_rspi_priv *rspi = platform_get_drvdata(pdev);
442 
443 	spi_unregister_controller(rspi->controller);
444 
445 	reset_control_bulk_assert(RSPI_RESET_NUM, rspi->resets);
446 }
447 
448 static const struct of_device_id rzv2h_rspi_match[] = {
449 	{ .compatible = "renesas,r9a09g057-rspi" },
450 	{ /* sentinel */ }
451 };
452 MODULE_DEVICE_TABLE(of, rzv2h_rspi_match);
453 
454 static struct platform_driver rzv2h_rspi_drv = {
455 	.probe = rzv2h_rspi_probe,
456 	.remove = rzv2h_rspi_remove,
457 	.driver = {
458 		.name = "rzv2h_rspi",
459 		.of_match_table = rzv2h_rspi_match,
460 	},
461 };
462 module_platform_driver(rzv2h_rspi_drv);
463 
464 MODULE_LICENSE("GPL");
465 MODULE_AUTHOR("Fabrizio Castro <fabrizio.castro.jz@renesas.com>");
466 MODULE_DESCRIPTION("Renesas RZ/V2H(P) Serial Peripheral Interface Driver");
467