1 /* 2 * SH RSPI driver 3 * 4 * Copyright (C) 2012, 2013 Renesas Solutions Corp. 5 * Copyright (C) 2014 Glider bvba 6 * 7 * Based on spi-sh.c: 8 * Copyright (C) 2011 Renesas Solutions Corp. 9 * 10 * This program is free software; you can redistribute it and/or modify 11 * it under the terms of the GNU General Public License as published by 12 * the Free Software Foundation; version 2 of the License. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 */ 19 20 #include <linux/module.h> 21 #include <linux/kernel.h> 22 #include <linux/sched.h> 23 #include <linux/errno.h> 24 #include <linux/interrupt.h> 25 #include <linux/platform_device.h> 26 #include <linux/io.h> 27 #include <linux/clk.h> 28 #include <linux/dmaengine.h> 29 #include <linux/dma-mapping.h> 30 #include <linux/of_device.h> 31 #include <linux/pm_runtime.h> 32 #include <linux/sh_dma.h> 33 #include <linux/spi/spi.h> 34 #include <linux/spi/rspi.h> 35 36 #define RSPI_SPCR 0x00 /* Control Register */ 37 #define RSPI_SSLP 0x01 /* Slave Select Polarity Register */ 38 #define RSPI_SPPCR 0x02 /* Pin Control Register */ 39 #define RSPI_SPSR 0x03 /* Status Register */ 40 #define RSPI_SPDR 0x04 /* Data Register */ 41 #define RSPI_SPSCR 0x08 /* Sequence Control Register */ 42 #define RSPI_SPSSR 0x09 /* Sequence Status Register */ 43 #define RSPI_SPBR 0x0a /* Bit Rate Register */ 44 #define RSPI_SPDCR 0x0b /* Data Control Register */ 45 #define RSPI_SPCKD 0x0c /* Clock Delay Register */ 46 #define RSPI_SSLND 0x0d /* Slave Select Negation Delay Register */ 47 #define RSPI_SPND 0x0e /* Next-Access Delay Register */ 48 #define RSPI_SPCR2 0x0f /* Control Register 2 (SH only) */ 49 #define RSPI_SPCMD0 0x10 /* Command Register 0 */ 50 #define RSPI_SPCMD1 0x12 /* Command Register 1 */ 51 #define RSPI_SPCMD2 0x14 /* Command Register 2 */ 52 #define RSPI_SPCMD3 0x16 /* Command Register 3 */ 53 #define RSPI_SPCMD4 0x18 /* Command Register 4 */ 54 #define RSPI_SPCMD5 0x1a /* Command Register 5 */ 55 #define RSPI_SPCMD6 0x1c /* Command Register 6 */ 56 #define RSPI_SPCMD7 0x1e /* Command Register 7 */ 57 #define RSPI_SPCMD(i) (RSPI_SPCMD0 + (i) * 2) 58 #define RSPI_NUM_SPCMD 8 59 #define RSPI_RZ_NUM_SPCMD 4 60 #define QSPI_NUM_SPCMD 4 61 62 /* RSPI on RZ only */ 63 #define RSPI_SPBFCR 0x20 /* Buffer Control Register */ 64 #define RSPI_SPBFDR 0x22 /* Buffer Data Count Setting Register */ 65 66 /* QSPI only */ 67 #define QSPI_SPBFCR 0x18 /* Buffer Control Register */ 68 #define QSPI_SPBDCR 0x1a /* Buffer Data Count Register */ 69 #define QSPI_SPBMUL0 0x1c /* Transfer Data Length Multiplier Setting Register 0 */ 70 #define QSPI_SPBMUL1 0x20 /* Transfer Data Length Multiplier Setting Register 1 */ 71 #define QSPI_SPBMUL2 0x24 /* Transfer Data Length Multiplier Setting Register 2 */ 72 #define QSPI_SPBMUL3 0x28 /* Transfer Data Length Multiplier Setting Register 3 */ 73 #define QSPI_SPBMUL(i) (QSPI_SPBMUL0 + (i) * 4) 74 75 /* SPCR - Control Register */ 76 #define SPCR_SPRIE 0x80 /* Receive Interrupt Enable */ 77 #define SPCR_SPE 0x40 /* Function Enable */ 78 #define SPCR_SPTIE 0x20 /* Transmit Interrupt Enable */ 79 #define SPCR_SPEIE 0x10 /* Error Interrupt Enable */ 80 #define SPCR_MSTR 0x08 /* Master/Slave Mode Select */ 81 #define SPCR_MODFEN 0x04 /* Mode Fault Error Detection Enable */ 82 /* RSPI on SH only */ 83 #define SPCR_TXMD 0x02 /* TX Only Mode (vs. Full Duplex) */ 84 #define SPCR_SPMS 0x01 /* 3-wire Mode (vs. 4-wire) */ 85 /* QSPI on R-Car Gen2 only */ 86 #define SPCR_WSWAP 0x02 /* Word Swap of read-data for DMAC */ 87 #define SPCR_BSWAP 0x01 /* Byte Swap of read-data for DMAC */ 88 89 /* SSLP - Slave Select Polarity Register */ 90 #define SSLP_SSL1P 0x02 /* SSL1 Signal Polarity Setting */ 91 #define SSLP_SSL0P 0x01 /* SSL0 Signal Polarity Setting */ 92 93 /* SPPCR - Pin Control Register */ 94 #define SPPCR_MOIFE 0x20 /* MOSI Idle Value Fixing Enable */ 95 #define SPPCR_MOIFV 0x10 /* MOSI Idle Fixed Value */ 96 #define SPPCR_SPOM 0x04 97 #define SPPCR_SPLP2 0x02 /* Loopback Mode 2 (non-inverting) */ 98 #define SPPCR_SPLP 0x01 /* Loopback Mode (inverting) */ 99 100 #define SPPCR_IO3FV 0x04 /* Single-/Dual-SPI Mode IO3 Output Fixed Value */ 101 #define SPPCR_IO2FV 0x04 /* Single-/Dual-SPI Mode IO2 Output Fixed Value */ 102 103 /* SPSR - Status Register */ 104 #define SPSR_SPRF 0x80 /* Receive Buffer Full Flag */ 105 #define SPSR_TEND 0x40 /* Transmit End */ 106 #define SPSR_SPTEF 0x20 /* Transmit Buffer Empty Flag */ 107 #define SPSR_PERF 0x08 /* Parity Error Flag */ 108 #define SPSR_MODF 0x04 /* Mode Fault Error Flag */ 109 #define SPSR_IDLNF 0x02 /* RSPI Idle Flag */ 110 #define SPSR_OVRF 0x01 /* Overrun Error Flag (RSPI only) */ 111 112 /* SPSCR - Sequence Control Register */ 113 #define SPSCR_SPSLN_MASK 0x07 /* Sequence Length Specification */ 114 115 /* SPSSR - Sequence Status Register */ 116 #define SPSSR_SPECM_MASK 0x70 /* Command Error Mask */ 117 #define SPSSR_SPCP_MASK 0x07 /* Command Pointer Mask */ 118 119 /* SPDCR - Data Control Register */ 120 #define SPDCR_TXDMY 0x80 /* Dummy Data Transmission Enable */ 121 #define SPDCR_SPLW1 0x40 /* Access Width Specification (RZ) */ 122 #define SPDCR_SPLW0 0x20 /* Access Width Specification (RZ) */ 123 #define SPDCR_SPLLWORD (SPDCR_SPLW1 | SPDCR_SPLW0) 124 #define SPDCR_SPLWORD SPDCR_SPLW1 125 #define SPDCR_SPLBYTE SPDCR_SPLW0 126 #define SPDCR_SPLW 0x20 /* Access Width Specification (SH) */ 127 #define SPDCR_SPRDTD 0x10 /* Receive Transmit Data Select (SH) */ 128 #define SPDCR_SLSEL1 0x08 129 #define SPDCR_SLSEL0 0x04 130 #define SPDCR_SLSEL_MASK 0x0c /* SSL1 Output Select (SH) */ 131 #define SPDCR_SPFC1 0x02 132 #define SPDCR_SPFC0 0x01 133 #define SPDCR_SPFC_MASK 0x03 /* Frame Count Setting (1-4) (SH) */ 134 135 /* SPCKD - Clock Delay Register */ 136 #define SPCKD_SCKDL_MASK 0x07 /* Clock Delay Setting (1-8) */ 137 138 /* SSLND - Slave Select Negation Delay Register */ 139 #define SSLND_SLNDL_MASK 0x07 /* SSL Negation Delay Setting (1-8) */ 140 141 /* SPND - Next-Access Delay Register */ 142 #define SPND_SPNDL_MASK 0x07 /* Next-Access Delay Setting (1-8) */ 143 144 /* SPCR2 - Control Register 2 */ 145 #define SPCR2_PTE 0x08 /* Parity Self-Test Enable */ 146 #define SPCR2_SPIE 0x04 /* Idle Interrupt Enable */ 147 #define SPCR2_SPOE 0x02 /* Odd Parity Enable (vs. Even) */ 148 #define SPCR2_SPPE 0x01 /* Parity Enable */ 149 150 /* SPCMDn - Command Registers */ 151 #define SPCMD_SCKDEN 0x8000 /* Clock Delay Setting Enable */ 152 #define SPCMD_SLNDEN 0x4000 /* SSL Negation Delay Setting Enable */ 153 #define SPCMD_SPNDEN 0x2000 /* Next-Access Delay Enable */ 154 #define SPCMD_LSBF 0x1000 /* LSB First */ 155 #define SPCMD_SPB_MASK 0x0f00 /* Data Length Setting */ 156 #define SPCMD_SPB_8_TO_16(bit) (((bit - 1) << 8) & SPCMD_SPB_MASK) 157 #define SPCMD_SPB_8BIT 0x0000 /* QSPI only */ 158 #define SPCMD_SPB_16BIT 0x0100 159 #define SPCMD_SPB_20BIT 0x0000 160 #define SPCMD_SPB_24BIT 0x0100 161 #define SPCMD_SPB_32BIT 0x0200 162 #define SPCMD_SSLKP 0x0080 /* SSL Signal Level Keeping */ 163 #define SPCMD_SPIMOD_MASK 0x0060 /* SPI Operating Mode (QSPI only) */ 164 #define SPCMD_SPIMOD1 0x0040 165 #define SPCMD_SPIMOD0 0x0020 166 #define SPCMD_SPIMOD_SINGLE 0 167 #define SPCMD_SPIMOD_DUAL SPCMD_SPIMOD0 168 #define SPCMD_SPIMOD_QUAD SPCMD_SPIMOD1 169 #define SPCMD_SPRW 0x0010 /* SPI Read/Write Access (Dual/Quad) */ 170 #define SPCMD_SSLA_MASK 0x0030 /* SSL Assert Signal Setting (RSPI) */ 171 #define SPCMD_BRDV_MASK 0x000c /* Bit Rate Division Setting */ 172 #define SPCMD_CPOL 0x0002 /* Clock Polarity Setting */ 173 #define SPCMD_CPHA 0x0001 /* Clock Phase Setting */ 174 175 /* SPBFCR - Buffer Control Register */ 176 #define SPBFCR_TXRST 0x80 /* Transmit Buffer Data Reset */ 177 #define SPBFCR_RXRST 0x40 /* Receive Buffer Data Reset */ 178 #define SPBFCR_TXTRG_MASK 0x30 /* Transmit Buffer Data Triggering Number */ 179 #define SPBFCR_RXTRG_MASK 0x07 /* Receive Buffer Data Triggering Number */ 180 181 struct rspi_data { 182 void __iomem *addr; 183 u32 max_speed_hz; 184 struct spi_master *master; 185 wait_queue_head_t wait; 186 struct clk *clk; 187 u16 spcmd; 188 u8 spsr; 189 u8 sppcr; 190 int rx_irq, tx_irq; 191 const struct spi_ops *ops; 192 193 unsigned dma_callbacked:1; 194 unsigned byte_access:1; 195 }; 196 197 static void rspi_write8(const struct rspi_data *rspi, u8 data, u16 offset) 198 { 199 iowrite8(data, rspi->addr + offset); 200 } 201 202 static void rspi_write16(const struct rspi_data *rspi, u16 data, u16 offset) 203 { 204 iowrite16(data, rspi->addr + offset); 205 } 206 207 static void rspi_write32(const struct rspi_data *rspi, u32 data, u16 offset) 208 { 209 iowrite32(data, rspi->addr + offset); 210 } 211 212 static u8 rspi_read8(const struct rspi_data *rspi, u16 offset) 213 { 214 return ioread8(rspi->addr + offset); 215 } 216 217 static u16 rspi_read16(const struct rspi_data *rspi, u16 offset) 218 { 219 return ioread16(rspi->addr + offset); 220 } 221 222 static void rspi_write_data(const struct rspi_data *rspi, u16 data) 223 { 224 if (rspi->byte_access) 225 rspi_write8(rspi, data, RSPI_SPDR); 226 else /* 16 bit */ 227 rspi_write16(rspi, data, RSPI_SPDR); 228 } 229 230 static u16 rspi_read_data(const struct rspi_data *rspi) 231 { 232 if (rspi->byte_access) 233 return rspi_read8(rspi, RSPI_SPDR); 234 else /* 16 bit */ 235 return rspi_read16(rspi, RSPI_SPDR); 236 } 237 238 /* optional functions */ 239 struct spi_ops { 240 int (*set_config_register)(struct rspi_data *rspi, int access_size); 241 int (*transfer_one)(struct spi_master *master, struct spi_device *spi, 242 struct spi_transfer *xfer); 243 u16 mode_bits; 244 u16 flags; 245 u16 fifo_size; 246 }; 247 248 /* 249 * functions for RSPI on legacy SH 250 */ 251 static int rspi_set_config_register(struct rspi_data *rspi, int access_size) 252 { 253 int spbr; 254 255 /* Sets output mode, MOSI signal, and (optionally) loopback */ 256 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); 257 258 /* Sets transfer bit rate */ 259 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 260 2 * rspi->max_speed_hz) - 1; 261 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); 262 263 /* Disable dummy transmission, set 16-bit word access, 1 frame */ 264 rspi_write8(rspi, 0, RSPI_SPDCR); 265 rspi->byte_access = 0; 266 267 /* Sets RSPCK, SSL, next-access delay value */ 268 rspi_write8(rspi, 0x00, RSPI_SPCKD); 269 rspi_write8(rspi, 0x00, RSPI_SSLND); 270 rspi_write8(rspi, 0x00, RSPI_SPND); 271 272 /* Sets parity, interrupt mask */ 273 rspi_write8(rspi, 0x00, RSPI_SPCR2); 274 275 /* Sets SPCMD */ 276 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size); 277 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); 278 279 /* Sets RSPI mode */ 280 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); 281 282 return 0; 283 } 284 285 /* 286 * functions for RSPI on RZ 287 */ 288 static int rspi_rz_set_config_register(struct rspi_data *rspi, int access_size) 289 { 290 int spbr; 291 292 /* Sets output mode, MOSI signal, and (optionally) loopback */ 293 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); 294 295 /* Sets transfer bit rate */ 296 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 297 2 * rspi->max_speed_hz) - 1; 298 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); 299 300 /* Disable dummy transmission, set byte access */ 301 rspi_write8(rspi, SPDCR_SPLBYTE, RSPI_SPDCR); 302 rspi->byte_access = 1; 303 304 /* Sets RSPCK, SSL, next-access delay value */ 305 rspi_write8(rspi, 0x00, RSPI_SPCKD); 306 rspi_write8(rspi, 0x00, RSPI_SSLND); 307 rspi_write8(rspi, 0x00, RSPI_SPND); 308 309 /* Sets SPCMD */ 310 rspi->spcmd |= SPCMD_SPB_8_TO_16(access_size); 311 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); 312 313 /* Sets RSPI mode */ 314 rspi_write8(rspi, SPCR_MSTR, RSPI_SPCR); 315 316 return 0; 317 } 318 319 /* 320 * functions for QSPI 321 */ 322 static int qspi_set_config_register(struct rspi_data *rspi, int access_size) 323 { 324 int spbr; 325 326 /* Sets output mode, MOSI signal, and (optionally) loopback */ 327 rspi_write8(rspi, rspi->sppcr, RSPI_SPPCR); 328 329 /* Sets transfer bit rate */ 330 spbr = DIV_ROUND_UP(clk_get_rate(rspi->clk), 2 * rspi->max_speed_hz); 331 rspi_write8(rspi, clamp(spbr, 0, 255), RSPI_SPBR); 332 333 /* Disable dummy transmission, set byte access */ 334 rspi_write8(rspi, 0, RSPI_SPDCR); 335 rspi->byte_access = 1; 336 337 /* Sets RSPCK, SSL, next-access delay value */ 338 rspi_write8(rspi, 0x00, RSPI_SPCKD); 339 rspi_write8(rspi, 0x00, RSPI_SSLND); 340 rspi_write8(rspi, 0x00, RSPI_SPND); 341 342 /* Data Length Setting */ 343 if (access_size == 8) 344 rspi->spcmd |= SPCMD_SPB_8BIT; 345 else if (access_size == 16) 346 rspi->spcmd |= SPCMD_SPB_16BIT; 347 else 348 rspi->spcmd |= SPCMD_SPB_32BIT; 349 350 rspi->spcmd |= SPCMD_SCKDEN | SPCMD_SLNDEN | SPCMD_SPNDEN; 351 352 /* Resets transfer data length */ 353 rspi_write32(rspi, 0, QSPI_SPBMUL0); 354 355 /* Resets transmit and receive buffer */ 356 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); 357 /* Sets buffer to allow normal operation */ 358 rspi_write8(rspi, 0x00, QSPI_SPBFCR); 359 360 /* Sets SPCMD */ 361 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); 362 363 /* Enables SPI function in master mode */ 364 rspi_write8(rspi, SPCR_SPE | SPCR_MSTR, RSPI_SPCR); 365 366 return 0; 367 } 368 369 #define set_config_register(spi, n) spi->ops->set_config_register(spi, n) 370 371 static void rspi_enable_irq(const struct rspi_data *rspi, u8 enable) 372 { 373 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | enable, RSPI_SPCR); 374 } 375 376 static void rspi_disable_irq(const struct rspi_data *rspi, u8 disable) 377 { 378 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~disable, RSPI_SPCR); 379 } 380 381 static int rspi_wait_for_interrupt(struct rspi_data *rspi, u8 wait_mask, 382 u8 enable_bit) 383 { 384 int ret; 385 386 rspi->spsr = rspi_read8(rspi, RSPI_SPSR); 387 if (rspi->spsr & wait_mask) 388 return 0; 389 390 rspi_enable_irq(rspi, enable_bit); 391 ret = wait_event_timeout(rspi->wait, rspi->spsr & wait_mask, HZ); 392 if (ret == 0 && !(rspi->spsr & wait_mask)) 393 return -ETIMEDOUT; 394 395 return 0; 396 } 397 398 static inline int rspi_wait_for_tx_empty(struct rspi_data *rspi) 399 { 400 return rspi_wait_for_interrupt(rspi, SPSR_SPTEF, SPCR_SPTIE); 401 } 402 403 static inline int rspi_wait_for_rx_full(struct rspi_data *rspi) 404 { 405 return rspi_wait_for_interrupt(rspi, SPSR_SPRF, SPCR_SPRIE); 406 } 407 408 static int rspi_data_out(struct rspi_data *rspi, u8 data) 409 { 410 int error = rspi_wait_for_tx_empty(rspi); 411 if (error < 0) { 412 dev_err(&rspi->master->dev, "transmit timeout\n"); 413 return error; 414 } 415 rspi_write_data(rspi, data); 416 return 0; 417 } 418 419 static int rspi_data_in(struct rspi_data *rspi) 420 { 421 int error; 422 u8 data; 423 424 error = rspi_wait_for_rx_full(rspi); 425 if (error < 0) { 426 dev_err(&rspi->master->dev, "receive timeout\n"); 427 return error; 428 } 429 data = rspi_read_data(rspi); 430 return data; 431 } 432 433 static int rspi_pio_transfer(struct rspi_data *rspi, const u8 *tx, u8 *rx, 434 unsigned int n) 435 { 436 while (n-- > 0) { 437 if (tx) { 438 int ret = rspi_data_out(rspi, *tx++); 439 if (ret < 0) 440 return ret; 441 } 442 if (rx) { 443 int ret = rspi_data_in(rspi); 444 if (ret < 0) 445 return ret; 446 *rx++ = ret; 447 } 448 } 449 450 return 0; 451 } 452 453 static void rspi_dma_complete(void *arg) 454 { 455 struct rspi_data *rspi = arg; 456 457 rspi->dma_callbacked = 1; 458 wake_up_interruptible(&rspi->wait); 459 } 460 461 static int rspi_dma_transfer(struct rspi_data *rspi, struct sg_table *tx, 462 struct sg_table *rx) 463 { 464 struct dma_async_tx_descriptor *desc_tx = NULL, *desc_rx = NULL; 465 u8 irq_mask = 0; 466 unsigned int other_irq = 0; 467 dma_cookie_t cookie; 468 int ret; 469 470 /* First prepare and submit the DMA request(s), as this may fail */ 471 if (rx) { 472 desc_rx = dmaengine_prep_slave_sg(rspi->master->dma_rx, 473 rx->sgl, rx->nents, DMA_FROM_DEVICE, 474 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 475 if (!desc_rx) { 476 ret = -EAGAIN; 477 goto no_dma_rx; 478 } 479 480 desc_rx->callback = rspi_dma_complete; 481 desc_rx->callback_param = rspi; 482 cookie = dmaengine_submit(desc_rx); 483 if (dma_submit_error(cookie)) { 484 ret = cookie; 485 goto no_dma_rx; 486 } 487 488 irq_mask |= SPCR_SPRIE; 489 } 490 491 if (tx) { 492 desc_tx = dmaengine_prep_slave_sg(rspi->master->dma_tx, 493 tx->sgl, tx->nents, DMA_TO_DEVICE, 494 DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 495 if (!desc_tx) { 496 ret = -EAGAIN; 497 goto no_dma_tx; 498 } 499 500 if (rx) { 501 /* No callback */ 502 desc_tx->callback = NULL; 503 } else { 504 desc_tx->callback = rspi_dma_complete; 505 desc_tx->callback_param = rspi; 506 } 507 cookie = dmaengine_submit(desc_tx); 508 if (dma_submit_error(cookie)) { 509 ret = cookie; 510 goto no_dma_tx; 511 } 512 513 irq_mask |= SPCR_SPTIE; 514 } 515 516 /* 517 * DMAC needs SPxIE, but if SPxIE is set, the IRQ routine will be 518 * called. So, this driver disables the IRQ while DMA transfer. 519 */ 520 if (tx) 521 disable_irq(other_irq = rspi->tx_irq); 522 if (rx && rspi->rx_irq != other_irq) 523 disable_irq(rspi->rx_irq); 524 525 rspi_enable_irq(rspi, irq_mask); 526 rspi->dma_callbacked = 0; 527 528 /* Now start DMA */ 529 if (rx) 530 dma_async_issue_pending(rspi->master->dma_rx); 531 if (tx) 532 dma_async_issue_pending(rspi->master->dma_tx); 533 534 ret = wait_event_interruptible_timeout(rspi->wait, 535 rspi->dma_callbacked, HZ); 536 if (ret > 0 && rspi->dma_callbacked) 537 ret = 0; 538 else if (!ret) { 539 dev_err(&rspi->master->dev, "DMA timeout\n"); 540 ret = -ETIMEDOUT; 541 if (tx) 542 dmaengine_terminate_all(rspi->master->dma_tx); 543 if (rx) 544 dmaengine_terminate_all(rspi->master->dma_rx); 545 } 546 547 rspi_disable_irq(rspi, irq_mask); 548 549 if (tx) 550 enable_irq(rspi->tx_irq); 551 if (rx && rspi->rx_irq != other_irq) 552 enable_irq(rspi->rx_irq); 553 554 return ret; 555 556 no_dma_tx: 557 if (rx) 558 dmaengine_terminate_all(rspi->master->dma_rx); 559 no_dma_rx: 560 if (ret == -EAGAIN) { 561 pr_warn_once("%s %s: DMA not available, falling back to PIO\n", 562 dev_driver_string(&rspi->master->dev), 563 dev_name(&rspi->master->dev)); 564 } 565 return ret; 566 } 567 568 static void rspi_receive_init(const struct rspi_data *rspi) 569 { 570 u8 spsr; 571 572 spsr = rspi_read8(rspi, RSPI_SPSR); 573 if (spsr & SPSR_SPRF) 574 rspi_read_data(rspi); /* dummy read */ 575 if (spsr & SPSR_OVRF) 576 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPSR) & ~SPSR_OVRF, 577 RSPI_SPSR); 578 } 579 580 static void rspi_rz_receive_init(const struct rspi_data *rspi) 581 { 582 rspi_receive_init(rspi); 583 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, RSPI_SPBFCR); 584 rspi_write8(rspi, 0, RSPI_SPBFCR); 585 } 586 587 static void qspi_receive_init(const struct rspi_data *rspi) 588 { 589 u8 spsr; 590 591 spsr = rspi_read8(rspi, RSPI_SPSR); 592 if (spsr & SPSR_SPRF) 593 rspi_read_data(rspi); /* dummy read */ 594 rspi_write8(rspi, SPBFCR_TXRST | SPBFCR_RXRST, QSPI_SPBFCR); 595 rspi_write8(rspi, 0, QSPI_SPBFCR); 596 } 597 598 static bool __rspi_can_dma(const struct rspi_data *rspi, 599 const struct spi_transfer *xfer) 600 { 601 return xfer->len > rspi->ops->fifo_size; 602 } 603 604 static bool rspi_can_dma(struct spi_master *master, struct spi_device *spi, 605 struct spi_transfer *xfer) 606 { 607 struct rspi_data *rspi = spi_master_get_devdata(master); 608 609 return __rspi_can_dma(rspi, xfer); 610 } 611 612 static int rspi_common_transfer(struct rspi_data *rspi, 613 struct spi_transfer *xfer) 614 { 615 int ret; 616 617 if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) { 618 /* rx_buf can be NULL on RSPI on SH in TX-only Mode */ 619 ret = rspi_dma_transfer(rspi, &xfer->tx_sg, 620 xfer->rx_buf ? &xfer->rx_sg : NULL); 621 if (ret != -EAGAIN) 622 return ret; 623 } 624 625 ret = rspi_pio_transfer(rspi, xfer->tx_buf, xfer->rx_buf, xfer->len); 626 if (ret < 0) 627 return ret; 628 629 /* Wait for the last transmission */ 630 rspi_wait_for_tx_empty(rspi); 631 632 return 0; 633 } 634 635 static int rspi_transfer_one(struct spi_master *master, struct spi_device *spi, 636 struct spi_transfer *xfer) 637 { 638 struct rspi_data *rspi = spi_master_get_devdata(master); 639 u8 spcr; 640 641 spcr = rspi_read8(rspi, RSPI_SPCR); 642 if (xfer->rx_buf) { 643 rspi_receive_init(rspi); 644 spcr &= ~SPCR_TXMD; 645 } else { 646 spcr |= SPCR_TXMD; 647 } 648 rspi_write8(rspi, spcr, RSPI_SPCR); 649 650 return rspi_common_transfer(rspi, xfer); 651 } 652 653 static int rspi_rz_transfer_one(struct spi_master *master, 654 struct spi_device *spi, 655 struct spi_transfer *xfer) 656 { 657 struct rspi_data *rspi = spi_master_get_devdata(master); 658 659 rspi_rz_receive_init(rspi); 660 661 return rspi_common_transfer(rspi, xfer); 662 } 663 664 static int qspi_transfer_out_in(struct rspi_data *rspi, 665 struct spi_transfer *xfer) 666 { 667 qspi_receive_init(rspi); 668 669 return rspi_common_transfer(rspi, xfer); 670 } 671 672 static int qspi_transfer_out(struct rspi_data *rspi, struct spi_transfer *xfer) 673 { 674 int ret; 675 676 if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) { 677 ret = rspi_dma_transfer(rspi, &xfer->tx_sg, NULL); 678 if (ret != -EAGAIN) 679 return ret; 680 } 681 682 ret = rspi_pio_transfer(rspi, xfer->tx_buf, NULL, xfer->len); 683 if (ret < 0) 684 return ret; 685 686 /* Wait for the last transmission */ 687 rspi_wait_for_tx_empty(rspi); 688 689 return 0; 690 } 691 692 static int qspi_transfer_in(struct rspi_data *rspi, struct spi_transfer *xfer) 693 { 694 if (rspi->master->can_dma && __rspi_can_dma(rspi, xfer)) { 695 int ret = rspi_dma_transfer(rspi, NULL, &xfer->rx_sg); 696 if (ret != -EAGAIN) 697 return ret; 698 } 699 700 return rspi_pio_transfer(rspi, NULL, xfer->rx_buf, xfer->len); 701 } 702 703 static int qspi_transfer_one(struct spi_master *master, struct spi_device *spi, 704 struct spi_transfer *xfer) 705 { 706 struct rspi_data *rspi = spi_master_get_devdata(master); 707 708 if (spi->mode & SPI_LOOP) { 709 return qspi_transfer_out_in(rspi, xfer); 710 } else if (xfer->tx_nbits > SPI_NBITS_SINGLE) { 711 /* Quad or Dual SPI Write */ 712 return qspi_transfer_out(rspi, xfer); 713 } else if (xfer->rx_nbits > SPI_NBITS_SINGLE) { 714 /* Quad or Dual SPI Read */ 715 return qspi_transfer_in(rspi, xfer); 716 } else { 717 /* Single SPI Transfer */ 718 return qspi_transfer_out_in(rspi, xfer); 719 } 720 } 721 722 static int rspi_setup(struct spi_device *spi) 723 { 724 struct rspi_data *rspi = spi_master_get_devdata(spi->master); 725 726 rspi->max_speed_hz = spi->max_speed_hz; 727 728 rspi->spcmd = SPCMD_SSLKP; 729 if (spi->mode & SPI_CPOL) 730 rspi->spcmd |= SPCMD_CPOL; 731 if (spi->mode & SPI_CPHA) 732 rspi->spcmd |= SPCMD_CPHA; 733 734 /* CMOS output mode and MOSI signal from previous transfer */ 735 rspi->sppcr = 0; 736 if (spi->mode & SPI_LOOP) 737 rspi->sppcr |= SPPCR_SPLP; 738 739 set_config_register(rspi, 8); 740 741 return 0; 742 } 743 744 static u16 qspi_transfer_mode(const struct spi_transfer *xfer) 745 { 746 if (xfer->tx_buf) 747 switch (xfer->tx_nbits) { 748 case SPI_NBITS_QUAD: 749 return SPCMD_SPIMOD_QUAD; 750 case SPI_NBITS_DUAL: 751 return SPCMD_SPIMOD_DUAL; 752 default: 753 return 0; 754 } 755 if (xfer->rx_buf) 756 switch (xfer->rx_nbits) { 757 case SPI_NBITS_QUAD: 758 return SPCMD_SPIMOD_QUAD | SPCMD_SPRW; 759 case SPI_NBITS_DUAL: 760 return SPCMD_SPIMOD_DUAL | SPCMD_SPRW; 761 default: 762 return 0; 763 } 764 765 return 0; 766 } 767 768 static int qspi_setup_sequencer(struct rspi_data *rspi, 769 const struct spi_message *msg) 770 { 771 const struct spi_transfer *xfer; 772 unsigned int i = 0, len = 0; 773 u16 current_mode = 0xffff, mode; 774 775 list_for_each_entry(xfer, &msg->transfers, transfer_list) { 776 mode = qspi_transfer_mode(xfer); 777 if (mode == current_mode) { 778 len += xfer->len; 779 continue; 780 } 781 782 /* Transfer mode change */ 783 if (i) { 784 /* Set transfer data length of previous transfer */ 785 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1)); 786 } 787 788 if (i >= QSPI_NUM_SPCMD) { 789 dev_err(&msg->spi->dev, 790 "Too many different transfer modes"); 791 return -EINVAL; 792 } 793 794 /* Program transfer mode for this transfer */ 795 rspi_write16(rspi, rspi->spcmd | mode, RSPI_SPCMD(i)); 796 current_mode = mode; 797 len = xfer->len; 798 i++; 799 } 800 if (i) { 801 /* Set final transfer data length and sequence length */ 802 rspi_write32(rspi, len, QSPI_SPBMUL(i - 1)); 803 rspi_write8(rspi, i - 1, RSPI_SPSCR); 804 } 805 806 return 0; 807 } 808 809 static int rspi_prepare_message(struct spi_master *master, 810 struct spi_message *msg) 811 { 812 struct rspi_data *rspi = spi_master_get_devdata(master); 813 int ret; 814 815 if (msg->spi->mode & 816 (SPI_TX_DUAL | SPI_TX_QUAD | SPI_RX_DUAL | SPI_RX_QUAD)) { 817 /* Setup sequencer for messages with multiple transfer modes */ 818 ret = qspi_setup_sequencer(rspi, msg); 819 if (ret < 0) 820 return ret; 821 } 822 823 /* Enable SPI function in master mode */ 824 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) | SPCR_SPE, RSPI_SPCR); 825 return 0; 826 } 827 828 static int rspi_unprepare_message(struct spi_master *master, 829 struct spi_message *msg) 830 { 831 struct rspi_data *rspi = spi_master_get_devdata(master); 832 833 /* Disable SPI function */ 834 rspi_write8(rspi, rspi_read8(rspi, RSPI_SPCR) & ~SPCR_SPE, RSPI_SPCR); 835 836 /* Reset sequencer for Single SPI Transfers */ 837 rspi_write16(rspi, rspi->spcmd, RSPI_SPCMD0); 838 rspi_write8(rspi, 0, RSPI_SPSCR); 839 return 0; 840 } 841 842 static irqreturn_t rspi_irq_mux(int irq, void *_sr) 843 { 844 struct rspi_data *rspi = _sr; 845 u8 spsr; 846 irqreturn_t ret = IRQ_NONE; 847 u8 disable_irq = 0; 848 849 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); 850 if (spsr & SPSR_SPRF) 851 disable_irq |= SPCR_SPRIE; 852 if (spsr & SPSR_SPTEF) 853 disable_irq |= SPCR_SPTIE; 854 855 if (disable_irq) { 856 ret = IRQ_HANDLED; 857 rspi_disable_irq(rspi, disable_irq); 858 wake_up(&rspi->wait); 859 } 860 861 return ret; 862 } 863 864 static irqreturn_t rspi_irq_rx(int irq, void *_sr) 865 { 866 struct rspi_data *rspi = _sr; 867 u8 spsr; 868 869 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); 870 if (spsr & SPSR_SPRF) { 871 rspi_disable_irq(rspi, SPCR_SPRIE); 872 wake_up(&rspi->wait); 873 return IRQ_HANDLED; 874 } 875 876 return 0; 877 } 878 879 static irqreturn_t rspi_irq_tx(int irq, void *_sr) 880 { 881 struct rspi_data *rspi = _sr; 882 u8 spsr; 883 884 rspi->spsr = spsr = rspi_read8(rspi, RSPI_SPSR); 885 if (spsr & SPSR_SPTEF) { 886 rspi_disable_irq(rspi, SPCR_SPTIE); 887 wake_up(&rspi->wait); 888 return IRQ_HANDLED; 889 } 890 891 return 0; 892 } 893 894 static struct dma_chan *rspi_request_dma_chan(struct device *dev, 895 enum dma_transfer_direction dir, 896 unsigned int id, 897 dma_addr_t port_addr) 898 { 899 dma_cap_mask_t mask; 900 struct dma_chan *chan; 901 struct dma_slave_config cfg; 902 int ret; 903 904 dma_cap_zero(mask); 905 dma_cap_set(DMA_SLAVE, mask); 906 907 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter, 908 (void *)(unsigned long)id, dev, 909 dir == DMA_MEM_TO_DEV ? "tx" : "rx"); 910 if (!chan) { 911 dev_warn(dev, "dma_request_slave_channel_compat failed\n"); 912 return NULL; 913 } 914 915 memset(&cfg, 0, sizeof(cfg)); 916 cfg.slave_id = id; 917 cfg.direction = dir; 918 if (dir == DMA_MEM_TO_DEV) { 919 cfg.dst_addr = port_addr; 920 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 921 } else { 922 cfg.src_addr = port_addr; 923 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_1_BYTE; 924 } 925 926 ret = dmaengine_slave_config(chan, &cfg); 927 if (ret) { 928 dev_warn(dev, "dmaengine_slave_config failed %d\n", ret); 929 dma_release_channel(chan); 930 return NULL; 931 } 932 933 return chan; 934 } 935 936 static int rspi_request_dma(struct device *dev, struct spi_master *master, 937 const struct resource *res) 938 { 939 const struct rspi_plat_data *rspi_pd = dev_get_platdata(dev); 940 unsigned int dma_tx_id, dma_rx_id; 941 942 if (dev->of_node) { 943 /* In the OF case we will get the slave IDs from the DT */ 944 dma_tx_id = 0; 945 dma_rx_id = 0; 946 } else if (rspi_pd && rspi_pd->dma_tx_id && rspi_pd->dma_rx_id) { 947 dma_tx_id = rspi_pd->dma_tx_id; 948 dma_rx_id = rspi_pd->dma_rx_id; 949 } else { 950 /* The driver assumes no error. */ 951 return 0; 952 } 953 954 master->dma_tx = rspi_request_dma_chan(dev, DMA_MEM_TO_DEV, dma_tx_id, 955 res->start + RSPI_SPDR); 956 if (!master->dma_tx) 957 return -ENODEV; 958 959 master->dma_rx = rspi_request_dma_chan(dev, DMA_DEV_TO_MEM, dma_rx_id, 960 res->start + RSPI_SPDR); 961 if (!master->dma_rx) { 962 dma_release_channel(master->dma_tx); 963 master->dma_tx = NULL; 964 return -ENODEV; 965 } 966 967 master->can_dma = rspi_can_dma; 968 dev_info(dev, "DMA available"); 969 return 0; 970 } 971 972 static void rspi_release_dma(struct spi_master *master) 973 { 974 if (master->dma_tx) 975 dma_release_channel(master->dma_tx); 976 if (master->dma_rx) 977 dma_release_channel(master->dma_rx); 978 } 979 980 static int rspi_remove(struct platform_device *pdev) 981 { 982 struct rspi_data *rspi = platform_get_drvdata(pdev); 983 984 rspi_release_dma(rspi->master); 985 pm_runtime_disable(&pdev->dev); 986 987 return 0; 988 } 989 990 static const struct spi_ops rspi_ops = { 991 .set_config_register = rspi_set_config_register, 992 .transfer_one = rspi_transfer_one, 993 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP, 994 .flags = SPI_MASTER_MUST_TX, 995 .fifo_size = 8, 996 }; 997 998 static const struct spi_ops rspi_rz_ops = { 999 .set_config_register = rspi_rz_set_config_register, 1000 .transfer_one = rspi_rz_transfer_one, 1001 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP, 1002 .flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX, 1003 .fifo_size = 8, /* 8 for TX, 32 for RX */ 1004 }; 1005 1006 static const struct spi_ops qspi_ops = { 1007 .set_config_register = qspi_set_config_register, 1008 .transfer_one = qspi_transfer_one, 1009 .mode_bits = SPI_CPHA | SPI_CPOL | SPI_LOOP | 1010 SPI_TX_DUAL | SPI_TX_QUAD | 1011 SPI_RX_DUAL | SPI_RX_QUAD, 1012 .flags = SPI_MASTER_MUST_RX | SPI_MASTER_MUST_TX, 1013 .fifo_size = 32, 1014 }; 1015 1016 #ifdef CONFIG_OF 1017 static const struct of_device_id rspi_of_match[] = { 1018 /* RSPI on legacy SH */ 1019 { .compatible = "renesas,rspi", .data = &rspi_ops }, 1020 /* RSPI on RZ/A1H */ 1021 { .compatible = "renesas,rspi-rz", .data = &rspi_rz_ops }, 1022 /* QSPI on R-Car Gen2 */ 1023 { .compatible = "renesas,qspi", .data = &qspi_ops }, 1024 { /* sentinel */ } 1025 }; 1026 1027 MODULE_DEVICE_TABLE(of, rspi_of_match); 1028 1029 static int rspi_parse_dt(struct device *dev, struct spi_master *master) 1030 { 1031 u32 num_cs; 1032 int error; 1033 1034 /* Parse DT properties */ 1035 error = of_property_read_u32(dev->of_node, "num-cs", &num_cs); 1036 if (error) { 1037 dev_err(dev, "of_property_read_u32 num-cs failed %d\n", error); 1038 return error; 1039 } 1040 1041 master->num_chipselect = num_cs; 1042 return 0; 1043 } 1044 #else 1045 #define rspi_of_match NULL 1046 static inline int rspi_parse_dt(struct device *dev, struct spi_master *master) 1047 { 1048 return -EINVAL; 1049 } 1050 #endif /* CONFIG_OF */ 1051 1052 static int rspi_request_irq(struct device *dev, unsigned int irq, 1053 irq_handler_t handler, const char *suffix, 1054 void *dev_id) 1055 { 1056 const char *name = devm_kasprintf(dev, GFP_KERNEL, "%s:%s", 1057 dev_name(dev), suffix); 1058 if (!name) 1059 return -ENOMEM; 1060 1061 return devm_request_irq(dev, irq, handler, 0, name, dev_id); 1062 } 1063 1064 static int rspi_probe(struct platform_device *pdev) 1065 { 1066 struct resource *res; 1067 struct spi_master *master; 1068 struct rspi_data *rspi; 1069 int ret; 1070 const struct of_device_id *of_id; 1071 const struct rspi_plat_data *rspi_pd; 1072 const struct spi_ops *ops; 1073 1074 master = spi_alloc_master(&pdev->dev, sizeof(struct rspi_data)); 1075 if (master == NULL) { 1076 dev_err(&pdev->dev, "spi_alloc_master error.\n"); 1077 return -ENOMEM; 1078 } 1079 1080 of_id = of_match_device(rspi_of_match, &pdev->dev); 1081 if (of_id) { 1082 ops = of_id->data; 1083 ret = rspi_parse_dt(&pdev->dev, master); 1084 if (ret) 1085 goto error1; 1086 } else { 1087 ops = (struct spi_ops *)pdev->id_entry->driver_data; 1088 rspi_pd = dev_get_platdata(&pdev->dev); 1089 if (rspi_pd && rspi_pd->num_chipselect) 1090 master->num_chipselect = rspi_pd->num_chipselect; 1091 else 1092 master->num_chipselect = 2; /* default */ 1093 } 1094 1095 /* ops parameter check */ 1096 if (!ops->set_config_register) { 1097 dev_err(&pdev->dev, "there is no set_config_register\n"); 1098 ret = -ENODEV; 1099 goto error1; 1100 } 1101 1102 rspi = spi_master_get_devdata(master); 1103 platform_set_drvdata(pdev, rspi); 1104 rspi->ops = ops; 1105 rspi->master = master; 1106 1107 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1108 rspi->addr = devm_ioremap_resource(&pdev->dev, res); 1109 if (IS_ERR(rspi->addr)) { 1110 ret = PTR_ERR(rspi->addr); 1111 goto error1; 1112 } 1113 1114 rspi->clk = devm_clk_get(&pdev->dev, NULL); 1115 if (IS_ERR(rspi->clk)) { 1116 dev_err(&pdev->dev, "cannot get clock\n"); 1117 ret = PTR_ERR(rspi->clk); 1118 goto error1; 1119 } 1120 1121 pm_runtime_enable(&pdev->dev); 1122 1123 init_waitqueue_head(&rspi->wait); 1124 1125 master->bus_num = pdev->id; 1126 master->setup = rspi_setup; 1127 master->auto_runtime_pm = true; 1128 master->transfer_one = ops->transfer_one; 1129 master->prepare_message = rspi_prepare_message; 1130 master->unprepare_message = rspi_unprepare_message; 1131 master->mode_bits = ops->mode_bits; 1132 master->flags = ops->flags; 1133 master->dev.of_node = pdev->dev.of_node; 1134 1135 ret = platform_get_irq_byname(pdev, "rx"); 1136 if (ret < 0) { 1137 ret = platform_get_irq_byname(pdev, "mux"); 1138 if (ret < 0) 1139 ret = platform_get_irq(pdev, 0); 1140 if (ret >= 0) 1141 rspi->rx_irq = rspi->tx_irq = ret; 1142 } else { 1143 rspi->rx_irq = ret; 1144 ret = platform_get_irq_byname(pdev, "tx"); 1145 if (ret >= 0) 1146 rspi->tx_irq = ret; 1147 } 1148 if (ret < 0) { 1149 dev_err(&pdev->dev, "platform_get_irq error\n"); 1150 goto error2; 1151 } 1152 1153 if (rspi->rx_irq == rspi->tx_irq) { 1154 /* Single multiplexed interrupt */ 1155 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_mux, 1156 "mux", rspi); 1157 } else { 1158 /* Multi-interrupt mode, only SPRI and SPTI are used */ 1159 ret = rspi_request_irq(&pdev->dev, rspi->rx_irq, rspi_irq_rx, 1160 "rx", rspi); 1161 if (!ret) 1162 ret = rspi_request_irq(&pdev->dev, rspi->tx_irq, 1163 rspi_irq_tx, "tx", rspi); 1164 } 1165 if (ret < 0) { 1166 dev_err(&pdev->dev, "request_irq error\n"); 1167 goto error2; 1168 } 1169 1170 ret = rspi_request_dma(&pdev->dev, master, res); 1171 if (ret < 0) 1172 dev_warn(&pdev->dev, "DMA not available, using PIO\n"); 1173 1174 ret = devm_spi_register_master(&pdev->dev, master); 1175 if (ret < 0) { 1176 dev_err(&pdev->dev, "spi_register_master error.\n"); 1177 goto error3; 1178 } 1179 1180 dev_info(&pdev->dev, "probed\n"); 1181 1182 return 0; 1183 1184 error3: 1185 rspi_release_dma(master); 1186 error2: 1187 pm_runtime_disable(&pdev->dev); 1188 error1: 1189 spi_master_put(master); 1190 1191 return ret; 1192 } 1193 1194 static struct platform_device_id spi_driver_ids[] = { 1195 { "rspi", (kernel_ulong_t)&rspi_ops }, 1196 { "rspi-rz", (kernel_ulong_t)&rspi_rz_ops }, 1197 { "qspi", (kernel_ulong_t)&qspi_ops }, 1198 {}, 1199 }; 1200 1201 MODULE_DEVICE_TABLE(platform, spi_driver_ids); 1202 1203 static struct platform_driver rspi_driver = { 1204 .probe = rspi_probe, 1205 .remove = rspi_remove, 1206 .id_table = spi_driver_ids, 1207 .driver = { 1208 .name = "renesas_spi", 1209 .of_match_table = of_match_ptr(rspi_of_match), 1210 }, 1211 }; 1212 module_platform_driver(rspi_driver); 1213 1214 MODULE_DESCRIPTION("Renesas RSPI bus driver"); 1215 MODULE_LICENSE("GPL v2"); 1216 MODULE_AUTHOR("Yoshihiro Shimoda"); 1217 MODULE_ALIAS("platform:rspi"); 1218