1 /* 2 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd 3 * Author: Addy Ke <addy.ke@rock-chips.com> 4 * 5 * This program is free software; you can redistribute it and/or modify it 6 * under the terms and conditions of the GNU General Public License, 7 * version 2, as published by the Free Software Foundation. 8 * 9 * This program is distributed in the hope it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for 12 * more details. 13 * 14 */ 15 16 #include <linux/init.h> 17 #include <linux/module.h> 18 #include <linux/clk.h> 19 #include <linux/err.h> 20 #include <linux/delay.h> 21 #include <linux/interrupt.h> 22 #include <linux/platform_device.h> 23 #include <linux/slab.h> 24 #include <linux/spi/spi.h> 25 #include <linux/scatterlist.h> 26 #include <linux/of.h> 27 #include <linux/pm_runtime.h> 28 #include <linux/io.h> 29 #include <linux/dmaengine.h> 30 31 #define DRIVER_NAME "rockchip-spi" 32 33 /* SPI register offsets */ 34 #define ROCKCHIP_SPI_CTRLR0 0x0000 35 #define ROCKCHIP_SPI_CTRLR1 0x0004 36 #define ROCKCHIP_SPI_SSIENR 0x0008 37 #define ROCKCHIP_SPI_SER 0x000c 38 #define ROCKCHIP_SPI_BAUDR 0x0010 39 #define ROCKCHIP_SPI_TXFTLR 0x0014 40 #define ROCKCHIP_SPI_RXFTLR 0x0018 41 #define ROCKCHIP_SPI_TXFLR 0x001c 42 #define ROCKCHIP_SPI_RXFLR 0x0020 43 #define ROCKCHIP_SPI_SR 0x0024 44 #define ROCKCHIP_SPI_IPR 0x0028 45 #define ROCKCHIP_SPI_IMR 0x002c 46 #define ROCKCHIP_SPI_ISR 0x0030 47 #define ROCKCHIP_SPI_RISR 0x0034 48 #define ROCKCHIP_SPI_ICR 0x0038 49 #define ROCKCHIP_SPI_DMACR 0x003c 50 #define ROCKCHIP_SPI_DMATDLR 0x0040 51 #define ROCKCHIP_SPI_DMARDLR 0x0044 52 #define ROCKCHIP_SPI_TXDR 0x0400 53 #define ROCKCHIP_SPI_RXDR 0x0800 54 55 /* Bit fields in CTRLR0 */ 56 #define CR0_DFS_OFFSET 0 57 58 #define CR0_CFS_OFFSET 2 59 60 #define CR0_SCPH_OFFSET 6 61 62 #define CR0_SCPOL_OFFSET 7 63 64 #define CR0_CSM_OFFSET 8 65 #define CR0_CSM_KEEP 0x0 66 /* ss_n be high for half sclk_out cycles */ 67 #define CR0_CSM_HALF 0X1 68 /* ss_n be high for one sclk_out cycle */ 69 #define CR0_CSM_ONE 0x2 70 71 /* ss_n to sclk_out delay */ 72 #define CR0_SSD_OFFSET 10 73 /* 74 * The period between ss_n active and 75 * sclk_out active is half sclk_out cycles 76 */ 77 #define CR0_SSD_HALF 0x0 78 /* 79 * The period between ss_n active and 80 * sclk_out active is one sclk_out cycle 81 */ 82 #define CR0_SSD_ONE 0x1 83 84 #define CR0_EM_OFFSET 11 85 #define CR0_EM_LITTLE 0x0 86 #define CR0_EM_BIG 0x1 87 88 #define CR0_FBM_OFFSET 12 89 #define CR0_FBM_MSB 0x0 90 #define CR0_FBM_LSB 0x1 91 92 #define CR0_BHT_OFFSET 13 93 #define CR0_BHT_16BIT 0x0 94 #define CR0_BHT_8BIT 0x1 95 96 #define CR0_RSD_OFFSET 14 97 98 #define CR0_FRF_OFFSET 16 99 #define CR0_FRF_SPI 0x0 100 #define CR0_FRF_SSP 0x1 101 #define CR0_FRF_MICROWIRE 0x2 102 103 #define CR0_XFM_OFFSET 18 104 #define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET) 105 #define CR0_XFM_TR 0x0 106 #define CR0_XFM_TO 0x1 107 #define CR0_XFM_RO 0x2 108 109 #define CR0_OPM_OFFSET 20 110 #define CR0_OPM_MASTER 0x0 111 #define CR0_OPM_SLAVE 0x1 112 113 #define CR0_MTM_OFFSET 0x21 114 115 /* Bit fields in SER, 2bit */ 116 #define SER_MASK 0x3 117 118 /* Bit fields in SR, 5bit */ 119 #define SR_MASK 0x1f 120 #define SR_BUSY (1 << 0) 121 #define SR_TF_FULL (1 << 1) 122 #define SR_TF_EMPTY (1 << 2) 123 #define SR_RF_EMPTY (1 << 3) 124 #define SR_RF_FULL (1 << 4) 125 126 /* Bit fields in ISR, IMR, ISR, RISR, 5bit */ 127 #define INT_MASK 0x1f 128 #define INT_TF_EMPTY (1 << 0) 129 #define INT_TF_OVERFLOW (1 << 1) 130 #define INT_RF_UNDERFLOW (1 << 2) 131 #define INT_RF_OVERFLOW (1 << 3) 132 #define INT_RF_FULL (1 << 4) 133 134 /* Bit fields in ICR, 4bit */ 135 #define ICR_MASK 0x0f 136 #define ICR_ALL (1 << 0) 137 #define ICR_RF_UNDERFLOW (1 << 1) 138 #define ICR_RF_OVERFLOW (1 << 2) 139 #define ICR_TF_OVERFLOW (1 << 3) 140 141 /* Bit fields in DMACR */ 142 #define RF_DMA_EN (1 << 0) 143 #define TF_DMA_EN (1 << 1) 144 145 #define RXBUSY (1 << 0) 146 #define TXBUSY (1 << 1) 147 148 /* sclk_out: spi master internal logic in rk3x can support 50Mhz */ 149 #define MAX_SCLK_OUT 50000000 150 151 enum rockchip_ssi_type { 152 SSI_MOTO_SPI = 0, 153 SSI_TI_SSP, 154 SSI_NS_MICROWIRE, 155 }; 156 157 struct rockchip_spi_dma_data { 158 struct dma_chan *ch; 159 enum dma_transfer_direction direction; 160 dma_addr_t addr; 161 }; 162 163 struct rockchip_spi { 164 struct device *dev; 165 struct spi_master *master; 166 167 struct clk *spiclk; 168 struct clk *apb_pclk; 169 170 void __iomem *regs; 171 /*depth of the FIFO buffer */ 172 u32 fifo_len; 173 /* max bus freq supported */ 174 u32 max_freq; 175 /* supported slave numbers */ 176 enum rockchip_ssi_type type; 177 178 u16 mode; 179 u8 tmode; 180 u8 bpw; 181 u8 n_bytes; 182 unsigned len; 183 u32 speed; 184 185 const void *tx; 186 const void *tx_end; 187 void *rx; 188 void *rx_end; 189 190 u32 state; 191 /* protect state */ 192 spinlock_t lock; 193 194 struct completion xfer_completion; 195 196 u32 use_dma; 197 struct sg_table tx_sg; 198 struct sg_table rx_sg; 199 struct rockchip_spi_dma_data dma_rx; 200 struct rockchip_spi_dma_data dma_tx; 201 }; 202 203 static inline void spi_enable_chip(struct rockchip_spi *rs, int enable) 204 { 205 writel_relaxed((enable ? 1 : 0), rs->regs + ROCKCHIP_SPI_SSIENR); 206 } 207 208 static inline void spi_set_clk(struct rockchip_spi *rs, u16 div) 209 { 210 writel_relaxed(div, rs->regs + ROCKCHIP_SPI_BAUDR); 211 } 212 213 static inline void flush_fifo(struct rockchip_spi *rs) 214 { 215 while (readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR)) 216 readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR); 217 } 218 219 static inline void wait_for_idle(struct rockchip_spi *rs) 220 { 221 unsigned long timeout = jiffies + msecs_to_jiffies(5); 222 223 do { 224 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)) 225 return; 226 } while (!time_after(jiffies, timeout)); 227 228 dev_warn(rs->dev, "spi controller is in busy state!\n"); 229 } 230 231 static u32 get_fifo_len(struct rockchip_spi *rs) 232 { 233 u32 fifo; 234 235 for (fifo = 2; fifo < 32; fifo++) { 236 writel_relaxed(fifo, rs->regs + ROCKCHIP_SPI_TXFTLR); 237 if (fifo != readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFTLR)) 238 break; 239 } 240 241 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_TXFTLR); 242 243 return (fifo == 31) ? 0 : fifo; 244 } 245 246 static inline u32 tx_max(struct rockchip_spi *rs) 247 { 248 u32 tx_left, tx_room; 249 250 tx_left = (rs->tx_end - rs->tx) / rs->n_bytes; 251 tx_room = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR); 252 253 return min(tx_left, tx_room); 254 } 255 256 static inline u32 rx_max(struct rockchip_spi *rs) 257 { 258 u32 rx_left = (rs->rx_end - rs->rx) / rs->n_bytes; 259 u32 rx_room = (u32)readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR); 260 261 return min(rx_left, rx_room); 262 } 263 264 static void rockchip_spi_set_cs(struct spi_device *spi, bool enable) 265 { 266 u32 ser; 267 struct rockchip_spi *rs = spi_master_get_devdata(spi->master); 268 269 ser = readl_relaxed(rs->regs + ROCKCHIP_SPI_SER) & SER_MASK; 270 271 /* 272 * drivers/spi/spi.c: 273 * static void spi_set_cs(struct spi_device *spi, bool enable) 274 * { 275 * if (spi->mode & SPI_CS_HIGH) 276 * enable = !enable; 277 * 278 * if (spi->cs_gpio >= 0) 279 * gpio_set_value(spi->cs_gpio, !enable); 280 * else if (spi->master->set_cs) 281 * spi->master->set_cs(spi, !enable); 282 * } 283 * 284 * Note: enable(rockchip_spi_set_cs) = !enable(spi_set_cs) 285 */ 286 if (!enable) 287 ser |= 1 << spi->chip_select; 288 else 289 ser &= ~(1 << spi->chip_select); 290 291 writel_relaxed(ser, rs->regs + ROCKCHIP_SPI_SER); 292 } 293 294 static int rockchip_spi_prepare_message(struct spi_master *master, 295 struct spi_message *msg) 296 { 297 struct rockchip_spi *rs = spi_master_get_devdata(master); 298 struct spi_device *spi = msg->spi; 299 300 rs->mode = spi->mode; 301 302 return 0; 303 } 304 305 static int rockchip_spi_unprepare_message(struct spi_master *master, 306 struct spi_message *msg) 307 { 308 unsigned long flags; 309 struct rockchip_spi *rs = spi_master_get_devdata(master); 310 311 spin_lock_irqsave(&rs->lock, flags); 312 313 /* 314 * For DMA mode, we need terminate DMA channel and flush 315 * fifo for the next transfer if DMA thansfer timeout. 316 * unprepare_message() was called by core if transfer complete 317 * or timeout. Maybe it is reasonable for error handling here. 318 */ 319 if (rs->use_dma) { 320 if (rs->state & RXBUSY) { 321 dmaengine_terminate_all(rs->dma_rx.ch); 322 flush_fifo(rs); 323 } 324 325 if (rs->state & TXBUSY) 326 dmaengine_terminate_all(rs->dma_tx.ch); 327 } 328 329 spin_unlock_irqrestore(&rs->lock, flags); 330 331 spi_enable_chip(rs, 0); 332 333 return 0; 334 } 335 336 static void rockchip_spi_pio_writer(struct rockchip_spi *rs) 337 { 338 u32 max = tx_max(rs); 339 u32 txw = 0; 340 341 while (max--) { 342 if (rs->n_bytes == 1) 343 txw = *(u8 *)(rs->tx); 344 else 345 txw = *(u16 *)(rs->tx); 346 347 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR); 348 rs->tx += rs->n_bytes; 349 } 350 } 351 352 static void rockchip_spi_pio_reader(struct rockchip_spi *rs) 353 { 354 u32 max = rx_max(rs); 355 u32 rxw; 356 357 while (max--) { 358 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR); 359 if (rs->n_bytes == 1) 360 *(u8 *)(rs->rx) = (u8)rxw; 361 else 362 *(u16 *)(rs->rx) = (u16)rxw; 363 rs->rx += rs->n_bytes; 364 } 365 } 366 367 static int rockchip_spi_pio_transfer(struct rockchip_spi *rs) 368 { 369 int remain = 0; 370 371 do { 372 if (rs->tx) { 373 remain = rs->tx_end - rs->tx; 374 rockchip_spi_pio_writer(rs); 375 } 376 377 if (rs->rx) { 378 remain = rs->rx_end - rs->rx; 379 rockchip_spi_pio_reader(rs); 380 } 381 382 cpu_relax(); 383 } while (remain); 384 385 /* If tx, wait until the FIFO data completely. */ 386 if (rs->tx) 387 wait_for_idle(rs); 388 389 spi_enable_chip(rs, 0); 390 391 return 0; 392 } 393 394 static void rockchip_spi_dma_rxcb(void *data) 395 { 396 unsigned long flags; 397 struct rockchip_spi *rs = data; 398 399 spin_lock_irqsave(&rs->lock, flags); 400 401 rs->state &= ~RXBUSY; 402 if (!(rs->state & TXBUSY)) { 403 spi_enable_chip(rs, 0); 404 spi_finalize_current_transfer(rs->master); 405 } 406 407 spin_unlock_irqrestore(&rs->lock, flags); 408 } 409 410 static void rockchip_spi_dma_txcb(void *data) 411 { 412 unsigned long flags; 413 struct rockchip_spi *rs = data; 414 415 /* Wait until the FIFO data completely. */ 416 wait_for_idle(rs); 417 418 spin_lock_irqsave(&rs->lock, flags); 419 420 rs->state &= ~TXBUSY; 421 if (!(rs->state & RXBUSY)) { 422 spi_enable_chip(rs, 0); 423 spi_finalize_current_transfer(rs->master); 424 } 425 426 spin_unlock_irqrestore(&rs->lock, flags); 427 } 428 429 static void rockchip_spi_prepare_dma(struct rockchip_spi *rs) 430 { 431 unsigned long flags; 432 struct dma_slave_config rxconf, txconf; 433 struct dma_async_tx_descriptor *rxdesc, *txdesc; 434 435 spin_lock_irqsave(&rs->lock, flags); 436 rs->state &= ~RXBUSY; 437 rs->state &= ~TXBUSY; 438 spin_unlock_irqrestore(&rs->lock, flags); 439 440 rxdesc = NULL; 441 if (rs->rx) { 442 rxconf.direction = rs->dma_rx.direction; 443 rxconf.src_addr = rs->dma_rx.addr; 444 rxconf.src_addr_width = rs->n_bytes; 445 rxconf.src_maxburst = rs->n_bytes; 446 dmaengine_slave_config(rs->dma_rx.ch, &rxconf); 447 448 rxdesc = dmaengine_prep_slave_sg( 449 rs->dma_rx.ch, 450 rs->rx_sg.sgl, rs->rx_sg.nents, 451 rs->dma_rx.direction, DMA_PREP_INTERRUPT); 452 453 rxdesc->callback = rockchip_spi_dma_rxcb; 454 rxdesc->callback_param = rs; 455 } 456 457 txdesc = NULL; 458 if (rs->tx) { 459 txconf.direction = rs->dma_tx.direction; 460 txconf.dst_addr = rs->dma_tx.addr; 461 txconf.dst_addr_width = rs->n_bytes; 462 txconf.dst_maxburst = rs->n_bytes; 463 dmaengine_slave_config(rs->dma_tx.ch, &txconf); 464 465 txdesc = dmaengine_prep_slave_sg( 466 rs->dma_tx.ch, 467 rs->tx_sg.sgl, rs->tx_sg.nents, 468 rs->dma_tx.direction, DMA_PREP_INTERRUPT); 469 470 txdesc->callback = rockchip_spi_dma_txcb; 471 txdesc->callback_param = rs; 472 } 473 474 /* rx must be started before tx due to spi instinct */ 475 if (rxdesc) { 476 spin_lock_irqsave(&rs->lock, flags); 477 rs->state |= RXBUSY; 478 spin_unlock_irqrestore(&rs->lock, flags); 479 dmaengine_submit(rxdesc); 480 dma_async_issue_pending(rs->dma_rx.ch); 481 } 482 483 if (txdesc) { 484 spin_lock_irqsave(&rs->lock, flags); 485 rs->state |= TXBUSY; 486 spin_unlock_irqrestore(&rs->lock, flags); 487 dmaengine_submit(txdesc); 488 dma_async_issue_pending(rs->dma_tx.ch); 489 } 490 } 491 492 static void rockchip_spi_config(struct rockchip_spi *rs) 493 { 494 u32 div = 0; 495 u32 dmacr = 0; 496 497 u32 cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET) 498 | (CR0_SSD_ONE << CR0_SSD_OFFSET); 499 500 cr0 |= (rs->n_bytes << CR0_DFS_OFFSET); 501 cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET); 502 cr0 |= (rs->tmode << CR0_XFM_OFFSET); 503 cr0 |= (rs->type << CR0_FRF_OFFSET); 504 505 if (rs->use_dma) { 506 if (rs->tx) 507 dmacr |= TF_DMA_EN; 508 if (rs->rx) 509 dmacr |= RF_DMA_EN; 510 } 511 512 if (WARN_ON(rs->speed > MAX_SCLK_OUT)) 513 rs->speed = MAX_SCLK_OUT; 514 515 /* the minimum divsor is 2 */ 516 if (rs->max_freq < 2 * rs->speed) { 517 clk_set_rate(rs->spiclk, 2 * rs->speed); 518 rs->max_freq = clk_get_rate(rs->spiclk); 519 } 520 521 /* div doesn't support odd number */ 522 div = max_t(u32, rs->max_freq / rs->speed, 1); 523 div = (div + 1) & 0xfffe; 524 525 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0); 526 527 writel_relaxed(rs->len - 1, rs->regs + ROCKCHIP_SPI_CTRLR1); 528 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_TXFTLR); 529 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR); 530 531 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMATDLR); 532 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMARDLR); 533 writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR); 534 535 spi_set_clk(rs, div); 536 537 dev_dbg(rs->dev, "cr0 0x%x, div %d\n", cr0, div); 538 } 539 540 static int rockchip_spi_transfer_one( 541 struct spi_master *master, 542 struct spi_device *spi, 543 struct spi_transfer *xfer) 544 { 545 int ret = 1; 546 struct rockchip_spi *rs = spi_master_get_devdata(master); 547 548 WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) && 549 (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)); 550 551 if (!xfer->tx_buf && !xfer->rx_buf) { 552 dev_err(rs->dev, "No buffer for transfer\n"); 553 return -EINVAL; 554 } 555 556 rs->speed = xfer->speed_hz; 557 rs->bpw = xfer->bits_per_word; 558 rs->n_bytes = rs->bpw >> 3; 559 560 rs->tx = xfer->tx_buf; 561 rs->tx_end = rs->tx + xfer->len; 562 rs->rx = xfer->rx_buf; 563 rs->rx_end = rs->rx + xfer->len; 564 rs->len = xfer->len; 565 566 rs->tx_sg = xfer->tx_sg; 567 rs->rx_sg = xfer->rx_sg; 568 569 if (rs->tx && rs->rx) 570 rs->tmode = CR0_XFM_TR; 571 else if (rs->tx) 572 rs->tmode = CR0_XFM_TO; 573 else if (rs->rx) 574 rs->tmode = CR0_XFM_RO; 575 576 /* we need prepare dma before spi was enabled */ 577 if (master->can_dma && master->can_dma(master, spi, xfer)) 578 rs->use_dma = 1; 579 else 580 rs->use_dma = 0; 581 582 rockchip_spi_config(rs); 583 584 if (rs->use_dma) { 585 if (rs->tmode == CR0_XFM_RO) { 586 /* rx: dma must be prepared first */ 587 rockchip_spi_prepare_dma(rs); 588 spi_enable_chip(rs, 1); 589 } else { 590 /* tx or tr: spi must be enabled first */ 591 spi_enable_chip(rs, 1); 592 rockchip_spi_prepare_dma(rs); 593 } 594 } else { 595 spi_enable_chip(rs, 1); 596 ret = rockchip_spi_pio_transfer(rs); 597 } 598 599 return ret; 600 } 601 602 static bool rockchip_spi_can_dma(struct spi_master *master, 603 struct spi_device *spi, 604 struct spi_transfer *xfer) 605 { 606 struct rockchip_spi *rs = spi_master_get_devdata(master); 607 608 return (xfer->len > rs->fifo_len); 609 } 610 611 static int rockchip_spi_probe(struct platform_device *pdev) 612 { 613 int ret = 0; 614 struct rockchip_spi *rs; 615 struct spi_master *master; 616 struct resource *mem; 617 618 master = spi_alloc_master(&pdev->dev, sizeof(struct rockchip_spi)); 619 if (!master) 620 return -ENOMEM; 621 622 platform_set_drvdata(pdev, master); 623 624 rs = spi_master_get_devdata(master); 625 memset(rs, 0, sizeof(struct rockchip_spi)); 626 627 /* Get basic io resource and map it */ 628 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 629 rs->regs = devm_ioremap_resource(&pdev->dev, mem); 630 if (IS_ERR(rs->regs)) { 631 ret = PTR_ERR(rs->regs); 632 goto err_ioremap_resource; 633 } 634 635 rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk"); 636 if (IS_ERR(rs->apb_pclk)) { 637 dev_err(&pdev->dev, "Failed to get apb_pclk\n"); 638 ret = PTR_ERR(rs->apb_pclk); 639 goto err_ioremap_resource; 640 } 641 642 rs->spiclk = devm_clk_get(&pdev->dev, "spiclk"); 643 if (IS_ERR(rs->spiclk)) { 644 dev_err(&pdev->dev, "Failed to get spi_pclk\n"); 645 ret = PTR_ERR(rs->spiclk); 646 goto err_ioremap_resource; 647 } 648 649 ret = clk_prepare_enable(rs->apb_pclk); 650 if (ret) { 651 dev_err(&pdev->dev, "Failed to enable apb_pclk\n"); 652 goto err_ioremap_resource; 653 } 654 655 ret = clk_prepare_enable(rs->spiclk); 656 if (ret) { 657 dev_err(&pdev->dev, "Failed to enable spi_clk\n"); 658 goto err_spiclk_enable; 659 } 660 661 spi_enable_chip(rs, 0); 662 663 rs->type = SSI_MOTO_SPI; 664 rs->master = master; 665 rs->dev = &pdev->dev; 666 rs->max_freq = clk_get_rate(rs->spiclk); 667 668 rs->fifo_len = get_fifo_len(rs); 669 if (!rs->fifo_len) { 670 dev_err(&pdev->dev, "Failed to get fifo length\n"); 671 ret = -EINVAL; 672 goto err_get_fifo_len; 673 } 674 675 spin_lock_init(&rs->lock); 676 677 pm_runtime_set_active(&pdev->dev); 678 pm_runtime_enable(&pdev->dev); 679 680 master->auto_runtime_pm = true; 681 master->bus_num = pdev->id; 682 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP; 683 master->num_chipselect = 2; 684 master->dev.of_node = pdev->dev.of_node; 685 master->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8); 686 687 master->set_cs = rockchip_spi_set_cs; 688 master->prepare_message = rockchip_spi_prepare_message; 689 master->unprepare_message = rockchip_spi_unprepare_message; 690 master->transfer_one = rockchip_spi_transfer_one; 691 692 rs->dma_tx.ch = dma_request_slave_channel(rs->dev, "tx"); 693 if (!rs->dma_tx.ch) 694 dev_warn(rs->dev, "Failed to request TX DMA channel\n"); 695 696 rs->dma_rx.ch = dma_request_slave_channel(rs->dev, "rx"); 697 if (!rs->dma_rx.ch) { 698 if (rs->dma_tx.ch) { 699 dma_release_channel(rs->dma_tx.ch); 700 rs->dma_tx.ch = NULL; 701 } 702 dev_warn(rs->dev, "Failed to request RX DMA channel\n"); 703 } 704 705 if (rs->dma_tx.ch && rs->dma_rx.ch) { 706 rs->dma_tx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_TXDR); 707 rs->dma_rx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_RXDR); 708 rs->dma_tx.direction = DMA_MEM_TO_DEV; 709 rs->dma_rx.direction = DMA_DEV_TO_MEM; 710 711 master->can_dma = rockchip_spi_can_dma; 712 master->dma_tx = rs->dma_tx.ch; 713 master->dma_rx = rs->dma_rx.ch; 714 } 715 716 ret = devm_spi_register_master(&pdev->dev, master); 717 if (ret) { 718 dev_err(&pdev->dev, "Failed to register master\n"); 719 goto err_register_master; 720 } 721 722 return 0; 723 724 err_register_master: 725 if (rs->dma_tx.ch) 726 dma_release_channel(rs->dma_tx.ch); 727 if (rs->dma_rx.ch) 728 dma_release_channel(rs->dma_rx.ch); 729 err_get_fifo_len: 730 clk_disable_unprepare(rs->spiclk); 731 err_spiclk_enable: 732 clk_disable_unprepare(rs->apb_pclk); 733 err_ioremap_resource: 734 spi_master_put(master); 735 736 return ret; 737 } 738 739 static int rockchip_spi_remove(struct platform_device *pdev) 740 { 741 struct spi_master *master = spi_master_get(platform_get_drvdata(pdev)); 742 struct rockchip_spi *rs = spi_master_get_devdata(master); 743 744 pm_runtime_disable(&pdev->dev); 745 746 clk_disable_unprepare(rs->spiclk); 747 clk_disable_unprepare(rs->apb_pclk); 748 749 if (rs->dma_tx.ch) 750 dma_release_channel(rs->dma_tx.ch); 751 if (rs->dma_rx.ch) 752 dma_release_channel(rs->dma_rx.ch); 753 754 return 0; 755 } 756 757 #ifdef CONFIG_PM_SLEEP 758 static int rockchip_spi_suspend(struct device *dev) 759 { 760 int ret = 0; 761 struct spi_master *master = dev_get_drvdata(dev); 762 struct rockchip_spi *rs = spi_master_get_devdata(master); 763 764 ret = spi_master_suspend(rs->master); 765 if (ret) 766 return ret; 767 768 if (!pm_runtime_suspended(dev)) { 769 clk_disable_unprepare(rs->spiclk); 770 clk_disable_unprepare(rs->apb_pclk); 771 } 772 773 return ret; 774 } 775 776 static int rockchip_spi_resume(struct device *dev) 777 { 778 int ret = 0; 779 struct spi_master *master = dev_get_drvdata(dev); 780 struct rockchip_spi *rs = spi_master_get_devdata(master); 781 782 if (!pm_runtime_suspended(dev)) { 783 ret = clk_prepare_enable(rs->apb_pclk); 784 if (ret < 0) 785 return ret; 786 787 ret = clk_prepare_enable(rs->spiclk); 788 if (ret < 0) { 789 clk_disable_unprepare(rs->apb_pclk); 790 return ret; 791 } 792 } 793 794 ret = spi_master_resume(rs->master); 795 if (ret < 0) { 796 clk_disable_unprepare(rs->spiclk); 797 clk_disable_unprepare(rs->apb_pclk); 798 } 799 800 return ret; 801 } 802 #endif /* CONFIG_PM_SLEEP */ 803 804 #ifdef CONFIG_PM 805 static int rockchip_spi_runtime_suspend(struct device *dev) 806 { 807 struct spi_master *master = dev_get_drvdata(dev); 808 struct rockchip_spi *rs = spi_master_get_devdata(master); 809 810 clk_disable_unprepare(rs->spiclk); 811 clk_disable_unprepare(rs->apb_pclk); 812 813 return 0; 814 } 815 816 static int rockchip_spi_runtime_resume(struct device *dev) 817 { 818 int ret; 819 struct spi_master *master = dev_get_drvdata(dev); 820 struct rockchip_spi *rs = spi_master_get_devdata(master); 821 822 ret = clk_prepare_enable(rs->apb_pclk); 823 if (ret) 824 return ret; 825 826 ret = clk_prepare_enable(rs->spiclk); 827 if (ret) 828 clk_disable_unprepare(rs->apb_pclk); 829 830 return ret; 831 } 832 #endif /* CONFIG_PM */ 833 834 static const struct dev_pm_ops rockchip_spi_pm = { 835 SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume) 836 SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend, 837 rockchip_spi_runtime_resume, NULL) 838 }; 839 840 static const struct of_device_id rockchip_spi_dt_match[] = { 841 { .compatible = "rockchip,rk3066-spi", }, 842 { .compatible = "rockchip,rk3188-spi", }, 843 { .compatible = "rockchip,rk3288-spi", }, 844 { }, 845 }; 846 MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match); 847 848 static struct platform_driver rockchip_spi_driver = { 849 .driver = { 850 .name = DRIVER_NAME, 851 .pm = &rockchip_spi_pm, 852 .of_match_table = of_match_ptr(rockchip_spi_dt_match), 853 }, 854 .probe = rockchip_spi_probe, 855 .remove = rockchip_spi_remove, 856 }; 857 858 module_platform_driver(rockchip_spi_driver); 859 860 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>"); 861 MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver"); 862 MODULE_LICENSE("GPL v2"); 863