1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd 4 * Author: Addy Ke <addy.ke@rock-chips.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/dmaengine.h> 9 #include <linux/interrupt.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/pinctrl/consumer.h> 13 #include <linux/platform_device.h> 14 #include <linux/spi/spi.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/scatterlist.h> 17 18 #define DRIVER_NAME "rockchip-spi" 19 20 #define ROCKCHIP_SPI_CLR_BITS(reg, bits) \ 21 writel_relaxed(readl_relaxed(reg) & ~(bits), reg) 22 #define ROCKCHIP_SPI_SET_BITS(reg, bits) \ 23 writel_relaxed(readl_relaxed(reg) | (bits), reg) 24 25 /* SPI register offsets */ 26 #define ROCKCHIP_SPI_CTRLR0 0x0000 27 #define ROCKCHIP_SPI_CTRLR1 0x0004 28 #define ROCKCHIP_SPI_SSIENR 0x0008 29 #define ROCKCHIP_SPI_SER 0x000c 30 #define ROCKCHIP_SPI_BAUDR 0x0010 31 #define ROCKCHIP_SPI_TXFTLR 0x0014 32 #define ROCKCHIP_SPI_RXFTLR 0x0018 33 #define ROCKCHIP_SPI_TXFLR 0x001c 34 #define ROCKCHIP_SPI_RXFLR 0x0020 35 #define ROCKCHIP_SPI_SR 0x0024 36 #define ROCKCHIP_SPI_IPR 0x0028 37 #define ROCKCHIP_SPI_IMR 0x002c 38 #define ROCKCHIP_SPI_ISR 0x0030 39 #define ROCKCHIP_SPI_RISR 0x0034 40 #define ROCKCHIP_SPI_ICR 0x0038 41 #define ROCKCHIP_SPI_DMACR 0x003c 42 #define ROCKCHIP_SPI_DMATDLR 0x0040 43 #define ROCKCHIP_SPI_DMARDLR 0x0044 44 #define ROCKCHIP_SPI_VERSION 0x0048 45 #define ROCKCHIP_SPI_TXDR 0x0400 46 #define ROCKCHIP_SPI_RXDR 0x0800 47 48 /* Bit fields in CTRLR0 */ 49 #define CR0_DFS_OFFSET 0 50 #define CR0_DFS_4BIT 0x0 51 #define CR0_DFS_8BIT 0x1 52 #define CR0_DFS_16BIT 0x2 53 54 #define CR0_CFS_OFFSET 2 55 56 #define CR0_SCPH_OFFSET 6 57 58 #define CR0_SCPOL_OFFSET 7 59 60 #define CR0_CSM_OFFSET 8 61 #define CR0_CSM_KEEP 0x0 62 /* ss_n be high for half sclk_out cycles */ 63 #define CR0_CSM_HALF 0X1 64 /* ss_n be high for one sclk_out cycle */ 65 #define CR0_CSM_ONE 0x2 66 67 /* ss_n to sclk_out delay */ 68 #define CR0_SSD_OFFSET 10 69 /* 70 * The period between ss_n active and 71 * sclk_out active is half sclk_out cycles 72 */ 73 #define CR0_SSD_HALF 0x0 74 /* 75 * The period between ss_n active and 76 * sclk_out active is one sclk_out cycle 77 */ 78 #define CR0_SSD_ONE 0x1 79 80 #define CR0_EM_OFFSET 11 81 #define CR0_EM_LITTLE 0x0 82 #define CR0_EM_BIG 0x1 83 84 #define CR0_FBM_OFFSET 12 85 #define CR0_FBM_MSB 0x0 86 #define CR0_FBM_LSB 0x1 87 88 #define CR0_BHT_OFFSET 13 89 #define CR0_BHT_16BIT 0x0 90 #define CR0_BHT_8BIT 0x1 91 92 #define CR0_RSD_OFFSET 14 93 #define CR0_RSD_MAX 0x3 94 95 #define CR0_FRF_OFFSET 16 96 #define CR0_FRF_SPI 0x0 97 #define CR0_FRF_SSP 0x1 98 #define CR0_FRF_MICROWIRE 0x2 99 100 #define CR0_XFM_OFFSET 18 101 #define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET) 102 #define CR0_XFM_TR 0x0 103 #define CR0_XFM_TO 0x1 104 #define CR0_XFM_RO 0x2 105 106 #define CR0_OPM_OFFSET 20 107 #define CR0_OPM_HOST 0x0 108 #define CR0_OPM_TARGET 0x1 109 110 #define CR0_SOI_OFFSET 23 111 112 #define CR0_MTM_OFFSET 0x21 113 114 /* Bit fields in SER, 2bit */ 115 #define SER_MASK 0x3 116 117 /* Bit fields in BAUDR */ 118 #define BAUDR_SCKDV_MIN 2 119 #define BAUDR_SCKDV_MAX 65534 120 121 /* Bit fields in SR, 6bit */ 122 #define SR_MASK 0x3f 123 #define SR_BUSY (1 << 0) 124 #define SR_TF_FULL (1 << 1) 125 #define SR_TF_EMPTY (1 << 2) 126 #define SR_RF_EMPTY (1 << 3) 127 #define SR_RF_FULL (1 << 4) 128 #define SR_TARGET_TX_BUSY (1 << 5) 129 130 /* Bit fields in ISR, IMR, ISR, RISR, 5bit */ 131 #define INT_MASK 0x1f 132 #define INT_TF_EMPTY (1 << 0) 133 #define INT_TF_OVERFLOW (1 << 1) 134 #define INT_RF_UNDERFLOW (1 << 2) 135 #define INT_RF_OVERFLOW (1 << 3) 136 #define INT_RF_FULL (1 << 4) 137 #define INT_CS_INACTIVE (1 << 6) 138 139 /* Bit fields in ICR, 4bit */ 140 #define ICR_MASK 0x0f 141 #define ICR_ALL (1 << 0) 142 #define ICR_RF_UNDERFLOW (1 << 1) 143 #define ICR_RF_OVERFLOW (1 << 2) 144 #define ICR_TF_OVERFLOW (1 << 3) 145 146 /* Bit fields in DMACR */ 147 #define RF_DMA_EN (1 << 0) 148 #define TF_DMA_EN (1 << 1) 149 150 /* Driver state flags */ 151 #define RXDMA (1 << 0) 152 #define TXDMA (1 << 1) 153 154 /* sclk_out: spi host internal logic in rk3x can support 50Mhz */ 155 #define MAX_SCLK_OUT 50000000U 156 157 /* 158 * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However, 159 * the controller seems to hang when given 0x10000, so stick with this for now. 160 */ 161 #define ROCKCHIP_SPI_MAX_TRANLEN 0xffff 162 163 /* 2 for native cs, 2 for cs-gpio */ 164 #define ROCKCHIP_SPI_MAX_CS_NUM 4 165 #define ROCKCHIP_SPI_VER2_TYPE1 0x05EC0002 166 #define ROCKCHIP_SPI_VER2_TYPE2 0x00110002 167 168 #define ROCKCHIP_AUTOSUSPEND_TIMEOUT 2000 169 170 struct rockchip_spi { 171 struct device *dev; 172 173 struct clk *spiclk; 174 struct clk *apb_pclk; 175 176 void __iomem *regs; 177 dma_addr_t dma_addr_rx; 178 dma_addr_t dma_addr_tx; 179 180 const void *tx; 181 void *rx; 182 unsigned int tx_left; 183 unsigned int rx_left; 184 185 atomic_t state; 186 187 /*depth of the FIFO buffer */ 188 u32 fifo_len; 189 /* frequency of spiclk */ 190 u32 freq; 191 192 u8 n_bytes; 193 u8 rsd; 194 195 bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM]; 196 197 bool target_abort; 198 bool cs_inactive; /* spi target tansmition stop when cs inactive */ 199 bool cs_high_supported; /* native CS supports active-high polarity */ 200 201 struct spi_transfer *xfer; /* Store xfer temporarily */ 202 }; 203 204 static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable) 205 { 206 writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR); 207 } 208 209 static inline void wait_for_tx_idle(struct rockchip_spi *rs, bool target_mode) 210 { 211 unsigned long timeout = jiffies + msecs_to_jiffies(5); 212 213 do { 214 if (target_mode) { 215 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_TARGET_TX_BUSY) && 216 !((readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))) 217 return; 218 } else { 219 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)) 220 return; 221 } 222 } while (!time_after(jiffies, timeout)); 223 224 dev_warn(rs->dev, "spi controller is in busy state!\n"); 225 } 226 227 static u32 get_fifo_len(struct rockchip_spi *rs) 228 { 229 u32 ver; 230 231 ver = readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION); 232 233 switch (ver) { 234 case ROCKCHIP_SPI_VER2_TYPE1: 235 case ROCKCHIP_SPI_VER2_TYPE2: 236 return 64; 237 default: 238 return 32; 239 } 240 } 241 242 static void rockchip_spi_set_cs(struct spi_device *spi, bool enable) 243 { 244 struct spi_controller *ctlr = spi->controller; 245 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 246 bool cs_asserted = spi->mode & SPI_CS_HIGH ? enable : !enable; 247 248 /* Return immediately for no-op */ 249 if (cs_asserted == rs->cs_asserted[spi_get_chipselect(spi, 0)]) 250 return; 251 252 if (cs_asserted) { 253 /* Keep things powered as long as CS is asserted */ 254 pm_runtime_get_sync(rs->dev); 255 256 if (spi_get_csgpiod(spi, 0)) 257 ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, 1); 258 else 259 ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, 260 BIT(spi_get_chipselect(spi, 0))); 261 } else { 262 if (spi_get_csgpiod(spi, 0)) 263 ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, 1); 264 else 265 ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, 266 BIT(spi_get_chipselect(spi, 0))); 267 268 /* Drop reference from when we first asserted CS */ 269 pm_runtime_put(rs->dev); 270 } 271 272 rs->cs_asserted[spi_get_chipselect(spi, 0)] = cs_asserted; 273 } 274 275 static void rockchip_spi_handle_err(struct spi_controller *ctlr, 276 struct spi_message *msg) 277 { 278 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 279 280 /* stop running spi transfer 281 * this also flushes both rx and tx fifos 282 */ 283 spi_enable_chip(rs, false); 284 285 /* make sure all interrupts are masked and status cleared */ 286 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR); 287 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR); 288 289 if (atomic_read(&rs->state) & TXDMA) 290 dmaengine_terminate_async(ctlr->dma_tx); 291 292 if (atomic_read(&rs->state) & RXDMA) 293 dmaengine_terminate_async(ctlr->dma_rx); 294 } 295 296 static void rockchip_spi_pio_writer(struct rockchip_spi *rs) 297 { 298 u32 tx_free = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR); 299 u32 words = min(rs->tx_left, tx_free); 300 301 rs->tx_left -= words; 302 for (; words; words--) { 303 u32 txw; 304 305 if (rs->n_bytes == 1) 306 txw = *(u8 *)rs->tx; 307 else 308 txw = *(u16 *)rs->tx; 309 310 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR); 311 rs->tx += rs->n_bytes; 312 } 313 } 314 315 static void rockchip_spi_pio_reader(struct rockchip_spi *rs) 316 { 317 u32 words = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR); 318 u32 rx_left = (rs->rx_left > words) ? rs->rx_left - words : 0; 319 320 /* the hardware doesn't allow us to change fifo threshold 321 * level while spi is enabled, so instead make sure to leave 322 * enough words in the rx fifo to get the last interrupt 323 * exactly when all words have been received 324 */ 325 if (rx_left) { 326 u32 ftl = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFTLR) + 1; 327 328 if (rx_left < ftl) { 329 rx_left = ftl; 330 words = rs->rx_left - rx_left; 331 } 332 } 333 334 rs->rx_left = rx_left; 335 for (; words; words--) { 336 u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR); 337 338 if (!rs->rx) 339 continue; 340 341 if (rs->n_bytes == 1) 342 *(u8 *)rs->rx = (u8)rxw; 343 else 344 *(u16 *)rs->rx = (u16)rxw; 345 rs->rx += rs->n_bytes; 346 } 347 } 348 349 static irqreturn_t rockchip_spi_isr(int irq, void *dev_id) 350 { 351 struct spi_controller *ctlr = dev_id; 352 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 353 354 /* When int_cs_inactive comes, spi target abort */ 355 if (rs->cs_inactive && readl_relaxed(rs->regs + ROCKCHIP_SPI_IMR) & INT_CS_INACTIVE) { 356 ctlr->target_abort(ctlr); 357 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR); 358 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR); 359 360 return IRQ_HANDLED; 361 } 362 363 if (rs->tx_left) 364 rockchip_spi_pio_writer(rs); 365 366 rockchip_spi_pio_reader(rs); 367 if (!rs->rx_left) { 368 spi_enable_chip(rs, false); 369 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR); 370 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR); 371 spi_finalize_current_transfer(ctlr); 372 } 373 374 return IRQ_HANDLED; 375 } 376 377 static int rockchip_spi_prepare_irq(struct rockchip_spi *rs, 378 struct spi_controller *ctlr, 379 struct spi_transfer *xfer) 380 { 381 rs->tx = xfer->tx_buf; 382 rs->rx = xfer->rx_buf; 383 rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0; 384 rs->rx_left = xfer->len / rs->n_bytes; 385 386 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR); 387 388 spi_enable_chip(rs, true); 389 390 if (rs->tx_left) 391 rockchip_spi_pio_writer(rs); 392 393 if (rs->cs_inactive) 394 writel_relaxed(INT_RF_FULL | INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR); 395 else 396 writel_relaxed(INT_RF_FULL, rs->regs + ROCKCHIP_SPI_IMR); 397 398 /* 1 means the transfer is in progress */ 399 return 1; 400 } 401 402 static void rockchip_spi_dma_rxcb(void *data) 403 { 404 struct spi_controller *ctlr = data; 405 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 406 int state = atomic_fetch_andnot(RXDMA, &rs->state); 407 408 if (state & TXDMA && !rs->target_abort) 409 return; 410 411 if (rs->cs_inactive) 412 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR); 413 414 spi_enable_chip(rs, false); 415 spi_finalize_current_transfer(ctlr); 416 } 417 418 static void rockchip_spi_dma_txcb(void *data) 419 { 420 struct spi_controller *ctlr = data; 421 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 422 int state = atomic_fetch_andnot(TXDMA, &rs->state); 423 424 if (state & RXDMA && !rs->target_abort) 425 return; 426 427 /* Wait until the FIFO data completely. */ 428 wait_for_tx_idle(rs, ctlr->target); 429 430 spi_enable_chip(rs, false); 431 spi_finalize_current_transfer(ctlr); 432 } 433 434 static u32 rockchip_spi_calc_burst_size(u32 data_len) 435 { 436 u32 i; 437 438 /* burst size: 1, 2, 4, 8 */ 439 for (i = 1; i < 8; i <<= 1) { 440 if (data_len & i) 441 break; 442 } 443 444 return i; 445 } 446 447 static int rockchip_spi_prepare_dma(struct rockchip_spi *rs, 448 struct spi_controller *ctlr, struct spi_transfer *xfer) 449 { 450 struct dma_async_tx_descriptor *rxdesc, *txdesc; 451 452 atomic_set(&rs->state, 0); 453 454 rs->tx = xfer->tx_buf; 455 rs->rx = xfer->rx_buf; 456 457 rxdesc = NULL; 458 if (xfer->rx_buf) { 459 struct dma_slave_config rxconf = { 460 .direction = DMA_DEV_TO_MEM, 461 .src_addr = rs->dma_addr_rx, 462 .src_addr_width = rs->n_bytes, 463 .src_maxburst = rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes), 464 }; 465 466 dmaengine_slave_config(ctlr->dma_rx, &rxconf); 467 468 rxdesc = dmaengine_prep_slave_sg( 469 ctlr->dma_rx, 470 xfer->rx_sg.sgl, xfer->rx_sg.nents, 471 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 472 if (!rxdesc) 473 return -EINVAL; 474 475 rxdesc->callback = rockchip_spi_dma_rxcb; 476 rxdesc->callback_param = ctlr; 477 } 478 479 txdesc = NULL; 480 if (xfer->tx_buf) { 481 struct dma_slave_config txconf = { 482 .direction = DMA_MEM_TO_DEV, 483 .dst_addr = rs->dma_addr_tx, 484 .dst_addr_width = rs->n_bytes, 485 .dst_maxburst = rs->fifo_len / 4, 486 }; 487 488 dmaengine_slave_config(ctlr->dma_tx, &txconf); 489 490 txdesc = dmaengine_prep_slave_sg( 491 ctlr->dma_tx, 492 xfer->tx_sg.sgl, xfer->tx_sg.nents, 493 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 494 if (!txdesc) { 495 if (rxdesc) 496 dmaengine_terminate_sync(ctlr->dma_rx); 497 return -EINVAL; 498 } 499 500 txdesc->callback = rockchip_spi_dma_txcb; 501 txdesc->callback_param = ctlr; 502 } 503 504 /* rx must be started before tx due to spi instinct */ 505 if (rxdesc) { 506 atomic_or(RXDMA, &rs->state); 507 ctlr->dma_rx->cookie = dmaengine_submit(rxdesc); 508 dma_async_issue_pending(ctlr->dma_rx); 509 } 510 511 if (rs->cs_inactive) 512 writel_relaxed(INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR); 513 514 spi_enable_chip(rs, true); 515 516 if (txdesc) { 517 atomic_or(TXDMA, &rs->state); 518 dmaengine_submit(txdesc); 519 dma_async_issue_pending(ctlr->dma_tx); 520 } 521 522 /* 1 means the transfer is in progress */ 523 return 1; 524 } 525 526 static int rockchip_spi_config(struct rockchip_spi *rs, 527 struct spi_device *spi, struct spi_transfer *xfer, 528 bool use_dma, bool target_mode) 529 { 530 u32 cr0 = CR0_FRF_SPI << CR0_FRF_OFFSET 531 | CR0_BHT_8BIT << CR0_BHT_OFFSET 532 | CR0_SSD_ONE << CR0_SSD_OFFSET 533 | CR0_EM_BIG << CR0_EM_OFFSET; 534 u32 cr1; 535 u32 dmacr = 0; 536 537 if (target_mode) 538 cr0 |= CR0_OPM_TARGET << CR0_OPM_OFFSET; 539 rs->target_abort = false; 540 541 cr0 |= rs->rsd << CR0_RSD_OFFSET; 542 cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET; 543 if (spi->mode & SPI_LSB_FIRST) 544 cr0 |= CR0_FBM_LSB << CR0_FBM_OFFSET; 545 if (spi->mode & SPI_CS_HIGH) 546 cr0 |= BIT(spi_get_chipselect(spi, 0)) << CR0_SOI_OFFSET; 547 548 if (xfer->rx_buf && xfer->tx_buf) 549 cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET; 550 else if (xfer->rx_buf) 551 cr0 |= CR0_XFM_RO << CR0_XFM_OFFSET; 552 else if (use_dma) 553 cr0 |= CR0_XFM_TO << CR0_XFM_OFFSET; 554 555 switch (xfer->bits_per_word) { 556 case 4: 557 cr0 |= CR0_DFS_4BIT << CR0_DFS_OFFSET; 558 cr1 = xfer->len - 1; 559 break; 560 case 8: 561 cr0 |= CR0_DFS_8BIT << CR0_DFS_OFFSET; 562 cr1 = xfer->len - 1; 563 break; 564 case 16: 565 cr0 |= CR0_DFS_16BIT << CR0_DFS_OFFSET; 566 cr1 = xfer->len / 2 - 1; 567 break; 568 default: 569 /* we only whitelist 4, 8 and 16 bit words in 570 * ctlr->bits_per_word_mask, so this shouldn't 571 * happen 572 */ 573 dev_err(rs->dev, "unknown bits per word: %d\n", 574 xfer->bits_per_word); 575 return -EINVAL; 576 } 577 578 if (use_dma) { 579 if (xfer->tx_buf) 580 dmacr |= TF_DMA_EN; 581 if (xfer->rx_buf) 582 dmacr |= RF_DMA_EN; 583 } 584 585 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0); 586 writel_relaxed(cr1, rs->regs + ROCKCHIP_SPI_CTRLR1); 587 588 /* unfortunately setting the fifo threshold level to generate an 589 * interrupt exactly when the fifo is full doesn't seem to work, 590 * so we need the strict inequality here 591 */ 592 if ((xfer->len / rs->n_bytes) < rs->fifo_len) 593 writel_relaxed(xfer->len / rs->n_bytes - 1, rs->regs + ROCKCHIP_SPI_RXFTLR); 594 else 595 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR); 596 597 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_DMATDLR); 598 writel_relaxed(rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes) - 1, 599 rs->regs + ROCKCHIP_SPI_DMARDLR); 600 writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR); 601 602 /* the hardware only supports an even clock divisor, so 603 * round divisor = spiclk / speed up to nearest even number 604 * so that the resulting speed is <= the requested speed 605 */ 606 writel_relaxed(2 * DIV_ROUND_UP(rs->freq, 2 * xfer->speed_hz), 607 rs->regs + ROCKCHIP_SPI_BAUDR); 608 609 return 0; 610 } 611 612 static size_t rockchip_spi_max_transfer_size(struct spi_device *spi) 613 { 614 return ROCKCHIP_SPI_MAX_TRANLEN; 615 } 616 617 static int rockchip_spi_target_abort(struct spi_controller *ctlr) 618 { 619 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 620 u32 rx_fifo_left; 621 struct dma_tx_state state; 622 enum dma_status status; 623 624 /* Get current dma rx point */ 625 if (atomic_read(&rs->state) & RXDMA) { 626 dmaengine_pause(ctlr->dma_rx); 627 status = dmaengine_tx_status(ctlr->dma_rx, ctlr->dma_rx->cookie, &state); 628 if (status == DMA_ERROR) { 629 rs->rx = rs->xfer->rx_buf; 630 rs->xfer->len = 0; 631 rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR); 632 for (; rx_fifo_left; rx_fifo_left--) 633 readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR); 634 goto out; 635 } else { 636 rs->rx += rs->xfer->len - rs->n_bytes * state.residue; 637 } 638 } 639 640 /* Get the valid data left in rx fifo and set rs->xfer->len real rx size */ 641 if (rs->rx) { 642 rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR); 643 for (; rx_fifo_left; rx_fifo_left--) { 644 u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR); 645 646 if (rs->n_bytes == 1) 647 *(u8 *)rs->rx = (u8)rxw; 648 else 649 *(u16 *)rs->rx = (u16)rxw; 650 rs->rx += rs->n_bytes; 651 } 652 rs->xfer->len = (unsigned int)(rs->rx - rs->xfer->rx_buf); 653 } 654 655 out: 656 if (atomic_read(&rs->state) & RXDMA) 657 dmaengine_terminate_sync(ctlr->dma_rx); 658 if (atomic_read(&rs->state) & TXDMA) 659 dmaengine_terminate_sync(ctlr->dma_tx); 660 atomic_set(&rs->state, 0); 661 spi_enable_chip(rs, false); 662 rs->target_abort = true; 663 spi_finalize_current_transfer(ctlr); 664 665 return 0; 666 } 667 668 static int rockchip_spi_transfer_one( 669 struct spi_controller *ctlr, 670 struct spi_device *spi, 671 struct spi_transfer *xfer) 672 { 673 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 674 int ret; 675 bool use_dma; 676 677 /* Zero length transfers won't trigger an interrupt on completion */ 678 if (!xfer->len) { 679 spi_finalize_current_transfer(ctlr); 680 return 1; 681 } 682 683 WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) && 684 (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)); 685 686 if (!xfer->tx_buf && !xfer->rx_buf) { 687 dev_err(rs->dev, "No buffer for transfer\n"); 688 return -EINVAL; 689 } 690 691 if (xfer->len > ROCKCHIP_SPI_MAX_TRANLEN) { 692 dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len); 693 return -EINVAL; 694 } 695 696 rs->n_bytes = xfer->bits_per_word <= 8 ? 1 : 2; 697 rs->xfer = xfer; 698 use_dma = ctlr->can_dma ? ctlr->can_dma(ctlr, spi, xfer) : false; 699 700 ret = rockchip_spi_config(rs, spi, xfer, use_dma, ctlr->target); 701 if (ret) 702 return ret; 703 704 if (use_dma) 705 return rockchip_spi_prepare_dma(rs, ctlr, xfer); 706 707 return rockchip_spi_prepare_irq(rs, ctlr, xfer); 708 } 709 710 static bool rockchip_spi_can_dma(struct spi_controller *ctlr, 711 struct spi_device *spi, 712 struct spi_transfer *xfer) 713 { 714 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 715 unsigned int bytes_per_word = xfer->bits_per_word <= 8 ? 1 : 2; 716 717 /* if the numbor of spi words to transfer is less than the fifo 718 * length we can just fill the fifo and wait for a single irq, 719 * so don't bother setting up dma 720 */ 721 return xfer->len / bytes_per_word >= rs->fifo_len; 722 } 723 724 static int rockchip_spi_setup(struct spi_device *spi) 725 { 726 struct rockchip_spi *rs = spi_controller_get_devdata(spi->controller); 727 u32 cr0; 728 729 if (!spi_get_csgpiod(spi, 0) && (spi->mode & SPI_CS_HIGH) && !rs->cs_high_supported) { 730 dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n"); 731 return -EINVAL; 732 } 733 734 pm_runtime_get_sync(rs->dev); 735 736 cr0 = readl_relaxed(rs->regs + ROCKCHIP_SPI_CTRLR0); 737 738 cr0 &= ~(0x3 << CR0_SCPH_OFFSET); 739 cr0 |= ((spi->mode & 0x3) << CR0_SCPH_OFFSET); 740 if (spi->mode & SPI_CS_HIGH && spi_get_chipselect(spi, 0) <= 1) 741 cr0 |= BIT(spi_get_chipselect(spi, 0)) << CR0_SOI_OFFSET; 742 else if (spi_get_chipselect(spi, 0) <= 1) 743 cr0 &= ~(BIT(spi_get_chipselect(spi, 0)) << CR0_SOI_OFFSET); 744 745 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0); 746 747 pm_runtime_put(rs->dev); 748 749 return 0; 750 } 751 752 static int rockchip_spi_probe(struct platform_device *pdev) 753 { 754 int ret; 755 struct rockchip_spi *rs; 756 struct spi_controller *ctlr; 757 struct resource *mem; 758 struct device_node *np = pdev->dev.of_node; 759 u32 rsd_nsecs, num_cs; 760 bool target_mode; 761 762 target_mode = of_property_read_bool(np, "spi-slave"); 763 764 if (target_mode) 765 ctlr = spi_alloc_target(&pdev->dev, 766 sizeof(struct rockchip_spi)); 767 else 768 ctlr = spi_alloc_host(&pdev->dev, 769 sizeof(struct rockchip_spi)); 770 771 if (!ctlr) 772 return -ENOMEM; 773 774 platform_set_drvdata(pdev, ctlr); 775 776 rs = spi_controller_get_devdata(ctlr); 777 778 /* Get basic io resource and map it */ 779 rs->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); 780 if (IS_ERR(rs->regs)) { 781 ret = PTR_ERR(rs->regs); 782 goto err_put_ctlr; 783 } 784 785 rs->apb_pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk"); 786 if (IS_ERR(rs->apb_pclk)) { 787 dev_err(&pdev->dev, "Failed to get apb_pclk\n"); 788 ret = PTR_ERR(rs->apb_pclk); 789 goto err_put_ctlr; 790 } 791 792 rs->spiclk = devm_clk_get_enabled(&pdev->dev, "spiclk"); 793 if (IS_ERR(rs->spiclk)) { 794 dev_err(&pdev->dev, "Failed to get spi_pclk\n"); 795 ret = PTR_ERR(rs->spiclk); 796 goto err_put_ctlr; 797 } 798 799 spi_enable_chip(rs, false); 800 801 ret = platform_get_irq(pdev, 0); 802 if (ret < 0) 803 goto err_put_ctlr; 804 805 ret = devm_request_threaded_irq(&pdev->dev, ret, rockchip_spi_isr, NULL, 806 IRQF_ONESHOT, dev_name(&pdev->dev), ctlr); 807 if (ret) 808 goto err_put_ctlr; 809 810 rs->dev = &pdev->dev; 811 rs->freq = clk_get_rate(rs->spiclk); 812 813 if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns", 814 &rsd_nsecs)) { 815 /* rx sample delay is expressed in parent clock cycles (max 3) */ 816 u32 rsd = DIV_ROUND_CLOSEST(rsd_nsecs * (rs->freq >> 8), 817 1000000000 >> 8); 818 if (!rsd) { 819 dev_warn(rs->dev, "%u Hz are too slow to express %u ns delay\n", 820 rs->freq, rsd_nsecs); 821 } else if (rsd > CR0_RSD_MAX) { 822 rsd = CR0_RSD_MAX; 823 dev_warn(rs->dev, "%u Hz are too fast to express %u ns delay, clamping at %u ns\n", 824 rs->freq, rsd_nsecs, 825 CR0_RSD_MAX * 1000000000U / rs->freq); 826 } 827 rs->rsd = rsd; 828 } 829 830 rs->fifo_len = get_fifo_len(rs); 831 if (!rs->fifo_len) { 832 dev_err(&pdev->dev, "Failed to get fifo length\n"); 833 ret = -EINVAL; 834 goto err_put_ctlr; 835 } 836 837 pm_runtime_set_autosuspend_delay(&pdev->dev, ROCKCHIP_AUTOSUSPEND_TIMEOUT); 838 pm_runtime_use_autosuspend(&pdev->dev); 839 pm_runtime_set_active(&pdev->dev); 840 pm_runtime_enable(&pdev->dev); 841 842 ctlr->auto_runtime_pm = true; 843 ctlr->bus_num = pdev->id; 844 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST; 845 if (target_mode) { 846 ctlr->mode_bits |= SPI_NO_CS; 847 ctlr->target_abort = rockchip_spi_target_abort; 848 } else { 849 ctlr->flags = SPI_CONTROLLER_GPIO_SS; 850 ctlr->max_native_cs = ROCKCHIP_SPI_MAX_CS_NUM; 851 /* 852 * rk spi0 has two native cs, spi1..5 one cs only 853 * if num-cs is missing in the dts, default to 1 854 */ 855 if (of_property_read_u32(np, "num-cs", &num_cs)) 856 num_cs = 1; 857 ctlr->num_chipselect = num_cs; 858 ctlr->use_gpio_descriptors = true; 859 } 860 ctlr->dev.of_node = pdev->dev.of_node; 861 ctlr->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8) | SPI_BPW_MASK(4); 862 ctlr->min_speed_hz = rs->freq / BAUDR_SCKDV_MAX; 863 ctlr->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT); 864 865 ctlr->setup = rockchip_spi_setup; 866 ctlr->set_cs = rockchip_spi_set_cs; 867 ctlr->transfer_one = rockchip_spi_transfer_one; 868 ctlr->max_transfer_size = rockchip_spi_max_transfer_size; 869 ctlr->handle_err = rockchip_spi_handle_err; 870 871 ctlr->dma_tx = dma_request_chan(rs->dev, "tx"); 872 if (IS_ERR(ctlr->dma_tx)) { 873 /* Check tx to see if we need defer probing driver */ 874 if (PTR_ERR(ctlr->dma_tx) == -EPROBE_DEFER) { 875 ret = -EPROBE_DEFER; 876 goto err_disable_pm_runtime; 877 } 878 dev_warn(rs->dev, "Failed to request TX DMA channel\n"); 879 ctlr->dma_tx = NULL; 880 } 881 882 ctlr->dma_rx = dma_request_chan(rs->dev, "rx"); 883 if (IS_ERR(ctlr->dma_rx)) { 884 if (PTR_ERR(ctlr->dma_rx) == -EPROBE_DEFER) { 885 ret = -EPROBE_DEFER; 886 goto err_free_dma_tx; 887 } 888 dev_warn(rs->dev, "Failed to request RX DMA channel\n"); 889 ctlr->dma_rx = NULL; 890 } 891 892 if (ctlr->dma_tx && ctlr->dma_rx) { 893 rs->dma_addr_tx = mem->start + ROCKCHIP_SPI_TXDR; 894 rs->dma_addr_rx = mem->start + ROCKCHIP_SPI_RXDR; 895 ctlr->can_dma = rockchip_spi_can_dma; 896 } 897 898 switch (readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION)) { 899 case ROCKCHIP_SPI_VER2_TYPE2: 900 rs->cs_high_supported = true; 901 ctlr->mode_bits |= SPI_CS_HIGH; 902 if (ctlr->can_dma && target_mode) 903 rs->cs_inactive = true; 904 else 905 rs->cs_inactive = false; 906 break; 907 default: 908 rs->cs_inactive = false; 909 break; 910 } 911 912 ret = devm_spi_register_controller(&pdev->dev, ctlr); 913 if (ret < 0) { 914 dev_err(&pdev->dev, "Failed to register controller\n"); 915 goto err_free_dma_rx; 916 } 917 918 return 0; 919 920 err_free_dma_rx: 921 if (ctlr->dma_rx) 922 dma_release_channel(ctlr->dma_rx); 923 err_free_dma_tx: 924 if (ctlr->dma_tx) 925 dma_release_channel(ctlr->dma_tx); 926 err_disable_pm_runtime: 927 pm_runtime_disable(&pdev->dev); 928 err_put_ctlr: 929 spi_controller_put(ctlr); 930 931 return ret; 932 } 933 934 static void rockchip_spi_remove(struct platform_device *pdev) 935 { 936 struct spi_controller *ctlr = spi_controller_get(platform_get_drvdata(pdev)); 937 938 pm_runtime_get_sync(&pdev->dev); 939 940 pm_runtime_put_noidle(&pdev->dev); 941 pm_runtime_disable(&pdev->dev); 942 pm_runtime_set_suspended(&pdev->dev); 943 944 if (ctlr->dma_tx) 945 dma_release_channel(ctlr->dma_tx); 946 if (ctlr->dma_rx) 947 dma_release_channel(ctlr->dma_rx); 948 949 spi_controller_put(ctlr); 950 } 951 952 #ifdef CONFIG_PM_SLEEP 953 static int rockchip_spi_suspend(struct device *dev) 954 { 955 int ret; 956 struct spi_controller *ctlr = dev_get_drvdata(dev); 957 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 958 959 ret = spi_controller_suspend(ctlr); 960 if (ret < 0) 961 return ret; 962 963 clk_disable_unprepare(rs->spiclk); 964 clk_disable_unprepare(rs->apb_pclk); 965 966 pinctrl_pm_select_sleep_state(dev); 967 968 return 0; 969 } 970 971 static int rockchip_spi_resume(struct device *dev) 972 { 973 int ret; 974 struct spi_controller *ctlr = dev_get_drvdata(dev); 975 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 976 977 pinctrl_pm_select_default_state(dev); 978 979 ret = clk_prepare_enable(rs->apb_pclk); 980 if (ret < 0) 981 return ret; 982 983 ret = clk_prepare_enable(rs->spiclk); 984 if (ret < 0) 985 clk_disable_unprepare(rs->apb_pclk); 986 987 ret = spi_controller_resume(ctlr); 988 if (ret < 0) { 989 clk_disable_unprepare(rs->spiclk); 990 clk_disable_unprepare(rs->apb_pclk); 991 } 992 993 return 0; 994 } 995 #endif /* CONFIG_PM_SLEEP */ 996 997 #ifdef CONFIG_PM 998 static int rockchip_spi_runtime_suspend(struct device *dev) 999 { 1000 struct spi_controller *ctlr = dev_get_drvdata(dev); 1001 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 1002 1003 clk_disable_unprepare(rs->spiclk); 1004 clk_disable_unprepare(rs->apb_pclk); 1005 1006 return 0; 1007 } 1008 1009 static int rockchip_spi_runtime_resume(struct device *dev) 1010 { 1011 int ret; 1012 struct spi_controller *ctlr = dev_get_drvdata(dev); 1013 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 1014 1015 ret = clk_prepare_enable(rs->apb_pclk); 1016 if (ret < 0) 1017 return ret; 1018 1019 ret = clk_prepare_enable(rs->spiclk); 1020 if (ret < 0) 1021 clk_disable_unprepare(rs->apb_pclk); 1022 1023 return 0; 1024 } 1025 #endif /* CONFIG_PM */ 1026 1027 static const struct dev_pm_ops rockchip_spi_pm = { 1028 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume) 1029 SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend, 1030 rockchip_spi_runtime_resume, NULL) 1031 }; 1032 1033 static const struct of_device_id rockchip_spi_dt_match[] = { 1034 { .compatible = "rockchip,px30-spi", }, 1035 { .compatible = "rockchip,rk3036-spi", }, 1036 { .compatible = "rockchip,rk3066-spi", }, 1037 { .compatible = "rockchip,rk3188-spi", }, 1038 { .compatible = "rockchip,rk3228-spi", }, 1039 { .compatible = "rockchip,rk3288-spi", }, 1040 { .compatible = "rockchip,rk3308-spi", }, 1041 { .compatible = "rockchip,rk3328-spi", }, 1042 { .compatible = "rockchip,rk3368-spi", }, 1043 { .compatible = "rockchip,rk3399-spi", }, 1044 { .compatible = "rockchip,rv1108-spi", }, 1045 { .compatible = "rockchip,rv1126-spi", }, 1046 { }, 1047 }; 1048 MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match); 1049 1050 static struct platform_driver rockchip_spi_driver = { 1051 .driver = { 1052 .name = DRIVER_NAME, 1053 .pm = &rockchip_spi_pm, 1054 .of_match_table = of_match_ptr(rockchip_spi_dt_match), 1055 }, 1056 .probe = rockchip_spi_probe, 1057 .remove_new = rockchip_spi_remove, 1058 }; 1059 1060 module_platform_driver(rockchip_spi_driver); 1061 1062 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>"); 1063 MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver"); 1064 MODULE_LICENSE("GPL v2"); 1065