1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd 4 * Author: Addy Ke <addy.ke@rock-chips.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/dmaengine.h> 9 #include <linux/interrupt.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/pinctrl/consumer.h> 13 #include <linux/platform_device.h> 14 #include <linux/spi/spi.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/scatterlist.h> 17 18 #define DRIVER_NAME "rockchip-spi" 19 20 #define ROCKCHIP_SPI_CLR_BITS(reg, bits) \ 21 writel_relaxed(readl_relaxed(reg) & ~(bits), reg) 22 #define ROCKCHIP_SPI_SET_BITS(reg, bits) \ 23 writel_relaxed(readl_relaxed(reg) | (bits), reg) 24 25 /* SPI register offsets */ 26 #define ROCKCHIP_SPI_CTRLR0 0x0000 27 #define ROCKCHIP_SPI_CTRLR1 0x0004 28 #define ROCKCHIP_SPI_SSIENR 0x0008 29 #define ROCKCHIP_SPI_SER 0x000c 30 #define ROCKCHIP_SPI_BAUDR 0x0010 31 #define ROCKCHIP_SPI_TXFTLR 0x0014 32 #define ROCKCHIP_SPI_RXFTLR 0x0018 33 #define ROCKCHIP_SPI_TXFLR 0x001c 34 #define ROCKCHIP_SPI_RXFLR 0x0020 35 #define ROCKCHIP_SPI_SR 0x0024 36 #define ROCKCHIP_SPI_IPR 0x0028 37 #define ROCKCHIP_SPI_IMR 0x002c 38 #define ROCKCHIP_SPI_ISR 0x0030 39 #define ROCKCHIP_SPI_RISR 0x0034 40 #define ROCKCHIP_SPI_ICR 0x0038 41 #define ROCKCHIP_SPI_DMACR 0x003c 42 #define ROCKCHIP_SPI_DMATDLR 0x0040 43 #define ROCKCHIP_SPI_DMARDLR 0x0044 44 #define ROCKCHIP_SPI_VERSION 0x0048 45 #define ROCKCHIP_SPI_TXDR 0x0400 46 #define ROCKCHIP_SPI_RXDR 0x0800 47 48 /* Bit fields in CTRLR0 */ 49 #define CR0_DFS_OFFSET 0 50 #define CR0_DFS_4BIT 0x0 51 #define CR0_DFS_8BIT 0x1 52 #define CR0_DFS_16BIT 0x2 53 54 #define CR0_CFS_OFFSET 2 55 56 #define CR0_SCPH_OFFSET 6 57 58 #define CR0_SCPOL_OFFSET 7 59 60 #define CR0_CSM_OFFSET 8 61 #define CR0_CSM_KEEP 0x0 62 /* ss_n be high for half sclk_out cycles */ 63 #define CR0_CSM_HALF 0X1 64 /* ss_n be high for one sclk_out cycle */ 65 #define CR0_CSM_ONE 0x2 66 67 /* ss_n to sclk_out delay */ 68 #define CR0_SSD_OFFSET 10 69 /* 70 * The period between ss_n active and 71 * sclk_out active is half sclk_out cycles 72 */ 73 #define CR0_SSD_HALF 0x0 74 /* 75 * The period between ss_n active and 76 * sclk_out active is one sclk_out cycle 77 */ 78 #define CR0_SSD_ONE 0x1 79 80 #define CR0_EM_OFFSET 11 81 #define CR0_EM_LITTLE 0x0 82 #define CR0_EM_BIG 0x1 83 84 #define CR0_FBM_OFFSET 12 85 #define CR0_FBM_MSB 0x0 86 #define CR0_FBM_LSB 0x1 87 88 #define CR0_BHT_OFFSET 13 89 #define CR0_BHT_16BIT 0x0 90 #define CR0_BHT_8BIT 0x1 91 92 #define CR0_RSD_OFFSET 14 93 #define CR0_RSD_MAX 0x3 94 95 #define CR0_FRF_OFFSET 16 96 #define CR0_FRF_SPI 0x0 97 #define CR0_FRF_SSP 0x1 98 #define CR0_FRF_MICROWIRE 0x2 99 100 #define CR0_XFM_OFFSET 18 101 #define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET) 102 #define CR0_XFM_TR 0x0 103 #define CR0_XFM_TO 0x1 104 #define CR0_XFM_RO 0x2 105 106 #define CR0_OPM_OFFSET 20 107 #define CR0_OPM_HOST 0x0 108 #define CR0_OPM_TARGET 0x1 109 110 #define CR0_SOI_OFFSET 23 111 112 #define CR0_MTM_OFFSET 0x21 113 114 /* Bit fields in SER, 2bit */ 115 #define SER_MASK 0x3 116 117 /* Bit fields in BAUDR */ 118 #define BAUDR_SCKDV_MIN 2 119 #define BAUDR_SCKDV_MAX 65534 120 121 /* Bit fields in SR, 6bit */ 122 #define SR_MASK 0x3f 123 #define SR_BUSY (1 << 0) 124 #define SR_TF_FULL (1 << 1) 125 #define SR_TF_EMPTY (1 << 2) 126 #define SR_RF_EMPTY (1 << 3) 127 #define SR_RF_FULL (1 << 4) 128 #define SR_TARGET_TX_BUSY (1 << 5) 129 130 /* Bit fields in ISR, IMR, ISR, RISR, 5bit */ 131 #define INT_MASK 0x1f 132 #define INT_TF_EMPTY (1 << 0) 133 #define INT_TF_OVERFLOW (1 << 1) 134 #define INT_RF_UNDERFLOW (1 << 2) 135 #define INT_RF_OVERFLOW (1 << 3) 136 #define INT_RF_FULL (1 << 4) 137 #define INT_CS_INACTIVE (1 << 6) 138 139 /* Bit fields in ICR, 4bit */ 140 #define ICR_MASK 0x0f 141 #define ICR_ALL (1 << 0) 142 #define ICR_RF_UNDERFLOW (1 << 1) 143 #define ICR_RF_OVERFLOW (1 << 2) 144 #define ICR_TF_OVERFLOW (1 << 3) 145 146 /* Bit fields in DMACR */ 147 #define RF_DMA_EN (1 << 0) 148 #define TF_DMA_EN (1 << 1) 149 150 /* Driver state flags */ 151 #define RXDMA (1 << 0) 152 #define TXDMA (1 << 1) 153 154 /* sclk_out: spi host internal logic in rk3x can support 50Mhz */ 155 #define MAX_SCLK_OUT 50000000U 156 157 /* 158 * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However, 159 * the controller seems to hang when given 0x10000, so stick with this for now. 160 */ 161 #define ROCKCHIP_SPI_MAX_TRANLEN 0xffff 162 163 #define ROCKCHIP_SPI_MAX_NATIVE_CS_NUM 2 164 #define ROCKCHIP_SPI_VER2_TYPE1 0x05EC0002 165 #define ROCKCHIP_SPI_VER2_TYPE2 0x00110002 166 167 #define ROCKCHIP_AUTOSUSPEND_TIMEOUT 2000 168 169 struct rockchip_spi { 170 struct device *dev; 171 172 struct clk *spiclk; 173 struct clk *apb_pclk; 174 175 void __iomem *regs; 176 dma_addr_t dma_addr_rx; 177 dma_addr_t dma_addr_tx; 178 179 const void *tx; 180 void *rx; 181 unsigned int tx_left; 182 unsigned int rx_left; 183 184 atomic_t state; 185 186 /*depth of the FIFO buffer */ 187 u32 fifo_len; 188 /* frequency of spiclk */ 189 u32 freq; 190 191 u8 n_bytes; 192 u8 rsd; 193 194 bool target_abort; 195 bool cs_inactive; /* spi target transmission stop when cs inactive */ 196 bool cs_high_supported; /* native CS supports active-high polarity */ 197 198 struct spi_transfer *xfer; /* Store xfer temporarily */ 199 }; 200 201 static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable) 202 { 203 writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR); 204 } 205 206 static inline void wait_for_tx_idle(struct rockchip_spi *rs, bool target_mode) 207 { 208 unsigned long timeout = jiffies + msecs_to_jiffies(5); 209 210 do { 211 if (target_mode) { 212 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_TARGET_TX_BUSY) && 213 !((readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))) 214 return; 215 } else { 216 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)) 217 return; 218 } 219 } while (!time_after(jiffies, timeout)); 220 221 dev_warn(rs->dev, "spi controller is in busy state!\n"); 222 } 223 224 static u32 get_fifo_len(struct rockchip_spi *rs) 225 { 226 u32 ver; 227 228 ver = readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION); 229 230 switch (ver) { 231 case ROCKCHIP_SPI_VER2_TYPE1: 232 case ROCKCHIP_SPI_VER2_TYPE2: 233 return 64; 234 default: 235 return 32; 236 } 237 } 238 239 static void rockchip_spi_set_cs(struct spi_device *spi, bool enable) 240 { 241 struct spi_controller *ctlr = spi->controller; 242 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 243 bool cs_asserted = spi->mode & SPI_CS_HIGH ? enable : !enable; 244 bool cs_actual; 245 246 /* 247 * SPI subsystem tries to avoid no-op calls that would break the PM 248 * refcount below. It can't however for the first time it is used. 249 * To detect this case we read it here and bail out early for no-ops. 250 */ 251 if (spi_get_csgpiod(spi, 0)) 252 cs_actual = !!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SER) & 1); 253 else 254 cs_actual = !!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SER) & 255 BIT(spi_get_chipselect(spi, 0))); 256 if (unlikely(cs_actual == cs_asserted)) 257 return; 258 259 if (cs_asserted) { 260 /* Keep things powered as long as CS is asserted */ 261 pm_runtime_get_sync(rs->dev); 262 263 if (spi_get_csgpiod(spi, 0)) 264 ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, 1); 265 else 266 ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, 267 BIT(spi_get_chipselect(spi, 0))); 268 } else { 269 if (spi_get_csgpiod(spi, 0)) 270 ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, 1); 271 else 272 ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, 273 BIT(spi_get_chipselect(spi, 0))); 274 275 /* Drop reference from when we first asserted CS */ 276 pm_runtime_put(rs->dev); 277 } 278 } 279 280 static void rockchip_spi_handle_err(struct spi_controller *ctlr, 281 struct spi_message *msg) 282 { 283 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 284 285 /* stop running spi transfer 286 * this also flushes both rx and tx fifos 287 */ 288 spi_enable_chip(rs, false); 289 290 /* make sure all interrupts are masked and status cleared */ 291 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR); 292 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR); 293 294 if (atomic_read(&rs->state) & TXDMA) 295 dmaengine_terminate_async(ctlr->dma_tx); 296 297 if (atomic_read(&rs->state) & RXDMA) 298 dmaengine_terminate_async(ctlr->dma_rx); 299 } 300 301 static void rockchip_spi_pio_writer(struct rockchip_spi *rs) 302 { 303 u32 tx_free = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR); 304 u32 words = min(rs->tx_left, tx_free); 305 306 rs->tx_left -= words; 307 for (; words; words--) { 308 u32 txw; 309 310 if (rs->n_bytes == 1) 311 txw = *(u8 *)rs->tx; 312 else 313 txw = *(u16 *)rs->tx; 314 315 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR); 316 rs->tx += rs->n_bytes; 317 } 318 } 319 320 static void rockchip_spi_pio_reader(struct rockchip_spi *rs) 321 { 322 u32 words = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR); 323 u32 rx_left = (rs->rx_left > words) ? rs->rx_left - words : 0; 324 325 /* the hardware doesn't allow us to change fifo threshold 326 * level while spi is enabled, so instead make sure to leave 327 * enough words in the rx fifo to get the last interrupt 328 * exactly when all words have been received 329 */ 330 if (rx_left) { 331 u32 ftl = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFTLR) + 1; 332 333 if (rx_left < ftl) { 334 rx_left = ftl; 335 words = rs->rx_left - rx_left; 336 } 337 } 338 339 rs->rx_left = rx_left; 340 for (; words; words--) { 341 u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR); 342 343 if (!rs->rx) 344 continue; 345 346 if (rs->n_bytes == 1) 347 *(u8 *)rs->rx = (u8)rxw; 348 else 349 *(u16 *)rs->rx = (u16)rxw; 350 rs->rx += rs->n_bytes; 351 } 352 } 353 354 static irqreturn_t rockchip_spi_isr(int irq, void *dev_id) 355 { 356 struct spi_controller *ctlr = dev_id; 357 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 358 359 /* When int_cs_inactive comes, spi target abort */ 360 if (rs->cs_inactive && readl_relaxed(rs->regs + ROCKCHIP_SPI_IMR) & INT_CS_INACTIVE) { 361 ctlr->target_abort(ctlr); 362 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR); 363 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR); 364 365 return IRQ_HANDLED; 366 } 367 368 if (rs->tx_left) 369 rockchip_spi_pio_writer(rs); 370 371 rockchip_spi_pio_reader(rs); 372 if (!rs->rx_left) { 373 spi_enable_chip(rs, false); 374 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR); 375 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR); 376 spi_finalize_current_transfer(ctlr); 377 } 378 379 return IRQ_HANDLED; 380 } 381 382 static int rockchip_spi_prepare_irq(struct rockchip_spi *rs, 383 struct spi_controller *ctlr, 384 struct spi_transfer *xfer) 385 { 386 rs->tx = xfer->tx_buf; 387 rs->rx = xfer->rx_buf; 388 rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0; 389 rs->rx_left = xfer->len / rs->n_bytes; 390 391 writel_relaxed(0xffffffff, rs->regs + ROCKCHIP_SPI_ICR); 392 393 spi_enable_chip(rs, true); 394 395 if (rs->tx_left) 396 rockchip_spi_pio_writer(rs); 397 398 if (rs->cs_inactive) 399 writel_relaxed(INT_RF_FULL | INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR); 400 else 401 writel_relaxed(INT_RF_FULL, rs->regs + ROCKCHIP_SPI_IMR); 402 403 /* 1 means the transfer is in progress */ 404 return 1; 405 } 406 407 static void rockchip_spi_dma_rxcb(void *data) 408 { 409 struct spi_controller *ctlr = data; 410 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 411 int state = atomic_fetch_andnot(RXDMA, &rs->state); 412 413 if (state & TXDMA && !rs->target_abort) 414 return; 415 416 if (rs->cs_inactive) 417 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR); 418 419 spi_enable_chip(rs, false); 420 spi_finalize_current_transfer(ctlr); 421 } 422 423 static void rockchip_spi_dma_txcb(void *data) 424 { 425 struct spi_controller *ctlr = data; 426 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 427 int state = atomic_fetch_andnot(TXDMA, &rs->state); 428 429 if (state & RXDMA && !rs->target_abort) 430 return; 431 432 /* Wait until the FIFO data completely. */ 433 wait_for_tx_idle(rs, ctlr->target); 434 435 spi_enable_chip(rs, false); 436 spi_finalize_current_transfer(ctlr); 437 } 438 439 static u32 rockchip_spi_calc_burst_size(u32 data_len) 440 { 441 u32 i; 442 443 /* burst size: 1, 2, 4, 8 */ 444 for (i = 1; i < 8; i <<= 1) { 445 if (data_len & i) 446 break; 447 } 448 449 return i; 450 } 451 452 static int rockchip_spi_prepare_dma(struct rockchip_spi *rs, 453 struct spi_controller *ctlr, struct spi_transfer *xfer) 454 { 455 struct dma_async_tx_descriptor *rxdesc, *txdesc; 456 457 atomic_set(&rs->state, 0); 458 459 rs->tx = xfer->tx_buf; 460 rs->rx = xfer->rx_buf; 461 462 rxdesc = NULL; 463 if (xfer->rx_buf) { 464 struct dma_slave_config rxconf = { 465 .direction = DMA_DEV_TO_MEM, 466 .src_addr = rs->dma_addr_rx, 467 .src_addr_width = rs->n_bytes, 468 .src_maxburst = rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes), 469 }; 470 471 dmaengine_slave_config(ctlr->dma_rx, &rxconf); 472 473 rxdesc = dmaengine_prep_slave_sg( 474 ctlr->dma_rx, 475 xfer->rx_sg.sgl, xfer->rx_sg.nents, 476 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 477 if (!rxdesc) 478 return -EINVAL; 479 480 rxdesc->callback = rockchip_spi_dma_rxcb; 481 rxdesc->callback_param = ctlr; 482 } 483 484 txdesc = NULL; 485 if (xfer->tx_buf) { 486 struct dma_slave_config txconf = { 487 .direction = DMA_MEM_TO_DEV, 488 .dst_addr = rs->dma_addr_tx, 489 .dst_addr_width = rs->n_bytes, 490 .dst_maxburst = rs->fifo_len / 4, 491 }; 492 493 dmaengine_slave_config(ctlr->dma_tx, &txconf); 494 495 txdesc = dmaengine_prep_slave_sg( 496 ctlr->dma_tx, 497 xfer->tx_sg.sgl, xfer->tx_sg.nents, 498 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 499 if (!txdesc) { 500 if (rxdesc) 501 dmaengine_terminate_sync(ctlr->dma_rx); 502 return -EINVAL; 503 } 504 505 txdesc->callback = rockchip_spi_dma_txcb; 506 txdesc->callback_param = ctlr; 507 } 508 509 /* rx must be started before tx due to spi instinct */ 510 if (rxdesc) { 511 atomic_or(RXDMA, &rs->state); 512 ctlr->dma_rx->cookie = dmaengine_submit(rxdesc); 513 dma_async_issue_pending(ctlr->dma_rx); 514 } 515 516 if (rs->cs_inactive) 517 writel_relaxed(INT_CS_INACTIVE, rs->regs + ROCKCHIP_SPI_IMR); 518 519 spi_enable_chip(rs, true); 520 521 if (txdesc) { 522 atomic_or(TXDMA, &rs->state); 523 dmaengine_submit(txdesc); 524 dma_async_issue_pending(ctlr->dma_tx); 525 } 526 527 /* 1 means the transfer is in progress */ 528 return 1; 529 } 530 531 static int rockchip_spi_config(struct rockchip_spi *rs, 532 struct spi_device *spi, struct spi_transfer *xfer, 533 bool use_dma, bool target_mode) 534 { 535 u32 cr0 = CR0_FRF_SPI << CR0_FRF_OFFSET 536 | CR0_BHT_8BIT << CR0_BHT_OFFSET 537 | CR0_SSD_ONE << CR0_SSD_OFFSET 538 | CR0_EM_BIG << CR0_EM_OFFSET; 539 u32 cr1; 540 u32 dmacr = 0; 541 542 if (target_mode) 543 cr0 |= CR0_OPM_TARGET << CR0_OPM_OFFSET; 544 rs->target_abort = false; 545 546 cr0 |= rs->rsd << CR0_RSD_OFFSET; 547 cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET; 548 if (spi->mode & SPI_LSB_FIRST) 549 cr0 |= CR0_FBM_LSB << CR0_FBM_OFFSET; 550 if (spi->mode & SPI_CS_HIGH) 551 cr0 |= BIT(spi_get_chipselect(spi, 0)) << CR0_SOI_OFFSET; 552 553 if (xfer->rx_buf && xfer->tx_buf) 554 cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET; 555 else if (xfer->rx_buf) 556 cr0 |= CR0_XFM_RO << CR0_XFM_OFFSET; 557 else if (use_dma) 558 cr0 |= CR0_XFM_TO << CR0_XFM_OFFSET; 559 560 switch (xfer->bits_per_word) { 561 case 4: 562 cr0 |= CR0_DFS_4BIT << CR0_DFS_OFFSET; 563 cr1 = xfer->len - 1; 564 break; 565 case 8: 566 cr0 |= CR0_DFS_8BIT << CR0_DFS_OFFSET; 567 cr1 = xfer->len - 1; 568 break; 569 case 16: 570 cr0 |= CR0_DFS_16BIT << CR0_DFS_OFFSET; 571 cr1 = xfer->len / 2 - 1; 572 break; 573 default: 574 /* we only whitelist 4, 8 and 16 bit words in 575 * ctlr->bits_per_word_mask, so this shouldn't 576 * happen 577 */ 578 dev_err(rs->dev, "unknown bits per word: %d\n", 579 xfer->bits_per_word); 580 return -EINVAL; 581 } 582 583 if (use_dma) { 584 if (xfer->tx_buf) 585 dmacr |= TF_DMA_EN; 586 if (xfer->rx_buf) 587 dmacr |= RF_DMA_EN; 588 } 589 590 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0); 591 writel_relaxed(cr1, rs->regs + ROCKCHIP_SPI_CTRLR1); 592 593 /* unfortunately setting the fifo threshold level to generate an 594 * interrupt exactly when the fifo is full doesn't seem to work, 595 * so we need the strict inequality here 596 */ 597 if ((xfer->len / rs->n_bytes) < rs->fifo_len) 598 writel_relaxed(xfer->len / rs->n_bytes - 1, rs->regs + ROCKCHIP_SPI_RXFTLR); 599 else 600 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR); 601 602 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_DMATDLR); 603 writel_relaxed(rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes) - 1, 604 rs->regs + ROCKCHIP_SPI_DMARDLR); 605 writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR); 606 607 /* the hardware only supports an even clock divisor, so 608 * round divisor = spiclk / speed up to nearest even number 609 * so that the resulting speed is <= the requested speed 610 */ 611 writel_relaxed(2 * DIV_ROUND_UP(rs->freq, 2 * xfer->speed_hz), 612 rs->regs + ROCKCHIP_SPI_BAUDR); 613 614 return 0; 615 } 616 617 static size_t rockchip_spi_max_transfer_size(struct spi_device *spi) 618 { 619 return ROCKCHIP_SPI_MAX_TRANLEN; 620 } 621 622 static int rockchip_spi_target_abort(struct spi_controller *ctlr) 623 { 624 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 625 u32 rx_fifo_left; 626 struct dma_tx_state state; 627 enum dma_status status; 628 629 /* Get current dma rx point */ 630 if (atomic_read(&rs->state) & RXDMA) { 631 dmaengine_pause(ctlr->dma_rx); 632 status = dmaengine_tx_status(ctlr->dma_rx, ctlr->dma_rx->cookie, &state); 633 if (status == DMA_ERROR) { 634 rs->rx = rs->xfer->rx_buf; 635 rs->xfer->len = 0; 636 rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR); 637 for (; rx_fifo_left; rx_fifo_left--) 638 readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR); 639 goto out; 640 } else { 641 rs->rx += rs->xfer->len - rs->n_bytes * state.residue; 642 } 643 } 644 645 /* Get the valid data left in rx fifo and set rs->xfer->len real rx size */ 646 if (rs->rx) { 647 rx_fifo_left = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR); 648 for (; rx_fifo_left; rx_fifo_left--) { 649 u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR); 650 651 if (rs->n_bytes == 1) 652 *(u8 *)rs->rx = (u8)rxw; 653 else 654 *(u16 *)rs->rx = (u16)rxw; 655 rs->rx += rs->n_bytes; 656 } 657 rs->xfer->len = (unsigned int)(rs->rx - rs->xfer->rx_buf); 658 } 659 660 out: 661 if (atomic_read(&rs->state) & RXDMA) 662 dmaengine_terminate_sync(ctlr->dma_rx); 663 if (atomic_read(&rs->state) & TXDMA) 664 dmaengine_terminate_sync(ctlr->dma_tx); 665 atomic_set(&rs->state, 0); 666 spi_enable_chip(rs, false); 667 rs->target_abort = true; 668 spi_finalize_current_transfer(ctlr); 669 670 return 0; 671 } 672 673 static int rockchip_spi_transfer_one( 674 struct spi_controller *ctlr, 675 struct spi_device *spi, 676 struct spi_transfer *xfer) 677 { 678 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 679 int ret; 680 bool use_dma; 681 682 /* Zero length transfers won't trigger an interrupt on completion */ 683 if (!xfer->len) { 684 spi_finalize_current_transfer(ctlr); 685 return 1; 686 } 687 688 WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) && 689 (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)); 690 691 if (!xfer->tx_buf && !xfer->rx_buf) { 692 dev_err(rs->dev, "No buffer for transfer\n"); 693 return -EINVAL; 694 } 695 696 if (xfer->len > ROCKCHIP_SPI_MAX_TRANLEN) { 697 dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len); 698 return -EINVAL; 699 } 700 701 rs->n_bytes = xfer->bits_per_word <= 8 ? 1 : 2; 702 rs->xfer = xfer; 703 use_dma = ctlr->can_dma ? ctlr->can_dma(ctlr, spi, xfer) : false; 704 705 ret = rockchip_spi_config(rs, spi, xfer, use_dma, ctlr->target); 706 if (ret) 707 return ret; 708 709 if (use_dma) 710 return rockchip_spi_prepare_dma(rs, ctlr, xfer); 711 712 return rockchip_spi_prepare_irq(rs, ctlr, xfer); 713 } 714 715 static bool rockchip_spi_can_dma(struct spi_controller *ctlr, 716 struct spi_device *spi, 717 struct spi_transfer *xfer) 718 { 719 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 720 unsigned int bytes_per_word = xfer->bits_per_word <= 8 ? 1 : 2; 721 722 /* if the numbor of spi words to transfer is less than the fifo 723 * length we can just fill the fifo and wait for a single irq, 724 * so don't bother setting up dma 725 */ 726 return xfer->len / bytes_per_word >= rs->fifo_len; 727 } 728 729 static int rockchip_spi_setup(struct spi_device *spi) 730 { 731 struct rockchip_spi *rs = spi_controller_get_devdata(spi->controller); 732 u32 cr0; 733 734 if (!spi_get_csgpiod(spi, 0) && (spi->mode & SPI_CS_HIGH) && !rs->cs_high_supported) { 735 dev_warn(&spi->dev, "setup: non GPIO CS can't be active-high\n"); 736 return -EINVAL; 737 } 738 739 pm_runtime_get_sync(rs->dev); 740 741 cr0 = readl_relaxed(rs->regs + ROCKCHIP_SPI_CTRLR0); 742 743 cr0 &= ~(0x3 << CR0_SCPH_OFFSET); 744 cr0 |= ((spi->mode & 0x3) << CR0_SCPH_OFFSET); 745 if (spi->mode & SPI_CS_HIGH && spi_get_chipselect(spi, 0) <= 1) 746 cr0 |= BIT(spi_get_chipselect(spi, 0)) << CR0_SOI_OFFSET; 747 else if (spi_get_chipselect(spi, 0) <= 1) 748 cr0 &= ~(BIT(spi_get_chipselect(spi, 0)) << CR0_SOI_OFFSET); 749 750 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0); 751 752 pm_runtime_put(rs->dev); 753 754 return 0; 755 } 756 757 static int rockchip_spi_probe(struct platform_device *pdev) 758 { 759 struct device_node *np = pdev->dev.of_node; 760 struct spi_controller *ctlr; 761 struct rockchip_spi *rs; 762 struct resource *mem; 763 u32 rsd_nsecs, num_cs; 764 bool target_mode; 765 int ret; 766 767 target_mode = of_property_read_bool(np, "spi-slave"); 768 769 if (target_mode) 770 ctlr = spi_alloc_target(&pdev->dev, sizeof(struct rockchip_spi)); 771 else 772 ctlr = spi_alloc_host(&pdev->dev, sizeof(struct rockchip_spi)); 773 774 if (!ctlr) 775 return -ENOMEM; 776 777 platform_set_drvdata(pdev, ctlr); 778 779 rs = spi_controller_get_devdata(ctlr); 780 781 /* Get basic io resource and map it */ 782 rs->regs = devm_platform_get_and_ioremap_resource(pdev, 0, &mem); 783 if (IS_ERR(rs->regs)) { 784 ret = PTR_ERR(rs->regs); 785 goto err_put_ctlr; 786 } 787 788 rs->apb_pclk = devm_clk_get_enabled(&pdev->dev, "apb_pclk"); 789 if (IS_ERR(rs->apb_pclk)) { 790 ret = dev_err_probe(&pdev->dev, PTR_ERR(rs->apb_pclk), 791 "Failed to get apb_pclk\n"); 792 goto err_put_ctlr; 793 } 794 795 rs->spiclk = devm_clk_get_enabled(&pdev->dev, "spiclk"); 796 if (IS_ERR(rs->spiclk)) { 797 ret = dev_err_probe(&pdev->dev, PTR_ERR(rs->spiclk), 798 "Failed to get spi_pclk\n"); 799 goto err_put_ctlr; 800 } 801 802 spi_enable_chip(rs, false); 803 804 ret = platform_get_irq(pdev, 0); 805 if (ret < 0) 806 goto err_put_ctlr; 807 808 ret = devm_request_threaded_irq(&pdev->dev, ret, rockchip_spi_isr, NULL, 809 IRQF_ONESHOT, dev_name(&pdev->dev), ctlr); 810 if (ret) 811 goto err_put_ctlr; 812 813 rs->dev = &pdev->dev; 814 rs->freq = clk_get_rate(rs->spiclk); 815 816 if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns", 817 &rsd_nsecs)) { 818 /* rx sample delay is expressed in parent clock cycles (max 3) */ 819 u32 rsd = DIV_ROUND_CLOSEST(rsd_nsecs * (rs->freq >> 8), 1000000000 >> 8); 820 if (!rsd) { 821 dev_warn(rs->dev, "%u Hz are too slow to express %u ns delay\n", 822 rs->freq, rsd_nsecs); 823 } else if (rsd > CR0_RSD_MAX) { 824 rsd = CR0_RSD_MAX; 825 dev_warn(rs->dev, 826 "%u Hz are too fast to express %u ns delay, clamping at %u ns\n", 827 rs->freq, rsd_nsecs, CR0_RSD_MAX * 1000000000U / rs->freq); 828 } 829 rs->rsd = rsd; 830 } 831 832 rs->fifo_len = get_fifo_len(rs); 833 if (!rs->fifo_len) { 834 ret = dev_err_probe(&pdev->dev, -EINVAL, "Failed to get fifo length\n"); 835 goto err_put_ctlr; 836 } 837 838 pm_runtime_set_autosuspend_delay(&pdev->dev, ROCKCHIP_AUTOSUSPEND_TIMEOUT); 839 pm_runtime_use_autosuspend(&pdev->dev); 840 pm_runtime_set_active(&pdev->dev); 841 pm_runtime_enable(&pdev->dev); 842 843 ctlr->auto_runtime_pm = true; 844 ctlr->bus_num = pdev->id; 845 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST; 846 if (target_mode) { 847 ctlr->mode_bits |= SPI_NO_CS; 848 ctlr->target_abort = rockchip_spi_target_abort; 849 } else { 850 ctlr->flags = SPI_CONTROLLER_GPIO_SS; 851 ctlr->max_native_cs = ROCKCHIP_SPI_MAX_NATIVE_CS_NUM; 852 /* 853 * rk spi0 has two native cs, spi1..5 one cs only 854 * if num-cs is missing in the dts, default to 1 855 */ 856 if (of_property_read_u32(np, "num-cs", &num_cs)) 857 num_cs = 1; 858 ctlr->num_chipselect = num_cs; 859 ctlr->use_gpio_descriptors = true; 860 } 861 ctlr->dev.of_node = pdev->dev.of_node; 862 ctlr->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8) | SPI_BPW_MASK(4); 863 ctlr->min_speed_hz = rs->freq / BAUDR_SCKDV_MAX; 864 ctlr->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT); 865 866 ctlr->setup = rockchip_spi_setup; 867 ctlr->set_cs = rockchip_spi_set_cs; 868 ctlr->transfer_one = rockchip_spi_transfer_one; 869 ctlr->max_transfer_size = rockchip_spi_max_transfer_size; 870 ctlr->handle_err = rockchip_spi_handle_err; 871 872 ctlr->dma_tx = dma_request_chan(rs->dev, "tx"); 873 if (IS_ERR(ctlr->dma_tx)) { 874 /* Check tx to see if we need to defer driver probing */ 875 ret = dev_warn_probe(rs->dev, PTR_ERR(ctlr->dma_tx), 876 "Failed to request optional TX DMA channel\n"); 877 if (ret == -EPROBE_DEFER) 878 goto err_disable_pm_runtime; 879 ctlr->dma_tx = NULL; 880 } 881 882 ctlr->dma_rx = dma_request_chan(rs->dev, "rx"); 883 if (IS_ERR(ctlr->dma_rx)) { 884 /* Check rx to see if we need to defer driver probing */ 885 ret = dev_warn_probe(rs->dev, PTR_ERR(ctlr->dma_rx), 886 "Failed to request optional RX DMA channel\n"); 887 if (ret == -EPROBE_DEFER) 888 goto err_free_dma_tx; 889 ctlr->dma_rx = NULL; 890 } 891 892 if (ctlr->dma_tx && ctlr->dma_rx) { 893 rs->dma_addr_tx = mem->start + ROCKCHIP_SPI_TXDR; 894 rs->dma_addr_rx = mem->start + ROCKCHIP_SPI_RXDR; 895 ctlr->can_dma = rockchip_spi_can_dma; 896 } 897 898 switch (readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION)) { 899 case ROCKCHIP_SPI_VER2_TYPE2: 900 rs->cs_high_supported = true; 901 ctlr->mode_bits |= SPI_CS_HIGH; 902 if (ctlr->can_dma && target_mode) 903 rs->cs_inactive = true; 904 else 905 rs->cs_inactive = false; 906 break; 907 default: 908 rs->cs_inactive = false; 909 break; 910 } 911 912 ret = devm_spi_register_controller(&pdev->dev, ctlr); 913 if (ret < 0) { 914 dev_err(&pdev->dev, "Failed to register controller\n"); 915 goto err_free_dma_rx; 916 } 917 918 return 0; 919 920 err_free_dma_rx: 921 if (ctlr->dma_rx) 922 dma_release_channel(ctlr->dma_rx); 923 err_free_dma_tx: 924 if (ctlr->dma_tx) 925 dma_release_channel(ctlr->dma_tx); 926 err_disable_pm_runtime: 927 pm_runtime_disable(&pdev->dev); 928 err_put_ctlr: 929 spi_controller_put(ctlr); 930 931 return ret; 932 } 933 934 static void rockchip_spi_remove(struct platform_device *pdev) 935 { 936 struct spi_controller *ctlr = spi_controller_get(platform_get_drvdata(pdev)); 937 938 pm_runtime_get_sync(&pdev->dev); 939 940 pm_runtime_put_noidle(&pdev->dev); 941 pm_runtime_disable(&pdev->dev); 942 pm_runtime_set_suspended(&pdev->dev); 943 944 if (ctlr->dma_tx) 945 dma_release_channel(ctlr->dma_tx); 946 if (ctlr->dma_rx) 947 dma_release_channel(ctlr->dma_rx); 948 949 spi_controller_put(ctlr); 950 } 951 952 #ifdef CONFIG_PM_SLEEP 953 static int rockchip_spi_suspend(struct device *dev) 954 { 955 int ret; 956 struct spi_controller *ctlr = dev_get_drvdata(dev); 957 958 ret = spi_controller_suspend(ctlr); 959 if (ret < 0) 960 return ret; 961 962 ret = pm_runtime_force_suspend(dev); 963 if (ret < 0) { 964 spi_controller_resume(ctlr); 965 return ret; 966 } 967 968 pinctrl_pm_select_sleep_state(dev); 969 970 return 0; 971 } 972 973 static int rockchip_spi_resume(struct device *dev) 974 { 975 int ret; 976 struct spi_controller *ctlr = dev_get_drvdata(dev); 977 978 pinctrl_pm_select_default_state(dev); 979 980 ret = pm_runtime_force_resume(dev); 981 if (ret < 0) 982 return ret; 983 984 return spi_controller_resume(ctlr); 985 } 986 #endif /* CONFIG_PM_SLEEP */ 987 988 #ifdef CONFIG_PM 989 static int rockchip_spi_runtime_suspend(struct device *dev) 990 { 991 struct spi_controller *ctlr = dev_get_drvdata(dev); 992 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 993 994 clk_disable_unprepare(rs->spiclk); 995 clk_disable_unprepare(rs->apb_pclk); 996 997 return 0; 998 } 999 1000 static int rockchip_spi_runtime_resume(struct device *dev) 1001 { 1002 int ret; 1003 struct spi_controller *ctlr = dev_get_drvdata(dev); 1004 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 1005 1006 ret = clk_prepare_enable(rs->apb_pclk); 1007 if (ret < 0) 1008 return ret; 1009 1010 ret = clk_prepare_enable(rs->spiclk); 1011 if (ret < 0) 1012 clk_disable_unprepare(rs->apb_pclk); 1013 1014 return 0; 1015 } 1016 #endif /* CONFIG_PM */ 1017 1018 static const struct dev_pm_ops rockchip_spi_pm = { 1019 SET_NOIRQ_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume) 1020 SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend, 1021 rockchip_spi_runtime_resume, NULL) 1022 }; 1023 1024 static const struct of_device_id rockchip_spi_dt_match[] = { 1025 { .compatible = "rockchip,px30-spi", }, 1026 { .compatible = "rockchip,rk3036-spi", }, 1027 { .compatible = "rockchip,rk3066-spi", }, 1028 { .compatible = "rockchip,rk3188-spi", }, 1029 { .compatible = "rockchip,rk3228-spi", }, 1030 { .compatible = "rockchip,rk3288-spi", }, 1031 { .compatible = "rockchip,rk3308-spi", }, 1032 { .compatible = "rockchip,rk3328-spi", }, 1033 { .compatible = "rockchip,rk3368-spi", }, 1034 { .compatible = "rockchip,rk3399-spi", }, 1035 { .compatible = "rockchip,rv1108-spi", }, 1036 { .compatible = "rockchip,rv1126-spi", }, 1037 { }, 1038 }; 1039 MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match); 1040 1041 static struct platform_driver rockchip_spi_driver = { 1042 .driver = { 1043 .name = DRIVER_NAME, 1044 .pm = &rockchip_spi_pm, 1045 .of_match_table = of_match_ptr(rockchip_spi_dt_match), 1046 }, 1047 .probe = rockchip_spi_probe, 1048 .remove = rockchip_spi_remove, 1049 }; 1050 1051 module_platform_driver(rockchip_spi_driver); 1052 1053 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>"); 1054 MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver"); 1055 MODULE_LICENSE("GPL v2"); 1056