1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd 4 * Author: Addy Ke <addy.ke@rock-chips.com> 5 */ 6 7 #include <linux/clk.h> 8 #include <linux/dmaengine.h> 9 #include <linux/interrupt.h> 10 #include <linux/module.h> 11 #include <linux/of.h> 12 #include <linux/pinctrl/consumer.h> 13 #include <linux/platform_device.h> 14 #include <linux/spi/spi.h> 15 #include <linux/pm_runtime.h> 16 #include <linux/scatterlist.h> 17 18 #define DRIVER_NAME "rockchip-spi" 19 20 #define ROCKCHIP_SPI_CLR_BITS(reg, bits) \ 21 writel_relaxed(readl_relaxed(reg) & ~(bits), reg) 22 #define ROCKCHIP_SPI_SET_BITS(reg, bits) \ 23 writel_relaxed(readl_relaxed(reg) | (bits), reg) 24 25 /* SPI register offsets */ 26 #define ROCKCHIP_SPI_CTRLR0 0x0000 27 #define ROCKCHIP_SPI_CTRLR1 0x0004 28 #define ROCKCHIP_SPI_SSIENR 0x0008 29 #define ROCKCHIP_SPI_SER 0x000c 30 #define ROCKCHIP_SPI_BAUDR 0x0010 31 #define ROCKCHIP_SPI_TXFTLR 0x0014 32 #define ROCKCHIP_SPI_RXFTLR 0x0018 33 #define ROCKCHIP_SPI_TXFLR 0x001c 34 #define ROCKCHIP_SPI_RXFLR 0x0020 35 #define ROCKCHIP_SPI_SR 0x0024 36 #define ROCKCHIP_SPI_IPR 0x0028 37 #define ROCKCHIP_SPI_IMR 0x002c 38 #define ROCKCHIP_SPI_ISR 0x0030 39 #define ROCKCHIP_SPI_RISR 0x0034 40 #define ROCKCHIP_SPI_ICR 0x0038 41 #define ROCKCHIP_SPI_DMACR 0x003c 42 #define ROCKCHIP_SPI_DMATDLR 0x0040 43 #define ROCKCHIP_SPI_DMARDLR 0x0044 44 #define ROCKCHIP_SPI_VERSION 0x0048 45 #define ROCKCHIP_SPI_TXDR 0x0400 46 #define ROCKCHIP_SPI_RXDR 0x0800 47 48 /* Bit fields in CTRLR0 */ 49 #define CR0_DFS_OFFSET 0 50 #define CR0_DFS_4BIT 0x0 51 #define CR0_DFS_8BIT 0x1 52 #define CR0_DFS_16BIT 0x2 53 54 #define CR0_CFS_OFFSET 2 55 56 #define CR0_SCPH_OFFSET 6 57 58 #define CR0_SCPOL_OFFSET 7 59 60 #define CR0_CSM_OFFSET 8 61 #define CR0_CSM_KEEP 0x0 62 /* ss_n be high for half sclk_out cycles */ 63 #define CR0_CSM_HALF 0X1 64 /* ss_n be high for one sclk_out cycle */ 65 #define CR0_CSM_ONE 0x2 66 67 /* ss_n to sclk_out delay */ 68 #define CR0_SSD_OFFSET 10 69 /* 70 * The period between ss_n active and 71 * sclk_out active is half sclk_out cycles 72 */ 73 #define CR0_SSD_HALF 0x0 74 /* 75 * The period between ss_n active and 76 * sclk_out active is one sclk_out cycle 77 */ 78 #define CR0_SSD_ONE 0x1 79 80 #define CR0_EM_OFFSET 11 81 #define CR0_EM_LITTLE 0x0 82 #define CR0_EM_BIG 0x1 83 84 #define CR0_FBM_OFFSET 12 85 #define CR0_FBM_MSB 0x0 86 #define CR0_FBM_LSB 0x1 87 88 #define CR0_BHT_OFFSET 13 89 #define CR0_BHT_16BIT 0x0 90 #define CR0_BHT_8BIT 0x1 91 92 #define CR0_RSD_OFFSET 14 93 #define CR0_RSD_MAX 0x3 94 95 #define CR0_FRF_OFFSET 16 96 #define CR0_FRF_SPI 0x0 97 #define CR0_FRF_SSP 0x1 98 #define CR0_FRF_MICROWIRE 0x2 99 100 #define CR0_XFM_OFFSET 18 101 #define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET) 102 #define CR0_XFM_TR 0x0 103 #define CR0_XFM_TO 0x1 104 #define CR0_XFM_RO 0x2 105 106 #define CR0_OPM_OFFSET 20 107 #define CR0_OPM_MASTER 0x0 108 #define CR0_OPM_SLAVE 0x1 109 110 #define CR0_MTM_OFFSET 0x21 111 112 /* Bit fields in SER, 2bit */ 113 #define SER_MASK 0x3 114 115 /* Bit fields in BAUDR */ 116 #define BAUDR_SCKDV_MIN 2 117 #define BAUDR_SCKDV_MAX 65534 118 119 /* Bit fields in SR, 5bit */ 120 #define SR_MASK 0x1f 121 #define SR_BUSY (1 << 0) 122 #define SR_TF_FULL (1 << 1) 123 #define SR_TF_EMPTY (1 << 2) 124 #define SR_RF_EMPTY (1 << 3) 125 #define SR_RF_FULL (1 << 4) 126 127 /* Bit fields in ISR, IMR, ISR, RISR, 5bit */ 128 #define INT_MASK 0x1f 129 #define INT_TF_EMPTY (1 << 0) 130 #define INT_TF_OVERFLOW (1 << 1) 131 #define INT_RF_UNDERFLOW (1 << 2) 132 #define INT_RF_OVERFLOW (1 << 3) 133 #define INT_RF_FULL (1 << 4) 134 135 /* Bit fields in ICR, 4bit */ 136 #define ICR_MASK 0x0f 137 #define ICR_ALL (1 << 0) 138 #define ICR_RF_UNDERFLOW (1 << 1) 139 #define ICR_RF_OVERFLOW (1 << 2) 140 #define ICR_TF_OVERFLOW (1 << 3) 141 142 /* Bit fields in DMACR */ 143 #define RF_DMA_EN (1 << 0) 144 #define TF_DMA_EN (1 << 1) 145 146 /* Driver state flags */ 147 #define RXDMA (1 << 0) 148 #define TXDMA (1 << 1) 149 150 /* sclk_out: spi master internal logic in rk3x can support 50Mhz */ 151 #define MAX_SCLK_OUT 50000000U 152 153 /* 154 * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However, 155 * the controller seems to hang when given 0x10000, so stick with this for now. 156 */ 157 #define ROCKCHIP_SPI_MAX_TRANLEN 0xffff 158 159 #define ROCKCHIP_SPI_MAX_CS_NUM 2 160 #define ROCKCHIP_SPI_VER2_TYPE1 0x05EC0002 161 #define ROCKCHIP_SPI_VER2_TYPE2 0x00110002 162 163 #define ROCKCHIP_AUTOSUSPEND_TIMEOUT 2000 164 165 struct rockchip_spi { 166 struct device *dev; 167 168 struct clk *spiclk; 169 struct clk *apb_pclk; 170 171 void __iomem *regs; 172 dma_addr_t dma_addr_rx; 173 dma_addr_t dma_addr_tx; 174 175 const void *tx; 176 void *rx; 177 unsigned int tx_left; 178 unsigned int rx_left; 179 180 atomic_t state; 181 182 /*depth of the FIFO buffer */ 183 u32 fifo_len; 184 /* frequency of spiclk */ 185 u32 freq; 186 187 u8 n_bytes; 188 u8 rsd; 189 190 bool cs_asserted[ROCKCHIP_SPI_MAX_CS_NUM]; 191 192 bool slave_abort; 193 }; 194 195 static inline void spi_enable_chip(struct rockchip_spi *rs, bool enable) 196 { 197 writel_relaxed((enable ? 1U : 0U), rs->regs + ROCKCHIP_SPI_SSIENR); 198 } 199 200 static inline void wait_for_idle(struct rockchip_spi *rs) 201 { 202 unsigned long timeout = jiffies + msecs_to_jiffies(5); 203 204 do { 205 if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)) 206 return; 207 } while (!time_after(jiffies, timeout)); 208 209 dev_warn(rs->dev, "spi controller is in busy state!\n"); 210 } 211 212 static u32 get_fifo_len(struct rockchip_spi *rs) 213 { 214 u32 ver; 215 216 ver = readl_relaxed(rs->regs + ROCKCHIP_SPI_VERSION); 217 218 switch (ver) { 219 case ROCKCHIP_SPI_VER2_TYPE1: 220 case ROCKCHIP_SPI_VER2_TYPE2: 221 return 64; 222 default: 223 return 32; 224 } 225 } 226 227 static void rockchip_spi_set_cs(struct spi_device *spi, bool enable) 228 { 229 struct spi_controller *ctlr = spi->controller; 230 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 231 bool cs_asserted = !enable; 232 233 /* Return immediately for no-op */ 234 if (cs_asserted == rs->cs_asserted[spi->chip_select]) 235 return; 236 237 if (cs_asserted) { 238 /* Keep things powered as long as CS is asserted */ 239 pm_runtime_get_sync(rs->dev); 240 241 ROCKCHIP_SPI_SET_BITS(rs->regs + ROCKCHIP_SPI_SER, 242 BIT(spi->chip_select)); 243 } else { 244 ROCKCHIP_SPI_CLR_BITS(rs->regs + ROCKCHIP_SPI_SER, 245 BIT(spi->chip_select)); 246 247 /* Drop reference from when we first asserted CS */ 248 pm_runtime_put(rs->dev); 249 } 250 251 rs->cs_asserted[spi->chip_select] = cs_asserted; 252 } 253 254 static void rockchip_spi_handle_err(struct spi_controller *ctlr, 255 struct spi_message *msg) 256 { 257 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 258 259 /* stop running spi transfer 260 * this also flushes both rx and tx fifos 261 */ 262 spi_enable_chip(rs, false); 263 264 /* make sure all interrupts are masked */ 265 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR); 266 267 if (atomic_read(&rs->state) & TXDMA) 268 dmaengine_terminate_async(ctlr->dma_tx); 269 270 if (atomic_read(&rs->state) & RXDMA) 271 dmaengine_terminate_async(ctlr->dma_rx); 272 } 273 274 static void rockchip_spi_pio_writer(struct rockchip_spi *rs) 275 { 276 u32 tx_free = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR); 277 u32 words = min(rs->tx_left, tx_free); 278 279 rs->tx_left -= words; 280 for (; words; words--) { 281 u32 txw; 282 283 if (rs->n_bytes == 1) 284 txw = *(u8 *)rs->tx; 285 else 286 txw = *(u16 *)rs->tx; 287 288 writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR); 289 rs->tx += rs->n_bytes; 290 } 291 } 292 293 static void rockchip_spi_pio_reader(struct rockchip_spi *rs) 294 { 295 u32 words = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR); 296 u32 rx_left = (rs->rx_left > words) ? rs->rx_left - words : 0; 297 298 /* the hardware doesn't allow us to change fifo threshold 299 * level while spi is enabled, so instead make sure to leave 300 * enough words in the rx fifo to get the last interrupt 301 * exactly when all words have been received 302 */ 303 if (rx_left) { 304 u32 ftl = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFTLR) + 1; 305 306 if (rx_left < ftl) { 307 rx_left = ftl; 308 words = rs->rx_left - rx_left; 309 } 310 } 311 312 rs->rx_left = rx_left; 313 for (; words; words--) { 314 u32 rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR); 315 316 if (!rs->rx) 317 continue; 318 319 if (rs->n_bytes == 1) 320 *(u8 *)rs->rx = (u8)rxw; 321 else 322 *(u16 *)rs->rx = (u16)rxw; 323 rs->rx += rs->n_bytes; 324 } 325 } 326 327 static irqreturn_t rockchip_spi_isr(int irq, void *dev_id) 328 { 329 struct spi_controller *ctlr = dev_id; 330 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 331 332 if (rs->tx_left) 333 rockchip_spi_pio_writer(rs); 334 335 rockchip_spi_pio_reader(rs); 336 if (!rs->rx_left) { 337 spi_enable_chip(rs, false); 338 writel_relaxed(0, rs->regs + ROCKCHIP_SPI_IMR); 339 spi_finalize_current_transfer(ctlr); 340 } 341 342 return IRQ_HANDLED; 343 } 344 345 static int rockchip_spi_prepare_irq(struct rockchip_spi *rs, 346 struct spi_transfer *xfer) 347 { 348 rs->tx = xfer->tx_buf; 349 rs->rx = xfer->rx_buf; 350 rs->tx_left = rs->tx ? xfer->len / rs->n_bytes : 0; 351 rs->rx_left = xfer->len / rs->n_bytes; 352 353 writel_relaxed(INT_RF_FULL, rs->regs + ROCKCHIP_SPI_IMR); 354 spi_enable_chip(rs, true); 355 356 if (rs->tx_left) 357 rockchip_spi_pio_writer(rs); 358 359 /* 1 means the transfer is in progress */ 360 return 1; 361 } 362 363 static void rockchip_spi_dma_rxcb(void *data) 364 { 365 struct spi_controller *ctlr = data; 366 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 367 int state = atomic_fetch_andnot(RXDMA, &rs->state); 368 369 if (state & TXDMA && !rs->slave_abort) 370 return; 371 372 spi_enable_chip(rs, false); 373 spi_finalize_current_transfer(ctlr); 374 } 375 376 static void rockchip_spi_dma_txcb(void *data) 377 { 378 struct spi_controller *ctlr = data; 379 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 380 int state = atomic_fetch_andnot(TXDMA, &rs->state); 381 382 if (state & RXDMA && !rs->slave_abort) 383 return; 384 385 /* Wait until the FIFO data completely. */ 386 wait_for_idle(rs); 387 388 spi_enable_chip(rs, false); 389 spi_finalize_current_transfer(ctlr); 390 } 391 392 static u32 rockchip_spi_calc_burst_size(u32 data_len) 393 { 394 u32 i; 395 396 /* burst size: 1, 2, 4, 8 */ 397 for (i = 1; i < 8; i <<= 1) { 398 if (data_len & i) 399 break; 400 } 401 402 return i; 403 } 404 405 static int rockchip_spi_prepare_dma(struct rockchip_spi *rs, 406 struct spi_controller *ctlr, struct spi_transfer *xfer) 407 { 408 struct dma_async_tx_descriptor *rxdesc, *txdesc; 409 410 atomic_set(&rs->state, 0); 411 412 rxdesc = NULL; 413 if (xfer->rx_buf) { 414 struct dma_slave_config rxconf = { 415 .direction = DMA_DEV_TO_MEM, 416 .src_addr = rs->dma_addr_rx, 417 .src_addr_width = rs->n_bytes, 418 .src_maxburst = rockchip_spi_calc_burst_size(xfer->len / 419 rs->n_bytes), 420 }; 421 422 dmaengine_slave_config(ctlr->dma_rx, &rxconf); 423 424 rxdesc = dmaengine_prep_slave_sg( 425 ctlr->dma_rx, 426 xfer->rx_sg.sgl, xfer->rx_sg.nents, 427 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT); 428 if (!rxdesc) 429 return -EINVAL; 430 431 rxdesc->callback = rockchip_spi_dma_rxcb; 432 rxdesc->callback_param = ctlr; 433 } 434 435 txdesc = NULL; 436 if (xfer->tx_buf) { 437 struct dma_slave_config txconf = { 438 .direction = DMA_MEM_TO_DEV, 439 .dst_addr = rs->dma_addr_tx, 440 .dst_addr_width = rs->n_bytes, 441 .dst_maxburst = rs->fifo_len / 4, 442 }; 443 444 dmaengine_slave_config(ctlr->dma_tx, &txconf); 445 446 txdesc = dmaengine_prep_slave_sg( 447 ctlr->dma_tx, 448 xfer->tx_sg.sgl, xfer->tx_sg.nents, 449 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT); 450 if (!txdesc) { 451 if (rxdesc) 452 dmaengine_terminate_sync(ctlr->dma_rx); 453 return -EINVAL; 454 } 455 456 txdesc->callback = rockchip_spi_dma_txcb; 457 txdesc->callback_param = ctlr; 458 } 459 460 /* rx must be started before tx due to spi instinct */ 461 if (rxdesc) { 462 atomic_or(RXDMA, &rs->state); 463 dmaengine_submit(rxdesc); 464 dma_async_issue_pending(ctlr->dma_rx); 465 } 466 467 spi_enable_chip(rs, true); 468 469 if (txdesc) { 470 atomic_or(TXDMA, &rs->state); 471 dmaengine_submit(txdesc); 472 dma_async_issue_pending(ctlr->dma_tx); 473 } 474 475 /* 1 means the transfer is in progress */ 476 return 1; 477 } 478 479 static int rockchip_spi_config(struct rockchip_spi *rs, 480 struct spi_device *spi, struct spi_transfer *xfer, 481 bool use_dma, bool slave_mode) 482 { 483 u32 cr0 = CR0_FRF_SPI << CR0_FRF_OFFSET 484 | CR0_BHT_8BIT << CR0_BHT_OFFSET 485 | CR0_SSD_ONE << CR0_SSD_OFFSET 486 | CR0_EM_BIG << CR0_EM_OFFSET; 487 u32 cr1; 488 u32 dmacr = 0; 489 490 if (slave_mode) 491 cr0 |= CR0_OPM_SLAVE << CR0_OPM_OFFSET; 492 rs->slave_abort = false; 493 494 cr0 |= rs->rsd << CR0_RSD_OFFSET; 495 cr0 |= (spi->mode & 0x3U) << CR0_SCPH_OFFSET; 496 if (spi->mode & SPI_LSB_FIRST) 497 cr0 |= CR0_FBM_LSB << CR0_FBM_OFFSET; 498 499 if (xfer->rx_buf && xfer->tx_buf) 500 cr0 |= CR0_XFM_TR << CR0_XFM_OFFSET; 501 else if (xfer->rx_buf) 502 cr0 |= CR0_XFM_RO << CR0_XFM_OFFSET; 503 else if (use_dma) 504 cr0 |= CR0_XFM_TO << CR0_XFM_OFFSET; 505 506 switch (xfer->bits_per_word) { 507 case 4: 508 cr0 |= CR0_DFS_4BIT << CR0_DFS_OFFSET; 509 cr1 = xfer->len - 1; 510 break; 511 case 8: 512 cr0 |= CR0_DFS_8BIT << CR0_DFS_OFFSET; 513 cr1 = xfer->len - 1; 514 break; 515 case 16: 516 cr0 |= CR0_DFS_16BIT << CR0_DFS_OFFSET; 517 cr1 = xfer->len / 2 - 1; 518 break; 519 default: 520 /* we only whitelist 4, 8 and 16 bit words in 521 * ctlr->bits_per_word_mask, so this shouldn't 522 * happen 523 */ 524 dev_err(rs->dev, "unknown bits per word: %d\n", 525 xfer->bits_per_word); 526 return -EINVAL; 527 } 528 529 if (use_dma) { 530 if (xfer->tx_buf) 531 dmacr |= TF_DMA_EN; 532 if (xfer->rx_buf) 533 dmacr |= RF_DMA_EN; 534 } 535 536 writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0); 537 writel_relaxed(cr1, rs->regs + ROCKCHIP_SPI_CTRLR1); 538 539 /* unfortunately setting the fifo threshold level to generate an 540 * interrupt exactly when the fifo is full doesn't seem to work, 541 * so we need the strict inequality here 542 */ 543 if (xfer->len < rs->fifo_len) 544 writel_relaxed(xfer->len - 1, rs->regs + ROCKCHIP_SPI_RXFTLR); 545 else 546 writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR); 547 548 writel_relaxed(rs->fifo_len / 2, rs->regs + ROCKCHIP_SPI_DMATDLR); 549 writel_relaxed(rockchip_spi_calc_burst_size(xfer->len / rs->n_bytes) - 1, 550 rs->regs + ROCKCHIP_SPI_DMARDLR); 551 writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR); 552 553 /* the hardware only supports an even clock divisor, so 554 * round divisor = spiclk / speed up to nearest even number 555 * so that the resulting speed is <= the requested speed 556 */ 557 writel_relaxed(2 * DIV_ROUND_UP(rs->freq, 2 * xfer->speed_hz), 558 rs->regs + ROCKCHIP_SPI_BAUDR); 559 560 return 0; 561 } 562 563 static size_t rockchip_spi_max_transfer_size(struct spi_device *spi) 564 { 565 return ROCKCHIP_SPI_MAX_TRANLEN; 566 } 567 568 static int rockchip_spi_slave_abort(struct spi_controller *ctlr) 569 { 570 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 571 572 rs->slave_abort = true; 573 spi_finalize_current_transfer(ctlr); 574 575 return 0; 576 } 577 578 static int rockchip_spi_transfer_one( 579 struct spi_controller *ctlr, 580 struct spi_device *spi, 581 struct spi_transfer *xfer) 582 { 583 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 584 int ret; 585 bool use_dma; 586 587 WARN_ON(readl_relaxed(rs->regs + ROCKCHIP_SPI_SSIENR) && 588 (readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY)); 589 590 if (!xfer->tx_buf && !xfer->rx_buf) { 591 dev_err(rs->dev, "No buffer for transfer\n"); 592 return -EINVAL; 593 } 594 595 if (xfer->len > ROCKCHIP_SPI_MAX_TRANLEN) { 596 dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len); 597 return -EINVAL; 598 } 599 600 rs->n_bytes = xfer->bits_per_word <= 8 ? 1 : 2; 601 602 use_dma = ctlr->can_dma ? ctlr->can_dma(ctlr, spi, xfer) : false; 603 604 ret = rockchip_spi_config(rs, spi, xfer, use_dma, ctlr->slave); 605 if (ret) 606 return ret; 607 608 if (use_dma) 609 return rockchip_spi_prepare_dma(rs, ctlr, xfer); 610 611 return rockchip_spi_prepare_irq(rs, xfer); 612 } 613 614 static bool rockchip_spi_can_dma(struct spi_controller *ctlr, 615 struct spi_device *spi, 616 struct spi_transfer *xfer) 617 { 618 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 619 unsigned int bytes_per_word = xfer->bits_per_word <= 8 ? 1 : 2; 620 621 /* if the numbor of spi words to transfer is less than the fifo 622 * length we can just fill the fifo and wait for a single irq, 623 * so don't bother setting up dma 624 */ 625 return xfer->len / bytes_per_word >= rs->fifo_len; 626 } 627 628 static int rockchip_spi_probe(struct platform_device *pdev) 629 { 630 int ret; 631 struct rockchip_spi *rs; 632 struct spi_controller *ctlr; 633 struct resource *mem; 634 struct device_node *np = pdev->dev.of_node; 635 u32 rsd_nsecs; 636 bool slave_mode; 637 638 slave_mode = of_property_read_bool(np, "spi-slave"); 639 640 if (slave_mode) 641 ctlr = spi_alloc_slave(&pdev->dev, 642 sizeof(struct rockchip_spi)); 643 else 644 ctlr = spi_alloc_master(&pdev->dev, 645 sizeof(struct rockchip_spi)); 646 647 if (!ctlr) 648 return -ENOMEM; 649 650 platform_set_drvdata(pdev, ctlr); 651 652 rs = spi_controller_get_devdata(ctlr); 653 ctlr->slave = slave_mode; 654 655 /* Get basic io resource and map it */ 656 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 657 rs->regs = devm_ioremap_resource(&pdev->dev, mem); 658 if (IS_ERR(rs->regs)) { 659 ret = PTR_ERR(rs->regs); 660 goto err_put_ctlr; 661 } 662 663 rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk"); 664 if (IS_ERR(rs->apb_pclk)) { 665 dev_err(&pdev->dev, "Failed to get apb_pclk\n"); 666 ret = PTR_ERR(rs->apb_pclk); 667 goto err_put_ctlr; 668 } 669 670 rs->spiclk = devm_clk_get(&pdev->dev, "spiclk"); 671 if (IS_ERR(rs->spiclk)) { 672 dev_err(&pdev->dev, "Failed to get spi_pclk\n"); 673 ret = PTR_ERR(rs->spiclk); 674 goto err_put_ctlr; 675 } 676 677 ret = clk_prepare_enable(rs->apb_pclk); 678 if (ret < 0) { 679 dev_err(&pdev->dev, "Failed to enable apb_pclk\n"); 680 goto err_put_ctlr; 681 } 682 683 ret = clk_prepare_enable(rs->spiclk); 684 if (ret < 0) { 685 dev_err(&pdev->dev, "Failed to enable spi_clk\n"); 686 goto err_disable_apbclk; 687 } 688 689 spi_enable_chip(rs, false); 690 691 ret = platform_get_irq(pdev, 0); 692 if (ret < 0) 693 goto err_disable_spiclk; 694 695 ret = devm_request_threaded_irq(&pdev->dev, ret, rockchip_spi_isr, NULL, 696 IRQF_ONESHOT, dev_name(&pdev->dev), ctlr); 697 if (ret) 698 goto err_disable_spiclk; 699 700 rs->dev = &pdev->dev; 701 rs->freq = clk_get_rate(rs->spiclk); 702 703 if (!of_property_read_u32(pdev->dev.of_node, "rx-sample-delay-ns", 704 &rsd_nsecs)) { 705 /* rx sample delay is expressed in parent clock cycles (max 3) */ 706 u32 rsd = DIV_ROUND_CLOSEST(rsd_nsecs * (rs->freq >> 8), 707 1000000000 >> 8); 708 if (!rsd) { 709 dev_warn(rs->dev, "%u Hz are too slow to express %u ns delay\n", 710 rs->freq, rsd_nsecs); 711 } else if (rsd > CR0_RSD_MAX) { 712 rsd = CR0_RSD_MAX; 713 dev_warn(rs->dev, "%u Hz are too fast to express %u ns delay, clamping at %u ns\n", 714 rs->freq, rsd_nsecs, 715 CR0_RSD_MAX * 1000000000U / rs->freq); 716 } 717 rs->rsd = rsd; 718 } 719 720 rs->fifo_len = get_fifo_len(rs); 721 if (!rs->fifo_len) { 722 dev_err(&pdev->dev, "Failed to get fifo length\n"); 723 ret = -EINVAL; 724 goto err_disable_spiclk; 725 } 726 727 pm_runtime_set_autosuspend_delay(&pdev->dev, ROCKCHIP_AUTOSUSPEND_TIMEOUT); 728 pm_runtime_use_autosuspend(&pdev->dev); 729 pm_runtime_set_active(&pdev->dev); 730 pm_runtime_enable(&pdev->dev); 731 732 ctlr->auto_runtime_pm = true; 733 ctlr->bus_num = pdev->id; 734 ctlr->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP | SPI_LSB_FIRST; 735 if (slave_mode) { 736 ctlr->mode_bits |= SPI_NO_CS; 737 ctlr->slave_abort = rockchip_spi_slave_abort; 738 } else { 739 ctlr->flags = SPI_MASTER_GPIO_SS; 740 ctlr->max_native_cs = ROCKCHIP_SPI_MAX_CS_NUM; 741 /* 742 * rk spi0 has two native cs, spi1..5 one cs only 743 * if num-cs is missing in the dts, default to 1 744 */ 745 if (of_property_read_u16(np, "num-cs", &ctlr->num_chipselect)) 746 ctlr->num_chipselect = 1; 747 ctlr->use_gpio_descriptors = true; 748 } 749 ctlr->dev.of_node = pdev->dev.of_node; 750 ctlr->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8) | SPI_BPW_MASK(4); 751 ctlr->min_speed_hz = rs->freq / BAUDR_SCKDV_MAX; 752 ctlr->max_speed_hz = min(rs->freq / BAUDR_SCKDV_MIN, MAX_SCLK_OUT); 753 754 ctlr->set_cs = rockchip_spi_set_cs; 755 ctlr->transfer_one = rockchip_spi_transfer_one; 756 ctlr->max_transfer_size = rockchip_spi_max_transfer_size; 757 ctlr->handle_err = rockchip_spi_handle_err; 758 759 ctlr->dma_tx = dma_request_chan(rs->dev, "tx"); 760 if (IS_ERR(ctlr->dma_tx)) { 761 /* Check tx to see if we need defer probing driver */ 762 if (PTR_ERR(ctlr->dma_tx) == -EPROBE_DEFER) { 763 ret = -EPROBE_DEFER; 764 goto err_disable_pm_runtime; 765 } 766 dev_warn(rs->dev, "Failed to request TX DMA channel\n"); 767 ctlr->dma_tx = NULL; 768 } 769 770 ctlr->dma_rx = dma_request_chan(rs->dev, "rx"); 771 if (IS_ERR(ctlr->dma_rx)) { 772 if (PTR_ERR(ctlr->dma_rx) == -EPROBE_DEFER) { 773 ret = -EPROBE_DEFER; 774 goto err_free_dma_tx; 775 } 776 dev_warn(rs->dev, "Failed to request RX DMA channel\n"); 777 ctlr->dma_rx = NULL; 778 } 779 780 if (ctlr->dma_tx && ctlr->dma_rx) { 781 rs->dma_addr_tx = mem->start + ROCKCHIP_SPI_TXDR; 782 rs->dma_addr_rx = mem->start + ROCKCHIP_SPI_RXDR; 783 ctlr->can_dma = rockchip_spi_can_dma; 784 } 785 786 ret = devm_spi_register_controller(&pdev->dev, ctlr); 787 if (ret < 0) { 788 dev_err(&pdev->dev, "Failed to register controller\n"); 789 goto err_free_dma_rx; 790 } 791 792 return 0; 793 794 err_free_dma_rx: 795 if (ctlr->dma_rx) 796 dma_release_channel(ctlr->dma_rx); 797 err_free_dma_tx: 798 if (ctlr->dma_tx) 799 dma_release_channel(ctlr->dma_tx); 800 err_disable_pm_runtime: 801 pm_runtime_disable(&pdev->dev); 802 err_disable_spiclk: 803 clk_disable_unprepare(rs->spiclk); 804 err_disable_apbclk: 805 clk_disable_unprepare(rs->apb_pclk); 806 err_put_ctlr: 807 spi_controller_put(ctlr); 808 809 return ret; 810 } 811 812 static int rockchip_spi_remove(struct platform_device *pdev) 813 { 814 struct spi_controller *ctlr = spi_controller_get(platform_get_drvdata(pdev)); 815 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 816 817 pm_runtime_get_sync(&pdev->dev); 818 819 clk_disable_unprepare(rs->spiclk); 820 clk_disable_unprepare(rs->apb_pclk); 821 822 pm_runtime_put_noidle(&pdev->dev); 823 pm_runtime_disable(&pdev->dev); 824 pm_runtime_set_suspended(&pdev->dev); 825 826 if (ctlr->dma_tx) 827 dma_release_channel(ctlr->dma_tx); 828 if (ctlr->dma_rx) 829 dma_release_channel(ctlr->dma_rx); 830 831 spi_controller_put(ctlr); 832 833 return 0; 834 } 835 836 #ifdef CONFIG_PM_SLEEP 837 static int rockchip_spi_suspend(struct device *dev) 838 { 839 int ret; 840 struct spi_controller *ctlr = dev_get_drvdata(dev); 841 842 ret = spi_controller_suspend(ctlr); 843 if (ret < 0) 844 return ret; 845 846 ret = pm_runtime_force_suspend(dev); 847 if (ret < 0) 848 return ret; 849 850 pinctrl_pm_select_sleep_state(dev); 851 852 return 0; 853 } 854 855 static int rockchip_spi_resume(struct device *dev) 856 { 857 int ret; 858 struct spi_controller *ctlr = dev_get_drvdata(dev); 859 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 860 861 pinctrl_pm_select_default_state(dev); 862 863 ret = pm_runtime_force_resume(dev); 864 if (ret < 0) 865 return ret; 866 867 ret = spi_controller_resume(ctlr); 868 if (ret < 0) { 869 clk_disable_unprepare(rs->spiclk); 870 clk_disable_unprepare(rs->apb_pclk); 871 } 872 873 return 0; 874 } 875 #endif /* CONFIG_PM_SLEEP */ 876 877 #ifdef CONFIG_PM 878 static int rockchip_spi_runtime_suspend(struct device *dev) 879 { 880 struct spi_controller *ctlr = dev_get_drvdata(dev); 881 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 882 883 clk_disable_unprepare(rs->spiclk); 884 clk_disable_unprepare(rs->apb_pclk); 885 886 return 0; 887 } 888 889 static int rockchip_spi_runtime_resume(struct device *dev) 890 { 891 int ret; 892 struct spi_controller *ctlr = dev_get_drvdata(dev); 893 struct rockchip_spi *rs = spi_controller_get_devdata(ctlr); 894 895 ret = clk_prepare_enable(rs->apb_pclk); 896 if (ret < 0) 897 return ret; 898 899 ret = clk_prepare_enable(rs->spiclk); 900 if (ret < 0) 901 clk_disable_unprepare(rs->apb_pclk); 902 903 return 0; 904 } 905 #endif /* CONFIG_PM */ 906 907 static const struct dev_pm_ops rockchip_spi_pm = { 908 SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume) 909 SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend, 910 rockchip_spi_runtime_resume, NULL) 911 }; 912 913 static const struct of_device_id rockchip_spi_dt_match[] = { 914 { .compatible = "rockchip,px30-spi", }, 915 { .compatible = "rockchip,rk3036-spi", }, 916 { .compatible = "rockchip,rk3066-spi", }, 917 { .compatible = "rockchip,rk3188-spi", }, 918 { .compatible = "rockchip,rk3228-spi", }, 919 { .compatible = "rockchip,rk3288-spi", }, 920 { .compatible = "rockchip,rk3308-spi", }, 921 { .compatible = "rockchip,rk3328-spi", }, 922 { .compatible = "rockchip,rk3368-spi", }, 923 { .compatible = "rockchip,rk3399-spi", }, 924 { .compatible = "rockchip,rv1108-spi", }, 925 { }, 926 }; 927 MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match); 928 929 static struct platform_driver rockchip_spi_driver = { 930 .driver = { 931 .name = DRIVER_NAME, 932 .pm = &rockchip_spi_pm, 933 .of_match_table = of_match_ptr(rockchip_spi_dt_match), 934 }, 935 .probe = rockchip_spi_probe, 936 .remove = rockchip_spi_remove, 937 }; 938 939 module_platform_driver(rockchip_spi_driver); 940 941 MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>"); 942 MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver"); 943 MODULE_LICENSE("GPL v2"); 944