1 /* 2 * SPDX-License-Identifier: GPL-2.0 3 * 4 * Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved. 5 * 6 * Authors: 7 * Md Sadre Alam <quic_mdalam@quicinc.com> 8 * Sricharan R <quic_srichara@quicinc.com> 9 * Varadarajan Narayanan <quic_varada@quicinc.com> 10 */ 11 #include <linux/bitops.h> 12 #include <linux/clk.h> 13 #include <linux/delay.h> 14 #include <linux/dmaengine.h> 15 #include <linux/dma-mapping.h> 16 #include <linux/dma/qcom_adm.h> 17 #include <linux/dma/qcom_bam_dma.h> 18 #include <linux/module.h> 19 #include <linux/of.h> 20 #include <linux/platform_device.h> 21 #include <linux/slab.h> 22 #include <linux/mtd/nand-qpic-common.h> 23 #include <linux/mtd/spinand.h> 24 #include <linux/bitfield.h> 25 26 #define NAND_FLASH_SPI_CFG 0xc0 27 #define NAND_NUM_ADDR_CYCLES 0xc4 28 #define NAND_BUSY_CHECK_WAIT_CNT 0xc8 29 #define NAND_FLASH_FEATURES 0xf64 30 31 /* QSPI NAND config reg bits */ 32 #define LOAD_CLK_CNTR_INIT_EN BIT(28) 33 #define CLK_CNTR_INIT_VAL_VEC 0x924 34 #define CLK_CNTR_INIT_VAL_VEC_MASK GENMASK(27, 16) 35 #define FEA_STATUS_DEV_ADDR 0xc0 36 #define FEA_STATUS_DEV_ADDR_MASK GENMASK(15, 8) 37 #define SPI_CFG BIT(0) 38 #define SPI_NUM_ADDR 0xDA4DB 39 #define SPI_WAIT_CNT 0x10 40 #define QPIC_QSPI_NUM_CS 1 41 #define SPI_TRANSFER_MODE_x1 BIT(29) 42 #define SPI_TRANSFER_MODE_x4 (3 << 29) 43 #define SPI_WP BIT(28) 44 #define SPI_HOLD BIT(27) 45 #define QPIC_SET_FEATURE BIT(31) 46 47 #define SPINAND_RESET 0xff 48 #define SPINAND_READID 0x9f 49 #define SPINAND_GET_FEATURE 0x0f 50 #define SPINAND_SET_FEATURE 0x1f 51 #define SPINAND_READ 0x13 52 #define SPINAND_ERASE 0xd8 53 #define SPINAND_WRITE_EN 0x06 54 #define SPINAND_PROGRAM_EXECUTE 0x10 55 #define SPINAND_PROGRAM_LOAD 0x84 56 57 #define ACC_FEATURE 0xe 58 #define BAD_BLOCK_MARKER_SIZE 0x2 59 #define OOB_BUF_SIZE 128 60 #define ecceng_to_qspi(eng) container_of(eng, struct qpic_spi_nand, ecc_eng) 61 62 struct snandc_read_status { 63 __le32 snandc_flash; 64 __le32 snandc_buffer; 65 __le32 snandc_erased_cw; 66 }; 67 68 /* 69 * ECC state struct 70 * @corrected: ECC corrected 71 * @bitflips: Max bit flip 72 * @failed: ECC failed 73 */ 74 struct qcom_ecc_stats { 75 u32 corrected; 76 u32 bitflips; 77 u32 failed; 78 }; 79 80 struct qpic_ecc { 81 struct device *dev; 82 int ecc_bytes_hw; 83 int spare_bytes; 84 int bbm_size; 85 int ecc_mode; 86 int bytes; 87 int steps; 88 int step_size; 89 int strength; 90 int cw_size; 91 int cw_data; 92 u32 cfg0; 93 u32 cfg1; 94 u32 cfg0_raw; 95 u32 cfg1_raw; 96 u32 ecc_buf_cfg; 97 u32 ecc_bch_cfg; 98 u32 clrflashstatus; 99 u32 clrreadstatus; 100 bool bch_enabled; 101 }; 102 103 struct qpic_spi_nand { 104 struct qcom_nand_controller *snandc; 105 struct spi_controller *ctlr; 106 struct mtd_info *mtd; 107 struct clk *iomacro_clk; 108 struct qpic_ecc *ecc; 109 struct qcom_ecc_stats ecc_stats; 110 struct nand_ecc_engine ecc_eng; 111 u8 *data_buf; 112 u8 *oob_buf; 113 __le32 addr1; 114 __le32 addr2; 115 __le32 cmd; 116 u32 num_cw; 117 bool oob_rw; 118 bool page_rw; 119 bool raw_rw; 120 }; 121 122 static void qcom_spi_set_read_loc_first(struct qcom_nand_controller *snandc, 123 int reg, int cw_offset, int read_size, 124 int is_last_read_loc) 125 { 126 __le32 locreg_val; 127 u32 val = FIELD_PREP(READ_LOCATION_OFFSET_MASK, cw_offset) | 128 FIELD_PREP(READ_LOCATION_SIZE_MASK, read_size) | 129 FIELD_PREP(READ_LOCATION_LAST_MASK, is_last_read_loc); 130 131 locreg_val = cpu_to_le32(val); 132 133 if (reg == NAND_READ_LOCATION_0) 134 snandc->regs->read_location0 = locreg_val; 135 else if (reg == NAND_READ_LOCATION_1) 136 snandc->regs->read_location1 = locreg_val; 137 else if (reg == NAND_READ_LOCATION_2) 138 snandc->regs->read_location2 = locreg_val; 139 else if (reg == NAND_READ_LOCATION_3) 140 snandc->regs->read_location3 = locreg_val; 141 } 142 143 static void qcom_spi_set_read_loc_last(struct qcom_nand_controller *snandc, 144 int reg, int cw_offset, int read_size, 145 int is_last_read_loc) 146 { 147 __le32 locreg_val; 148 u32 val = FIELD_PREP(READ_LOCATION_OFFSET_MASK, cw_offset) | 149 FIELD_PREP(READ_LOCATION_SIZE_MASK, read_size) | 150 FIELD_PREP(READ_LOCATION_LAST_MASK, is_last_read_loc); 151 152 locreg_val = cpu_to_le32(val); 153 154 if (reg == NAND_READ_LOCATION_LAST_CW_0) 155 snandc->regs->read_location_last0 = locreg_val; 156 else if (reg == NAND_READ_LOCATION_LAST_CW_1) 157 snandc->regs->read_location_last1 = locreg_val; 158 else if (reg == NAND_READ_LOCATION_LAST_CW_2) 159 snandc->regs->read_location_last2 = locreg_val; 160 else if (reg == NAND_READ_LOCATION_LAST_CW_3) 161 snandc->regs->read_location_last3 = locreg_val; 162 } 163 164 static struct qcom_nand_controller *nand_to_qcom_snand(struct nand_device *nand) 165 { 166 struct nand_ecc_engine *eng = nand->ecc.engine; 167 struct qpic_spi_nand *qspi = ecceng_to_qspi(eng); 168 169 return qspi->snandc; 170 } 171 172 static int qcom_spi_init(struct qcom_nand_controller *snandc) 173 { 174 u32 snand_cfg_val = 0x0; 175 int ret; 176 177 snand_cfg_val = FIELD_PREP(CLK_CNTR_INIT_VAL_VEC_MASK, CLK_CNTR_INIT_VAL_VEC) | 178 FIELD_PREP(LOAD_CLK_CNTR_INIT_EN, 0) | 179 FIELD_PREP(FEA_STATUS_DEV_ADDR_MASK, FEA_STATUS_DEV_ADDR) | 180 FIELD_PREP(SPI_CFG, 0); 181 182 snandc->regs->spi_cfg = cpu_to_le32(snand_cfg_val); 183 snandc->regs->num_addr_cycle = cpu_to_le32(SPI_NUM_ADDR); 184 snandc->regs->busy_wait_cnt = cpu_to_le32(SPI_WAIT_CNT); 185 186 qcom_write_reg_dma(snandc, &snandc->regs->spi_cfg, NAND_FLASH_SPI_CFG, 1, 0); 187 188 snand_cfg_val &= ~LOAD_CLK_CNTR_INIT_EN; 189 snandc->regs->spi_cfg = cpu_to_le32(snand_cfg_val); 190 191 qcom_write_reg_dma(snandc, &snandc->regs->spi_cfg, NAND_FLASH_SPI_CFG, 1, 0); 192 193 qcom_write_reg_dma(snandc, &snandc->regs->num_addr_cycle, NAND_NUM_ADDR_CYCLES, 1, 0); 194 qcom_write_reg_dma(snandc, &snandc->regs->busy_wait_cnt, NAND_BUSY_CHECK_WAIT_CNT, 1, 195 NAND_BAM_NEXT_SGL); 196 197 ret = qcom_submit_descs(snandc); 198 if (ret) { 199 dev_err(snandc->dev, "failure in submitting spi init descriptor\n"); 200 return ret; 201 } 202 203 return ret; 204 } 205 206 static int qcom_spi_ooblayout_ecc(struct mtd_info *mtd, int section, 207 struct mtd_oob_region *oobregion) 208 { 209 struct nand_device *nand = mtd_to_nanddev(mtd); 210 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand); 211 struct qpic_ecc *qecc = snandc->qspi->ecc; 212 213 switch (section) { 214 case 0: 215 oobregion->offset = 0; 216 oobregion->length = qecc->bytes * (qecc->steps - 1) + 217 qecc->bbm_size; 218 return 0; 219 case 1: 220 oobregion->offset = qecc->bytes * (qecc->steps - 1) + 221 qecc->bbm_size + 222 qecc->steps * 4; 223 oobregion->length = mtd->oobsize - oobregion->offset; 224 return 0; 225 } 226 227 return -ERANGE; 228 } 229 230 static int qcom_spi_ooblayout_free(struct mtd_info *mtd, int section, 231 struct mtd_oob_region *oobregion) 232 { 233 struct nand_device *nand = mtd_to_nanddev(mtd); 234 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand); 235 struct qpic_ecc *qecc = snandc->qspi->ecc; 236 237 if (section) 238 return -ERANGE; 239 240 oobregion->length = qecc->steps * 4; 241 oobregion->offset = ((qecc->steps - 1) * qecc->bytes) + qecc->bbm_size; 242 243 return 0; 244 } 245 246 static const struct mtd_ooblayout_ops qcom_spi_ooblayout = { 247 .ecc = qcom_spi_ooblayout_ecc, 248 .free = qcom_spi_ooblayout_free, 249 }; 250 251 static int qcom_spi_ecc_init_ctx_pipelined(struct nand_device *nand) 252 { 253 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand); 254 struct nand_ecc_props *reqs = &nand->ecc.requirements; 255 struct nand_ecc_props *user = &nand->ecc.user_conf; 256 struct nand_ecc_props *conf = &nand->ecc.ctx.conf; 257 struct mtd_info *mtd = nanddev_to_mtd(nand); 258 int cwperpage, bad_block_byte, ret; 259 struct qpic_ecc *ecc_cfg; 260 261 cwperpage = mtd->writesize / NANDC_STEP_SIZE; 262 snandc->qspi->num_cw = cwperpage; 263 264 ecc_cfg = kzalloc(sizeof(*ecc_cfg), GFP_KERNEL); 265 if (!ecc_cfg) 266 return -ENOMEM; 267 268 if (user->step_size && user->strength) { 269 ecc_cfg->step_size = user->step_size; 270 ecc_cfg->strength = user->strength; 271 } else if (reqs->step_size && reqs->strength) { 272 ecc_cfg->step_size = reqs->step_size; 273 ecc_cfg->strength = reqs->strength; 274 } else { 275 /* use defaults */ 276 ecc_cfg->step_size = NANDC_STEP_SIZE; 277 ecc_cfg->strength = 4; 278 } 279 280 if (ecc_cfg->step_size != NANDC_STEP_SIZE) { 281 dev_err(snandc->dev, 282 "only %u bytes ECC step size is supported\n", 283 NANDC_STEP_SIZE); 284 ret = -EOPNOTSUPP; 285 goto err_free_ecc_cfg; 286 } 287 288 switch (ecc_cfg->strength) { 289 case 4: 290 ecc_cfg->ecc_mode = ECC_MODE_4BIT; 291 ecc_cfg->ecc_bytes_hw = 7; 292 ecc_cfg->spare_bytes = 4; 293 break; 294 295 case 8: 296 ecc_cfg->ecc_mode = ECC_MODE_8BIT; 297 ecc_cfg->ecc_bytes_hw = 13; 298 ecc_cfg->spare_bytes = 2; 299 break; 300 301 default: 302 dev_err(snandc->dev, 303 "only 4 or 8 bits ECC strength is supported\n"); 304 ret = -EOPNOTSUPP; 305 goto err_free_ecc_cfg; 306 } 307 308 snandc->qspi->oob_buf = kmalloc(mtd->writesize + mtd->oobsize, 309 GFP_KERNEL); 310 if (!snandc->qspi->oob_buf) { 311 ret = -ENOMEM; 312 goto err_free_ecc_cfg; 313 } 314 315 memset(snandc->qspi->oob_buf, 0xff, mtd->writesize + mtd->oobsize); 316 317 nand->ecc.ctx.priv = ecc_cfg; 318 snandc->qspi->mtd = mtd; 319 320 ecc_cfg->bbm_size = 1; 321 ecc_cfg->bch_enabled = true; 322 ecc_cfg->bytes = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes + ecc_cfg->bbm_size; 323 324 ecc_cfg->steps = cwperpage; 325 ecc_cfg->cw_data = 516; 326 ecc_cfg->cw_size = ecc_cfg->cw_data + ecc_cfg->bytes; 327 bad_block_byte = mtd->writesize - ecc_cfg->cw_size * (cwperpage - 1) + 1; 328 329 mtd_set_ooblayout(mtd, &qcom_spi_ooblayout); 330 331 /* 332 * Free the temporary BAM transaction allocated initially by 333 * qcom_nandc_alloc(), and allocate a new one based on the 334 * updated max_cwperpage value. 335 */ 336 qcom_free_bam_transaction(snandc); 337 338 snandc->max_cwperpage = cwperpage; 339 340 snandc->bam_txn = qcom_alloc_bam_transaction(snandc); 341 if (!snandc->bam_txn) { 342 dev_err(snandc->dev, "failed to allocate BAM transaction\n"); 343 ret = -ENOMEM; 344 goto err_free_ecc_cfg; 345 } 346 347 ecc_cfg->cfg0 = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) | 348 FIELD_PREP(UD_SIZE_BYTES_MASK, ecc_cfg->cw_data) | 349 FIELD_PREP(DISABLE_STATUS_AFTER_WRITE, 1) | 350 FIELD_PREP(NUM_ADDR_CYCLES_MASK, 3) | 351 FIELD_PREP(ECC_PARITY_SIZE_BYTES_RS, ecc_cfg->ecc_bytes_hw) | 352 FIELD_PREP(STATUS_BFR_READ, 0) | 353 FIELD_PREP(SET_RD_MODE_AFTER_STATUS, 1) | 354 FIELD_PREP(SPARE_SIZE_BYTES_MASK, ecc_cfg->spare_bytes); 355 356 ecc_cfg->cfg1 = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 0) | 357 FIELD_PREP(CS_ACTIVE_BSY, 0) | 358 FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, bad_block_byte) | 359 FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 0) | 360 FIELD_PREP(WR_RD_BSY_GAP_MASK, 20) | 361 FIELD_PREP(WIDE_FLASH, 0) | 362 FIELD_PREP(ENABLE_BCH_ECC, ecc_cfg->bch_enabled); 363 364 ecc_cfg->cfg0_raw = FIELD_PREP(CW_PER_PAGE_MASK, (cwperpage - 1)) | 365 FIELD_PREP(NUM_ADDR_CYCLES_MASK, 3) | 366 FIELD_PREP(UD_SIZE_BYTES_MASK, ecc_cfg->cw_size) | 367 FIELD_PREP(SPARE_SIZE_BYTES_MASK, 0); 368 369 ecc_cfg->cfg1_raw = FIELD_PREP(NAND_RECOVERY_CYCLES_MASK, 0) | 370 FIELD_PREP(CS_ACTIVE_BSY, 0) | 371 FIELD_PREP(BAD_BLOCK_BYTE_NUM_MASK, 17) | 372 FIELD_PREP(BAD_BLOCK_IN_SPARE_AREA, 1) | 373 FIELD_PREP(WR_RD_BSY_GAP_MASK, 20) | 374 FIELD_PREP(WIDE_FLASH, 0) | 375 FIELD_PREP(DEV0_CFG1_ECC_DISABLE, 1); 376 377 ecc_cfg->ecc_bch_cfg = FIELD_PREP(ECC_CFG_ECC_DISABLE, !ecc_cfg->bch_enabled) | 378 FIELD_PREP(ECC_SW_RESET, 0) | 379 FIELD_PREP(ECC_NUM_DATA_BYTES_MASK, ecc_cfg->cw_data) | 380 FIELD_PREP(ECC_FORCE_CLK_OPEN, 1) | 381 FIELD_PREP(ECC_MODE_MASK, ecc_cfg->ecc_mode) | 382 FIELD_PREP(ECC_PARITY_SIZE_BYTES_BCH_MASK, ecc_cfg->ecc_bytes_hw); 383 384 ecc_cfg->ecc_buf_cfg = FIELD_PREP(NUM_STEPS_MASK, 0x203); 385 ecc_cfg->clrflashstatus = FS_READY_BSY_N; 386 ecc_cfg->clrreadstatus = 0xc0; 387 388 conf->step_size = ecc_cfg->step_size; 389 conf->strength = ecc_cfg->strength; 390 391 snandc->regs->erased_cw_detect_cfg_clr = cpu_to_le32(CLR_ERASED_PAGE_DET); 392 snandc->regs->erased_cw_detect_cfg_set = cpu_to_le32(SET_ERASED_PAGE_DET); 393 394 dev_dbg(snandc->dev, "ECC strength: %u bits per %u bytes\n", 395 ecc_cfg->strength, ecc_cfg->step_size); 396 397 return 0; 398 399 err_free_ecc_cfg: 400 kfree(ecc_cfg); 401 return ret; 402 } 403 404 static void qcom_spi_ecc_cleanup_ctx_pipelined(struct nand_device *nand) 405 { 406 struct qpic_ecc *ecc_cfg = nand_to_ecc_ctx(nand); 407 408 kfree(ecc_cfg); 409 } 410 411 static int qcom_spi_ecc_prepare_io_req_pipelined(struct nand_device *nand, 412 struct nand_page_io_req *req) 413 { 414 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand); 415 struct qpic_ecc *ecc_cfg = nand_to_ecc_ctx(nand); 416 417 snandc->qspi->ecc = ecc_cfg; 418 snandc->qspi->raw_rw = false; 419 snandc->qspi->oob_rw = false; 420 snandc->qspi->page_rw = false; 421 422 if (req->datalen) 423 snandc->qspi->page_rw = true; 424 425 if (req->ooblen) 426 snandc->qspi->oob_rw = true; 427 428 if (req->mode == MTD_OPS_RAW) 429 snandc->qspi->raw_rw = true; 430 431 return 0; 432 } 433 434 static int qcom_spi_ecc_finish_io_req_pipelined(struct nand_device *nand, 435 struct nand_page_io_req *req) 436 { 437 struct qcom_nand_controller *snandc = nand_to_qcom_snand(nand); 438 struct mtd_info *mtd = nanddev_to_mtd(nand); 439 440 if (req->mode == MTD_OPS_RAW || req->type != NAND_PAGE_READ) 441 return 0; 442 443 if (snandc->qspi->ecc_stats.failed) 444 mtd->ecc_stats.failed += snandc->qspi->ecc_stats.failed; 445 else 446 mtd->ecc_stats.corrected += snandc->qspi->ecc_stats.corrected; 447 448 if (snandc->qspi->ecc_stats.failed) 449 return -EBADMSG; 450 else 451 return snandc->qspi->ecc_stats.bitflips; 452 } 453 454 static struct nand_ecc_engine_ops qcom_spi_ecc_engine_ops_pipelined = { 455 .init_ctx = qcom_spi_ecc_init_ctx_pipelined, 456 .cleanup_ctx = qcom_spi_ecc_cleanup_ctx_pipelined, 457 .prepare_io_req = qcom_spi_ecc_prepare_io_req_pipelined, 458 .finish_io_req = qcom_spi_ecc_finish_io_req_pipelined, 459 }; 460 461 /* helper to configure location register values */ 462 static void qcom_spi_set_read_loc(struct qcom_nand_controller *snandc, int cw, int reg, 463 int cw_offset, int read_size, int is_last_read_loc) 464 { 465 int reg_base = NAND_READ_LOCATION_0; 466 int num_cw = snandc->qspi->num_cw; 467 468 if (cw == (num_cw - 1)) 469 reg_base = NAND_READ_LOCATION_LAST_CW_0; 470 471 reg_base += reg * 4; 472 473 if (cw == (num_cw - 1)) 474 return qcom_spi_set_read_loc_last(snandc, reg_base, cw_offset, 475 read_size, is_last_read_loc); 476 else 477 return qcom_spi_set_read_loc_first(snandc, reg_base, cw_offset, 478 read_size, is_last_read_loc); 479 } 480 481 static void 482 qcom_spi_config_cw_read(struct qcom_nand_controller *snandc, bool use_ecc, int cw) 483 { 484 __le32 *reg = &snandc->regs->read_location0; 485 int num_cw = snandc->qspi->num_cw; 486 487 qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_0, 4, NAND_BAM_NEXT_SGL); 488 if (cw == (num_cw - 1)) { 489 reg = &snandc->regs->read_location_last0; 490 qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_LAST_CW_0, 4, 491 NAND_BAM_NEXT_SGL); 492 } 493 494 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); 495 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); 496 497 qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 2, 0); 498 qcom_read_reg_dma(snandc, NAND_ERASED_CW_DETECT_STATUS, 1, 499 NAND_BAM_NEXT_SGL); 500 } 501 502 static int qcom_spi_block_erase(struct qcom_nand_controller *snandc) 503 { 504 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; 505 int ret; 506 507 snandc->buf_count = 0; 508 snandc->buf_start = 0; 509 qcom_clear_read_regs(snandc); 510 qcom_clear_bam_transaction(snandc); 511 512 snandc->regs->cmd = snandc->qspi->cmd; 513 snandc->regs->addr0 = snandc->qspi->addr1; 514 snandc->regs->addr1 = snandc->qspi->addr2; 515 snandc->regs->cfg0 = cpu_to_le32((ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) | 516 FIELD_PREP(CW_PER_PAGE_MASK, 0)); 517 snandc->regs->cfg1 = cpu_to_le32(ecc_cfg->cfg1_raw); 518 snandc->regs->exec = cpu_to_le32(1); 519 520 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL); 521 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 2, NAND_BAM_NEXT_SGL); 522 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); 523 524 ret = qcom_submit_descs(snandc); 525 if (ret) { 526 dev_err(snandc->dev, "failure to erase block\n"); 527 return ret; 528 } 529 530 return 0; 531 } 532 533 static void qcom_spi_config_single_cw_page_read(struct qcom_nand_controller *snandc, 534 bool use_ecc, int cw) 535 { 536 __le32 *reg = &snandc->regs->read_location0; 537 int num_cw = snandc->qspi->num_cw; 538 539 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0); 540 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); 541 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr, 542 NAND_ERASED_CW_DETECT_CFG, 1, 0); 543 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set, 544 NAND_ERASED_CW_DETECT_CFG, 1, 545 NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL); 546 547 if (cw == (num_cw - 1)) { 548 reg = &snandc->regs->read_location_last0; 549 qcom_write_reg_dma(snandc, reg, NAND_READ_LOCATION_LAST_CW_0, 4, NAND_BAM_NEXT_SGL); 550 } 551 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); 552 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); 553 554 qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1, 0); 555 } 556 557 static int qcom_spi_check_raw_flash_errors(struct qcom_nand_controller *snandc, int cw_cnt) 558 { 559 int i; 560 561 qcom_nandc_dev_to_mem(snandc, true); 562 563 for (i = 0; i < cw_cnt; i++) { 564 u32 flash = le32_to_cpu(snandc->reg_read_buf[i]); 565 566 if (flash & (FS_OP_ERR | FS_MPU_ERR)) 567 return -EIO; 568 } 569 570 return 0; 571 } 572 573 static int qcom_spi_read_last_cw(struct qcom_nand_controller *snandc, 574 const struct spi_mem_op *op) 575 { 576 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; 577 struct mtd_info *mtd = snandc->qspi->mtd; 578 int size, ret = 0; 579 int col, bbpos; 580 u32 cfg0, cfg1, ecc_bch_cfg; 581 u32 num_cw = snandc->qspi->num_cw; 582 583 qcom_clear_bam_transaction(snandc); 584 qcom_clear_read_regs(snandc); 585 586 size = ecc_cfg->cw_size; 587 col = ecc_cfg->cw_size * (num_cw - 1); 588 589 memset(snandc->data_buffer, 0xff, size); 590 snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col)); 591 snandc->regs->addr1 = snandc->qspi->addr2; 592 593 cfg0 = (ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) | 594 FIELD_PREP(CW_PER_PAGE_MASK, 0); 595 cfg1 = ecc_cfg->cfg1_raw; 596 ecc_bch_cfg = ECC_CFG_ECC_DISABLE; 597 598 snandc->regs->cmd = snandc->qspi->cmd; 599 snandc->regs->cfg0 = cpu_to_le32(cfg0); 600 snandc->regs->cfg1 = cpu_to_le32(cfg1); 601 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); 602 snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus); 603 snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus); 604 snandc->regs->exec = cpu_to_le32(1); 605 606 qcom_spi_set_read_loc(snandc, num_cw - 1, 0, 0, ecc_cfg->cw_size, 1); 607 608 qcom_spi_config_single_cw_page_read(snandc, false, num_cw - 1); 609 610 qcom_read_data_dma(snandc, FLASH_BUF_ACC, snandc->data_buffer, size, 0); 611 612 ret = qcom_submit_descs(snandc); 613 if (ret) { 614 dev_err(snandc->dev, "failed to read last cw\n"); 615 return ret; 616 } 617 618 ret = qcom_spi_check_raw_flash_errors(snandc, 1); 619 if (ret) 620 return ret; 621 622 bbpos = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1); 623 624 /* 625 * TODO: The SPINAND code expects two bad block marker bytes 626 * at the beginning of the OOB area, but the OOB layout used by 627 * the driver has only one. Duplicate that for now in order to 628 * avoid certain blocks to be marked as bad. 629 * 630 * This can be removed once single-byte bad block marker support 631 * gets implemented in the SPINAND code. 632 */ 633 snandc->data_buffer[bbpos + 1] = snandc->data_buffer[bbpos]; 634 635 memcpy(op->data.buf.in, snandc->data_buffer + bbpos, op->data.nbytes); 636 637 return ret; 638 } 639 640 static int qcom_spi_check_error(struct qcom_nand_controller *snandc) 641 { 642 struct snandc_read_status *buf; 643 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; 644 int i, num_cw = snandc->qspi->num_cw; 645 bool flash_op_err = false, erased; 646 unsigned int max_bitflips = 0; 647 unsigned int uncorrectable_cws = 0; 648 649 snandc->qspi->ecc_stats.failed = 0; 650 snandc->qspi->ecc_stats.corrected = 0; 651 652 qcom_nandc_dev_to_mem(snandc, true); 653 buf = (struct snandc_read_status *)snandc->reg_read_buf; 654 655 for (i = 0; i < num_cw; i++, buf++) { 656 u32 flash, buffer, erased_cw; 657 658 flash = le32_to_cpu(buf->snandc_flash); 659 buffer = le32_to_cpu(buf->snandc_buffer); 660 erased_cw = le32_to_cpu(buf->snandc_erased_cw); 661 662 if ((flash & FS_OP_ERR) && (buffer & BS_UNCORRECTABLE_BIT)) { 663 if (ecc_cfg->bch_enabled) 664 erased = (erased_cw & ERASED_CW) == ERASED_CW; 665 else 666 erased = false; 667 668 if (!erased) 669 uncorrectable_cws |= BIT(i); 670 671 } else if (flash & (FS_OP_ERR | FS_MPU_ERR)) { 672 flash_op_err = true; 673 } else { 674 unsigned int stat; 675 676 stat = buffer & BS_CORRECTABLE_ERR_MSK; 677 678 /* 679 * The exact number of the corrected bits is 680 * unknown because the hardware only reports the 681 * number of the corrected bytes. 682 * 683 * Since we have no better solution at the moment, 684 * report that value as the number of bit errors 685 * despite that it is inaccurate in most cases. 686 */ 687 if (stat && stat != ecc_cfg->strength) 688 dev_warn_once(snandc->dev, 689 "Warning: due to hw limitation, the reported number of the corrected bits may be inaccurate\n"); 690 691 snandc->qspi->ecc_stats.corrected += stat; 692 max_bitflips = max(max_bitflips, stat); 693 } 694 } 695 696 if (flash_op_err) 697 return -EIO; 698 699 if (!uncorrectable_cws) 700 snandc->qspi->ecc_stats.bitflips = max_bitflips; 701 else 702 snandc->qspi->ecc_stats.failed++; 703 704 return 0; 705 } 706 707 static int qcom_spi_read_cw_raw(struct qcom_nand_controller *snandc, u8 *data_buf, 708 u8 *oob_buf, int cw) 709 { 710 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; 711 struct mtd_info *mtd = snandc->qspi->mtd; 712 int data_size1, data_size2, oob_size1, oob_size2; 713 int ret, reg_off = FLASH_BUF_ACC, read_loc = 0; 714 int raw_cw = cw; 715 u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw; 716 int col; 717 718 snandc->buf_count = 0; 719 snandc->buf_start = 0; 720 qcom_clear_read_regs(snandc); 721 qcom_clear_bam_transaction(snandc); 722 raw_cw = num_cw - 1; 723 724 cfg0 = (ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) | 725 FIELD_PREP(CW_PER_PAGE_MASK, 0); 726 cfg1 = ecc_cfg->cfg1_raw; 727 ecc_bch_cfg = ECC_CFG_ECC_DISABLE; 728 729 col = ecc_cfg->cw_size * cw; 730 731 snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col)); 732 snandc->regs->addr1 = snandc->qspi->addr2; 733 snandc->regs->cmd = snandc->qspi->cmd; 734 snandc->regs->cfg0 = cpu_to_le32(cfg0); 735 snandc->regs->cfg1 = cpu_to_le32(cfg1); 736 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); 737 snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus); 738 snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus); 739 snandc->regs->exec = cpu_to_le32(1); 740 741 qcom_spi_set_read_loc(snandc, raw_cw, 0, 0, ecc_cfg->cw_size, 1); 742 743 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0); 744 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); 745 qcom_write_reg_dma(snandc, &snandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG, 1, 0); 746 747 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr, 748 NAND_ERASED_CW_DETECT_CFG, 1, 0); 749 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set, 750 NAND_ERASED_CW_DETECT_CFG, 1, 751 NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL); 752 753 data_size1 = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1); 754 oob_size1 = ecc_cfg->bbm_size; 755 756 if (cw == (num_cw - 1)) { 757 data_size2 = NANDC_STEP_SIZE - data_size1 - 758 ((num_cw - 1) * 4); 759 oob_size2 = (num_cw * 4) + ecc_cfg->ecc_bytes_hw + 760 ecc_cfg->spare_bytes; 761 } else { 762 data_size2 = ecc_cfg->cw_data - data_size1; 763 oob_size2 = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes; 764 } 765 766 qcom_spi_set_read_loc(snandc, cw, 0, read_loc, data_size1, 0); 767 read_loc += data_size1; 768 769 qcom_spi_set_read_loc(snandc, cw, 1, read_loc, oob_size1, 0); 770 read_loc += oob_size1; 771 772 qcom_spi_set_read_loc(snandc, cw, 2, read_loc, data_size2, 0); 773 read_loc += data_size2; 774 775 qcom_spi_set_read_loc(snandc, cw, 3, read_loc, oob_size2, 1); 776 777 qcom_spi_config_cw_read(snandc, false, raw_cw); 778 779 qcom_read_data_dma(snandc, reg_off, data_buf, data_size1, 0); 780 reg_off += data_size1; 781 782 qcom_read_data_dma(snandc, reg_off, oob_buf, oob_size1, 0); 783 reg_off += oob_size1; 784 785 qcom_read_data_dma(snandc, reg_off, data_buf + data_size1, data_size2, 0); 786 reg_off += data_size2; 787 788 qcom_read_data_dma(snandc, reg_off, oob_buf + oob_size1, oob_size2, 0); 789 790 ret = qcom_submit_descs(snandc); 791 if (ret) { 792 dev_err(snandc->dev, "failure to read raw cw %d\n", cw); 793 return ret; 794 } 795 796 return qcom_spi_check_raw_flash_errors(snandc, 1); 797 } 798 799 static int qcom_spi_read_page_raw(struct qcom_nand_controller *snandc, 800 const struct spi_mem_op *op) 801 { 802 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; 803 u8 *data_buf = NULL, *oob_buf = NULL; 804 int ret, cw; 805 u32 num_cw = snandc->qspi->num_cw; 806 807 if (snandc->qspi->page_rw) 808 data_buf = op->data.buf.in; 809 810 oob_buf = snandc->qspi->oob_buf; 811 memset(oob_buf, 0xff, OOB_BUF_SIZE); 812 813 for (cw = 0; cw < num_cw; cw++) { 814 ret = qcom_spi_read_cw_raw(snandc, data_buf, oob_buf, cw); 815 if (ret) 816 return ret; 817 818 if (data_buf) 819 data_buf += ecc_cfg->cw_data; 820 if (oob_buf) 821 oob_buf += ecc_cfg->bytes; 822 } 823 824 return 0; 825 } 826 827 static int qcom_spi_read_page_ecc(struct qcom_nand_controller *snandc, 828 const struct spi_mem_op *op) 829 { 830 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; 831 u8 *data_buf = NULL, *oob_buf = NULL; 832 int ret, i; 833 u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw; 834 835 data_buf = op->data.buf.in; 836 oob_buf = snandc->qspi->oob_buf; 837 838 snandc->buf_count = 0; 839 snandc->buf_start = 0; 840 qcom_clear_read_regs(snandc); 841 842 cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) | 843 FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1); 844 cfg1 = ecc_cfg->cfg1; 845 ecc_bch_cfg = ecc_cfg->ecc_bch_cfg; 846 847 snandc->regs->addr0 = snandc->qspi->addr1; 848 snandc->regs->addr1 = snandc->qspi->addr2; 849 snandc->regs->cmd = snandc->qspi->cmd; 850 snandc->regs->cfg0 = cpu_to_le32(cfg0); 851 snandc->regs->cfg1 = cpu_to_le32(cfg1); 852 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); 853 snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus); 854 snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus); 855 snandc->regs->exec = cpu_to_le32(1); 856 857 qcom_spi_set_read_loc(snandc, 0, 0, 0, ecc_cfg->cw_data, 1); 858 859 qcom_clear_bam_transaction(snandc); 860 861 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0); 862 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); 863 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr, 864 NAND_ERASED_CW_DETECT_CFG, 1, 0); 865 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set, 866 NAND_ERASED_CW_DETECT_CFG, 1, 867 NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL); 868 869 for (i = 0; i < num_cw; i++) { 870 int data_size, oob_size; 871 872 if (i == (num_cw - 1)) { 873 data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2); 874 oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw + 875 ecc_cfg->spare_bytes; 876 } else { 877 data_size = ecc_cfg->cw_data; 878 oob_size = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes; 879 } 880 881 if (data_buf && oob_buf) { 882 qcom_spi_set_read_loc(snandc, i, 0, 0, data_size, 0); 883 qcom_spi_set_read_loc(snandc, i, 1, data_size, oob_size, 1); 884 } else if (data_buf) { 885 qcom_spi_set_read_loc(snandc, i, 0, 0, data_size, 1); 886 } else { 887 qcom_spi_set_read_loc(snandc, i, 0, data_size, oob_size, 1); 888 } 889 890 qcom_spi_config_cw_read(snandc, true, i); 891 892 if (data_buf) 893 qcom_read_data_dma(snandc, FLASH_BUF_ACC, data_buf, 894 data_size, 0); 895 if (oob_buf) { 896 int j; 897 898 for (j = 0; j < ecc_cfg->bbm_size; j++) 899 *oob_buf++ = 0xff; 900 901 qcom_read_data_dma(snandc, FLASH_BUF_ACC + data_size, 902 oob_buf, oob_size, 0); 903 } 904 905 if (data_buf) 906 data_buf += data_size; 907 if (oob_buf) 908 oob_buf += oob_size; 909 } 910 911 ret = qcom_submit_descs(snandc); 912 if (ret) { 913 dev_err(snandc->dev, "failure to read page\n"); 914 return ret; 915 } 916 917 return qcom_spi_check_error(snandc); 918 } 919 920 static int qcom_spi_read_page_oob(struct qcom_nand_controller *snandc, 921 const struct spi_mem_op *op) 922 { 923 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; 924 u8 *oob_buf = NULL; 925 int ret, i; 926 u32 cfg0, cfg1, ecc_bch_cfg, num_cw = snandc->qspi->num_cw; 927 928 oob_buf = op->data.buf.in; 929 930 snandc->buf_count = 0; 931 snandc->buf_start = 0; 932 qcom_clear_read_regs(snandc); 933 qcom_clear_bam_transaction(snandc); 934 935 cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) | 936 FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1); 937 cfg1 = ecc_cfg->cfg1; 938 ecc_bch_cfg = ecc_cfg->ecc_bch_cfg; 939 940 snandc->regs->addr0 = snandc->qspi->addr1; 941 snandc->regs->addr1 = snandc->qspi->addr2; 942 snandc->regs->cmd = snandc->qspi->cmd; 943 snandc->regs->cfg0 = cpu_to_le32(cfg0); 944 snandc->regs->cfg1 = cpu_to_le32(cfg1); 945 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); 946 snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus); 947 snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus); 948 snandc->regs->exec = cpu_to_le32(1); 949 950 qcom_spi_set_read_loc(snandc, 0, 0, 0, ecc_cfg->cw_data, 1); 951 952 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0); 953 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); 954 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_clr, 955 NAND_ERASED_CW_DETECT_CFG, 1, 0); 956 qcom_write_reg_dma(snandc, &snandc->regs->erased_cw_detect_cfg_set, 957 NAND_ERASED_CW_DETECT_CFG, 1, 958 NAND_ERASED_CW_SET | NAND_BAM_NEXT_SGL); 959 960 for (i = 0; i < num_cw; i++) { 961 int data_size, oob_size; 962 963 if (i == (num_cw - 1)) { 964 data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2); 965 oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw + 966 ecc_cfg->spare_bytes; 967 } else { 968 data_size = ecc_cfg->cw_data; 969 oob_size = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes; 970 } 971 972 qcom_spi_set_read_loc(snandc, i, 0, data_size, oob_size, 1); 973 974 qcom_spi_config_cw_read(snandc, true, i); 975 976 if (oob_buf) { 977 int j; 978 979 for (j = 0; j < ecc_cfg->bbm_size; j++) 980 *oob_buf++ = 0xff; 981 982 qcom_read_data_dma(snandc, FLASH_BUF_ACC + data_size, 983 oob_buf, oob_size, 0); 984 } 985 986 if (oob_buf) 987 oob_buf += oob_size; 988 } 989 990 ret = qcom_submit_descs(snandc); 991 if (ret) { 992 dev_err(snandc->dev, "failure to read oob\n"); 993 return ret; 994 } 995 996 return qcom_spi_check_error(snandc); 997 } 998 999 static int qcom_spi_read_page(struct qcom_nand_controller *snandc, 1000 const struct spi_mem_op *op) 1001 { 1002 if (snandc->qspi->page_rw && snandc->qspi->raw_rw) 1003 return qcom_spi_read_page_raw(snandc, op); 1004 1005 if (snandc->qspi->page_rw) 1006 return qcom_spi_read_page_ecc(snandc, op); 1007 1008 if (snandc->qspi->oob_rw && snandc->qspi->raw_rw) 1009 return qcom_spi_read_last_cw(snandc, op); 1010 1011 if (snandc->qspi->oob_rw) 1012 return qcom_spi_read_page_oob(snandc, op); 1013 1014 return 0; 1015 } 1016 1017 static void qcom_spi_config_page_write(struct qcom_nand_controller *snandc) 1018 { 1019 qcom_write_reg_dma(snandc, &snandc->regs->addr0, NAND_ADDR0, 2, 0); 1020 qcom_write_reg_dma(snandc, &snandc->regs->cfg0, NAND_DEV0_CFG0, 3, 0); 1021 qcom_write_reg_dma(snandc, &snandc->regs->ecc_buf_cfg, NAND_EBI2_ECC_BUF_CFG, 1022 1, NAND_BAM_NEXT_SGL); 1023 } 1024 1025 static void qcom_spi_config_cw_write(struct qcom_nand_controller *snandc) 1026 { 1027 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 1, NAND_BAM_NEXT_SGL); 1028 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); 1029 qcom_read_reg_dma(snandc, NAND_FLASH_STATUS, 1, NAND_BAM_NEXT_SGL); 1030 1031 qcom_write_reg_dma(snandc, &snandc->regs->clrflashstatus, NAND_FLASH_STATUS, 1, 0); 1032 qcom_write_reg_dma(snandc, &snandc->regs->clrreadstatus, NAND_READ_STATUS, 1, 1033 NAND_BAM_NEXT_SGL); 1034 } 1035 1036 static int qcom_spi_program_raw(struct qcom_nand_controller *snandc, 1037 const struct spi_mem_op *op) 1038 { 1039 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; 1040 struct mtd_info *mtd = snandc->qspi->mtd; 1041 u8 *data_buf = NULL, *oob_buf = NULL; 1042 int i, ret; 1043 int num_cw = snandc->qspi->num_cw; 1044 u32 cfg0, cfg1, ecc_bch_cfg; 1045 1046 cfg0 = (ecc_cfg->cfg0_raw & ~CW_PER_PAGE_MASK) | 1047 FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1); 1048 cfg1 = ecc_cfg->cfg1_raw; 1049 ecc_bch_cfg = ECC_CFG_ECC_DISABLE; 1050 1051 data_buf = snandc->qspi->data_buf; 1052 1053 oob_buf = snandc->qspi->oob_buf; 1054 memset(oob_buf, 0xff, OOB_BUF_SIZE); 1055 1056 snandc->buf_count = 0; 1057 snandc->buf_start = 0; 1058 qcom_clear_read_regs(snandc); 1059 qcom_clear_bam_transaction(snandc); 1060 1061 snandc->regs->addr0 = snandc->qspi->addr1; 1062 snandc->regs->addr1 = snandc->qspi->addr2; 1063 snandc->regs->cmd = snandc->qspi->cmd; 1064 snandc->regs->cfg0 = cpu_to_le32(cfg0); 1065 snandc->regs->cfg1 = cpu_to_le32(cfg1); 1066 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); 1067 snandc->regs->clrflashstatus = cpu_to_le32(ecc_cfg->clrflashstatus); 1068 snandc->regs->clrreadstatus = cpu_to_le32(ecc_cfg->clrreadstatus); 1069 snandc->regs->exec = cpu_to_le32(1); 1070 1071 qcom_spi_config_page_write(snandc); 1072 1073 for (i = 0; i < num_cw; i++) { 1074 int data_size1, data_size2, oob_size1, oob_size2; 1075 int reg_off = FLASH_BUF_ACC; 1076 1077 data_size1 = mtd->writesize - ecc_cfg->cw_size * (num_cw - 1); 1078 oob_size1 = ecc_cfg->bbm_size; 1079 1080 if (i == (num_cw - 1)) { 1081 data_size2 = NANDC_STEP_SIZE - data_size1 - 1082 ((num_cw - 1) << 2); 1083 oob_size2 = (num_cw << 2) + ecc_cfg->ecc_bytes_hw + 1084 ecc_cfg->spare_bytes; 1085 } else { 1086 data_size2 = ecc_cfg->cw_data - data_size1; 1087 oob_size2 = ecc_cfg->ecc_bytes_hw + ecc_cfg->spare_bytes; 1088 } 1089 1090 qcom_write_data_dma(snandc, reg_off, data_buf, data_size1, 1091 NAND_BAM_NO_EOT); 1092 reg_off += data_size1; 1093 data_buf += data_size1; 1094 1095 qcom_write_data_dma(snandc, reg_off, oob_buf, oob_size1, 1096 NAND_BAM_NO_EOT); 1097 oob_buf += oob_size1; 1098 reg_off += oob_size1; 1099 1100 qcom_write_data_dma(snandc, reg_off, data_buf, data_size2, 1101 NAND_BAM_NO_EOT); 1102 reg_off += data_size2; 1103 data_buf += data_size2; 1104 1105 qcom_write_data_dma(snandc, reg_off, oob_buf, oob_size2, 0); 1106 oob_buf += oob_size2; 1107 1108 qcom_spi_config_cw_write(snandc); 1109 } 1110 1111 ret = qcom_submit_descs(snandc); 1112 if (ret) { 1113 dev_err(snandc->dev, "failure to write raw page\n"); 1114 return ret; 1115 } 1116 1117 return 0; 1118 } 1119 1120 static int qcom_spi_program_ecc(struct qcom_nand_controller *snandc, 1121 const struct spi_mem_op *op) 1122 { 1123 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; 1124 u8 *data_buf = NULL, *oob_buf = NULL; 1125 int i, ret; 1126 int num_cw = snandc->qspi->num_cw; 1127 u32 cfg0, cfg1, ecc_bch_cfg, ecc_buf_cfg; 1128 1129 cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) | 1130 FIELD_PREP(CW_PER_PAGE_MASK, num_cw - 1); 1131 cfg1 = ecc_cfg->cfg1; 1132 ecc_bch_cfg = ecc_cfg->ecc_bch_cfg; 1133 ecc_buf_cfg = ecc_cfg->ecc_buf_cfg; 1134 1135 if (snandc->qspi->data_buf) 1136 data_buf = snandc->qspi->data_buf; 1137 1138 oob_buf = snandc->qspi->oob_buf; 1139 1140 snandc->buf_count = 0; 1141 snandc->buf_start = 0; 1142 qcom_clear_read_regs(snandc); 1143 qcom_clear_bam_transaction(snandc); 1144 1145 snandc->regs->addr0 = snandc->qspi->addr1; 1146 snandc->regs->addr1 = snandc->qspi->addr2; 1147 snandc->regs->cmd = snandc->qspi->cmd; 1148 snandc->regs->cfg0 = cpu_to_le32(cfg0); 1149 snandc->regs->cfg1 = cpu_to_le32(cfg1); 1150 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); 1151 snandc->regs->ecc_buf_cfg = cpu_to_le32(ecc_buf_cfg); 1152 snandc->regs->exec = cpu_to_le32(1); 1153 1154 qcom_spi_config_page_write(snandc); 1155 1156 for (i = 0; i < num_cw; i++) { 1157 int data_size, oob_size; 1158 1159 if (i == (num_cw - 1)) { 1160 data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2); 1161 oob_size = (num_cw << 2) + ecc_cfg->ecc_bytes_hw + 1162 ecc_cfg->spare_bytes; 1163 } else { 1164 data_size = ecc_cfg->cw_data; 1165 oob_size = ecc_cfg->bytes; 1166 } 1167 1168 if (data_buf) 1169 qcom_write_data_dma(snandc, FLASH_BUF_ACC, data_buf, data_size, 1170 i == (num_cw - 1) ? NAND_BAM_NO_EOT : 0); 1171 1172 if (i == (num_cw - 1)) { 1173 if (oob_buf) { 1174 oob_buf += ecc_cfg->bbm_size; 1175 qcom_write_data_dma(snandc, FLASH_BUF_ACC + data_size, 1176 oob_buf, oob_size, 0); 1177 } 1178 } 1179 1180 qcom_spi_config_cw_write(snandc); 1181 1182 if (data_buf) 1183 data_buf += data_size; 1184 if (oob_buf) 1185 oob_buf += oob_size; 1186 } 1187 1188 ret = qcom_submit_descs(snandc); 1189 if (ret) { 1190 dev_err(snandc->dev, "failure to write page\n"); 1191 return ret; 1192 } 1193 1194 return 0; 1195 } 1196 1197 static int qcom_spi_program_oob(struct qcom_nand_controller *snandc, 1198 const struct spi_mem_op *op) 1199 { 1200 struct qpic_ecc *ecc_cfg = snandc->qspi->ecc; 1201 u8 *oob_buf = NULL; 1202 int ret, col, data_size, oob_size; 1203 int num_cw = snandc->qspi->num_cw; 1204 u32 cfg0, cfg1, ecc_bch_cfg, ecc_buf_cfg; 1205 1206 cfg0 = (ecc_cfg->cfg0 & ~CW_PER_PAGE_MASK) | 1207 FIELD_PREP(CW_PER_PAGE_MASK, 0); 1208 cfg1 = ecc_cfg->cfg1; 1209 ecc_bch_cfg = ecc_cfg->ecc_bch_cfg; 1210 ecc_buf_cfg = ecc_cfg->ecc_buf_cfg; 1211 1212 col = ecc_cfg->cw_size * (num_cw - 1); 1213 1214 oob_buf = snandc->qspi->data_buf; 1215 1216 snandc->buf_count = 0; 1217 snandc->buf_start = 0; 1218 qcom_clear_read_regs(snandc); 1219 qcom_clear_bam_transaction(snandc); 1220 snandc->regs->addr0 = (snandc->qspi->addr1 | cpu_to_le32(col)); 1221 snandc->regs->addr1 = snandc->qspi->addr2; 1222 snandc->regs->cmd = snandc->qspi->cmd; 1223 snandc->regs->cfg0 = cpu_to_le32(cfg0); 1224 snandc->regs->cfg1 = cpu_to_le32(cfg1); 1225 snandc->regs->ecc_bch_cfg = cpu_to_le32(ecc_bch_cfg); 1226 snandc->regs->ecc_buf_cfg = cpu_to_le32(ecc_buf_cfg); 1227 snandc->regs->exec = cpu_to_le32(1); 1228 1229 /* calculate the data and oob size for the last codeword/step */ 1230 data_size = NANDC_STEP_SIZE - ((num_cw - 1) << 2); 1231 oob_size = snandc->qspi->mtd->oobavail; 1232 1233 memset(snandc->data_buffer, 0xff, ecc_cfg->cw_data); 1234 /* override new oob content to last codeword */ 1235 mtd_ooblayout_get_databytes(snandc->qspi->mtd, snandc->data_buffer + data_size, 1236 oob_buf, 0, snandc->qspi->mtd->oobavail); 1237 qcom_spi_config_page_write(snandc); 1238 qcom_write_data_dma(snandc, FLASH_BUF_ACC, snandc->data_buffer, data_size + oob_size, 0); 1239 qcom_spi_config_cw_write(snandc); 1240 1241 ret = qcom_submit_descs(snandc); 1242 if (ret) { 1243 dev_err(snandc->dev, "failure to write oob\n"); 1244 return ret; 1245 } 1246 1247 return 0; 1248 } 1249 1250 static int qcom_spi_program_execute(struct qcom_nand_controller *snandc, 1251 const struct spi_mem_op *op) 1252 { 1253 if (snandc->qspi->page_rw && snandc->qspi->raw_rw) 1254 return qcom_spi_program_raw(snandc, op); 1255 1256 if (snandc->qspi->page_rw) 1257 return qcom_spi_program_ecc(snandc, op); 1258 1259 if (snandc->qspi->oob_rw) 1260 return qcom_spi_program_oob(snandc, op); 1261 1262 return 0; 1263 } 1264 1265 static int qcom_spi_cmd_mapping(struct qcom_nand_controller *snandc, u32 opcode, u32 *cmd) 1266 { 1267 switch (opcode) { 1268 case SPINAND_RESET: 1269 *cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_RESET_DEVICE); 1270 break; 1271 case SPINAND_READID: 1272 *cmd = (SPI_WP | SPI_HOLD | SPI_TRANSFER_MODE_x1 | OP_FETCH_ID); 1273 break; 1274 case SPINAND_GET_FEATURE: 1275 *cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE); 1276 break; 1277 case SPINAND_SET_FEATURE: 1278 *cmd = (SPI_TRANSFER_MODE_x1 | SPI_WP | SPI_HOLD | ACC_FEATURE | 1279 QPIC_SET_FEATURE); 1280 break; 1281 case SPINAND_READ: 1282 if (snandc->qspi->raw_rw) { 1283 *cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 | 1284 SPI_WP | SPI_HOLD | OP_PAGE_READ); 1285 } else { 1286 *cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 | 1287 SPI_WP | SPI_HOLD | OP_PAGE_READ_WITH_ECC); 1288 } 1289 1290 break; 1291 case SPINAND_ERASE: 1292 *cmd = OP_BLOCK_ERASE | PAGE_ACC | LAST_PAGE | SPI_WP | 1293 SPI_HOLD | SPI_TRANSFER_MODE_x1; 1294 break; 1295 case SPINAND_WRITE_EN: 1296 *cmd = SPINAND_WRITE_EN; 1297 break; 1298 case SPINAND_PROGRAM_EXECUTE: 1299 *cmd = (PAGE_ACC | LAST_PAGE | SPI_TRANSFER_MODE_x1 | 1300 SPI_WP | SPI_HOLD | OP_PROGRAM_PAGE); 1301 break; 1302 case SPINAND_PROGRAM_LOAD: 1303 *cmd = SPINAND_PROGRAM_LOAD; 1304 break; 1305 default: 1306 dev_err(snandc->dev, "Opcode not supported: %u\n", opcode); 1307 return -EOPNOTSUPP; 1308 } 1309 1310 return 0; 1311 } 1312 1313 static int qcom_spi_write_page(struct qcom_nand_controller *snandc, 1314 const struct spi_mem_op *op) 1315 { 1316 int ret; 1317 u32 cmd; 1318 1319 ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode, &cmd); 1320 if (ret < 0) 1321 return ret; 1322 1323 if (op->cmd.opcode == SPINAND_PROGRAM_LOAD) 1324 snandc->qspi->data_buf = (u8 *)op->data.buf.out; 1325 1326 return 0; 1327 } 1328 1329 static int qcom_spi_send_cmdaddr(struct qcom_nand_controller *snandc, 1330 const struct spi_mem_op *op) 1331 { 1332 u32 cmd; 1333 int ret, opcode; 1334 1335 ret = qcom_spi_cmd_mapping(snandc, op->cmd.opcode, &cmd); 1336 if (ret < 0) 1337 return ret; 1338 1339 opcode = op->cmd.opcode; 1340 1341 switch (opcode) { 1342 case SPINAND_WRITE_EN: 1343 return 0; 1344 case SPINAND_PROGRAM_EXECUTE: 1345 snandc->qspi->addr1 = cpu_to_le32(op->addr.val << 16); 1346 snandc->qspi->addr2 = cpu_to_le32(op->addr.val >> 16 & 0xff); 1347 snandc->qspi->cmd = cpu_to_le32(cmd); 1348 return qcom_spi_program_execute(snandc, op); 1349 case SPINAND_READ: 1350 snandc->qspi->addr1 = cpu_to_le32(op->addr.val << 16); 1351 snandc->qspi->addr2 = cpu_to_le32(op->addr.val >> 16 & 0xff); 1352 snandc->qspi->cmd = cpu_to_le32(cmd); 1353 return 0; 1354 case SPINAND_ERASE: 1355 snandc->qspi->addr1 = cpu_to_le32(op->addr.val << 16); 1356 snandc->qspi->addr2 = cpu_to_le32(op->addr.val >> 16 & 0xffff); 1357 snandc->qspi->cmd = cpu_to_le32(cmd); 1358 return qcom_spi_block_erase(snandc); 1359 default: 1360 break; 1361 } 1362 1363 snandc->buf_count = 0; 1364 snandc->buf_start = 0; 1365 qcom_clear_read_regs(snandc); 1366 qcom_clear_bam_transaction(snandc); 1367 1368 snandc->regs->cmd = cpu_to_le32(cmd); 1369 snandc->regs->exec = cpu_to_le32(1); 1370 snandc->regs->addr0 = cpu_to_le32(op->addr.val); 1371 snandc->regs->addr1 = cpu_to_le32(0); 1372 1373 qcom_write_reg_dma(snandc, &snandc->regs->cmd, NAND_FLASH_CMD, 3, NAND_BAM_NEXT_SGL); 1374 qcom_write_reg_dma(snandc, &snandc->regs->exec, NAND_EXEC_CMD, 1, NAND_BAM_NEXT_SGL); 1375 1376 ret = qcom_submit_descs(snandc); 1377 if (ret) 1378 dev_err(snandc->dev, "failure in submitting cmd descriptor\n"); 1379 1380 return ret; 1381 } 1382 1383 static int qcom_spi_io_op(struct qcom_nand_controller *snandc, const struct spi_mem_op *op) 1384 { 1385 int ret, val, opcode; 1386 bool copy = false, copy_ftr = false; 1387 1388 ret = qcom_spi_send_cmdaddr(snandc, op); 1389 if (ret) 1390 return ret; 1391 1392 snandc->buf_count = 0; 1393 snandc->buf_start = 0; 1394 qcom_clear_read_regs(snandc); 1395 qcom_clear_bam_transaction(snandc); 1396 opcode = op->cmd.opcode; 1397 1398 switch (opcode) { 1399 case SPINAND_READID: 1400 snandc->buf_count = 4; 1401 qcom_read_reg_dma(snandc, NAND_READ_ID, 1, NAND_BAM_NEXT_SGL); 1402 copy = true; 1403 break; 1404 case SPINAND_GET_FEATURE: 1405 snandc->buf_count = 4; 1406 qcom_read_reg_dma(snandc, NAND_FLASH_FEATURES, 1, NAND_BAM_NEXT_SGL); 1407 copy_ftr = true; 1408 break; 1409 case SPINAND_SET_FEATURE: 1410 snandc->regs->flash_feature = cpu_to_le32(*(u32 *)op->data.buf.out); 1411 qcom_write_reg_dma(snandc, &snandc->regs->flash_feature, 1412 NAND_FLASH_FEATURES, 1, NAND_BAM_NEXT_SGL); 1413 break; 1414 case SPINAND_PROGRAM_EXECUTE: 1415 case SPINAND_WRITE_EN: 1416 case SPINAND_RESET: 1417 case SPINAND_ERASE: 1418 case SPINAND_READ: 1419 return 0; 1420 default: 1421 return -EOPNOTSUPP; 1422 } 1423 1424 ret = qcom_submit_descs(snandc); 1425 if (ret) { 1426 dev_err(snandc->dev, "failure in submitting descriptor for:%d\n", opcode); 1427 return ret; 1428 } 1429 1430 if (copy) { 1431 qcom_nandc_dev_to_mem(snandc, true); 1432 memcpy(op->data.buf.in, snandc->reg_read_buf, snandc->buf_count); 1433 } 1434 1435 if (copy_ftr) { 1436 qcom_nandc_dev_to_mem(snandc, true); 1437 val = le32_to_cpu(*(__le32 *)snandc->reg_read_buf); 1438 val >>= 8; 1439 memcpy(op->data.buf.in, &val, snandc->buf_count); 1440 } 1441 1442 return 0; 1443 } 1444 1445 static bool qcom_spi_is_page_op(const struct spi_mem_op *op) 1446 { 1447 if (op->addr.buswidth != 1 && op->addr.buswidth != 2 && op->addr.buswidth != 4) 1448 return false; 1449 1450 if (op->data.dir == SPI_MEM_DATA_IN) { 1451 if (op->addr.buswidth == 4 && op->data.buswidth == 4) 1452 return true; 1453 1454 if (op->addr.nbytes == 2 && op->addr.buswidth == 1) 1455 return true; 1456 1457 } else if (op->data.dir == SPI_MEM_DATA_OUT) { 1458 if (op->data.buswidth == 4) 1459 return true; 1460 if (op->addr.nbytes == 2 && op->addr.buswidth == 1) 1461 return true; 1462 } 1463 1464 return false; 1465 } 1466 1467 static bool qcom_spi_supports_op(struct spi_mem *mem, const struct spi_mem_op *op) 1468 { 1469 if (!spi_mem_default_supports_op(mem, op)) 1470 return false; 1471 1472 if (op->cmd.nbytes != 1 || op->cmd.buswidth != 1) 1473 return false; 1474 1475 if (qcom_spi_is_page_op(op)) 1476 return true; 1477 1478 return ((!op->addr.nbytes || op->addr.buswidth == 1) && 1479 (!op->dummy.nbytes || op->dummy.buswidth == 1) && 1480 (!op->data.nbytes || op->data.buswidth == 1)); 1481 } 1482 1483 static int qcom_spi_exec_op(struct spi_mem *mem, const struct spi_mem_op *op) 1484 { 1485 struct qcom_nand_controller *snandc = spi_controller_get_devdata(mem->spi->controller); 1486 1487 dev_dbg(snandc->dev, "OP %02x ADDR %08llX@%d:%u DATA %d:%u", op->cmd.opcode, 1488 op->addr.val, op->addr.buswidth, op->addr.nbytes, 1489 op->data.buswidth, op->data.nbytes); 1490 1491 if (qcom_spi_is_page_op(op)) { 1492 if (op->data.dir == SPI_MEM_DATA_IN) 1493 return qcom_spi_read_page(snandc, op); 1494 if (op->data.dir == SPI_MEM_DATA_OUT) 1495 return qcom_spi_write_page(snandc, op); 1496 } else { 1497 return qcom_spi_io_op(snandc, op); 1498 } 1499 1500 return 0; 1501 } 1502 1503 static const struct spi_controller_mem_ops qcom_spi_mem_ops = { 1504 .supports_op = qcom_spi_supports_op, 1505 .exec_op = qcom_spi_exec_op, 1506 }; 1507 1508 static const struct spi_controller_mem_caps qcom_spi_mem_caps = { 1509 .ecc = true, 1510 }; 1511 1512 static int qcom_spi_probe(struct platform_device *pdev) 1513 { 1514 struct device *dev = &pdev->dev; 1515 struct spi_controller *ctlr; 1516 struct qcom_nand_controller *snandc; 1517 struct qpic_spi_nand *qspi; 1518 struct qpic_ecc *ecc; 1519 struct resource *res; 1520 const void *dev_data; 1521 int ret; 1522 1523 ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL); 1524 if (!ecc) 1525 return -ENOMEM; 1526 1527 qspi = devm_kzalloc(dev, sizeof(*qspi), GFP_KERNEL); 1528 if (!qspi) 1529 return -ENOMEM; 1530 1531 ctlr = __devm_spi_alloc_controller(dev, sizeof(*snandc), false); 1532 if (!ctlr) 1533 return -ENOMEM; 1534 1535 platform_set_drvdata(pdev, ctlr); 1536 1537 snandc = spi_controller_get_devdata(ctlr); 1538 qspi->snandc = snandc; 1539 1540 snandc->dev = dev; 1541 snandc->qspi = qspi; 1542 snandc->qspi->ctlr = ctlr; 1543 snandc->qspi->ecc = ecc; 1544 1545 dev_data = of_device_get_match_data(dev); 1546 if (!dev_data) { 1547 dev_err(&pdev->dev, "failed to get device data\n"); 1548 return -ENODEV; 1549 } 1550 1551 snandc->props = dev_data; 1552 snandc->dev = &pdev->dev; 1553 1554 snandc->core_clk = devm_clk_get(dev, "core"); 1555 if (IS_ERR(snandc->core_clk)) 1556 return PTR_ERR(snandc->core_clk); 1557 1558 snandc->aon_clk = devm_clk_get(dev, "aon"); 1559 if (IS_ERR(snandc->aon_clk)) 1560 return PTR_ERR(snandc->aon_clk); 1561 1562 snandc->qspi->iomacro_clk = devm_clk_get(dev, "iom"); 1563 if (IS_ERR(snandc->qspi->iomacro_clk)) 1564 return PTR_ERR(snandc->qspi->iomacro_clk); 1565 1566 snandc->base = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 1567 if (IS_ERR(snandc->base)) 1568 return PTR_ERR(snandc->base); 1569 1570 snandc->base_phys = res->start; 1571 snandc->base_dma = dma_map_resource(dev, res->start, resource_size(res), 1572 DMA_BIDIRECTIONAL, 0); 1573 if (dma_mapping_error(dev, snandc->base_dma)) 1574 return -ENXIO; 1575 1576 ret = clk_prepare_enable(snandc->core_clk); 1577 if (ret) 1578 goto err_dis_core_clk; 1579 1580 ret = clk_prepare_enable(snandc->aon_clk); 1581 if (ret) 1582 goto err_dis_aon_clk; 1583 1584 ret = clk_prepare_enable(snandc->qspi->iomacro_clk); 1585 if (ret) 1586 goto err_dis_iom_clk; 1587 1588 ret = qcom_nandc_alloc(snandc); 1589 if (ret) 1590 goto err_snand_alloc; 1591 1592 ret = qcom_spi_init(snandc); 1593 if (ret) 1594 goto err_spi_init; 1595 1596 /* setup ECC engine */ 1597 snandc->qspi->ecc_eng.dev = &pdev->dev; 1598 snandc->qspi->ecc_eng.integration = NAND_ECC_ENGINE_INTEGRATION_PIPELINED; 1599 snandc->qspi->ecc_eng.ops = &qcom_spi_ecc_engine_ops_pipelined; 1600 snandc->qspi->ecc_eng.priv = snandc; 1601 1602 ret = nand_ecc_register_on_host_hw_engine(&snandc->qspi->ecc_eng); 1603 if (ret) { 1604 dev_err(&pdev->dev, "failed to register ecc engine:%d\n", ret); 1605 goto err_spi_init; 1606 } 1607 1608 ctlr->num_chipselect = QPIC_QSPI_NUM_CS; 1609 ctlr->mem_ops = &qcom_spi_mem_ops; 1610 ctlr->mem_caps = &qcom_spi_mem_caps; 1611 ctlr->dev.of_node = pdev->dev.of_node; 1612 ctlr->mode_bits = SPI_TX_DUAL | SPI_RX_DUAL | 1613 SPI_TX_QUAD | SPI_RX_QUAD; 1614 1615 ret = spi_register_controller(ctlr); 1616 if (ret) { 1617 dev_err(&pdev->dev, "spi_register_controller failed.\n"); 1618 goto err_spi_init; 1619 } 1620 1621 return 0; 1622 1623 err_spi_init: 1624 qcom_nandc_unalloc(snandc); 1625 err_snand_alloc: 1626 clk_disable_unprepare(snandc->qspi->iomacro_clk); 1627 err_dis_iom_clk: 1628 clk_disable_unprepare(snandc->aon_clk); 1629 err_dis_aon_clk: 1630 clk_disable_unprepare(snandc->core_clk); 1631 err_dis_core_clk: 1632 dma_unmap_resource(dev, res->start, resource_size(res), 1633 DMA_BIDIRECTIONAL, 0); 1634 return ret; 1635 } 1636 1637 static void qcom_spi_remove(struct platform_device *pdev) 1638 { 1639 struct spi_controller *ctlr = platform_get_drvdata(pdev); 1640 struct qcom_nand_controller *snandc = spi_controller_get_devdata(ctlr); 1641 struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1642 1643 spi_unregister_controller(ctlr); 1644 1645 qcom_nandc_unalloc(snandc); 1646 1647 clk_disable_unprepare(snandc->aon_clk); 1648 clk_disable_unprepare(snandc->core_clk); 1649 clk_disable_unprepare(snandc->qspi->iomacro_clk); 1650 1651 dma_unmap_resource(&pdev->dev, snandc->base_dma, resource_size(res), 1652 DMA_BIDIRECTIONAL, 0); 1653 } 1654 1655 static const struct qcom_nandc_props ipq9574_snandc_props = { 1656 .dev_cmd_reg_start = 0x7000, 1657 .bam_offset = 0x30000, 1658 .supports_bam = true, 1659 }; 1660 1661 static const struct of_device_id qcom_snandc_of_match[] = { 1662 { 1663 .compatible = "qcom,ipq9574-snand", 1664 .data = &ipq9574_snandc_props, 1665 }, 1666 {} 1667 }; 1668 MODULE_DEVICE_TABLE(of, qcom_snandc_of_match); 1669 1670 static struct platform_driver qcom_spi_driver = { 1671 .driver = { 1672 .name = "qcom_snand", 1673 .of_match_table = qcom_snandc_of_match, 1674 }, 1675 .probe = qcom_spi_probe, 1676 .remove = qcom_spi_remove, 1677 }; 1678 module_platform_driver(qcom_spi_driver); 1679 1680 MODULE_DESCRIPTION("SPI driver for QPIC QSPI cores"); 1681 MODULE_AUTHOR("Md Sadre Alam <quic_mdalam@quicinc.com>"); 1682 MODULE_LICENSE("GPL"); 1683 1684