1 /* 2 * Copyright (C) 2005 Stephen Street / StreetFire Sound Labs 3 * Copyright (C) 2013, Intel Corporation 4 * 5 * This program is free software; you can redistribute it and/or modify 6 * it under the terms of the GNU General Public License as published by 7 * the Free Software Foundation; either version 2 of the License, or 8 * (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 */ 15 16 #include <linux/bitops.h> 17 #include <linux/init.h> 18 #include <linux/module.h> 19 #include <linux/device.h> 20 #include <linux/ioport.h> 21 #include <linux/errno.h> 22 #include <linux/err.h> 23 #include <linux/interrupt.h> 24 #include <linux/kernel.h> 25 #include <linux/pci.h> 26 #include <linux/platform_device.h> 27 #include <linux/spi/pxa2xx_spi.h> 28 #include <linux/spi/spi.h> 29 #include <linux/delay.h> 30 #include <linux/gpio.h> 31 #include <linux/gpio/consumer.h> 32 #include <linux/slab.h> 33 #include <linux/clk.h> 34 #include <linux/pm_runtime.h> 35 #include <linux/acpi.h> 36 37 #include "spi-pxa2xx.h" 38 39 MODULE_AUTHOR("Stephen Street"); 40 MODULE_DESCRIPTION("PXA2xx SSP SPI Controller"); 41 MODULE_LICENSE("GPL"); 42 MODULE_ALIAS("platform:pxa2xx-spi"); 43 44 #define TIMOUT_DFLT 1000 45 46 /* 47 * for testing SSCR1 changes that require SSP restart, basically 48 * everything except the service and interrupt enables, the pxa270 developer 49 * manual says only SSCR1_SCFR, SSCR1_SPH, SSCR1_SPO need to be in this 50 * list, but the PXA255 dev man says all bits without really meaning the 51 * service and interrupt enables 52 */ 53 #define SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ 54 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ 55 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ 56 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ 57 | SSCR1_RFT | SSCR1_TFT | SSCR1_MWDS \ 58 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 59 60 #define QUARK_X1000_SSCR1_CHANGE_MASK (QUARK_X1000_SSCR1_STRF \ 61 | QUARK_X1000_SSCR1_EFWR \ 62 | QUARK_X1000_SSCR1_RFT \ 63 | QUARK_X1000_SSCR1_TFT \ 64 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 65 66 #define CE4100_SSCR1_CHANGE_MASK (SSCR1_TTELP | SSCR1_TTE | SSCR1_SCFR \ 67 | SSCR1_ECRA | SSCR1_ECRB | SSCR1_SCLKDIR \ 68 | SSCR1_SFRMDIR | SSCR1_RWOT | SSCR1_TRAIL \ 69 | SSCR1_IFS | SSCR1_STRF | SSCR1_EFWR \ 70 | CE4100_SSCR1_RFT | CE4100_SSCR1_TFT | SSCR1_MWDS \ 71 | SSCR1_SPH | SSCR1_SPO | SSCR1_LBM) 72 73 #define LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE BIT(24) 74 #define LPSS_CS_CONTROL_SW_MODE BIT(0) 75 #define LPSS_CS_CONTROL_CS_HIGH BIT(1) 76 #define LPSS_CAPS_CS_EN_SHIFT 9 77 #define LPSS_CAPS_CS_EN_MASK (0xf << LPSS_CAPS_CS_EN_SHIFT) 78 79 struct lpss_config { 80 /* LPSS offset from drv_data->ioaddr */ 81 unsigned offset; 82 /* Register offsets from drv_data->lpss_base or -1 */ 83 int reg_general; 84 int reg_ssp; 85 int reg_cs_ctrl; 86 int reg_capabilities; 87 /* FIFO thresholds */ 88 u32 rx_threshold; 89 u32 tx_threshold_lo; 90 u32 tx_threshold_hi; 91 /* Chip select control */ 92 unsigned cs_sel_shift; 93 unsigned cs_sel_mask; 94 unsigned cs_num; 95 }; 96 97 /* Keep these sorted with enum pxa_ssp_type */ 98 static const struct lpss_config lpss_platforms[] = { 99 { /* LPSS_LPT_SSP */ 100 .offset = 0x800, 101 .reg_general = 0x08, 102 .reg_ssp = 0x0c, 103 .reg_cs_ctrl = 0x18, 104 .reg_capabilities = -1, 105 .rx_threshold = 64, 106 .tx_threshold_lo = 160, 107 .tx_threshold_hi = 224, 108 }, 109 { /* LPSS_BYT_SSP */ 110 .offset = 0x400, 111 .reg_general = 0x08, 112 .reg_ssp = 0x0c, 113 .reg_cs_ctrl = 0x18, 114 .reg_capabilities = -1, 115 .rx_threshold = 64, 116 .tx_threshold_lo = 160, 117 .tx_threshold_hi = 224, 118 }, 119 { /* LPSS_BSW_SSP */ 120 .offset = 0x400, 121 .reg_general = 0x08, 122 .reg_ssp = 0x0c, 123 .reg_cs_ctrl = 0x18, 124 .reg_capabilities = -1, 125 .rx_threshold = 64, 126 .tx_threshold_lo = 160, 127 .tx_threshold_hi = 224, 128 .cs_sel_shift = 2, 129 .cs_sel_mask = 1 << 2, 130 .cs_num = 2, 131 }, 132 { /* LPSS_SPT_SSP */ 133 .offset = 0x200, 134 .reg_general = -1, 135 .reg_ssp = 0x20, 136 .reg_cs_ctrl = 0x24, 137 .reg_capabilities = -1, 138 .rx_threshold = 1, 139 .tx_threshold_lo = 32, 140 .tx_threshold_hi = 56, 141 }, 142 { /* LPSS_BXT_SSP */ 143 .offset = 0x200, 144 .reg_general = -1, 145 .reg_ssp = 0x20, 146 .reg_cs_ctrl = 0x24, 147 .reg_capabilities = 0xfc, 148 .rx_threshold = 1, 149 .tx_threshold_lo = 16, 150 .tx_threshold_hi = 48, 151 .cs_sel_shift = 8, 152 .cs_sel_mask = 3 << 8, 153 }, 154 { /* LPSS_CNL_SSP */ 155 .offset = 0x200, 156 .reg_general = -1, 157 .reg_ssp = 0x20, 158 .reg_cs_ctrl = 0x24, 159 .reg_capabilities = 0xfc, 160 .rx_threshold = 1, 161 .tx_threshold_lo = 32, 162 .tx_threshold_hi = 56, 163 .cs_sel_shift = 8, 164 .cs_sel_mask = 3 << 8, 165 }, 166 }; 167 168 static inline const struct lpss_config 169 *lpss_get_config(const struct driver_data *drv_data) 170 { 171 return &lpss_platforms[drv_data->ssp_type - LPSS_LPT_SSP]; 172 } 173 174 static bool is_lpss_ssp(const struct driver_data *drv_data) 175 { 176 switch (drv_data->ssp_type) { 177 case LPSS_LPT_SSP: 178 case LPSS_BYT_SSP: 179 case LPSS_BSW_SSP: 180 case LPSS_SPT_SSP: 181 case LPSS_BXT_SSP: 182 case LPSS_CNL_SSP: 183 return true; 184 default: 185 return false; 186 } 187 } 188 189 static bool is_quark_x1000_ssp(const struct driver_data *drv_data) 190 { 191 return drv_data->ssp_type == QUARK_X1000_SSP; 192 } 193 194 static u32 pxa2xx_spi_get_ssrc1_change_mask(const struct driver_data *drv_data) 195 { 196 switch (drv_data->ssp_type) { 197 case QUARK_X1000_SSP: 198 return QUARK_X1000_SSCR1_CHANGE_MASK; 199 case CE4100_SSP: 200 return CE4100_SSCR1_CHANGE_MASK; 201 default: 202 return SSCR1_CHANGE_MASK; 203 } 204 } 205 206 static u32 207 pxa2xx_spi_get_rx_default_thre(const struct driver_data *drv_data) 208 { 209 switch (drv_data->ssp_type) { 210 case QUARK_X1000_SSP: 211 return RX_THRESH_QUARK_X1000_DFLT; 212 case CE4100_SSP: 213 return RX_THRESH_CE4100_DFLT; 214 default: 215 return RX_THRESH_DFLT; 216 } 217 } 218 219 static bool pxa2xx_spi_txfifo_full(const struct driver_data *drv_data) 220 { 221 u32 mask; 222 223 switch (drv_data->ssp_type) { 224 case QUARK_X1000_SSP: 225 mask = QUARK_X1000_SSSR_TFL_MASK; 226 break; 227 case CE4100_SSP: 228 mask = CE4100_SSSR_TFL_MASK; 229 break; 230 default: 231 mask = SSSR_TFL_MASK; 232 break; 233 } 234 235 return (pxa2xx_spi_read(drv_data, SSSR) & mask) == mask; 236 } 237 238 static void pxa2xx_spi_clear_rx_thre(const struct driver_data *drv_data, 239 u32 *sccr1_reg) 240 { 241 u32 mask; 242 243 switch (drv_data->ssp_type) { 244 case QUARK_X1000_SSP: 245 mask = QUARK_X1000_SSCR1_RFT; 246 break; 247 case CE4100_SSP: 248 mask = CE4100_SSCR1_RFT; 249 break; 250 default: 251 mask = SSCR1_RFT; 252 break; 253 } 254 *sccr1_reg &= ~mask; 255 } 256 257 static void pxa2xx_spi_set_rx_thre(const struct driver_data *drv_data, 258 u32 *sccr1_reg, u32 threshold) 259 { 260 switch (drv_data->ssp_type) { 261 case QUARK_X1000_SSP: 262 *sccr1_reg |= QUARK_X1000_SSCR1_RxTresh(threshold); 263 break; 264 case CE4100_SSP: 265 *sccr1_reg |= CE4100_SSCR1_RxTresh(threshold); 266 break; 267 default: 268 *sccr1_reg |= SSCR1_RxTresh(threshold); 269 break; 270 } 271 } 272 273 static u32 pxa2xx_configure_sscr0(const struct driver_data *drv_data, 274 u32 clk_div, u8 bits) 275 { 276 switch (drv_data->ssp_type) { 277 case QUARK_X1000_SSP: 278 return clk_div 279 | QUARK_X1000_SSCR0_Motorola 280 | QUARK_X1000_SSCR0_DataSize(bits > 32 ? 8 : bits) 281 | SSCR0_SSE; 282 default: 283 return clk_div 284 | SSCR0_Motorola 285 | SSCR0_DataSize(bits > 16 ? bits - 16 : bits) 286 | SSCR0_SSE 287 | (bits > 16 ? SSCR0_EDSS : 0); 288 } 289 } 290 291 /* 292 * Read and write LPSS SSP private registers. Caller must first check that 293 * is_lpss_ssp() returns true before these can be called. 294 */ 295 static u32 __lpss_ssp_read_priv(struct driver_data *drv_data, unsigned offset) 296 { 297 WARN_ON(!drv_data->lpss_base); 298 return readl(drv_data->lpss_base + offset); 299 } 300 301 static void __lpss_ssp_write_priv(struct driver_data *drv_data, 302 unsigned offset, u32 value) 303 { 304 WARN_ON(!drv_data->lpss_base); 305 writel(value, drv_data->lpss_base + offset); 306 } 307 308 /* 309 * lpss_ssp_setup - perform LPSS SSP specific setup 310 * @drv_data: pointer to the driver private data 311 * 312 * Perform LPSS SSP specific setup. This function must be called first if 313 * one is going to use LPSS SSP private registers. 314 */ 315 static void lpss_ssp_setup(struct driver_data *drv_data) 316 { 317 const struct lpss_config *config; 318 u32 value; 319 320 config = lpss_get_config(drv_data); 321 drv_data->lpss_base = drv_data->ioaddr + config->offset; 322 323 /* Enable software chip select control */ 324 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); 325 value &= ~(LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH); 326 value |= LPSS_CS_CONTROL_SW_MODE | LPSS_CS_CONTROL_CS_HIGH; 327 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); 328 329 /* Enable multiblock DMA transfers */ 330 if (drv_data->master_info->enable_dma) { 331 __lpss_ssp_write_priv(drv_data, config->reg_ssp, 1); 332 333 if (config->reg_general >= 0) { 334 value = __lpss_ssp_read_priv(drv_data, 335 config->reg_general); 336 value |= LPSS_GENERAL_REG_RXTO_HOLDOFF_DISABLE; 337 __lpss_ssp_write_priv(drv_data, 338 config->reg_general, value); 339 } 340 } 341 } 342 343 static void lpss_ssp_select_cs(struct spi_device *spi, 344 const struct lpss_config *config) 345 { 346 struct driver_data *drv_data = 347 spi_controller_get_devdata(spi->controller); 348 u32 value, cs; 349 350 if (!config->cs_sel_mask) 351 return; 352 353 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); 354 355 cs = spi->chip_select; 356 cs <<= config->cs_sel_shift; 357 if (cs != (value & config->cs_sel_mask)) { 358 /* 359 * When switching another chip select output active the 360 * output must be selected first and wait 2 ssp_clk cycles 361 * before changing state to active. Otherwise a short 362 * glitch will occur on the previous chip select since 363 * output select is latched but state control is not. 364 */ 365 value &= ~config->cs_sel_mask; 366 value |= cs; 367 __lpss_ssp_write_priv(drv_data, 368 config->reg_cs_ctrl, value); 369 ndelay(1000000000 / 370 (drv_data->master->max_speed_hz / 2)); 371 } 372 } 373 374 static void lpss_ssp_cs_control(struct spi_device *spi, bool enable) 375 { 376 struct driver_data *drv_data = 377 spi_controller_get_devdata(spi->controller); 378 const struct lpss_config *config; 379 u32 value; 380 381 config = lpss_get_config(drv_data); 382 383 if (enable) 384 lpss_ssp_select_cs(spi, config); 385 386 value = __lpss_ssp_read_priv(drv_data, config->reg_cs_ctrl); 387 if (enable) 388 value &= ~LPSS_CS_CONTROL_CS_HIGH; 389 else 390 value |= LPSS_CS_CONTROL_CS_HIGH; 391 __lpss_ssp_write_priv(drv_data, config->reg_cs_ctrl, value); 392 } 393 394 static void cs_assert(struct spi_device *spi) 395 { 396 struct chip_data *chip = spi_get_ctldata(spi); 397 struct driver_data *drv_data = 398 spi_controller_get_devdata(spi->controller); 399 400 if (drv_data->ssp_type == CE4100_SSP) { 401 pxa2xx_spi_write(drv_data, SSSR, chip->frm); 402 return; 403 } 404 405 if (chip->cs_control) { 406 chip->cs_control(PXA2XX_CS_ASSERT); 407 return; 408 } 409 410 if (chip->gpiod_cs) { 411 gpiod_set_value(chip->gpiod_cs, chip->gpio_cs_inverted); 412 return; 413 } 414 415 if (is_lpss_ssp(drv_data)) 416 lpss_ssp_cs_control(spi, true); 417 } 418 419 static void cs_deassert(struct spi_device *spi) 420 { 421 struct chip_data *chip = spi_get_ctldata(spi); 422 struct driver_data *drv_data = 423 spi_controller_get_devdata(spi->controller); 424 unsigned long timeout; 425 426 if (drv_data->ssp_type == CE4100_SSP) 427 return; 428 429 /* Wait until SSP becomes idle before deasserting the CS */ 430 timeout = jiffies + msecs_to_jiffies(10); 431 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY && 432 !time_after(jiffies, timeout)) 433 cpu_relax(); 434 435 if (chip->cs_control) { 436 chip->cs_control(PXA2XX_CS_DEASSERT); 437 return; 438 } 439 440 if (chip->gpiod_cs) { 441 gpiod_set_value(chip->gpiod_cs, !chip->gpio_cs_inverted); 442 return; 443 } 444 445 if (is_lpss_ssp(drv_data)) 446 lpss_ssp_cs_control(spi, false); 447 } 448 449 static void pxa2xx_spi_set_cs(struct spi_device *spi, bool level) 450 { 451 if (level) 452 cs_deassert(spi); 453 else 454 cs_assert(spi); 455 } 456 457 int pxa2xx_spi_flush(struct driver_data *drv_data) 458 { 459 unsigned long limit = loops_per_jiffy << 1; 460 461 do { 462 while (pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 463 pxa2xx_spi_read(drv_data, SSDR); 464 } while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_BSY) && --limit); 465 write_SSSR_CS(drv_data, SSSR_ROR); 466 467 return limit; 468 } 469 470 static int null_writer(struct driver_data *drv_data) 471 { 472 u8 n_bytes = drv_data->n_bytes; 473 474 if (pxa2xx_spi_txfifo_full(drv_data) 475 || (drv_data->tx == drv_data->tx_end)) 476 return 0; 477 478 pxa2xx_spi_write(drv_data, SSDR, 0); 479 drv_data->tx += n_bytes; 480 481 return 1; 482 } 483 484 static int null_reader(struct driver_data *drv_data) 485 { 486 u8 n_bytes = drv_data->n_bytes; 487 488 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 489 && (drv_data->rx < drv_data->rx_end)) { 490 pxa2xx_spi_read(drv_data, SSDR); 491 drv_data->rx += n_bytes; 492 } 493 494 return drv_data->rx == drv_data->rx_end; 495 } 496 497 static int u8_writer(struct driver_data *drv_data) 498 { 499 if (pxa2xx_spi_txfifo_full(drv_data) 500 || (drv_data->tx == drv_data->tx_end)) 501 return 0; 502 503 pxa2xx_spi_write(drv_data, SSDR, *(u8 *)(drv_data->tx)); 504 ++drv_data->tx; 505 506 return 1; 507 } 508 509 static int u8_reader(struct driver_data *drv_data) 510 { 511 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 512 && (drv_data->rx < drv_data->rx_end)) { 513 *(u8 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); 514 ++drv_data->rx; 515 } 516 517 return drv_data->rx == drv_data->rx_end; 518 } 519 520 static int u16_writer(struct driver_data *drv_data) 521 { 522 if (pxa2xx_spi_txfifo_full(drv_data) 523 || (drv_data->tx == drv_data->tx_end)) 524 return 0; 525 526 pxa2xx_spi_write(drv_data, SSDR, *(u16 *)(drv_data->tx)); 527 drv_data->tx += 2; 528 529 return 1; 530 } 531 532 static int u16_reader(struct driver_data *drv_data) 533 { 534 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 535 && (drv_data->rx < drv_data->rx_end)) { 536 *(u16 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); 537 drv_data->rx += 2; 538 } 539 540 return drv_data->rx == drv_data->rx_end; 541 } 542 543 static int u32_writer(struct driver_data *drv_data) 544 { 545 if (pxa2xx_spi_txfifo_full(drv_data) 546 || (drv_data->tx == drv_data->tx_end)) 547 return 0; 548 549 pxa2xx_spi_write(drv_data, SSDR, *(u32 *)(drv_data->tx)); 550 drv_data->tx += 4; 551 552 return 1; 553 } 554 555 static int u32_reader(struct driver_data *drv_data) 556 { 557 while ((pxa2xx_spi_read(drv_data, SSSR) & SSSR_RNE) 558 && (drv_data->rx < drv_data->rx_end)) { 559 *(u32 *)(drv_data->rx) = pxa2xx_spi_read(drv_data, SSDR); 560 drv_data->rx += 4; 561 } 562 563 return drv_data->rx == drv_data->rx_end; 564 } 565 566 static void reset_sccr1(struct driver_data *drv_data) 567 { 568 struct chip_data *chip = 569 spi_get_ctldata(drv_data->master->cur_msg->spi); 570 u32 sccr1_reg; 571 572 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1; 573 switch (drv_data->ssp_type) { 574 case QUARK_X1000_SSP: 575 sccr1_reg &= ~QUARK_X1000_SSCR1_RFT; 576 break; 577 case CE4100_SSP: 578 sccr1_reg &= ~CE4100_SSCR1_RFT; 579 break; 580 default: 581 sccr1_reg &= ~SSCR1_RFT; 582 break; 583 } 584 sccr1_reg |= chip->threshold; 585 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); 586 } 587 588 static void int_error_stop(struct driver_data *drv_data, const char* msg) 589 { 590 /* Stop and reset SSP */ 591 write_SSSR_CS(drv_data, drv_data->clear_sr); 592 reset_sccr1(drv_data); 593 if (!pxa25x_ssp_comp(drv_data)) 594 pxa2xx_spi_write(drv_data, SSTO, 0); 595 pxa2xx_spi_flush(drv_data); 596 pxa2xx_spi_write(drv_data, SSCR0, 597 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); 598 599 dev_err(&drv_data->pdev->dev, "%s\n", msg); 600 601 drv_data->master->cur_msg->status = -EIO; 602 spi_finalize_current_transfer(drv_data->master); 603 } 604 605 static void int_transfer_complete(struct driver_data *drv_data) 606 { 607 /* Clear and disable interrupts */ 608 write_SSSR_CS(drv_data, drv_data->clear_sr); 609 reset_sccr1(drv_data); 610 if (!pxa25x_ssp_comp(drv_data)) 611 pxa2xx_spi_write(drv_data, SSTO, 0); 612 613 spi_finalize_current_transfer(drv_data->master); 614 } 615 616 static irqreturn_t interrupt_transfer(struct driver_data *drv_data) 617 { 618 u32 irq_mask = (pxa2xx_spi_read(drv_data, SSCR1) & SSCR1_TIE) ? 619 drv_data->mask_sr : drv_data->mask_sr & ~SSSR_TFS; 620 621 u32 irq_status = pxa2xx_spi_read(drv_data, SSSR) & irq_mask; 622 623 if (irq_status & SSSR_ROR) { 624 int_error_stop(drv_data, "interrupt_transfer: fifo overrun"); 625 return IRQ_HANDLED; 626 } 627 628 if (irq_status & SSSR_TINT) { 629 pxa2xx_spi_write(drv_data, SSSR, SSSR_TINT); 630 if (drv_data->read(drv_data)) { 631 int_transfer_complete(drv_data); 632 return IRQ_HANDLED; 633 } 634 } 635 636 /* Drain rx fifo, Fill tx fifo and prevent overruns */ 637 do { 638 if (drv_data->read(drv_data)) { 639 int_transfer_complete(drv_data); 640 return IRQ_HANDLED; 641 } 642 } while (drv_data->write(drv_data)); 643 644 if (drv_data->read(drv_data)) { 645 int_transfer_complete(drv_data); 646 return IRQ_HANDLED; 647 } 648 649 if (drv_data->tx == drv_data->tx_end) { 650 u32 bytes_left; 651 u32 sccr1_reg; 652 653 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); 654 sccr1_reg &= ~SSCR1_TIE; 655 656 /* 657 * PXA25x_SSP has no timeout, set up rx threshould for the 658 * remaining RX bytes. 659 */ 660 if (pxa25x_ssp_comp(drv_data)) { 661 u32 rx_thre; 662 663 pxa2xx_spi_clear_rx_thre(drv_data, &sccr1_reg); 664 665 bytes_left = drv_data->rx_end - drv_data->rx; 666 switch (drv_data->n_bytes) { 667 case 4: 668 bytes_left >>= 1; 669 case 2: 670 bytes_left >>= 1; 671 } 672 673 rx_thre = pxa2xx_spi_get_rx_default_thre(drv_data); 674 if (rx_thre > bytes_left) 675 rx_thre = bytes_left; 676 677 pxa2xx_spi_set_rx_thre(drv_data, &sccr1_reg, rx_thre); 678 } 679 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); 680 } 681 682 /* We did something */ 683 return IRQ_HANDLED; 684 } 685 686 static void handle_bad_msg(struct driver_data *drv_data) 687 { 688 pxa2xx_spi_write(drv_data, SSCR0, 689 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); 690 pxa2xx_spi_write(drv_data, SSCR1, 691 pxa2xx_spi_read(drv_data, SSCR1) & ~drv_data->int_cr1); 692 if (!pxa25x_ssp_comp(drv_data)) 693 pxa2xx_spi_write(drv_data, SSTO, 0); 694 write_SSSR_CS(drv_data, drv_data->clear_sr); 695 696 dev_err(&drv_data->pdev->dev, 697 "bad message state in interrupt handler\n"); 698 } 699 700 static irqreturn_t ssp_int(int irq, void *dev_id) 701 { 702 struct driver_data *drv_data = dev_id; 703 u32 sccr1_reg; 704 u32 mask = drv_data->mask_sr; 705 u32 status; 706 707 /* 708 * The IRQ might be shared with other peripherals so we must first 709 * check that are we RPM suspended or not. If we are we assume that 710 * the IRQ was not for us (we shouldn't be RPM suspended when the 711 * interrupt is enabled). 712 */ 713 if (pm_runtime_suspended(&drv_data->pdev->dev)) 714 return IRQ_NONE; 715 716 /* 717 * If the device is not yet in RPM suspended state and we get an 718 * interrupt that is meant for another device, check if status bits 719 * are all set to one. That means that the device is already 720 * powered off. 721 */ 722 status = pxa2xx_spi_read(drv_data, SSSR); 723 if (status == ~0) 724 return IRQ_NONE; 725 726 sccr1_reg = pxa2xx_spi_read(drv_data, SSCR1); 727 728 /* Ignore possible writes if we don't need to write */ 729 if (!(sccr1_reg & SSCR1_TIE)) 730 mask &= ~SSSR_TFS; 731 732 /* Ignore RX timeout interrupt if it is disabled */ 733 if (!(sccr1_reg & SSCR1_TINTE)) 734 mask &= ~SSSR_TINT; 735 736 if (!(status & mask)) 737 return IRQ_NONE; 738 739 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg & ~drv_data->int_cr1); 740 pxa2xx_spi_write(drv_data, SSCR1, sccr1_reg); 741 742 if (!drv_data->master->cur_msg) { 743 handle_bad_msg(drv_data); 744 /* Never fail */ 745 return IRQ_HANDLED; 746 } 747 748 return drv_data->transfer_handler(drv_data); 749 } 750 751 /* 752 * The Quark SPI has an additional 24 bit register (DDS_CLK_RATE) to multiply 753 * input frequency by fractions of 2^24. It also has a divider by 5. 754 * 755 * There are formulas to get baud rate value for given input frequency and 756 * divider parameters, such as DDS_CLK_RATE and SCR: 757 * 758 * Fsys = 200MHz 759 * 760 * Fssp = Fsys * DDS_CLK_RATE / 2^24 (1) 761 * Baud rate = Fsclk = Fssp / (2 * (SCR + 1)) (2) 762 * 763 * DDS_CLK_RATE either 2^n or 2^n / 5. 764 * SCR is in range 0 .. 255 765 * 766 * Divisor = 5^i * 2^j * 2 * k 767 * i = [0, 1] i = 1 iff j = 0 or j > 3 768 * j = [0, 23] j = 0 iff i = 1 769 * k = [1, 256] 770 * Special case: j = 0, i = 1: Divisor = 2 / 5 771 * 772 * Accordingly to the specification the recommended values for DDS_CLK_RATE 773 * are: 774 * Case 1: 2^n, n = [0, 23] 775 * Case 2: 2^24 * 2 / 5 (0x666666) 776 * Case 3: less than or equal to 2^24 / 5 / 16 (0x33333) 777 * 778 * In all cases the lowest possible value is better. 779 * 780 * The function calculates parameters for all cases and chooses the one closest 781 * to the asked baud rate. 782 */ 783 static unsigned int quark_x1000_get_clk_div(int rate, u32 *dds) 784 { 785 unsigned long xtal = 200000000; 786 unsigned long fref = xtal / 2; /* mandatory division by 2, 787 see (2) */ 788 /* case 3 */ 789 unsigned long fref1 = fref / 2; /* case 1 */ 790 unsigned long fref2 = fref * 2 / 5; /* case 2 */ 791 unsigned long scale; 792 unsigned long q, q1, q2; 793 long r, r1, r2; 794 u32 mul; 795 796 /* Case 1 */ 797 798 /* Set initial value for DDS_CLK_RATE */ 799 mul = (1 << 24) >> 1; 800 801 /* Calculate initial quot */ 802 q1 = DIV_ROUND_UP(fref1, rate); 803 804 /* Scale q1 if it's too big */ 805 if (q1 > 256) { 806 /* Scale q1 to range [1, 512] */ 807 scale = fls_long(q1 - 1); 808 if (scale > 9) { 809 q1 >>= scale - 9; 810 mul >>= scale - 9; 811 } 812 813 /* Round the result if we have a remainder */ 814 q1 += q1 & 1; 815 } 816 817 /* Decrease DDS_CLK_RATE as much as we can without loss in precision */ 818 scale = __ffs(q1); 819 q1 >>= scale; 820 mul >>= scale; 821 822 /* Get the remainder */ 823 r1 = abs(fref1 / (1 << (24 - fls_long(mul))) / q1 - rate); 824 825 /* Case 2 */ 826 827 q2 = DIV_ROUND_UP(fref2, rate); 828 r2 = abs(fref2 / q2 - rate); 829 830 /* 831 * Choose the best between two: less remainder we have the better. We 832 * can't go case 2 if q2 is greater than 256 since SCR register can 833 * hold only values 0 .. 255. 834 */ 835 if (r2 >= r1 || q2 > 256) { 836 /* case 1 is better */ 837 r = r1; 838 q = q1; 839 } else { 840 /* case 2 is better */ 841 r = r2; 842 q = q2; 843 mul = (1 << 24) * 2 / 5; 844 } 845 846 /* Check case 3 only if the divisor is big enough */ 847 if (fref / rate >= 80) { 848 u64 fssp; 849 u32 m; 850 851 /* Calculate initial quot */ 852 q1 = DIV_ROUND_UP(fref, rate); 853 m = (1 << 24) / q1; 854 855 /* Get the remainder */ 856 fssp = (u64)fref * m; 857 do_div(fssp, 1 << 24); 858 r1 = abs(fssp - rate); 859 860 /* Choose this one if it suits better */ 861 if (r1 < r) { 862 /* case 3 is better */ 863 q = 1; 864 mul = m; 865 } 866 } 867 868 *dds = mul; 869 return q - 1; 870 } 871 872 static unsigned int ssp_get_clk_div(struct driver_data *drv_data, int rate) 873 { 874 unsigned long ssp_clk = drv_data->master->max_speed_hz; 875 const struct ssp_device *ssp = drv_data->ssp; 876 877 rate = min_t(int, ssp_clk, rate); 878 879 if (ssp->type == PXA25x_SSP || ssp->type == CE4100_SSP) 880 return (ssp_clk / (2 * rate) - 1) & 0xff; 881 else 882 return (ssp_clk / rate - 1) & 0xfff; 883 } 884 885 static unsigned int pxa2xx_ssp_get_clk_div(struct driver_data *drv_data, 886 int rate) 887 { 888 struct chip_data *chip = 889 spi_get_ctldata(drv_data->master->cur_msg->spi); 890 unsigned int clk_div; 891 892 switch (drv_data->ssp_type) { 893 case QUARK_X1000_SSP: 894 clk_div = quark_x1000_get_clk_div(rate, &chip->dds_rate); 895 break; 896 default: 897 clk_div = ssp_get_clk_div(drv_data, rate); 898 break; 899 } 900 return clk_div << 8; 901 } 902 903 static bool pxa2xx_spi_can_dma(struct spi_controller *master, 904 struct spi_device *spi, 905 struct spi_transfer *xfer) 906 { 907 struct chip_data *chip = spi_get_ctldata(spi); 908 909 return chip->enable_dma && 910 xfer->len <= MAX_DMA_LEN && 911 xfer->len >= chip->dma_burst_size; 912 } 913 914 static int pxa2xx_spi_transfer_one(struct spi_controller *master, 915 struct spi_device *spi, 916 struct spi_transfer *transfer) 917 { 918 struct driver_data *drv_data = spi_controller_get_devdata(master); 919 struct spi_message *message = master->cur_msg; 920 struct chip_data *chip = spi_get_ctldata(message->spi); 921 u32 dma_thresh = chip->dma_threshold; 922 u32 dma_burst = chip->dma_burst_size; 923 u32 change_mask = pxa2xx_spi_get_ssrc1_change_mask(drv_data); 924 u32 clk_div; 925 u8 bits; 926 u32 speed; 927 u32 cr0; 928 u32 cr1; 929 int err; 930 int dma_mapped; 931 932 /* Check if we can DMA this transfer */ 933 if (transfer->len > MAX_DMA_LEN && chip->enable_dma) { 934 935 /* reject already-mapped transfers; PIO won't always work */ 936 if (message->is_dma_mapped 937 || transfer->rx_dma || transfer->tx_dma) { 938 dev_err(&drv_data->pdev->dev, 939 "Mapped transfer length of %u is greater than %d\n", 940 transfer->len, MAX_DMA_LEN); 941 return -EINVAL; 942 } 943 944 /* warn ... we force this to PIO mode */ 945 dev_warn_ratelimited(&message->spi->dev, 946 "DMA disabled for transfer length %ld greater than %d\n", 947 (long)transfer->len, MAX_DMA_LEN); 948 } 949 950 /* Setup the transfer state based on the type of transfer */ 951 if (pxa2xx_spi_flush(drv_data) == 0) { 952 dev_err(&drv_data->pdev->dev, "Flush failed\n"); 953 return -EIO; 954 } 955 drv_data->n_bytes = chip->n_bytes; 956 drv_data->tx = (void *)transfer->tx_buf; 957 drv_data->tx_end = drv_data->tx + transfer->len; 958 drv_data->rx = transfer->rx_buf; 959 drv_data->rx_end = drv_data->rx + transfer->len; 960 drv_data->write = drv_data->tx ? chip->write : null_writer; 961 drv_data->read = drv_data->rx ? chip->read : null_reader; 962 963 /* Change speed and bit per word on a per transfer */ 964 bits = transfer->bits_per_word; 965 speed = transfer->speed_hz; 966 967 clk_div = pxa2xx_ssp_get_clk_div(drv_data, speed); 968 969 if (bits <= 8) { 970 drv_data->n_bytes = 1; 971 drv_data->read = drv_data->read != null_reader ? 972 u8_reader : null_reader; 973 drv_data->write = drv_data->write != null_writer ? 974 u8_writer : null_writer; 975 } else if (bits <= 16) { 976 drv_data->n_bytes = 2; 977 drv_data->read = drv_data->read != null_reader ? 978 u16_reader : null_reader; 979 drv_data->write = drv_data->write != null_writer ? 980 u16_writer : null_writer; 981 } else if (bits <= 32) { 982 drv_data->n_bytes = 4; 983 drv_data->read = drv_data->read != null_reader ? 984 u32_reader : null_reader; 985 drv_data->write = drv_data->write != null_writer ? 986 u32_writer : null_writer; 987 } 988 /* 989 * if bits/word is changed in dma mode, then must check the 990 * thresholds and burst also 991 */ 992 if (chip->enable_dma) { 993 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, 994 message->spi, 995 bits, &dma_burst, 996 &dma_thresh)) 997 dev_warn_ratelimited(&message->spi->dev, 998 "DMA burst size reduced to match bits_per_word\n"); 999 } 1000 1001 dma_mapped = master->can_dma && 1002 master->can_dma(master, message->spi, transfer) && 1003 master->cur_msg_mapped; 1004 if (dma_mapped) { 1005 1006 /* Ensure we have the correct interrupt handler */ 1007 drv_data->transfer_handler = pxa2xx_spi_dma_transfer; 1008 1009 err = pxa2xx_spi_dma_prepare(drv_data, transfer); 1010 if (err) 1011 return err; 1012 1013 /* Clear status and start DMA engine */ 1014 cr1 = chip->cr1 | dma_thresh | drv_data->dma_cr1; 1015 pxa2xx_spi_write(drv_data, SSSR, drv_data->clear_sr); 1016 1017 pxa2xx_spi_dma_start(drv_data); 1018 } else { 1019 /* Ensure we have the correct interrupt handler */ 1020 drv_data->transfer_handler = interrupt_transfer; 1021 1022 /* Clear status */ 1023 cr1 = chip->cr1 | chip->threshold | drv_data->int_cr1; 1024 write_SSSR_CS(drv_data, drv_data->clear_sr); 1025 } 1026 1027 /* NOTE: PXA25x_SSP _could_ use external clocking ... */ 1028 cr0 = pxa2xx_configure_sscr0(drv_data, clk_div, bits); 1029 if (!pxa25x_ssp_comp(drv_data)) 1030 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n", 1031 master->max_speed_hz 1032 / (1 + ((cr0 & SSCR0_SCR(0xfff)) >> 8)), 1033 dma_mapped ? "DMA" : "PIO"); 1034 else 1035 dev_dbg(&message->spi->dev, "%u Hz actual, %s\n", 1036 master->max_speed_hz / 2 1037 / (1 + ((cr0 & SSCR0_SCR(0x0ff)) >> 8)), 1038 dma_mapped ? "DMA" : "PIO"); 1039 1040 if (is_lpss_ssp(drv_data)) { 1041 if ((pxa2xx_spi_read(drv_data, SSIRF) & 0xff) 1042 != chip->lpss_rx_threshold) 1043 pxa2xx_spi_write(drv_data, SSIRF, 1044 chip->lpss_rx_threshold); 1045 if ((pxa2xx_spi_read(drv_data, SSITF) & 0xffff) 1046 != chip->lpss_tx_threshold) 1047 pxa2xx_spi_write(drv_data, SSITF, 1048 chip->lpss_tx_threshold); 1049 } 1050 1051 if (is_quark_x1000_ssp(drv_data) && 1052 (pxa2xx_spi_read(drv_data, DDS_RATE) != chip->dds_rate)) 1053 pxa2xx_spi_write(drv_data, DDS_RATE, chip->dds_rate); 1054 1055 /* see if we need to reload the config registers */ 1056 if ((pxa2xx_spi_read(drv_data, SSCR0) != cr0) 1057 || (pxa2xx_spi_read(drv_data, SSCR1) & change_mask) 1058 != (cr1 & change_mask)) { 1059 /* stop the SSP, and update the other bits */ 1060 pxa2xx_spi_write(drv_data, SSCR0, cr0 & ~SSCR0_SSE); 1061 if (!pxa25x_ssp_comp(drv_data)) 1062 pxa2xx_spi_write(drv_data, SSTO, chip->timeout); 1063 /* first set CR1 without interrupt and service enables */ 1064 pxa2xx_spi_write(drv_data, SSCR1, cr1 & change_mask); 1065 /* restart the SSP */ 1066 pxa2xx_spi_write(drv_data, SSCR0, cr0); 1067 1068 } else { 1069 if (!pxa25x_ssp_comp(drv_data)) 1070 pxa2xx_spi_write(drv_data, SSTO, chip->timeout); 1071 } 1072 1073 /* 1074 * Release the data by enabling service requests and interrupts, 1075 * without changing any mode bits 1076 */ 1077 pxa2xx_spi_write(drv_data, SSCR1, cr1); 1078 1079 return 1; 1080 } 1081 1082 static void pxa2xx_spi_handle_err(struct spi_controller *master, 1083 struct spi_message *msg) 1084 { 1085 struct driver_data *drv_data = spi_controller_get_devdata(master); 1086 1087 /* Disable the SSP */ 1088 pxa2xx_spi_write(drv_data, SSCR0, 1089 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); 1090 /* Clear and disable interrupts and service requests */ 1091 write_SSSR_CS(drv_data, drv_data->clear_sr); 1092 pxa2xx_spi_write(drv_data, SSCR1, 1093 pxa2xx_spi_read(drv_data, SSCR1) 1094 & ~(drv_data->int_cr1 | drv_data->dma_cr1)); 1095 if (!pxa25x_ssp_comp(drv_data)) 1096 pxa2xx_spi_write(drv_data, SSTO, 0); 1097 1098 /* 1099 * Stop the DMA if running. Note DMA callback handler may have unset 1100 * the dma_running already, which is fine as stopping is not needed 1101 * then but we shouldn't rely this flag for anything else than 1102 * stopping. For instance to differentiate between PIO and DMA 1103 * transfers. 1104 */ 1105 if (atomic_read(&drv_data->dma_running)) 1106 pxa2xx_spi_dma_stop(drv_data); 1107 } 1108 1109 static int pxa2xx_spi_unprepare_transfer(struct spi_controller *master) 1110 { 1111 struct driver_data *drv_data = spi_controller_get_devdata(master); 1112 1113 /* Disable the SSP now */ 1114 pxa2xx_spi_write(drv_data, SSCR0, 1115 pxa2xx_spi_read(drv_data, SSCR0) & ~SSCR0_SSE); 1116 1117 return 0; 1118 } 1119 1120 static int setup_cs(struct spi_device *spi, struct chip_data *chip, 1121 struct pxa2xx_spi_chip *chip_info) 1122 { 1123 struct driver_data *drv_data = 1124 spi_controller_get_devdata(spi->controller); 1125 struct gpio_desc *gpiod; 1126 int err = 0; 1127 1128 if (chip == NULL) 1129 return 0; 1130 1131 if (drv_data->cs_gpiods) { 1132 gpiod = drv_data->cs_gpiods[spi->chip_select]; 1133 if (gpiod) { 1134 chip->gpiod_cs = gpiod; 1135 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; 1136 gpiod_set_value(gpiod, chip->gpio_cs_inverted); 1137 } 1138 1139 return 0; 1140 } 1141 1142 if (chip_info == NULL) 1143 return 0; 1144 1145 /* NOTE: setup() can be called multiple times, possibly with 1146 * different chip_info, release previously requested GPIO 1147 */ 1148 if (chip->gpiod_cs) { 1149 gpiod_put(chip->gpiod_cs); 1150 chip->gpiod_cs = NULL; 1151 } 1152 1153 /* If (*cs_control) is provided, ignore GPIO chip select */ 1154 if (chip_info->cs_control) { 1155 chip->cs_control = chip_info->cs_control; 1156 return 0; 1157 } 1158 1159 if (gpio_is_valid(chip_info->gpio_cs)) { 1160 err = gpio_request(chip_info->gpio_cs, "SPI_CS"); 1161 if (err) { 1162 dev_err(&spi->dev, "failed to request chip select GPIO%d\n", 1163 chip_info->gpio_cs); 1164 return err; 1165 } 1166 1167 gpiod = gpio_to_desc(chip_info->gpio_cs); 1168 chip->gpiod_cs = gpiod; 1169 chip->gpio_cs_inverted = spi->mode & SPI_CS_HIGH; 1170 1171 err = gpiod_direction_output(gpiod, !chip->gpio_cs_inverted); 1172 } 1173 1174 return err; 1175 } 1176 1177 static int setup(struct spi_device *spi) 1178 { 1179 struct pxa2xx_spi_chip *chip_info; 1180 struct chip_data *chip; 1181 const struct lpss_config *config; 1182 struct driver_data *drv_data = 1183 spi_controller_get_devdata(spi->controller); 1184 uint tx_thres, tx_hi_thres, rx_thres; 1185 1186 switch (drv_data->ssp_type) { 1187 case QUARK_X1000_SSP: 1188 tx_thres = TX_THRESH_QUARK_X1000_DFLT; 1189 tx_hi_thres = 0; 1190 rx_thres = RX_THRESH_QUARK_X1000_DFLT; 1191 break; 1192 case CE4100_SSP: 1193 tx_thres = TX_THRESH_CE4100_DFLT; 1194 tx_hi_thres = 0; 1195 rx_thres = RX_THRESH_CE4100_DFLT; 1196 break; 1197 case LPSS_LPT_SSP: 1198 case LPSS_BYT_SSP: 1199 case LPSS_BSW_SSP: 1200 case LPSS_SPT_SSP: 1201 case LPSS_BXT_SSP: 1202 case LPSS_CNL_SSP: 1203 config = lpss_get_config(drv_data); 1204 tx_thres = config->tx_threshold_lo; 1205 tx_hi_thres = config->tx_threshold_hi; 1206 rx_thres = config->rx_threshold; 1207 break; 1208 default: 1209 tx_thres = TX_THRESH_DFLT; 1210 tx_hi_thres = 0; 1211 rx_thres = RX_THRESH_DFLT; 1212 break; 1213 } 1214 1215 /* Only alloc on first setup */ 1216 chip = spi_get_ctldata(spi); 1217 if (!chip) { 1218 chip = kzalloc(sizeof(struct chip_data), GFP_KERNEL); 1219 if (!chip) 1220 return -ENOMEM; 1221 1222 if (drv_data->ssp_type == CE4100_SSP) { 1223 if (spi->chip_select > 4) { 1224 dev_err(&spi->dev, 1225 "failed setup: cs number must not be > 4.\n"); 1226 kfree(chip); 1227 return -EINVAL; 1228 } 1229 1230 chip->frm = spi->chip_select; 1231 } 1232 chip->enable_dma = drv_data->master_info->enable_dma; 1233 chip->timeout = TIMOUT_DFLT; 1234 } 1235 1236 /* protocol drivers may change the chip settings, so... 1237 * if chip_info exists, use it */ 1238 chip_info = spi->controller_data; 1239 1240 /* chip_info isn't always needed */ 1241 chip->cr1 = 0; 1242 if (chip_info) { 1243 if (chip_info->timeout) 1244 chip->timeout = chip_info->timeout; 1245 if (chip_info->tx_threshold) 1246 tx_thres = chip_info->tx_threshold; 1247 if (chip_info->tx_hi_threshold) 1248 tx_hi_thres = chip_info->tx_hi_threshold; 1249 if (chip_info->rx_threshold) 1250 rx_thres = chip_info->rx_threshold; 1251 chip->dma_threshold = 0; 1252 if (chip_info->enable_loopback) 1253 chip->cr1 = SSCR1_LBM; 1254 } 1255 1256 chip->lpss_rx_threshold = SSIRF_RxThresh(rx_thres); 1257 chip->lpss_tx_threshold = SSITF_TxLoThresh(tx_thres) 1258 | SSITF_TxHiThresh(tx_hi_thres); 1259 1260 /* set dma burst and threshold outside of chip_info path so that if 1261 * chip_info goes away after setting chip->enable_dma, the 1262 * burst and threshold can still respond to changes in bits_per_word */ 1263 if (chip->enable_dma) { 1264 /* set up legal burst and threshold for dma */ 1265 if (pxa2xx_spi_set_dma_burst_and_threshold(chip, spi, 1266 spi->bits_per_word, 1267 &chip->dma_burst_size, 1268 &chip->dma_threshold)) { 1269 dev_warn(&spi->dev, 1270 "in setup: DMA burst size reduced to match bits_per_word\n"); 1271 } 1272 } 1273 1274 switch (drv_data->ssp_type) { 1275 case QUARK_X1000_SSP: 1276 chip->threshold = (QUARK_X1000_SSCR1_RxTresh(rx_thres) 1277 & QUARK_X1000_SSCR1_RFT) 1278 | (QUARK_X1000_SSCR1_TxTresh(tx_thres) 1279 & QUARK_X1000_SSCR1_TFT); 1280 break; 1281 case CE4100_SSP: 1282 chip->threshold = (CE4100_SSCR1_RxTresh(rx_thres) & CE4100_SSCR1_RFT) | 1283 (CE4100_SSCR1_TxTresh(tx_thres) & CE4100_SSCR1_TFT); 1284 break; 1285 default: 1286 chip->threshold = (SSCR1_RxTresh(rx_thres) & SSCR1_RFT) | 1287 (SSCR1_TxTresh(tx_thres) & SSCR1_TFT); 1288 break; 1289 } 1290 1291 chip->cr1 &= ~(SSCR1_SPO | SSCR1_SPH); 1292 chip->cr1 |= (((spi->mode & SPI_CPHA) != 0) ? SSCR1_SPH : 0) 1293 | (((spi->mode & SPI_CPOL) != 0) ? SSCR1_SPO : 0); 1294 1295 if (spi->mode & SPI_LOOP) 1296 chip->cr1 |= SSCR1_LBM; 1297 1298 if (spi->bits_per_word <= 8) { 1299 chip->n_bytes = 1; 1300 chip->read = u8_reader; 1301 chip->write = u8_writer; 1302 } else if (spi->bits_per_word <= 16) { 1303 chip->n_bytes = 2; 1304 chip->read = u16_reader; 1305 chip->write = u16_writer; 1306 } else if (spi->bits_per_word <= 32) { 1307 chip->n_bytes = 4; 1308 chip->read = u32_reader; 1309 chip->write = u32_writer; 1310 } 1311 1312 spi_set_ctldata(spi, chip); 1313 1314 if (drv_data->ssp_type == CE4100_SSP) 1315 return 0; 1316 1317 return setup_cs(spi, chip, chip_info); 1318 } 1319 1320 static void cleanup(struct spi_device *spi) 1321 { 1322 struct chip_data *chip = spi_get_ctldata(spi); 1323 struct driver_data *drv_data = 1324 spi_controller_get_devdata(spi->controller); 1325 1326 if (!chip) 1327 return; 1328 1329 if (drv_data->ssp_type != CE4100_SSP && !drv_data->cs_gpiods && 1330 chip->gpiod_cs) 1331 gpiod_put(chip->gpiod_cs); 1332 1333 kfree(chip); 1334 } 1335 1336 #ifdef CONFIG_PCI 1337 #ifdef CONFIG_ACPI 1338 1339 static const struct acpi_device_id pxa2xx_spi_acpi_match[] = { 1340 { "INT33C0", LPSS_LPT_SSP }, 1341 { "INT33C1", LPSS_LPT_SSP }, 1342 { "INT3430", LPSS_LPT_SSP }, 1343 { "INT3431", LPSS_LPT_SSP }, 1344 { "80860F0E", LPSS_BYT_SSP }, 1345 { "8086228E", LPSS_BSW_SSP }, 1346 { }, 1347 }; 1348 MODULE_DEVICE_TABLE(acpi, pxa2xx_spi_acpi_match); 1349 1350 static int pxa2xx_spi_get_port_id(struct acpi_device *adev) 1351 { 1352 unsigned int devid; 1353 int port_id = -1; 1354 1355 if (adev && adev->pnp.unique_id && 1356 !kstrtouint(adev->pnp.unique_id, 0, &devid)) 1357 port_id = devid; 1358 return port_id; 1359 } 1360 #else /* !CONFIG_ACPI */ 1361 static int pxa2xx_spi_get_port_id(struct acpi_device *adev) 1362 { 1363 return -1; 1364 } 1365 #endif 1366 1367 /* 1368 * PCI IDs of compound devices that integrate both host controller and private 1369 * integrated DMA engine. Please note these are not used in module 1370 * autoloading and probing in this module but matching the LPSS SSP type. 1371 */ 1372 static const struct pci_device_id pxa2xx_spi_pci_compound_match[] = { 1373 /* SPT-LP */ 1374 { PCI_VDEVICE(INTEL, 0x9d29), LPSS_SPT_SSP }, 1375 { PCI_VDEVICE(INTEL, 0x9d2a), LPSS_SPT_SSP }, 1376 /* SPT-H */ 1377 { PCI_VDEVICE(INTEL, 0xa129), LPSS_SPT_SSP }, 1378 { PCI_VDEVICE(INTEL, 0xa12a), LPSS_SPT_SSP }, 1379 /* KBL-H */ 1380 { PCI_VDEVICE(INTEL, 0xa2a9), LPSS_SPT_SSP }, 1381 { PCI_VDEVICE(INTEL, 0xa2aa), LPSS_SPT_SSP }, 1382 /* BXT A-Step */ 1383 { PCI_VDEVICE(INTEL, 0x0ac2), LPSS_BXT_SSP }, 1384 { PCI_VDEVICE(INTEL, 0x0ac4), LPSS_BXT_SSP }, 1385 { PCI_VDEVICE(INTEL, 0x0ac6), LPSS_BXT_SSP }, 1386 /* BXT B-Step */ 1387 { PCI_VDEVICE(INTEL, 0x1ac2), LPSS_BXT_SSP }, 1388 { PCI_VDEVICE(INTEL, 0x1ac4), LPSS_BXT_SSP }, 1389 { PCI_VDEVICE(INTEL, 0x1ac6), LPSS_BXT_SSP }, 1390 /* GLK */ 1391 { PCI_VDEVICE(INTEL, 0x31c2), LPSS_BXT_SSP }, 1392 { PCI_VDEVICE(INTEL, 0x31c4), LPSS_BXT_SSP }, 1393 { PCI_VDEVICE(INTEL, 0x31c6), LPSS_BXT_SSP }, 1394 /* APL */ 1395 { PCI_VDEVICE(INTEL, 0x5ac2), LPSS_BXT_SSP }, 1396 { PCI_VDEVICE(INTEL, 0x5ac4), LPSS_BXT_SSP }, 1397 { PCI_VDEVICE(INTEL, 0x5ac6), LPSS_BXT_SSP }, 1398 /* CNL-LP */ 1399 { PCI_VDEVICE(INTEL, 0x9daa), LPSS_CNL_SSP }, 1400 { PCI_VDEVICE(INTEL, 0x9dab), LPSS_CNL_SSP }, 1401 { PCI_VDEVICE(INTEL, 0x9dfb), LPSS_CNL_SSP }, 1402 /* CNL-H */ 1403 { PCI_VDEVICE(INTEL, 0xa32a), LPSS_CNL_SSP }, 1404 { PCI_VDEVICE(INTEL, 0xa32b), LPSS_CNL_SSP }, 1405 { PCI_VDEVICE(INTEL, 0xa37b), LPSS_CNL_SSP }, 1406 { }, 1407 }; 1408 1409 static bool pxa2xx_spi_idma_filter(struct dma_chan *chan, void *param) 1410 { 1411 struct device *dev = param; 1412 1413 if (dev != chan->device->dev->parent) 1414 return false; 1415 1416 return true; 1417 } 1418 1419 static struct pxa2xx_spi_master * 1420 pxa2xx_spi_init_pdata(struct platform_device *pdev) 1421 { 1422 struct pxa2xx_spi_master *pdata; 1423 struct acpi_device *adev; 1424 struct ssp_device *ssp; 1425 struct resource *res; 1426 const struct acpi_device_id *adev_id = NULL; 1427 const struct pci_device_id *pcidev_id = NULL; 1428 int type; 1429 1430 adev = ACPI_COMPANION(&pdev->dev); 1431 1432 if (dev_is_pci(pdev->dev.parent)) 1433 pcidev_id = pci_match_id(pxa2xx_spi_pci_compound_match, 1434 to_pci_dev(pdev->dev.parent)); 1435 else if (adev) 1436 adev_id = acpi_match_device(pdev->dev.driver->acpi_match_table, 1437 &pdev->dev); 1438 else 1439 return NULL; 1440 1441 if (adev_id) 1442 type = (int)adev_id->driver_data; 1443 else if (pcidev_id) 1444 type = (int)pcidev_id->driver_data; 1445 else 1446 return NULL; 1447 1448 pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); 1449 if (!pdata) 1450 return NULL; 1451 1452 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1453 if (!res) 1454 return NULL; 1455 1456 ssp = &pdata->ssp; 1457 1458 ssp->phys_base = res->start; 1459 ssp->mmio_base = devm_ioremap_resource(&pdev->dev, res); 1460 if (IS_ERR(ssp->mmio_base)) 1461 return NULL; 1462 1463 if (pcidev_id) { 1464 pdata->tx_param = pdev->dev.parent; 1465 pdata->rx_param = pdev->dev.parent; 1466 pdata->dma_filter = pxa2xx_spi_idma_filter; 1467 } 1468 1469 ssp->clk = devm_clk_get(&pdev->dev, NULL); 1470 ssp->irq = platform_get_irq(pdev, 0); 1471 ssp->type = type; 1472 ssp->pdev = pdev; 1473 ssp->port_id = pxa2xx_spi_get_port_id(adev); 1474 1475 pdata->num_chipselect = 1; 1476 pdata->enable_dma = true; 1477 1478 return pdata; 1479 } 1480 1481 #else /* !CONFIG_PCI */ 1482 static inline struct pxa2xx_spi_master * 1483 pxa2xx_spi_init_pdata(struct platform_device *pdev) 1484 { 1485 return NULL; 1486 } 1487 #endif 1488 1489 static int pxa2xx_spi_fw_translate_cs(struct spi_controller *master, 1490 unsigned int cs) 1491 { 1492 struct driver_data *drv_data = spi_controller_get_devdata(master); 1493 1494 if (has_acpi_companion(&drv_data->pdev->dev)) { 1495 switch (drv_data->ssp_type) { 1496 /* 1497 * For Atoms the ACPI DeviceSelection used by the Windows 1498 * driver starts from 1 instead of 0 so translate it here 1499 * to match what Linux expects. 1500 */ 1501 case LPSS_BYT_SSP: 1502 case LPSS_BSW_SSP: 1503 return cs - 1; 1504 1505 default: 1506 break; 1507 } 1508 } 1509 1510 return cs; 1511 } 1512 1513 static int pxa2xx_spi_probe(struct platform_device *pdev) 1514 { 1515 struct device *dev = &pdev->dev; 1516 struct pxa2xx_spi_master *platform_info; 1517 struct spi_controller *master; 1518 struct driver_data *drv_data; 1519 struct ssp_device *ssp; 1520 const struct lpss_config *config; 1521 int status, count; 1522 u32 tmp; 1523 1524 platform_info = dev_get_platdata(dev); 1525 if (!platform_info) { 1526 platform_info = pxa2xx_spi_init_pdata(pdev); 1527 if (!platform_info) { 1528 dev_err(&pdev->dev, "missing platform data\n"); 1529 return -ENODEV; 1530 } 1531 } 1532 1533 ssp = pxa_ssp_request(pdev->id, pdev->name); 1534 if (!ssp) 1535 ssp = &platform_info->ssp; 1536 1537 if (!ssp->mmio_base) { 1538 dev_err(&pdev->dev, "failed to get ssp\n"); 1539 return -ENODEV; 1540 } 1541 1542 master = spi_alloc_master(dev, sizeof(struct driver_data)); 1543 if (!master) { 1544 dev_err(&pdev->dev, "cannot alloc spi_master\n"); 1545 pxa_ssp_free(ssp); 1546 return -ENOMEM; 1547 } 1548 drv_data = spi_controller_get_devdata(master); 1549 drv_data->master = master; 1550 drv_data->master_info = platform_info; 1551 drv_data->pdev = pdev; 1552 drv_data->ssp = ssp; 1553 1554 master->dev.of_node = pdev->dev.of_node; 1555 /* the spi->mode bits understood by this driver: */ 1556 master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_CS_HIGH | SPI_LOOP; 1557 1558 master->bus_num = ssp->port_id; 1559 master->dma_alignment = DMA_ALIGNMENT; 1560 master->cleanup = cleanup; 1561 master->setup = setup; 1562 master->set_cs = pxa2xx_spi_set_cs; 1563 master->transfer_one = pxa2xx_spi_transfer_one; 1564 master->handle_err = pxa2xx_spi_handle_err; 1565 master->unprepare_transfer_hardware = pxa2xx_spi_unprepare_transfer; 1566 master->fw_translate_cs = pxa2xx_spi_fw_translate_cs; 1567 master->auto_runtime_pm = true; 1568 master->flags = SPI_CONTROLLER_MUST_RX | SPI_CONTROLLER_MUST_TX; 1569 1570 drv_data->ssp_type = ssp->type; 1571 1572 drv_data->ioaddr = ssp->mmio_base; 1573 drv_data->ssdr_physical = ssp->phys_base + SSDR; 1574 if (pxa25x_ssp_comp(drv_data)) { 1575 switch (drv_data->ssp_type) { 1576 case QUARK_X1000_SSP: 1577 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1578 break; 1579 default: 1580 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 16); 1581 break; 1582 } 1583 1584 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE; 1585 drv_data->dma_cr1 = 0; 1586 drv_data->clear_sr = SSSR_ROR; 1587 drv_data->mask_sr = SSSR_RFS | SSSR_TFS | SSSR_ROR; 1588 } else { 1589 master->bits_per_word_mask = SPI_BPW_RANGE_MASK(4, 32); 1590 drv_data->int_cr1 = SSCR1_TIE | SSCR1_RIE | SSCR1_TINTE; 1591 drv_data->dma_cr1 = DEFAULT_DMA_CR1; 1592 drv_data->clear_sr = SSSR_ROR | SSSR_TINT; 1593 drv_data->mask_sr = SSSR_TINT | SSSR_RFS | SSSR_TFS | SSSR_ROR; 1594 } 1595 1596 status = request_irq(ssp->irq, ssp_int, IRQF_SHARED, dev_name(dev), 1597 drv_data); 1598 if (status < 0) { 1599 dev_err(&pdev->dev, "cannot get IRQ %d\n", ssp->irq); 1600 goto out_error_master_alloc; 1601 } 1602 1603 /* Setup DMA if requested */ 1604 if (platform_info->enable_dma) { 1605 status = pxa2xx_spi_dma_setup(drv_data); 1606 if (status) { 1607 dev_dbg(dev, "no DMA channels available, using PIO\n"); 1608 platform_info->enable_dma = false; 1609 } else { 1610 master->can_dma = pxa2xx_spi_can_dma; 1611 } 1612 } 1613 1614 /* Enable SOC clock */ 1615 status = clk_prepare_enable(ssp->clk); 1616 if (status) 1617 goto out_error_dma_irq_alloc; 1618 1619 master->max_speed_hz = clk_get_rate(ssp->clk); 1620 1621 /* Load default SSP configuration */ 1622 pxa2xx_spi_write(drv_data, SSCR0, 0); 1623 switch (drv_data->ssp_type) { 1624 case QUARK_X1000_SSP: 1625 tmp = QUARK_X1000_SSCR1_RxTresh(RX_THRESH_QUARK_X1000_DFLT) | 1626 QUARK_X1000_SSCR1_TxTresh(TX_THRESH_QUARK_X1000_DFLT); 1627 pxa2xx_spi_write(drv_data, SSCR1, tmp); 1628 1629 /* using the Motorola SPI protocol and use 8 bit frame */ 1630 tmp = QUARK_X1000_SSCR0_Motorola | QUARK_X1000_SSCR0_DataSize(8); 1631 pxa2xx_spi_write(drv_data, SSCR0, tmp); 1632 break; 1633 case CE4100_SSP: 1634 tmp = CE4100_SSCR1_RxTresh(RX_THRESH_CE4100_DFLT) | 1635 CE4100_SSCR1_TxTresh(TX_THRESH_CE4100_DFLT); 1636 pxa2xx_spi_write(drv_data, SSCR1, tmp); 1637 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8); 1638 pxa2xx_spi_write(drv_data, SSCR0, tmp); 1639 break; 1640 default: 1641 tmp = SSCR1_RxTresh(RX_THRESH_DFLT) | 1642 SSCR1_TxTresh(TX_THRESH_DFLT); 1643 pxa2xx_spi_write(drv_data, SSCR1, tmp); 1644 tmp = SSCR0_SCR(2) | SSCR0_Motorola | SSCR0_DataSize(8); 1645 pxa2xx_spi_write(drv_data, SSCR0, tmp); 1646 break; 1647 } 1648 1649 if (!pxa25x_ssp_comp(drv_data)) 1650 pxa2xx_spi_write(drv_data, SSTO, 0); 1651 1652 if (!is_quark_x1000_ssp(drv_data)) 1653 pxa2xx_spi_write(drv_data, SSPSP, 0); 1654 1655 if (is_lpss_ssp(drv_data)) { 1656 lpss_ssp_setup(drv_data); 1657 config = lpss_get_config(drv_data); 1658 if (config->reg_capabilities >= 0) { 1659 tmp = __lpss_ssp_read_priv(drv_data, 1660 config->reg_capabilities); 1661 tmp &= LPSS_CAPS_CS_EN_MASK; 1662 tmp >>= LPSS_CAPS_CS_EN_SHIFT; 1663 platform_info->num_chipselect = ffz(tmp); 1664 } else if (config->cs_num) { 1665 platform_info->num_chipselect = config->cs_num; 1666 } 1667 } 1668 master->num_chipselect = platform_info->num_chipselect; 1669 1670 count = gpiod_count(&pdev->dev, "cs"); 1671 if (count > 0) { 1672 int i; 1673 1674 master->num_chipselect = max_t(int, count, 1675 master->num_chipselect); 1676 1677 drv_data->cs_gpiods = devm_kcalloc(&pdev->dev, 1678 master->num_chipselect, sizeof(struct gpio_desc *), 1679 GFP_KERNEL); 1680 if (!drv_data->cs_gpiods) { 1681 status = -ENOMEM; 1682 goto out_error_clock_enabled; 1683 } 1684 1685 for (i = 0; i < master->num_chipselect; i++) { 1686 struct gpio_desc *gpiod; 1687 1688 gpiod = devm_gpiod_get_index(dev, "cs", i, GPIOD_ASIS); 1689 if (IS_ERR(gpiod)) { 1690 /* Means use native chip select */ 1691 if (PTR_ERR(gpiod) == -ENOENT) 1692 continue; 1693 1694 status = (int)PTR_ERR(gpiod); 1695 goto out_error_clock_enabled; 1696 } else { 1697 drv_data->cs_gpiods[i] = gpiod; 1698 } 1699 } 1700 } 1701 1702 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 1703 pm_runtime_use_autosuspend(&pdev->dev); 1704 pm_runtime_set_active(&pdev->dev); 1705 pm_runtime_enable(&pdev->dev); 1706 1707 /* Register with the SPI framework */ 1708 platform_set_drvdata(pdev, drv_data); 1709 status = devm_spi_register_controller(&pdev->dev, master); 1710 if (status != 0) { 1711 dev_err(&pdev->dev, "problem registering spi master\n"); 1712 goto out_error_clock_enabled; 1713 } 1714 1715 return status; 1716 1717 out_error_clock_enabled: 1718 pm_runtime_put_noidle(&pdev->dev); 1719 pm_runtime_disable(&pdev->dev); 1720 clk_disable_unprepare(ssp->clk); 1721 1722 out_error_dma_irq_alloc: 1723 pxa2xx_spi_dma_release(drv_data); 1724 free_irq(ssp->irq, drv_data); 1725 1726 out_error_master_alloc: 1727 spi_controller_put(master); 1728 pxa_ssp_free(ssp); 1729 return status; 1730 } 1731 1732 static int pxa2xx_spi_remove(struct platform_device *pdev) 1733 { 1734 struct driver_data *drv_data = platform_get_drvdata(pdev); 1735 struct ssp_device *ssp; 1736 1737 if (!drv_data) 1738 return 0; 1739 ssp = drv_data->ssp; 1740 1741 pm_runtime_get_sync(&pdev->dev); 1742 1743 /* Disable the SSP at the peripheral and SOC level */ 1744 pxa2xx_spi_write(drv_data, SSCR0, 0); 1745 clk_disable_unprepare(ssp->clk); 1746 1747 /* Release DMA */ 1748 if (drv_data->master_info->enable_dma) 1749 pxa2xx_spi_dma_release(drv_data); 1750 1751 pm_runtime_put_noidle(&pdev->dev); 1752 pm_runtime_disable(&pdev->dev); 1753 1754 /* Release IRQ */ 1755 free_irq(ssp->irq, drv_data); 1756 1757 /* Release SSP */ 1758 pxa_ssp_free(ssp); 1759 1760 return 0; 1761 } 1762 1763 static void pxa2xx_spi_shutdown(struct platform_device *pdev) 1764 { 1765 int status = 0; 1766 1767 if ((status = pxa2xx_spi_remove(pdev)) != 0) 1768 dev_err(&pdev->dev, "shutdown failed with %d\n", status); 1769 } 1770 1771 #ifdef CONFIG_PM_SLEEP 1772 static int pxa2xx_spi_suspend(struct device *dev) 1773 { 1774 struct driver_data *drv_data = dev_get_drvdata(dev); 1775 struct ssp_device *ssp = drv_data->ssp; 1776 int status; 1777 1778 status = spi_controller_suspend(drv_data->master); 1779 if (status != 0) 1780 return status; 1781 pxa2xx_spi_write(drv_data, SSCR0, 0); 1782 1783 if (!pm_runtime_suspended(dev)) 1784 clk_disable_unprepare(ssp->clk); 1785 1786 return 0; 1787 } 1788 1789 static int pxa2xx_spi_resume(struct device *dev) 1790 { 1791 struct driver_data *drv_data = dev_get_drvdata(dev); 1792 struct ssp_device *ssp = drv_data->ssp; 1793 int status; 1794 1795 /* Enable the SSP clock */ 1796 if (!pm_runtime_suspended(dev)) { 1797 status = clk_prepare_enable(ssp->clk); 1798 if (status) 1799 return status; 1800 } 1801 1802 /* Restore LPSS private register bits */ 1803 if (is_lpss_ssp(drv_data)) 1804 lpss_ssp_setup(drv_data); 1805 1806 /* Start the queue running */ 1807 status = spi_controller_resume(drv_data->master); 1808 if (status != 0) { 1809 dev_err(dev, "problem starting queue (%d)\n", status); 1810 return status; 1811 } 1812 1813 return 0; 1814 } 1815 #endif 1816 1817 #ifdef CONFIG_PM 1818 static int pxa2xx_spi_runtime_suspend(struct device *dev) 1819 { 1820 struct driver_data *drv_data = dev_get_drvdata(dev); 1821 1822 clk_disable_unprepare(drv_data->ssp->clk); 1823 return 0; 1824 } 1825 1826 static int pxa2xx_spi_runtime_resume(struct device *dev) 1827 { 1828 struct driver_data *drv_data = dev_get_drvdata(dev); 1829 int status; 1830 1831 status = clk_prepare_enable(drv_data->ssp->clk); 1832 return status; 1833 } 1834 #endif 1835 1836 static const struct dev_pm_ops pxa2xx_spi_pm_ops = { 1837 SET_SYSTEM_SLEEP_PM_OPS(pxa2xx_spi_suspend, pxa2xx_spi_resume) 1838 SET_RUNTIME_PM_OPS(pxa2xx_spi_runtime_suspend, 1839 pxa2xx_spi_runtime_resume, NULL) 1840 }; 1841 1842 static struct platform_driver driver = { 1843 .driver = { 1844 .name = "pxa2xx-spi", 1845 .pm = &pxa2xx_spi_pm_ops, 1846 .acpi_match_table = ACPI_PTR(pxa2xx_spi_acpi_match), 1847 }, 1848 .probe = pxa2xx_spi_probe, 1849 .remove = pxa2xx_spi_remove, 1850 .shutdown = pxa2xx_spi_shutdown, 1851 }; 1852 1853 static int __init pxa2xx_spi_init(void) 1854 { 1855 return platform_driver_register(&driver); 1856 } 1857 subsys_initcall(pxa2xx_spi_init); 1858 1859 static void __exit pxa2xx_spi_exit(void) 1860 { 1861 platform_driver_unregister(&driver); 1862 } 1863 module_exit(pxa2xx_spi_exit); 1864